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[187.189.51.143]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-2f78ff55633sm531448fac.20.2025.07.04.07.28.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jul 2025 07:28:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751639335; x=1752244135; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/y6ae8MFtHgdri3B/hfnDJLsIID9R8RxmBlWT9Y9/4M=; b=xEJZEzQ+2ractfUc8ROuAGifbDV7hDlHIF57lACNxDpOUVxSKkp9qKKwJBQkRlgbNL enefb9WquFXVhAM8uE7cM601okabF0Wj3Bp/bmmZViIvohkE6/JpmPpz6wlwMuR90Gt2 5zcmiu+9Ym8KRdc9yk5SiZIdPXhzuQa1tjtdR5iTuUkLGoKfMob5Ib8sCDAIzx+xgAnH RIfWK+vcbRLrhl9PGWGagIfp0q1BFtgjkptzRM34CaMPFr+Z0i6G6WZ7MyY5EnvD/Ijl MYZJOx0d9mv6Y4FL0p2vizaToei16xrComXw5wRU4W6X/kx12nWqnbkM8Q/RFfoB3Fhs rh3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751639335; x=1752244135; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/y6ae8MFtHgdri3B/hfnDJLsIID9R8RxmBlWT9Y9/4M=; b=aYvycXTMwKRfYG35YX4yRkuWCG7tDLxLoBjOsIMdaZVmh+hU3r/4LkGLuz2s/hJibM Ljyh2LCVq6dcFFi2YltQeMiWmPOfipXl8vdN72VXTXt0y8bVspvgxZoBmcbkJbfv8GPq CVeaYb0FJl+LHhaMk/leTmm+7TGxLgcbK7OZ5OOwRsK4ztpTmmY/mdcmEZv+VbNcIZ+q 4Y7Udw7du5cWb5NVeVa5SeU/hY+9By2wRB5zdaF8uxdH6QP1326sepUaODpm8pEMYud6 asEBT3nW0aVO3SBINLebKMjc96iYMvVjqbvOTqv3mmtDynrBtZy8lz1uWy0PyXN/YzOG oAyg== X-Gm-Message-State: AOJu0YxOaanju7nAyeUwLmWvMVmi5zyMTkqP+wVDLlxf4CXqG6M1NDoB Ql6GCVAcFtdf+TUebegh0RIiDUZoUQstrxtdKnm/uGUzLsQY1prZ+7Z9gidlsupuL8WcUpsX3dx wHYnfT2A= X-Gm-Gg: ASbGncvl4Bc8eVmguQvkr9oJjAInG/hbuJRRSejAD2HgwvtxpVSopgsEipwdxpCLC5Q CdaGXkfzDr23GSpD+9y3uWifzKrR8aSuZGdAAt2RYwoXwoJm3J7OlSMsOQ2UqpJdLIJZ3J/21bn 7PyexPTRmE/2nPwHNGvCM6tSBfASsL3vNQGrjXR7rtzyfPyyfv6ZuaSVqzPwLlahqQpuBDO7oCB oel7hQSHd7hRKbiQnzFvwtGigFss6aBN4WBudlQQ6BAyK4UOXIaFkk3v4Vvl/Hp7SbIk+6QNn9T 11nOR3ggtvkJ5MmRdXd1CpGlmJ3T7HExsNJ9Wy6FWmgcyfJvqyxT6o5sOfjlXgLGcqTNt6y+Q2T fErVE+ZrTxT/Zo9mCPofJ/pwxsHkVa7+xPgcaniV0JOUscwdJ X-Google-Smtp-Source: AGHT+IHgnqO+DkDMrMm+Rn7hUSH6P72TTWpBMEjvQy3i+NOoSdDhhDfGHpRrBDolrVyY3I1fzPAXlQ== X-Received: by 2002:a05:6870:79e:b0:28c:8476:dd76 with SMTP id 586e51a60fabf-2f796cae8d2mr2117805fac.29.1751639334864; Fri, 04 Jul 2025 07:28:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v4 096/108] target/arm: Move ld1qq and st1qq primitives to sve_ldst_internal.h Date: Fri, 4 Jul 2025 08:20:59 -0600 Message-ID: <20250704142112.1018902-97-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250704142112.1018902-1-richard.henderson@linaro.org> References: <20250704142112.1018902-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2e; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751640893920116600 Content-Type: text/plain; charset="utf-8" Move from sme_helper.c to the shared header. Add a comment noting the lack of atomicity. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/sve_ldst_internal.h | 63 ++++++++++++++++++++++++++++++ target/arm/tcg/sme_helper.c | 44 +++------------------ 2 files changed, 69 insertions(+), 38 deletions(-) diff --git a/target/arm/tcg/sve_ldst_internal.h b/target/arm/tcg/sve_ldst_i= nternal.h index e87beba435..c67cda9d3b 100644 --- a/target/arm/tcg/sve_ldst_internal.h +++ b/target/arm/tcg/sve_ldst_internal.h @@ -141,6 +141,69 @@ DO_LD_PRIM_3(ld1dqu_le, ld1dd_le) #define sve_st1dq_be_tlb sve_st1dd_be_tlb #define sve_st1dq_le_tlb sve_st1dd_le_tlb =20 +/* + * The ARMVectorReg elements are stored in host-endian 64-bit units. + * For 128-bit quantities, the sequence defined by the Elem[] pseudocode + * corresponds to storing the two 64-bit pieces in little-endian order. + */ +/* FIXME: Nothing in this file makes any effort at atomicity. */ + +static inline void sve_ld1qq_be_host(void *vd, intptr_t reg_off, void *hos= t) +{ + sve_ld1dd_be_host(vd, reg_off + 8, host); + sve_ld1dd_be_host(vd, reg_off, host + 8); +} + +static inline void sve_ld1qq_le_host(void *vd, intptr_t reg_off, void *hos= t) +{ + sve_ld1dd_le_host(vd, reg_off, host); + sve_ld1dd_le_host(vd, reg_off + 8, host + 8); +} + +static inline void +sve_ld1qq_be_tlb(CPUARMState *env, void *vd, intptr_t reg_off, + target_ulong addr, uintptr_t ra) +{ + sve_ld1dd_be_tlb(env, vd, reg_off + 8, addr, ra); + sve_ld1dd_be_tlb(env, vd, reg_off, addr + 8, ra); +} + +static inline void +sve_ld1qq_le_tlb(CPUARMState *env, void *vd, intptr_t reg_off, + target_ulong addr, uintptr_t ra) +{ + sve_ld1dd_le_tlb(env, vd, reg_off, addr, ra); + sve_ld1dd_le_tlb(env, vd, reg_off + 8, addr + 8, ra); +} + +static inline void sve_st1qq_be_host(void *vd, intptr_t reg_off, void *hos= t) +{ + sve_st1dd_be_host(vd, reg_off + 8, host); + sve_st1dd_be_host(vd, reg_off, host + 8); +} + +static inline void sve_st1qq_le_host(void *vd, intptr_t reg_off, void *hos= t) +{ + sve_st1dd_le_host(vd, reg_off, host); + sve_st1dd_le_host(vd, reg_off + 8, host + 8); +} + +static inline void +sve_st1qq_be_tlb(CPUARMState *env, void *vd, intptr_t reg_off, + target_ulong addr, uintptr_t ra) +{ + sve_st1dd_be_tlb(env, vd, reg_off + 8, addr, ra); + sve_st1dd_be_tlb(env, vd, reg_off, addr + 8, ra); +} + +static inline void +sve_st1qq_le_tlb(CPUARMState *env, void *vd, intptr_t reg_off, + target_ulong addr, uintptr_t ra) +{ + sve_st1dd_le_tlb(env, vd, reg_off, addr, ra); + sve_st1dd_le_tlb(env, vd, reg_off + 8, addr + 8, ra); +} + #undef DO_LD_TLB #undef DO_ST_TLB #undef DO_LD_HOST diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index c1166e4ffa..df16bb2f9c 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -415,54 +415,22 @@ static inline void sme_##NAME##_v_tlb(CPUARMState *en= v, void *za, \ TLB(env, useronly_clean_ptr(addr), val, ra); = \ } =20 -/* - * The ARMVectorReg elements are stored in host-endian 64-bit units. - * For 128-bit quantities, the sequence defined by the Elem[] pseudocode - * corresponds to storing the two 64-bit pieces in little-endian order. - */ -#define DO_LDQ(HNAME, VNAME, BE, HOST, TLB) = \ -static inline void HNAME##_host(void *za, intptr_t off, void *host) = \ -{ = \ - uint64_t val0 =3D HOST(host), val1 =3D HOST(host + 8); = \ - uint64_t *ptr =3D za + off; = \ - ptr[0] =3D BE ? val1 : val0, ptr[1] =3D BE ? val0 : val1; = \ -} = \ +#define DO_LDQ(HNAME, VNAME) \ static inline void VNAME##_v_host(void *za, intptr_t off, void *host) = \ { = \ HNAME##_host(za, tile_vslice_offset(off), host); = \ } = \ -static inline void HNAME##_tlb(CPUARMState *env, void *za, intptr_t off, = \ - target_ulong addr, uintptr_t ra) = \ -{ = \ - uint64_t val0 =3D TLB(env, useronly_clean_ptr(addr), ra); = \ - uint64_t val1 =3D TLB(env, useronly_clean_ptr(addr + 8), ra); = \ - uint64_t *ptr =3D za + off; = \ - ptr[0] =3D BE ? val1 : val0, ptr[1] =3D BE ? val0 : val1; = \ -} = \ static inline void VNAME##_v_tlb(CPUARMState *env, void *za, intptr_t off,= \ target_ulong addr, uintptr_t ra) = \ { = \ HNAME##_tlb(env, za, tile_vslice_offset(off), addr, ra); = \ } =20 -#define DO_STQ(HNAME, VNAME, BE, HOST, TLB) = \ -static inline void HNAME##_host(void *za, intptr_t off, void *host) = \ -{ = \ - uint64_t *ptr =3D za + off; = \ - HOST(host, ptr[BE]); = \ - HOST(host + 8, ptr[!BE]); = \ -} = \ +#define DO_STQ(HNAME, VNAME) \ static inline void VNAME##_v_host(void *za, intptr_t off, void *host) = \ { = \ HNAME##_host(za, tile_vslice_offset(off), host); = \ } = \ -static inline void HNAME##_tlb(CPUARMState *env, void *za, intptr_t off, = \ - target_ulong addr, uintptr_t ra) = \ -{ = \ - uint64_t *ptr =3D za + off; = \ - TLB(env, useronly_clean_ptr(addr), ptr[BE], ra); = \ - TLB(env, useronly_clean_ptr(addr + 8), ptr[!BE], ra); = \ -} = \ static inline void VNAME##_v_tlb(CPUARMState *env, void *za, intptr_t off,= \ target_ulong addr, uintptr_t ra) = \ { = \ @@ -477,8 +445,8 @@ DO_LD(ld1s_le, uint32_t, ldl_le_p, cpu_ldl_le_data_ra) DO_LD(ld1d_be, uint64_t, ldq_be_p, cpu_ldq_be_data_ra) DO_LD(ld1d_le, uint64_t, ldq_le_p, cpu_ldq_le_data_ra) =20 -DO_LDQ(sve_ld1qq_be, sme_ld1q_be, 1, ldq_be_p, cpu_ldq_be_data_ra) -DO_LDQ(sve_ld1qq_le, sme_ld1q_le, 0, ldq_le_p, cpu_ldq_le_data_ra) +DO_LDQ(sve_ld1qq_be, sme_ld1q_be) +DO_LDQ(sve_ld1qq_le, sme_ld1q_le) =20 DO_ST(st1b, uint8_t, stb_p, cpu_stb_data_ra) DO_ST(st1h_be, uint16_t, stw_be_p, cpu_stw_be_data_ra) @@ -488,8 +456,8 @@ DO_ST(st1s_le, uint32_t, stl_le_p, cpu_stl_le_data_ra) DO_ST(st1d_be, uint64_t, stq_be_p, cpu_stq_be_data_ra) DO_ST(st1d_le, uint64_t, stq_le_p, cpu_stq_le_data_ra) =20 -DO_STQ(sve_st1qq_be, sme_st1q_be, 1, stq_be_p, cpu_stq_be_data_ra) -DO_STQ(sve_st1qq_le, sme_st1q_le, 0, stq_le_p, cpu_stq_le_data_ra) +DO_STQ(sve_st1qq_be, sme_st1q_be) +DO_STQ(sve_st1qq_le, sme_st1q_le) =20 #undef DO_LD #undef DO_ST --=20 2.43.0