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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1751618279; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=d/VrHbWi3qt+IqVCDnvLAyU6uKWggJeSDh/Nh9fbyWo=; b=XIB+81eaTk85ZyOidWbHmM2FGKZVdUgk0hBn7mdPa70iUPyJ5hArwR0rCEpQTOZhf+C8AL AFfGA3E1PLcv24WWyG4MIH+EFxhD36yvHe1J/JoCpll6IYXr3qwpxGB2LlYfTmwqUU8jtm nuELErgsCriwzcMbDoR5HMhwU1gfZps= X-MC-Unique: gs_n5eJkO2C2jWi5TzvSjQ-1 X-Mimecast-MFC-AGG-ID: gs_n5eJkO2C2jWi5TzvSjQ_1751618275 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Ed Tanous , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 08/11] hw/arm/aspeed: Add second SPI chip to Aspeed model Date: Fri, 4 Jul 2025 10:37:20 +0200 Message-ID: <20250704083723.1410455-9-clg@redhat.com> In-Reply-To: <20250704083723.1410455-1-clg@redhat.com> References: <20250704083723.1410455-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.237, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1751618371186116600 From: Ed Tanous Aspeed2600 has two spi lanes; Add a new struct that can mount the second SPI. Signed-off-by: Ed Tanous Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20250703144249.3348879-2-etanous@n= vidia.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed.h | 2 ++ hw/arm/aspeed.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h index 973277bea655..6c364556565a 100644 --- a/include/hw/arm/aspeed.h +++ b/include/hw/arm/aspeed.h @@ -35,7 +35,9 @@ struct AspeedMachineClass { uint32_t hw_strap2; const char *fmc_model; const char *spi_model; + const char *spi2_model; uint32_t num_cs; + uint32_t num_cs2; uint32_t macs_mask; void (*i2c_init)(AspeedMachineState *bmc); uint32_t uart_default; diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 94897505f8e3..8d7757e11f1c 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -465,6 +465,8 @@ static void aspeed_machine_init(MachineState *machine) aspeed_board_init_flashes(&bmc->soc->spi[0], bmc->spi_model ? bmc->spi_model : amc->spi_m= odel, 1, amc->num_cs); + aspeed_board_init_flashes(&bmc->soc->spi[1], + amc->spi2_model, 1, amc->num_cs2); } =20 if (machine->kernel_filename && sc->num_cpus > 1) { --=20 2.50.0