The following changes since commit c77283dd5d79149f4e7e9edd00f65416c648ee59: Merge tag 'pull-request-2025-07-02' of https://gitlab.com/thuth/qemu into staging (2025-07-03 06:01:41 -0400) are available in the Git repository at: https://github.com/legoater/qemu/ tags/pull-aspeed-20250704 for you to fetch changes up to 3a34dad2c0d25cebafed40696bbbdeb7ff4b9c7d: tests/functional: Add gb200 tests (2025-07-03 17:36:45 +0200) ---------------------------------------------------------------- aspeed queue: * Improved AST2700 SoC modeling (SDMC, SCU) * Fixed hardware strapping of 'bletchley-bmc' machine * Added new Meta 'catalina-bmc' machine and functional test using OpenBMC * Improved AST2600 SCU protection key modeling * Introduced AST2600 SCU unit tests * Deprecated 'ast2700a0-evb' machine * Added new NVIDIA 'gb200-bmc' machine and functional test using OpenBMC ---------------------------------------------------------------- Ed Tanous (4): hw/arm/aspeed: Add second SPI chip to Aspeed model docs: add support for gb200-bmc hw/arm/aspeed: Add GB200 BMC target tests/functional: Add gb200 tests Jamin Lin (3): hw/misc/aspeed_sdmc: Skipping dram_init in u-boot for AST2700 hw/misc/aspeed_scu: Support the Frequency Counter Control register for AST2700 aspeed: Deprecate the ast2700a0-evb machine Patrick Williams (2): hw/arm/aspeed: bletchley: update hw strap values hw/arm/aspeed: add Catalina machine type Tan Siewert (2): hw/misc/aspeed_scu: Handle AST2600 protection key registers correctly tests/qtest: Add test for ASPEED SCU docs/about/deprecated.rst | 8 + docs/system/arm/aspeed.rst | 4 +- hw/arm/aspeed_eeprom.h | 3 + include/hw/arm/aspeed.h | 2 + hw/arm/aspeed.c | 285 ++++++++++++++++++++++- hw/arm/aspeed_eeprom.c | 21 ++ hw/misc/aspeed_scu.c | 22 +- hw/misc/aspeed_sdmc.c | 3 + tests/qtest/aspeed_scu-test.c | 231 ++++++++++++++++++ hw/arm/Kconfig | 1 + tests/functional/aspeed.py | 9 +- tests/functional/meson.build | 4 + tests/functional/test_arm_aspeed_catalina.py | 25 ++ tests/functional/test_arm_aspeed_gb200nvl_bmc.py | 26 +++ tests/qtest/meson.build | 1 + 15 files changed, 636 insertions(+), 9 deletions(-) create mode 100644 tests/qtest/aspeed_scu-test.c create mode 100755 tests/functional/test_arm_aspeed_catalina.py create mode 100644 tests/functional/test_arm_aspeed_gb200nvl_bmc.py From: Jamin Lin <jamin_lin@aspeedtech.com> On AST2700 SoC, QEMU now sets BIT6 in VGA0 SCRATCH register to indicate that DDR training has completed, thus skipping the dram_init(). To align with the recent U-Boot changes, where the Main Control Register's BIT16 is checked to skip the dram_init() process, this patch sets BIT16 in the SDMC Main Control Register at reset time. This allows both the main U-Boot stage to correctly detect and bypass DRAM initialization when running under QEMU. Reference: - QEMU: https://github.com/qemu/qemu/commit/2d082fea485ee455a70ed3e963cdf9a70f34858a - U-Boot: https://github.com/AspeedTech-BMC/u-boot/commit/94e5435504fb0d8888f5c1bfd3fa284cdd6aaf9b Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250618080006.846355-2-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- hw/misc/aspeed_sdmc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c index XXXXXXX..XXXXXXX 100644 --- a/hw/misc/aspeed_sdmc.c +++ b/hw/misc/aspeed_sdmc.c @@ -XXX,XX +XXX,XX @@ static void aspeed_2700_sdmc_reset(DeviceState *dev) /* Set ram size bit and defaults values */ s->regs[R_MAIN_CONF] = asc->compute_conf(s, 0); + /* Skipping dram init */ + s->regs[R_MAIN_CONTROL] = BIT(16); + if (s->unlocked) { s->regs[R_2700_PROT] = PROT_UNLOCKED; } -- 2.50.0 From: Jamin Lin <jamin_lin@aspeedtech.com> According to the datasheet: BIT[1] (SCU_FREQ_OSC_EN) enables the oscillator frequency measurement counter. BIT[6] (SCU_FREQ_DONE) indicates the measurement is finished. Firmware polls BIT[6] to determine when measurement is complete. The flag can be cleared by writing BIT[1] to 0. To simulate this hardware behavior in QEMU: If BIT[1] is set to 1, BIT[6] is immediately set to 1 to avoid firmware hanging during polling. If BIT[1] is cleared to 0, BIT[6] is also cleared to 0 to match hardware semantics. The initial value of this register is initialized to 0x80, reflecting the default value confirmed from an EVB register dump. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250618080006.846355-3-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- hw/misc/aspeed_scu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index XXXXXXX..XXXXXXX 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -XXX,XX +XXX,XX @@ #define AST2700_SCUIO_UARTCLK_GEN TO_REG(0x330) #define AST2700_SCUIO_HUARTCLK_GEN TO_REG(0x334) #define AST2700_SCUIO_CLK_DUTY_MEAS_RST TO_REG(0x388) +#define AST2700_SCUIO_FREQ_CNT_CTL TO_REG(0x3A0) #define SCU_IO_REGION_SIZE 0x1000 @@ -XXX,XX +XXX,XX @@ static void aspeed_ast2700_scuio_write(void *opaque, hwaddr offset, s->regs[reg - 1] ^= data; updated = true; break; + case AST2700_SCUIO_FREQ_CNT_CTL: + s->regs[reg] = deposit32(s->regs[reg], 6, 1, !!(data & BIT(1))); + updated = true; + break; default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Unhandled write at offset 0x%" HWADDR_PRIx "\n", @@ -XXX,XX +XXX,XX @@ static const uint32_t ast2700_a0_resets_io[ASPEED_AST2700_SCU_NR_REGS] = { [AST2700_SCUIO_UARTCLK_GEN] = 0x00014506, [AST2700_SCUIO_HUARTCLK_GEN] = 0x000145c0, [AST2700_SCUIO_CLK_DUTY_MEAS_RST] = 0x0c9100d2, + [AST2700_SCUIO_FREQ_CNT_CTL] = 0x00000080, }; static void aspeed_2700_scuio_class_init(ObjectClass *klass, const void *data) -- 2.50.0 From: Patrick Williams <patrick@stwcx.xyz> Update the Bletchley hardware strap register values per actual hardware: ``` root@bmc:~# devmem 0x1e6e2500 0x00002000 root@bmc:~# devmem 0x1e6e2510 0x00000801 ``` Signed-off-by: Patrick Williams <patrick@stwcx.xyz> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250619035850.2682690-1-patrick@stwcx.xyz Signed-off-by: Cédric Le Goater <clg@redhat.com> --- hw/arm/aspeed.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -XXX,XX +XXX,XX @@ struct AspeedMachineState { #define FUJI_BMC_HW_STRAP2 0x00000000 /* Bletchley hardware value */ -/* TODO: Leave same as EVB for now. */ -#define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1 -#define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2 +#define BLETCHLEY_BMC_HW_STRAP1 0x00002000 +#define BLETCHLEY_BMC_HW_STRAP2 0x00000801 /* Qualcomm DC-SCM hardware value */ #define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000 -- 2.50.0 From: Patrick Williams <patrick@stwcx.xyz> Add the 'catalina-bmc' machine type based on the kernel DTS[1] as of 6.16-rc2. The i2c model is as complete as the current QEMU models support, but in some cases I substituted devices that are close enough for present functionality. Strap registers are were verified with hardware. This has been tested with an openbmc image built from [2]. Add a functional test in line with Bletchley, pointing at an image obtained from the OpenBMC Jenkins server. [1]: https://github.com/torvalds/linux/blob/v6.16-rc2/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-catalina.dts [2]: https://github.com/openbmc/openbmc/commit/5bc73ec261f981d5e586bda5ac78eb0cbd5f92b0 Signed-off-by: Patrick Williams <patrick@stwcx.xyz> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250619151458.2831859-1-patrick@stwcx.xyz Signed-off-by: Cédric Le Goater <clg@redhat.com> --- hw/arm/aspeed.c | 200 +++++++++++++++++++ hw/arm/Kconfig | 1 + tests/functional/meson.build | 2 + tests/functional/test_arm_aspeed_catalina.py | 25 +++ 4 files changed, 228 insertions(+) create mode 100755 tests/functional/test_arm_aspeed_catalina.py diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -XXX,XX +XXX,XX @@ #include "hw/i2c/i2c_mux_pca954x.h" #include "hw/i2c/smbus_eeprom.h" #include "hw/gpio/pca9552.h" +#include "hw/gpio/pca9554.h" #include "hw/nvram/eeprom_at24c.h" #include "hw/sensor/tmp105.h" #include "hw/misc/led.h" @@ -XXX,XX +XXX,XX @@ static void fuji_bmc_i2c_init(AspeedMachineState *bmc) } #define TYPE_TMP421 "tmp421" +#define TYPE_DS1338 "ds1338" + +/* Catalina hardware value */ +#define CATALINA_BMC_HW_STRAP1 0x00002002 +#define CATALINA_BMC_HW_STRAP2 0x00000800 + +#define CATALINA_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) + +static void catalina_bmc_i2c_init(AspeedMachineState *bmc) +{ + /* Reference from v6.16-rc2 aspeed-bmc-facebook-catalina.dts */ + + AspeedSoCState *soc = bmc->soc; + I2CBus *i2c[16] = {}; + I2CSlave *i2c_mux; + + /* busses 0-15 are all used. */ + for (int i = 0; i < ARRAY_SIZE(i2c); i++) { + i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); + } + + /* &i2c0 */ + /* i2c-mux@71 (PCA9546) on i2c0 */ + i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x71); + + /* i2c-mux@72 (PCA9546) on i2c0 */ + i2c_mux = i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x72); + + /* i2c0mux1ch1 */ + /* io_expander7 - pca9535@20 */ + i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 1), + TYPE_PCA9552, 0x20); + /* eeprom@50 */ + at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x50, 8 * KiB); + + /* i2c-mux@73 (PCA9546) on i2c0 */ + i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x73); + + /* i2c-mux@75 (PCA9546) on i2c0 */ + i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x75); + + /* i2c-mux@76 (PCA9546) on i2c0 */ + i2c_mux = i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x76); + + /* i2c0mux4ch1 */ + /* io_expander8 - pca9535@21 */ + i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 1), + TYPE_PCA9552, 0x21); + /* eeprom@50 */ + at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x50, 8 * KiB); + + /* i2c-mux@77 (PCA9546) on i2c0 */ + i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x77); + + + /* &i2c1 */ + /* i2c-mux@70 (PCA9548) on i2c1 */ + i2c_mux = i2c_slave_create_simple(i2c[1], TYPE_PCA9548, 0x70); + /* i2c1mux0ch0 */ + /* ina238@41 - no model */ + /* ina238@42 - no model */ + /* ina238@44 - no model */ + /* i2c1mux0ch1 */ + /* ina238@41 - no model */ + /* ina238@43 - no model */ + /* i2c1mux0ch4 */ + /* ltc4287@42 - no model */ + /* ltc4287@43 - no model */ + + /* i2c1mux0ch5 */ + /* eeprom@54 */ + at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 5), 0x54, 8 * KiB); + /* tpm75@4f */ + i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 5), TYPE_TMP75, 0x4f); + + /* i2c1mux0ch6 */ + /* io_expander5 - pca9554@27 */ + i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 6), + TYPE_PCA9554, 0x27); + /* io_expander6 - pca9555@25 */ + i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 6), + TYPE_PCA9552, 0x25); + /* eeprom@51 */ + at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 6), 0x51, 8 * KiB); + + /* i2c1mux0ch7 */ + /* eeprom@53 */ + at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 7), 0x53, 8 * KiB); + /* temperature-sensor@4b - tmp75 */ + i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 7), TYPE_TMP75, 0x4b); + + /* &i2c2 */ + /* io_expander0 - pca9555@20 */ + i2c_slave_create_simple(i2c[2], TYPE_PCA9552, 0x20); + /* io_expander0 - pca9555@21 */ + i2c_slave_create_simple(i2c[2], TYPE_PCA9552, 0x21); + /* io_expander0 - pca9555@27 */ + i2c_slave_create_simple(i2c[2], TYPE_PCA9552, 0x27); + /* eeprom@50 */ + at24c_eeprom_init(i2c[2], 0x50, 8 * KiB); + /* eeprom@51 */ + at24c_eeprom_init(i2c[2], 0x51, 8 * KiB); + + /* &i2c5 */ + /* i2c-mux@70 (PCA9548) on i2c5 */ + i2c_mux = i2c_slave_create_simple(i2c[5], TYPE_PCA9548, 0x70); + /* i2c5mux0ch6 */ + /* eeprom@52 */ + at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 6), 0x52, 8 * KiB); + /* i2c5mux0ch7 */ + /* ina230@40 - no model */ + /* ina230@41 - no model */ + /* ina230@44 - no model */ + /* ina230@45 - no model */ + + /* &i2c6 */ + /* io_expander3 - pca9555@21 */ + i2c_slave_create_simple(i2c[6], TYPE_PCA9552, 0x21); + /* rtc@6f - nct3018y */ + i2c_slave_create_simple(i2c[6], TYPE_DS1338, 0x6f); + + /* &i2c9 */ + /* io_expander4 - pca9555@4f */ + i2c_slave_create_simple(i2c[9], TYPE_PCA9552, 0x4f); + /* temperature-sensor@4b - tpm75 */ + i2c_slave_create_simple(i2c[9], TYPE_TMP75, 0x4b); + /* eeprom@50 */ + at24c_eeprom_init(i2c[9], 0x50, 8 * KiB); + /* eeprom@56 */ + at24c_eeprom_init(i2c[9], 0x56, 8 * KiB); + + /* &i2c10 */ + /* temperature-sensor@1f - tpm421 */ + i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x1f); + /* eeprom@50 */ + at24c_eeprom_init(i2c[10], 0x50, 8 * KiB); + + /* &i2c11 */ + /* ssif-bmc@10 - no model */ + + /* &i2c12 */ + /* eeprom@50 */ + at24c_eeprom_init(i2c[12], 0x50, 8 * KiB); + + /* &i2c13 */ + /* eeprom@50 */ + at24c_eeprom_init(i2c[13], 0x50, 8 * KiB); + /* eeprom@54 */ + at24c_eeprom_init(i2c[13], 0x54, 256); + /* eeprom@55 */ + at24c_eeprom_init(i2c[13], 0x55, 256); + /* eeprom@57 */ + at24c_eeprom_init(i2c[13], 0x57, 256); + + /* &i2c14 */ + /* io_expander9 - pca9555@10 */ + i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x10); + /* io_expander10 - pca9555@11 */ + i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x11); + /* io_expander11 - pca9555@12 */ + i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x12); + /* io_expander12 - pca9555@13 */ + i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x13); + /* io_expander13 - pca9555@14 */ + i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x14); + /* io_expander14 - pca9555@15 */ + i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x15); + + /* &i2c15 */ + /* temperature-sensor@1f - tmp421 */ + i2c_slave_create_simple(i2c[15], TYPE_TMP421, 0x1f); + /* eeprom@52 */ + at24c_eeprom_init(i2c[15], 0x52, 8 * KiB); +} static void bletchley_bmc_i2c_init(AspeedMachineState *bmc) { @@ -XXX,XX +XXX,XX @@ static void aspeed_machine_bletchley_class_init(ObjectClass *oc, aspeed_machine_class_init_cpus_defaults(mc); } +static void aspeed_machine_catalina_class_init(ObjectClass *oc, + const void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); + + mc->desc = "Facebook Catalina BMC (Cortex-A7)"; + amc->soc_name = "ast2600-a3"; + amc->hw_strap1 = CATALINA_BMC_HW_STRAP1; + amc->hw_strap2 = CATALINA_BMC_HW_STRAP2; + amc->fmc_model = "w25q01jvq"; + amc->spi_model = NULL; + amc->num_cs = 2; + amc->macs_mask = ASPEED_MAC2_ON; + amc->i2c_init = catalina_bmc_i2c_init; + mc->auto_create_sdcard = true; + mc->default_ram_size = CATALINA_BMC_RAM_SIZE; + aspeed_machine_class_init_cpus_defaults(mc); + aspeed_machine_ast2600_class_emmc_init(oc); +} + static void fby35_reset(MachineState *state, ResetType type) { AspeedMachineState *bmc = ASPEED_MACHINE(state); @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_machine_types[] = { .name = MACHINE_TYPE_NAME("bletchley-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_bletchley_class_init, + }, { + .name = MACHINE_TYPE_NAME("catalina-bmc"), + .parent = TYPE_ASPEED_MACHINE, + .class_init = aspeed_machine_catalina_class_init, }, { .name = MACHINE_TYPE_NAME("fby35-bmc"), .parent = MACHINE_TYPE_NAME("ast2600-evb"), diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -XXX,XX +XXX,XX @@ config ASPEED_SOC select I2C select DPS310 select PCA9552 + select PCA9554 select SERIAL_MM select SMBUS_EEPROM select PCA954X diff --git a/tests/functional/meson.build b/tests/functional/meson.build index XXXXXXX..XXXXXXX 100644 --- a/tests/functional/meson.build +++ b/tests/functional/meson.build @@ -XXX,XX +XXX,XX @@ test_timeouts = { 'arm_aspeed_ast2500' : 720, 'arm_aspeed_ast2600' : 1200, 'arm_aspeed_bletchley' : 480, + 'arm_aspeed_catalina' : 480, 'arm_aspeed_rainier' : 480, 'arm_bpim2u' : 500, 'arm_collie' : 180, @@ -XXX,XX +XXX,XX @@ tests_arm_system_thorough = [ 'arm_aspeed_ast2500', 'arm_aspeed_ast2600', 'arm_aspeed_bletchley', + 'arm_aspeed_catalina', 'arm_aspeed_rainier', 'arm_bpim2u', 'arm_canona1100', diff --git a/tests/functional/test_arm_aspeed_catalina.py b/tests/functional/test_arm_aspeed_catalina.py new file mode 100755 index XXXXXXX..XXXXXXX --- /dev/null +++ b/tests/functional/test_arm_aspeed_catalina.py @@ -XXX,XX +XXX,XX @@ +#!/usr/bin/env python3 +# +# Functional test that boots the ASPEED machines +# +# SPDX-License-Identifier: GPL-2.0-or-later + +from qemu_test import Asset +from aspeed import AspeedTest + + +class CatalinaMachine(AspeedTest): + + ASSET_CATALINA_FLASH = Asset( + 'https://github.com/legoater/qemu-aspeed-boot/raw/a866feb5ef81245b4827a214584bf6bcc72939f6/images/catalina-bmc/obmc-phosphor-image-catalina-20250619123021.static.mtd.xz', + '287402e1ba021991e06be1d098f509444a02a3d81a73a932f66528b159e864f9') + + def test_arm_ast2600_catalina_openbmc(self): + image_path = self.uncompress(self.ASSET_CATALINA_FLASH) + + self.do_test_arm_aspeed_openbmc('catalina-bmc', image=image_path, + uboot='2019.04', cpu_id='0xf00', + soc='AST2600 rev A3') + +if __name__ == '__main__': + AspeedTest.main() -- 2.50.0 From: Tan Siewert <tan@siewert.io> The AST2600 SCU has two protection key registers (0x00 and 0x10) that both need to be unlocked. (Un-)locking 0x00 modifies both protection key registers, while modifying 0x10 only modifies itself. This commit updates the SCU write logic to reject writes unless both protection key registers are unlocked, matching the behaviour of real hardware. Signed-off-by: Tan Siewert <tan@siewert.io> Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Link: https://lore.kernel.org/qemu-devel/20250619085329.42125-1-tan@siewert.io Signed-off-by: Cédric Le Goater <clg@redhat.com> --- hw/misc/aspeed_scu.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index XXXXXXX..XXXXXXX 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -XXX,XX +XXX,XX @@ #define BMC_DEV_ID TO_REG(0x1A4) #define AST2600_PROT_KEY TO_REG(0x00) +#define AST2600_PROT_KEY2 TO_REG(0x10) #define AST2600_SILICON_REV TO_REG(0x04) #define AST2600_SILICON_REV2 TO_REG(0x14) #define AST2600_SYS_RST_CTRL TO_REG(0x40) @@ -XXX,XX +XXX,XX @@ static void aspeed_ast2600_scu_write(void *opaque, hwaddr offset, int reg = TO_REG(offset); /* Truncate here so bitwise operations below behave as expected */ uint32_t data = data64; + bool prot_data_state = data == ASPEED_SCU_PROT_KEY; + bool unlocked = s->regs[AST2600_PROT_KEY] && s->regs[AST2600_PROT_KEY2]; if (reg >= ASPEED_AST2600_SCU_NR_REGS) { qemu_log_mask(LOG_GUEST_ERROR, @@ -XXX,XX +XXX,XX @@ static void aspeed_ast2600_scu_write(void *opaque, hwaddr offset, return; } - if (reg > PROT_KEY && !s->regs[PROT_KEY]) { + if ((reg != AST2600_PROT_KEY && reg != AST2600_PROT_KEY2) && !unlocked) { qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__); + return; } trace_aspeed_scu_write(offset, size, data); switch (reg) { case AST2600_PROT_KEY: - s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0; + /* + * Writing a value to SCU000 will modify both protection + * registers to each protection register individually. + */ + s->regs[AST2600_PROT_KEY] = prot_data_state; + s->regs[AST2600_PROT_KEY2] = prot_data_state; + return; + case AST2600_PROT_KEY2: + s->regs[AST2600_PROT_KEY2] = prot_data_state; return; case AST2600_HW_STRAP1: case AST2600_HW_STRAP2: -- 2.50.0 From: Tan Siewert <tan@siewert.io> This adds basic tests for the ASPEED System Control Unit (SCU) and its protection mechanism on the AST2500 and AST2600 platforms. The tests verify: - That SCU protection registers can be unlocked and locked again - That modifying the primary protection register on AST2600 also affects the secondary one - That writes to protected SCU registers are blocked unless protection registers are unlocked explicitly These tests ensure proper emulation of hardware locking behaviour and help catch regressions in SCU access logic. Signed-off-by: Tan Siewert <tan@siewert.io> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250630112646.74944-1-tan@siewert.io [ clg: Reordered file list in meson.build ] Signed-off-by: Cédric Le Goater <clg@redhat.com> --- tests/qtest/aspeed_scu-test.c | 231 ++++++++++++++++++++++++++++++++++ tests/qtest/meson.build | 1 + 2 files changed, 232 insertions(+) create mode 100644 tests/qtest/aspeed_scu-test.c diff --git a/tests/qtest/aspeed_scu-test.c b/tests/qtest/aspeed_scu-test.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/tests/qtest/aspeed_scu-test.c @@ -XXX,XX +XXX,XX @@ +/* + * QTest testcase for the ASPEED AST2500 and AST2600 SCU. + * + * SPDX-License-Identifier: GPL-2.0-or-later + * Copyright (C) 2025 Tan Siewert + */ + +#include "qemu/osdep.h" +#include "libqtest-single.h" + +/* + * SCU base, as well as protection key are + * the same on AST2500 and 2600. + */ +#define AST_SCU_BASE 0x1E6E2000 +#define AST_SCU_PROT_LOCK_STATE 0x0 +#define AST_SCU_PROT_LOCK_VALUE 0x2 +#define AST_SCU_PROT_UNLOCK_STATE 0x1 +#define AST_SCU_PROT_UNLOCK_VALUE 0x1688A8A8 + +#define AST2500_MACHINE "-machine ast2500-evb" +#define AST2500_SCU_PROT_REG 0x00 +#define AST2500_SCU_MISC_2_CONTROL_REG 0x4C + +#define AST2600_MACHINE "-machine ast2600-evb" +/* AST2600 has two protection registers */ +#define AST2600_SCU_PROT_REG 0x000 +#define AST2600_SCU_PROT_REG2 0x010 +#define AST2600_SCU_MISC_2_CONTROL_REG 0x0C4 + +#define TEST_LOCK_ARBITRARY_VALUE 0xABCDEFAB + +/** + * Assert that a given register matches an expected value. + * + * Reads the register and checks if its value equals the expected value. + * + * @param *s - QTest machine state + * @param reg - Address of the register to be checked + * @param expected - Expected register value + */ +static inline void assert_register_eq(QTestState *s, + uint32_t reg, + uint32_t expected) +{ + uint32_t value = qtest_readl(s, reg); + g_assert_cmphex(value, ==, expected); +} + +/** + * Assert that a given register does not match a specific value. + * + * Reads the register and checks that its value is not equal to the + * provided value. + * + * @param *s - QTest machine state + * @param reg - Address of the register to be checked + * @param not_expected - Value the register must not contain + */ +static inline void assert_register_neq(QTestState *s, + uint32_t reg, + uint32_t not_expected) +{ + uint32_t value = qtest_readl(s, reg); + g_assert_cmphex(value, !=, not_expected); +} + +/** + * Test whether the SCU can be locked and unlocked correctly. + * + * When testing multiple registers, this function assumes that writing + * to the first register also affects the others. However, writing to + * any other register only affects itself. + * + * @param *machine - input machine configuration, passed directly + * to QTest + * @param regs[] - List of registers to be checked + * @param regc - amount of arguments for registers to be checked + */ +static void test_protection_register(const char *machine, + const uint32_t regs[], + const int regc) +{ + QTestState *s = qtest_init(machine); + + for (int i = 0; i < regc; i++) { + uint32_t reg = regs[i]; + + qtest_writel(s, reg, AST_SCU_PROT_UNLOCK_VALUE); + assert_register_eq(s, reg, AST_SCU_PROT_UNLOCK_STATE); + + /** + * Check that other registers are unlocked too, if more + * than one is available. + */ + if (regc > 1 && i == 0) { + /* Initialise at 1 instead of 0 to skip first */ + for (int j = 1; j < regc; j++) { + uint32_t add_reg = regs[j]; + assert_register_eq(s, add_reg, AST_SCU_PROT_UNLOCK_STATE); + } + } + + /* Lock the register again */ + qtest_writel(s, reg, AST_SCU_PROT_LOCK_VALUE); + assert_register_eq(s, reg, AST_SCU_PROT_LOCK_STATE); + + /* And the same for locked state */ + if (regc > 1 && i == 0) { + /* Initialise at 1 instead of 0 to skip first */ + for (int j = 1; j < regc; j++) { + uint32_t add_reg = regs[j]; + assert_register_eq(s, add_reg, AST_SCU_PROT_LOCK_STATE); + } + } + } + + qtest_quit(s); +} + +static void test_2500_protection_register(void) +{ + uint32_t regs[] = { AST_SCU_BASE + AST2500_SCU_PROT_REG }; + + test_protection_register(AST2500_MACHINE, + regs, + ARRAY_SIZE(regs)); +} + +static void test_2600_protection_register(void) +{ + /** + * The AST2600 has two protection registers, both + * being required to be unlocked to do any operation. + * + * Modifying SCU000 also modifies SCU010, but modifying + * SCU010 only will keep SCU000 untouched. + */ + uint32_t regs[] = { AST_SCU_BASE + AST2600_SCU_PROT_REG, + AST_SCU_BASE + AST2600_SCU_PROT_REG2 }; + + test_protection_register(AST2600_MACHINE, + regs, + ARRAY_SIZE(regs)); +} + +/** + * Test if SCU register writes are correctly allowed or blocked + * depending on the protection register state. + * + * The test first locks the protection register and verifies that + * writes to the target SCU register are rejected. It then unlocks + * the protection register and confirms that the written value is + * retained when unlocked. + * + * @param *machine - input machine configuration, passed directly + * to QTest + * @param protection_register - first SCU protection key register + * (only one for keeping it simple) + * @param test_register - Register to be used for writing arbitrary + * values + */ +static void test_write_permission_lock_state(const char *machine, + const uint32_t protection_register, + const uint32_t test_register) +{ + QTestState *s = qtest_init(machine); + + /* Arbitrary value to lock provided SCU protection register */ + qtest_writel(s, protection_register, AST_SCU_PROT_LOCK_VALUE); + + /* Ensure that the SCU is really locked */ + assert_register_eq(s, protection_register, AST_SCU_PROT_LOCK_STATE); + + /* Write a known arbitrary value to test that the write is blocked */ + qtest_writel(s, test_register, TEST_LOCK_ARBITRARY_VALUE); + + /* We do not want to have the written value to be saved */ + assert_register_neq(s, test_register, TEST_LOCK_ARBITRARY_VALUE); + + /** + * Unlock the SCU and verify that it can be written to. + * Assumes that the first SCU protection register is sufficient to + * unlock all protection registers, if multiple are present. + */ + qtest_writel(s, protection_register, AST_SCU_PROT_UNLOCK_VALUE); + assert_register_eq(s, protection_register, AST_SCU_PROT_UNLOCK_STATE); + + /* Write a known arbitrary value to test that the write works */ + qtest_writel(s, test_register, TEST_LOCK_ARBITRARY_VALUE); + + /* Ensure that the written value is retained */ + assert_register_eq(s, test_register, TEST_LOCK_ARBITRARY_VALUE); + + qtest_quit(s); +} + +static void test_2500_write_permission_lock_state(void) +{ + test_write_permission_lock_state( + AST2500_MACHINE, + AST_SCU_BASE + AST2500_SCU_PROT_REG, + AST_SCU_BASE + AST2500_SCU_MISC_2_CONTROL_REG + ); +} + +static void test_2600_write_permission_lock_state(void) +{ + test_write_permission_lock_state( + AST2600_MACHINE, + AST_SCU_BASE + AST2600_SCU_PROT_REG, + AST_SCU_BASE + AST2600_SCU_MISC_2_CONTROL_REG + ); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + qtest_add_func("/ast2500/scu/protection_register", + test_2500_protection_register); + qtest_add_func("/ast2600/scu/protection_register", + test_2600_protection_register); + + qtest_add_func("/ast2500/scu/write_permission_lock_state", + test_2500_write_permission_lock_state); + qtest_add_func("/ast2600/scu/write_permission_lock_state", + test_2600_write_permission_lock_state); + + return g_test_run(); +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index XXXXXXX..XXXXXXX 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -XXX,XX +XXX,XX @@ qtests_npcm8xx = \ qtests_aspeed = \ ['aspeed_gpio-test', 'aspeed_hace-test', + 'aspeed_scu-test', 'aspeed_smc-test'] qtests_aspeed64 = \ ['ast2700-gpio-test', -- 2.50.0 From: Jamin Lin <jamin_lin@aspeedtech.com> The ast2700a0-evb machine represents the first revision of the AST2700 and serves as the initial engineering sample rather than a production version. A newer revision, A1, is now supported, and the ast2700a1-evb should replace the older A0 version. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250703052400.2927831-1-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- docs/about/deprecated.rst | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index XXXXXXX..XXXXXXX 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -XXX,XX +XXX,XX @@ deprecated; use the new name ``dtb-randomness`` instead. The new name better reflects the way this property affects all random data within the device tree blob, not just the ``kaslr-seed`` node. +Arm ``ast2700a0-evb`` machine (since 10.1) +'''''''''''''''''''''''''''''''''''''''''' + +The ``ast2700a0-evb`` machine represents the first revision of the AST2700 +and serves as the initial engineering sample rather than a production version. +A newer revision, A1, is now supported, and the ``ast2700a1-evb`` should +replace the older A0 version. + Mips ``mipssim`` machine (since 10.0) ''''''''''''''''''''''''''''''''''''' -- 2.50.0 From: Ed Tanous <etanous@nvidia.com> Aspeed2600 has two spi lanes; Add a new struct that can mount the second SPI. Signed-off-by: Ed Tanous <etanous@nvidia.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250703144249.3348879-2-etanous@nvidia.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- include/hw/arm/aspeed.h | 2 ++ hw/arm/aspeed.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/aspeed.h +++ b/include/hw/arm/aspeed.h @@ -XXX,XX +XXX,XX @@ struct AspeedMachineClass { uint32_t hw_strap2; const char *fmc_model; const char *spi_model; + const char *spi2_model; uint32_t num_cs; + uint32_t num_cs2; uint32_t macs_mask; void (*i2c_init)(AspeedMachineState *bmc); uint32_t uart_default; diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine) aspeed_board_init_flashes(&bmc->soc->spi[0], bmc->spi_model ? bmc->spi_model : amc->spi_model, 1, amc->num_cs); + aspeed_board_init_flashes(&bmc->soc->spi[1], + amc->spi2_model, 1, amc->num_cs2); } if (machine->kernel_filename && sc->num_cpus > 1) { -- 2.50.0 From: Ed Tanous <etanous@nvidia.com> This patch updates the docs for support of gb200-bmc. Signed-off-by: Ed Tanous <etanous@nvidia.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250703144249.3348879-3-etanous@nvidia.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- docs/system/arm/aspeed.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index XXXXXXX..XXXXXXX 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -XXX,XX +XXX,XX @@ -Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``supermicrox11-bmc``, ``supermicrox11spi-bmc``, ``tiogapass-bmc``, ``witherspoon-bmc``, ``yosemitev2-bmc``) -================================================================================================================================================================================================================================================================================================================================================================================================================================= +Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``gb200nvl-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``supermicrox11-bmc``, ``supermicrox11spi-bmc``, ``tiogapass-bmc``, ``witherspoon-bmc``, ``yosemitev2-bmc``) The QEMU Aspeed machines model BMCs of various OpenPOWER systems and Aspeed evaluation boards. They are based on different releases of the @@ -XXX,XX +XXX,XX @@ AST2600 SoC based machines : - ``fuji-bmc`` Facebook Fuji BMC - ``bletchley-bmc`` Facebook Bletchley BMC - ``fby35-bmc`` Facebook fby35 BMC +- ``gb200nvl-bmc`` Nvidia GB200nvl BMC - ``qcom-dc-scm-v1-bmc`` Qualcomm DC-SCM V1 BMC - ``qcom-firework-bmc`` Qualcomm Firework BMC -- 2.50.0 From: Ed Tanous <etanous@nvidia.com> GB200nvl72 is a system for for accelerated compute. This is a model for the BMC target within the system. This is based on the device tree aspeed-bmc-nvidia-gb200nvl-bmc.dts from: [1] https://github.com/openbmc/linux/blob/dev-6.6/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts Signed-off-by: Ed Tanous <etanous@nvidia.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250703144249.3348879-4-etanous@nvidia.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- hw/arm/aspeed_eeprom.h | 3 ++ hw/arm/aspeed.c | 78 ++++++++++++++++++++++++++++++++++++++++++ hw/arm/aspeed_eeprom.c | 21 ++++++++++++ 3 files changed, 102 insertions(+) diff --git a/hw/arm/aspeed_eeprom.h b/hw/arm/aspeed_eeprom.h index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/aspeed_eeprom.h +++ b/hw/arm/aspeed_eeprom.h @@ -XXX,XX +XXX,XX @@ extern const size_t rainier_bb_fruid_len; extern const uint8_t rainier_bmc_fruid[]; extern const size_t rainier_bmc_fruid_len; +extern const uint8_t gb200nvl_bmc_fruid[]; +extern const size_t gb200nvl_bmc_fruid_len; + #endif diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -XXX,XX +XXX,XX @@ struct AspeedMachineState { #define BLETCHLEY_BMC_HW_STRAP1 0x00002000 #define BLETCHLEY_BMC_HW_STRAP2 0x00000801 +/* GB200NVL hardware value */ +#define GB200NVL_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1 +#define GB200NVL_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2 + /* Qualcomm DC-SCM hardware value */ #define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000 #define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041 @@ -XXX,XX +XXX,XX @@ static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr) TYPE_PCA9552, addr); } +static I2CSlave *create_pca9554(AspeedSoCState *soc, int bus_id, int addr) +{ + return i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id), + TYPE_PCA9554, addr); +} + static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) { AspeedSoCState *soc = bmc->soc; @@ -XXX,XX +XXX,XX @@ static void bletchley_bmc_i2c_init(AspeedMachineState *bmc) i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67); } + +static void gb200nvl_bmc_i2c_init(AspeedMachineState *bmc) +{ + AspeedSoCState *soc = bmc->soc; + I2CBus *i2c[15] = {}; + DeviceState *dev; + for (int i = 0; i < sizeof(i2c) / sizeof(i2c[0]); i++) { + if ((i == 11) || (i == 12) || (i == 13)) { + continue; + } + i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); + } + + /* Bus 5 Expander */ + create_pca9554(soc, 4, 0x21); + + /* Mux I2c Expanders */ + i2c_slave_create_simple(i2c[5], "pca9546", 0x71); + i2c_slave_create_simple(i2c[5], "pca9546", 0x72); + i2c_slave_create_simple(i2c[5], "pca9546", 0x73); + i2c_slave_create_simple(i2c[5], "pca9546", 0x75); + i2c_slave_create_simple(i2c[5], "pca9546", 0x76); + i2c_slave_create_simple(i2c[5], "pca9546", 0x77); + + /* Bus 10 */ + dev = DEVICE(create_pca9554(soc, 9, 0x20)); + + /* Set FPGA_READY */ + object_property_set_str(OBJECT(dev), "pin1", "high", &error_fatal); + + create_pca9554(soc, 9, 0x21); + at24c_eeprom_init(i2c[9], 0x50, 64 * KiB); + at24c_eeprom_init(i2c[9], 0x51, 64 * KiB); + + /* Bus 11 */ + at24c_eeprom_init_rom(i2c[10], 0x50, 256, gb200nvl_bmc_fruid, + gb200nvl_bmc_fruid_len); +} + static void fby35_i2c_init(AspeedMachineState *bmc) { AspeedSoCState *soc = bmc->soc; @@ -XXX,XX +XXX,XX @@ static void aspeed_machine_catalina_class_init(ObjectClass *oc, aspeed_machine_ast2600_class_emmc_init(oc); } +#define GB200NVL_BMC_RAM_SIZE ASPEED_RAM_SIZE(1 * GiB) + +static void aspeed_machine_gb200nvl_class_init(ObjectClass *oc, + const void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); + + mc->desc = "Nvidia GB200NVL BMC (Cortex-A7)"; + amc->soc_name = "ast2600-a3"; + amc->hw_strap1 = GB200NVL_BMC_HW_STRAP1; + amc->hw_strap2 = GB200NVL_BMC_HW_STRAP2; + amc->fmc_model = "mx66u51235f"; + amc->spi_model = "mx66u51235f"; + amc->num_cs = 2; + + amc->spi2_model = "mx66u51235f"; + amc->num_cs2 = 1; + amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; + amc->i2c_init = gb200nvl_bmc_i2c_init; + mc->default_ram_size = GB200NVL_BMC_RAM_SIZE; + aspeed_machine_class_init_cpus_defaults(mc); + aspeed_machine_ast2600_class_emmc_init(oc); +} + static void fby35_reset(MachineState *state, ResetType type) { AspeedMachineState *bmc = ASPEED_MACHINE(state); @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_machine_types[] = { .name = MACHINE_TYPE_NAME("bletchley-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_bletchley_class_init, + }, { + .name = MACHINE_TYPE_NAME("gb200nvl-bmc"), + .parent = TYPE_ASPEED_MACHINE, + .class_init = aspeed_machine_gb200nvl_class_init, }, { .name = MACHINE_TYPE_NAME("catalina-bmc"), .parent = TYPE_ASPEED_MACHINE, diff --git a/hw/arm/aspeed_eeprom.c b/hw/arm/aspeed_eeprom.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/aspeed_eeprom.c +++ b/hw/arm/aspeed_eeprom.c @@ -XXX,XX +XXX,XX @@ const uint8_t rainier_bmc_fruid[] = { 0x31, 0x50, 0x46, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, }; +const uint8_t gb200nvl_bmc_fruid[] = { + 0x01, 0x00, 0x00, 0x01, 0x0b, 0x00, 0x00, 0xf3, 0x01, 0x0a, 0x19, 0x1f, + 0x0f, 0xe6, 0xc6, 0x4e, 0x56, 0x49, 0x44, 0x49, 0x41, 0xc5, 0x50, 0x33, + 0x38, 0x30, 0x39, 0xcd, 0x31, 0x35, 0x38, 0x33, 0x33, 0x32, 0x34, 0x38, + 0x30, 0x30, 0x31, 0x35, 0x30, 0xd2, 0x36, 0x39, 0x39, 0x2d, 0x31, 0x33, + 0x38, 0x30, 0x39, 0x2d, 0x30, 0x34, 0x30, 0x34, 0x2d, 0x36, 0x30, 0x30, + 0xc0, 0x01, 0x01, 0xd6, 0x4d, 0x41, 0x43, 0x3a, 0x20, 0x33, 0x43, 0x3a, + 0x36, 0x44, 0x3a, 0x36, 0x36, 0x3a, 0x31, 0x34, 0x3a, 0x43, 0x38, 0x3a, + 0x37, 0x41, 0xc1, 0x3b, 0x01, 0x09, 0x19, 0xc6, 0x4e, 0x56, 0x49, 0x44, + 0x49, 0x41, 0xc9, 0x50, 0x33, 0x38, 0x30, 0x39, 0x2d, 0x42, 0x4d, 0x43, + 0xd2, 0x36, 0x39, 0x39, 0x2d, 0x31, 0x33, 0x38, 0x30, 0x39, 0x2d, 0x30, + 0x34, 0x30, 0x34, 0x2d, 0x36, 0x30, 0x30, 0xc4, 0x41, 0x45, 0x2e, 0x31, + 0xcd, 0x31, 0x35, 0x38, 0x33, 0x33, 0x32, 0x34, 0x38, 0x30, 0x30, 0x31, + 0x35, 0x30, 0xc0, 0xc4, 0x76, 0x30, 0x2e, 0x31, 0xc1, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xb4, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + +}; + const size_t tiogapass_bmc_fruid_len = sizeof(tiogapass_bmc_fruid); const size_t fby35_nic_fruid_len = sizeof(fby35_nic_fruid); const size_t fby35_bb_fruid_len = sizeof(fby35_bb_fruid); @@ -XXX,XX +XXX,XX @@ const size_t fby35_bmc_fruid_len = sizeof(fby35_bmc_fruid); const size_t yosemitev2_bmc_fruid_len = sizeof(yosemitev2_bmc_fruid); const size_t rainier_bb_fruid_len = sizeof(rainier_bb_fruid); const size_t rainier_bmc_fruid_len = sizeof(rainier_bmc_fruid); +const size_t gb200nvl_bmc_fruid_len = sizeof(gb200nvl_bmc_fruid); + -- 2.50.0 From: Ed Tanous <etanous@nvidia.com> To support the newly added gb200 machine, add appropriate tests and extend do_test_arm_aspeed_openbmc() to support the hostname of this new system: "gb200nvl-obmc". Signed-off-by: Ed Tanous <etanous@nvidia.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250703144249.3348879-5-etanous@nvidia.com [ clg: Adjust commit log to document do_test_arm_aspeed_openbmc() change ] Signed-off-by: Cédric Le Goater <clg@redhat.com> --- tests/functional/aspeed.py | 9 +++++-- tests/functional/meson.build | 2 ++ .../test_arm_aspeed_gb200nvl_bmc.py | 26 +++++++++++++++++++ 3 files changed, 35 insertions(+), 2 deletions(-) create mode 100644 tests/functional/test_arm_aspeed_gb200nvl_bmc.py diff --git a/tests/functional/aspeed.py b/tests/functional/aspeed.py index XXXXXXX..XXXXXXX 100644 --- a/tests/functional/aspeed.py +++ b/tests/functional/aspeed.py @@ -XXX,XX +XXX,XX @@ class AspeedTest(LinuxKernelTest): def do_test_arm_aspeed_openbmc(self, machine, image, uboot='2019.04', - cpu_id='0x0', soc='AST2500 rev A1'): - hostname = machine.removesuffix('-bmc') + cpu_id='0x0', soc='AST2500 rev A1', + image_hostname=None): + # Allow for the image hostname to not end in "-bmc" + if image_hostname is not None: + hostname = image_hostname + else: + hostname = machine.removesuffix('-bmc') self.set_machine(machine) self.vm.set_console() diff --git a/tests/functional/meson.build b/tests/functional/meson.build index XXXXXXX..XXXXXXX 100644 --- a/tests/functional/meson.build +++ b/tests/functional/meson.build @@ -XXX,XX +XXX,XX @@ test_timeouts = { 'arm_aspeed_ast2600' : 1200, 'arm_aspeed_bletchley' : 480, 'arm_aspeed_catalina' : 480, + 'arm_aspeed_gb200nvl_bmc' : 480, 'arm_aspeed_rainier' : 480, 'arm_bpim2u' : 500, 'arm_collie' : 180, @@ -XXX,XX +XXX,XX @@ tests_arm_system_thorough = [ 'arm_aspeed_ast2600', 'arm_aspeed_bletchley', 'arm_aspeed_catalina', + 'arm_aspeed_gb200nvl_bmc', 'arm_aspeed_rainier', 'arm_bpim2u', 'arm_canona1100', diff --git a/tests/functional/test_arm_aspeed_gb200nvl_bmc.py b/tests/functional/test_arm_aspeed_gb200nvl_bmc.py new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/tests/functional/test_arm_aspeed_gb200nvl_bmc.py @@ -XXX,XX +XXX,XX @@ +#!/usr/bin/env python3 +# +# Functional test that boots the ASPEED machines +# +# SPDX-License-Identifier: GPL-2.0-or-later + +from qemu_test import Asset +from aspeed import AspeedTest + + +class GB200Machine(AspeedTest): + + ASSET_GB200_FLASH = Asset( + 'https://github.com/legoater/qemu-aspeed-boot/raw/refs/heads/master/images/gb200nvl-obmc/obmc-phosphor-image-gb200nvl-obmc-20250702182348.static.mtd.xz', + 'b84819317cb3dc762895ad507705978ef000bfc77c50c33a63bdd37921db0dbc') + + def test_arm_aspeed_gb200_openbmc(self): + image_path = self.uncompress(self.ASSET_GB200_FLASH) + + self.do_test_arm_aspeed_openbmc('gb200nvl-bmc', image=image_path, + uboot='2019.04', cpu_id='0xf00', + soc='AST2600 rev A3', + image_hostname='gb200nvl-obmc') + +if __name__ == '__main__': + AspeedTest.main() -- 2.50.0 The following changes since commit ae6e281633769bbc7424523d0ca1163e214571ad: Merge tag 'pull-loongarch-20260302' of https://github.com/gaosong715/qemu into staging (2026-03-05 10:48:38 +0000) are available in the Git repository at: https://github.com/legoater/qemu/ tags/pull-aspeed-20260305 for you to fetch changes up to ee357844b13904a826ffa77834cd08e10ba1e9ba: tests/functional/aarch64/test_aspeed_ast2700fc: Update test ASPEED OpenBMC SDK v11.01 (2026-03-05 18:47:46 +0100) ---------------------------------------------------------------- aspeed queue: * Add I3C support to QEMU, add an dummy I3C device and extend the Aspeed I3C controller * Update test ASPEED OpenBMC SDK v11.01 * Fix DMA64 address handling in Aspeed I2C model (AST2700 SoC) ---------------------------------------------------------------- Cédric Le Goater (1): hw/i3c: Fix array bounds and storage in i3c_addr_is_rsvd() Jamin Lin (37): hw/i2c/aspeed_i2c: Fix DMA64 address handling hw/misc/aspeed_i3c: Move to i3c directory hw/i3c/aspeed_i3c: Switch to DEFINE_TYPES() and align parent_obj naming hw/i3c: Add bus support hw/i3c: Split DesignWare I3C out of Aspeed I3C hw/i3c/dw-i3c: Add more register fields hw/i3c/aspeed_i3c: Add more register fields hw/i3c/dw-i3c: Add more reset values hw/i3c/aspeed_i3c: Add register RO field masks hw/i3c/dw-i3c: Add register RO field masks hw/i3c/dw-i3c: Treat more registers as read-as-zero hw/i3c/dw-i3c: Use 32 bits on MMIO writes hw/i3c/dw-i3c: Add IRQ MMIO behavior hw/i3c/dw-i3c: Add data TX and RX hw/i3c/dw-i3c: Add IBI handling hw/i3c/dw-i3c: Add ctrl MMIO handling hw/i3c/dw-i3c: Add controller resets hw/i3c/aspeed: Add I3C bus get function hw/i3c: Add Mock target hw/arm/aspeed: Build with I3C_DEVICES hw/i3c: Add hotplug support tests/functional/arm/test_aspeed_ast2600_sdk: Add i3c functional test MAINTAINERS: Add I3C maintainers and reviewer hw/i3c/dw-i3c: Use ROUND_UP() for RX buffer allocation alignment hw/i3c/mock-i3c-target: Set num_sent in TX callback to fix trace reporting hw/i3c/core: Initialize num_sent in i3c_send_byte() hw/i3c/mock-i3c-target: Simplify GETMRL byte extraction logic tests/functional/arm/test_aspeed_ast1030: Update test ASPEED Zephyr SDK v03.06 tests/functional/arm/test_aspeed_ast1060: Update test aspeed-zephyr-project v03.05 tests/functional/arm/test_aspeed_ast2500_sdk: Update test ASPEED OpenBMC SDK v11.01 tests/functional/arm/test_aspeed_ast2500_sdk_515: Update test ASPEED OpenBMC SDK v11.01 tests/functional/arm/test_aspeed_ast2600_sdk: Update test ASPEED OpenBMC SDK v11.01 tests/functional/arm/test_aspeed_ast2600_sdk_otp: Update test ASPEED OpenBMC SDK v11.01 tests/functional/arm/test_aspeed_ast2600_sdk_515: Update test ASPEED OpenBMC SDK v11.01 tests/functional/aarch64/test_aspeed_ast2700a1: Update test ASPEED OpenBMC SDK v11.01 tests/functional/aarch64/test_aspeed_ast2700a2: Update test ASPEED OpenBMC SDK v11.01 tests/functional/aarch64/test_aspeed_ast2700fc: Update test ASPEED OpenBMC SDK v11.01 MAINTAINERS | 13 + meson.build | 1 + hw/i3c/trace.h | 2 + include/hw/arm/aspeed_soc.h | 2 +- include/hw/{misc => i3c}/aspeed_i3c.h | 31 +- include/hw/i3c/dw-i3c.h | 199 +++ include/hw/i3c/i3c.h | 277 +++ include/hw/i3c/mock-i3c-target.h | 52 + hw/i2c/aspeed_i2c.c | 4 +- hw/i3c/aspeed_i3c.c | 258 +++ hw/i3c/core.c | 664 +++++++ hw/i3c/dw-i3c.c | 1862 ++++++++++++++++++++ hw/i3c/mock-i3c-target.c | 303 ++++ hw/misc/aspeed_i3c.c | 383 ---- hw/Kconfig | 1 + hw/arm/Kconfig | 3 + hw/i3c/Kconfig | 15 + hw/i3c/meson.build | 6 + hw/i3c/trace-events | 48 + hw/meson.build | 1 + hw/misc/meson.build | 1 - hw/misc/trace-events | 6 - tests/functional/aarch64/test_aspeed_ast2700a1.py | 30 +- tests/functional/aarch64/test_aspeed_ast2700a2.py | 30 +- tests/functional/aarch64/test_aspeed_ast2700fc.py | 18 +- tests/functional/arm/test_aspeed_ast1030.py | 12 +- tests/functional/arm/test_aspeed_ast1060.py | 14 +- tests/functional/arm/test_aspeed_ast2500_sdk.py | 8 +- .../functional/arm/test_aspeed_ast2500_sdk_515.py | 8 +- tests/functional/arm/test_aspeed_ast2600_sdk.py | 22 +- .../functional/arm/test_aspeed_ast2600_sdk_515.py | 10 +- .../functional/arm/test_aspeed_ast2600_sdk_otp.py | 10 +- 32 files changed, 3805 insertions(+), 489 deletions(-) create mode 100644 hw/i3c/trace.h rename include/hw/{misc => i3c}/aspeed_i3c.h (53%) create mode 100644 include/hw/i3c/dw-i3c.h create mode 100644 include/hw/i3c/i3c.h create mode 100644 include/hw/i3c/mock-i3c-target.h create mode 100644 hw/i3c/aspeed_i3c.c create mode 100644 hw/i3c/core.c create mode 100644 hw/i3c/dw-i3c.c create mode 100644 hw/i3c/mock-i3c-target.c delete mode 100644 hw/misc/aspeed_i3c.c create mode 100644 hw/i3c/Kconfig create mode 100644 hw/i3c/meson.build create mode 100644 hw/i3c/trace-events From: Jamin Lin <jamin_lin@aspeedtech.com> The current code updates the upper 32 bits of dma_dram_offset only when aic->has_dma64 is false, which is incorrect. If aic->has_dma64 is true, the controller supports 64-bit DMA addressing and the upper 32-bit DMA address register must be used to update the dma_dram_offset accordingly. Fix the condition so that the upper 32 bits are updated only when 64-bit DMA is supported. Fixes: efea7ddb4689a1ac4bce63a9ddb32887c7f3ac50 ("hw/i2c/aspeed_i2c: Fix DMA moving data into incorrect address") Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260224073207.985162-1-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- hw/i2c/aspeed_i2c.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c index XXXXXXX..XXXXXXX 100644 --- a/hw/i2c/aspeed_i2c.c +++ b/hw/i2c/aspeed_i2c.c @@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_set_tx_dma_dram_offset(AspeedI2CBus *bus) bus->dma_dram_offset = deposit64(bus->dma_dram_offset, 0, 32, FIELD_EX32(value, I2CM_DMA_TX_ADDR, ADDR)); - if (!aic->has_dma64) { + if (aic->has_dma64) { value = bus->regs[R_I2CM_DMA_TX_ADDR_HI]; bus->dma_dram_offset = deposit64(bus->dma_dram_offset, 32, 32, @@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_set_rx_dma_dram_offset(AspeedI2CBus *bus) bus->dma_dram_offset = deposit64(bus->dma_dram_offset, 0, 32, FIELD_EX32(value, I2CM_DMA_RX_ADDR, ADDR)); - if (!aic->has_dma64) { + if (aic->has_dma64) { value = bus->regs[R_I2CM_DMA_RX_ADDR_HI]; bus->dma_dram_offset = deposit64(bus->dma_dram_offset, 32, 32, -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> Moves the Aspeed I3C model and traces into hw/i3c and creates I3C build files. Signed-off-by: Joe Komlodi <komlodi@google.com> Reviewed-by: Patrick Venture <venture@google.com> Reviewed-by: Titus Rwantare <titusr@google.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Tested-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260225021158.1586584-2-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- meson.build | 1 + hw/i3c/trace.h | 2 ++ include/hw/arm/aspeed_soc.h | 2 +- include/hw/{misc => i3c}/aspeed_i3c.h | 0 hw/{misc => i3c}/aspeed_i3c.c | 2 +- hw/Kconfig | 1 + hw/arm/Kconfig | 1 + hw/i3c/Kconfig | 2 ++ hw/i3c/meson.build | 3 +++ hw/i3c/trace-events | 7 +++++++ hw/meson.build | 1 + hw/misc/meson.build | 1 - hw/misc/trace-events | 6 ------ 13 files changed, 20 insertions(+), 9 deletions(-) create mode 100644 hw/i3c/trace.h rename include/hw/{misc => i3c}/aspeed_i3c.h (100%) rename hw/{misc => i3c}/aspeed_i3c.c (99%) create mode 100644 hw/i3c/Kconfig create mode 100644 hw/i3c/meson.build create mode 100644 hw/i3c/trace-events diff --git a/meson.build b/meson.build index XXXXXXX..XXXXXXX 100644 --- a/meson.build +++ b/meson.build @@ -XXX,XX +XXX,XX @@ if have_system 'hw/fsi', 'hw/hyperv', 'hw/i2c', + 'hw/i3c', 'hw/i386', 'hw/i386/xen', 'hw/i386/kvm', diff --git a/hw/i3c/trace.h b/hw/i3c/trace.h new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/hw/i3c/trace.h @@ -XXX,XX +XXX,XX @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#include "trace/trace-hw_i3c.h" diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -XXX,XX +XXX,XX @@ #include "hw/timer/aspeed_timer.h" #include "hw/rtc/aspeed_rtc.h" #include "hw/i2c/aspeed_i2c.h" -#include "hw/misc/aspeed_i3c.h" +#include "hw/i3c/aspeed_i3c.h" #include "hw/ssi/aspeed_smc.h" #include "hw/misc/aspeed_hace.h" #include "hw/misc/aspeed_sbc.h" diff --git a/include/hw/misc/aspeed_i3c.h b/include/hw/i3c/aspeed_i3c.h similarity index 100% rename from include/hw/misc/aspeed_i3c.h rename to include/hw/i3c/aspeed_i3c.h diff --git a/hw/misc/aspeed_i3c.c b/hw/i3c/aspeed_i3c.c similarity index 99% rename from hw/misc/aspeed_i3c.c rename to hw/i3c/aspeed_i3c.c index XXXXXXX..XXXXXXX 100644 --- a/hw/misc/aspeed_i3c.c +++ b/hw/i3c/aspeed_i3c.c @@ -XXX,XX +XXX,XX @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "qemu/error-report.h" -#include "hw/misc/aspeed_i3c.h" +#include "hw/i3c/aspeed_i3c.h" #include "hw/core/registerfields.h" #include "hw/core/qdev-properties.h" #include "qapi/error.h" diff --git a/hw/Kconfig b/hw/Kconfig index XXXXXXX..XXXXXXX 100644 --- a/hw/Kconfig +++ b/hw/Kconfig @@ -XXX,XX +XXX,XX @@ source fsi/Kconfig source gpio/Kconfig source hyperv/Kconfig source i2c/Kconfig +source i3c/Kconfig source ide/Kconfig source input/Kconfig source intc/Kconfig diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -XXX,XX +XXX,XX @@ config ASPEED_SOC select DS1338 select FTGMAC100 select I2C + select I3C select DPS310 select PCA9552 select PCA9554 diff --git a/hw/i3c/Kconfig b/hw/i3c/Kconfig new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/hw/i3c/Kconfig @@ -XXX,XX +XXX,XX @@ +config I3C + bool diff --git a/hw/i3c/meson.build b/hw/i3c/meson.build new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/hw/i3c/meson.build @@ -XXX,XX +XXX,XX @@ +i3c_ss = ss.source_set() +i3c_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_i3c.c')) +system_ss.add_all(when: 'CONFIG_I3C', if_true: i3c_ss) diff --git a/hw/i3c/trace-events b/hw/i3c/trace-events new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/hw/i3c/trace-events @@ -XXX,XX +XXX,XX @@ +# See docs/devel/tracing.rst for syntax documentation. + +# aspeed_i3c.c +aspeed_i3c_read(uint64_t offset, uint64_t data) "I3C read: offset 0x%" PRIx64 " data 0x%" PRIx64 +aspeed_i3c_write(uint64_t offset, uint64_t data) "I3C write: offset 0x%" PRIx64 " data 0x%" PRIx64 +aspeed_i3c_device_read(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] read: offset 0x%" PRIx64 " data 0x%" PRIx64 +aspeed_i3c_device_write(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] write: offset 0x%" PRIx64 " data 0x%" PRIx64 diff --git a/hw/meson.build b/hw/meson.build index XXXXXXX..XXXXXXX 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -XXX,XX +XXX,XX @@ subdir('dma') subdir('gpio') subdir('hyperv') subdir('i2c') +subdir('i3c') subdir('ide') subdir('input') subdir('intc') diff --git a/hw/misc/meson.build b/hw/misc/meson.build index XXXXXXX..XXXXXXX 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_PVPANIC_MMIO', if_true: files('pvpanic-mmio.c')) system_ss.add(when: 'CONFIG_AUX', if_true: files('auxbus.c')) system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed_hace.c', - 'aspeed_i3c.c', 'aspeed_lpc.c', 'aspeed_ltpi.c', 'aspeed_pwm.c', diff --git a/hw/misc/trace-events b/hw/misc/trace-events index XXXXXXX..XXXXXXX 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -XXX,XX +XXX,XX @@ armsse_mhu_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU wri # aspeed_xdma.c aspeed_xdma_write(uint64_t offset, uint64_t data) "XDMA write: offset 0x%" PRIx64 " data 0x%" PRIx64 -# aspeed_i3c.c -aspeed_i3c_read(uint64_t offset, uint64_t data) "I3C read: offset 0x%" PRIx64 " data 0x%" PRIx64 -aspeed_i3c_write(uint64_t offset, uint64_t data) "I3C write: offset 0x%" PRIx64 " data 0x%" PRIx64 -aspeed_i3c_device_read(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] read: offset 0x%" PRIx64 " data 0x%" PRIx64 -aspeed_i3c_device_write(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] write: offset 0x%" PRIx64 " data 0x%" PRIx64 - # aspeed_pwm.c aspeed_pwm_read(uint64_t offset, uint64_t data) "read: offset 0x%" PRIx64 " data 0x%" PRIx64 aspeed_pwm_write(uint64_t offset, uint64_t data) "write: offset 0x%" PRIx64 " data 0x%" PRIx64 -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> Following review feedback, update the Aspeed I3C device to use the DEFINE_TYPES() macro instead of an explicit type registration function. DEFINE_TYPES() is the currently recommended approach in QEMU for registering multiple TypeInfo entries and avoids boilerplate type_init() code. Additionally, rename embedded SysBusDevice fields from "parent" to "parent_obj" to comply with the QEMU coding style guidelines for QOM objects. No functional change. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Tested-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260225021158.1586584-3-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- include/hw/i3c/aspeed_i3c.h | 16 ++++++---------- hw/i3c/aspeed_i3c.c | 35 +++++++++++++++-------------------- 2 files changed, 21 insertions(+), 30 deletions(-) diff --git a/include/hw/i3c/aspeed_i3c.h b/include/hw/i3c/aspeed_i3c.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/i3c/aspeed_i3c.h +++ b/include/hw/i3c/aspeed_i3c.h @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(AspeedI3CState, AspeedI3CClass, ASPEED_I3C) #define ASPEED_I3C_NR_DEVICES 6 OBJECT_DECLARE_SIMPLE_TYPE(AspeedI3CDevice, ASPEED_I3C_DEVICE) -typedef struct AspeedI3CDevice { - /* <private> */ - SysBusDevice parent; +struct AspeedI3CDevice { + SysBusDevice parent_obj; - /* <public> */ MemoryRegion mr; qemu_irq irq; uint8_t id; uint32_t regs[ASPEED_I3C_DEVICE_NR_REGS]; -} AspeedI3CDevice; +}; -typedef struct AspeedI3CState { - /* <private> */ - SysBusDevice parent; +struct AspeedI3CState { + SysBusDevice parent_obj; - /* <public> */ MemoryRegion iomem; MemoryRegion iomem_container; qemu_irq irq; uint32_t regs[ASPEED_I3C_NR_REGS]; AspeedI3CDevice devices[ASPEED_I3C_NR_DEVICES]; -} AspeedI3CState; +}; #endif /* ASPEED_I3C_H */ diff --git a/hw/i3c/aspeed_i3c.c b/hw/i3c/aspeed_i3c.c index XXXXXXX..XXXXXXX 100644 --- a/hw/i3c/aspeed_i3c.c +++ b/hw/i3c/aspeed_i3c.c @@ -XXX,XX +XXX,XX @@ static void aspeed_i3c_device_class_init(ObjectClass *klass, const void *data) device_class_set_props(dc, aspeed_i3c_device_properties); } -static const TypeInfo aspeed_i3c_device_info = { - .name = TYPE_ASPEED_I3C_DEVICE, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(AspeedI3CDevice), - .class_init = aspeed_i3c_device_class_init, -}; - static const VMStateDescription vmstate_aspeed_i3c = { .name = TYPE_ASPEED_I3C, .version_id = 1, @@ -XXX,XX +XXX,XX @@ static void aspeed_i3c_class_init(ObjectClass *klass, const void *data) dc->vmsd = &vmstate_aspeed_i3c; } -static const TypeInfo aspeed_i3c_info = { - .name = TYPE_ASPEED_I3C, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_init = aspeed_i3c_instance_init, - .instance_size = sizeof(AspeedI3CState), - .class_init = aspeed_i3c_class_init, +static const TypeInfo aspeed_i3c_types[] = { + { + .name = TYPE_ASPEED_I3C, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_init = aspeed_i3c_instance_init, + .instance_size = sizeof(AspeedI3CState), + .class_init = aspeed_i3c_class_init, + }, + { + .name = TYPE_ASPEED_I3C_DEVICE, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(AspeedI3CDevice), + .class_init = aspeed_i3c_device_class_init, + }, }; -static void aspeed_i3c_register_types(void) -{ - type_register_static(&aspeed_i3c_device_info); - type_register_static(&aspeed_i3c_info); -} - -type_init(aspeed_i3c_register_types); +DEFINE_TYPES(aspeed_i3c_types) -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> Adds an I3C bus and a target class. The bus supports: - I3C data transmission and reception - CCCs (including ENTDAA) - IBIs - legacy I2C transactions General usage of the bus is similar to I2C. Users are expected to initialize a bus via i3c_init_bus, and use the bus returned from the init function to do transactions on the bus. In order to handle IBIs, the controller provides callbacks to handle receiving an IBI from a target, receiving (optional) additional IBI bytes from a target, and handling when a target is done with its IBI. Similarly, target creation is done via i3c_target_create_simple and users use the provided I3CTarget to handle transactions. The target has functions provided that it can use to invoke an IBI and send additional bytes. Along with the send, recv, and event callbacks that are expected of an I3C target, which are similar to I2C, there is a separate callback for CCC handling. This is to help encapsulate CCC handling and keep it separate from target-specific read/write functionality. To avoid repition for required CCCs among I3C targets, there is some class-level CCC handling added. The CCC is then passed to the target in case it needs to handle it in some way. Signed-off-by: Joe Komlodi <komlodi@google.com> Reviewed-by: Patrick Venture <venture@google.com> Reviewed-by: Titus Rwantare <titusr@google.com> Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Tested-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260225021158.1586584-4-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- include/hw/i3c/i3c.h | 277 ++++++++++++++++++ hw/i3c/core.c | 647 +++++++++++++++++++++++++++++++++++++++++++ hw/i3c/meson.build | 1 + hw/i3c/trace-events | 16 ++ 4 files changed, 941 insertions(+) create mode 100644 include/hw/i3c/i3c.h create mode 100644 hw/i3c/core.c diff --git a/include/hw/i3c/i3c.h b/include/hw/i3c/i3c.h new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/include/hw/i3c/i3c.h @@ -XXX,XX +XXX,XX @@ +/* + * QEMU I3C bus interface. + * + * Copyright 2025 Google LLC + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef QEMU_INCLUDE_HW_I3C_I3C_H_ +#define QEMU_INCLUDE_HW_I3C_I3C_H_ + +#include "hw/core/qdev.h" +#include "qom/object.h" +#include "hw/i2c/i2c.h" + +#define TYPE_I3C_TARGET "i3c-target" +OBJECT_DECLARE_TYPE(I3CTarget, I3CTargetClass, I3C_TARGET) + +typedef enum I3CEvent { + I3C_START_RECV, + I3C_START_SEND, + I3C_STOP, + I3C_NACK, +} I3CEvent; + +typedef enum I3CCCC { + /* Broadcast CCCs */ + I3C_CCC_ENEC = 0x00, + I3C_CCC_DISEC = 0x01, + I3C_CCC_ENTAS0 = 0x02, + I3C_CCC_ENTAS1 = 0x03, + I3C_CCC_ENTAS2 = 0x04, + I3C_CCC_ENTAS3 = 0x05, + I3C_CCC_RSTDAA = 0x06, + I3C_CCC_ENTDAA = 0x07, + I3C_CCC_DEFTGTS = 0x08, + I3C_CCC_SETMWL = 0x09, + I3C_CCC_SETMRL = 0x0a, + I3C_CCC_ENTTM = 0x0b, + I3C_CCC_SETBUSCON = 0x0c, + I3C_CCC_ENDXFER = 0x12, + I3C_CCC_ENTHDR0 = 0x20, + I3C_CCC_ENTHDR1 = 0x21, + I3C_CCC_ENTHDR2 = 0x22, + I3C_CCC_ENTHDR3 = 0x23, + I3C_CCC_ENTHDR4 = 0x24, + I3C_CCC_ENTHDR5 = 0x25, + I3C_CCC_ENTHDR6 = 0x26, + I3C_CCC_ENTHDR7 = 0x27, + I3C_CCC_SETXTIME = 0x28, + I3C_CCC_SETAASA = 0x29, + I3C_CCC_RSTACT = 0x2a, + I3C_CCC_DEFGRPA = 0x2b, + I3C_CCC_RSTGRPA = 0x2c, + I3C_CCC_MLANE = 0x2d, + /* Direct CCCs */ + I3C_CCCD_ENEC = 0x80, + I3C_CCCD_DISEC = 0x81, + I3C_CCCD_ENTAS0 = 0x82, + I3C_CCCD_ENTAS1 = 0x83, + I3C_CCCD_ENTAS2 = 0x84, + I3C_CCCD_ENTAS3 = 0x85, + I3C_CCCD_SETDASA = 0x87, + I3C_CCCD_SETNEWDA = 0x88, + I3C_CCCD_SETMWL = 0x89, + I3C_CCCD_SETMRL = 0x8a, + I3C_CCCD_GETMWL = 0x8b, + I3C_CCCD_GETMRL = 0x8c, + I3C_CCCD_GETPID = 0x8d, + I3C_CCCD_GETBCR = 0x8e, + I3C_CCCD_GETDCR = 0x8f, + I3C_CCCD_GETSTATUS = 0x90, + I3C_CCCD_GETACCCR = 0x91, + I3C_CCCD_ENDXFER = 0x92, + I3C_CCCD_SETBRGTGT = 0x93, + I3C_CCCD_GETMXDS = 0x94, + I3C_CCCD_GETCAPS = 0x95, + I3C_CCCD_SETROUTE = 0x96, + I3C_CCCD_SETXTIME = 0x98, + I3C_CCCD_GETXTIME = 0x99, + I3C_CCCD_RSTACT = 0x9a, + I3C_CCCD_SETGRPA = 0x9b, + I3C_CCCD_RSTGRPA = 0x9c, + I3C_CCCD_MLANE = 0x9d, +} I3CCCC; + +#define CCC_IS_DIRECT(_ccc) (_ccc & 0x80) + +#define I3C_BROADCAST 0x7e +#define I3C_HJ_ADDR 0x02 +#define I3C_ENTDAA_SIZE 8 + +struct I3CTargetClass { + DeviceClass parent_class; + + /* + * Controller to target. Returns 0 for success, non-zero for NAK or other + * error. + */ + int (*send)(I3CTarget *s, const uint8_t *data, uint32_t num_to_send, + uint32_t *num_sent); + /* + * Target to controller. I3C targets are able to terminate reads early, so + * this returns the number of bytes read from the target. + */ + uint32_t (*recv)(I3CTarget *s, uint8_t *data, uint32_t num_to_read); + /* Notify the target of a bus state change. */ + int (*event)(I3CTarget *s, enum I3CEvent event); + /* + * Handle a read CCC transmitted from a controller. + * CCCs are I3C commands that I3C targets support. + * The target can NACK the CCC if it does not support it. + */ + int (*handle_ccc_read)(I3CTarget *s, uint8_t *data, uint32_t num_to_read, + uint32_t *num_read); + /* + * Handle a write CCC transmitted from a controller. + * CCCs are I3C commands that I3C targets support. + * The target can NACK the CCC if it does not support it. + */ + int (*handle_ccc_write)(I3CTarget *s, const uint8_t *data, + uint32_t num_to_send, uint32_t *num_sent); + + /* + * Matches and adds the candidate if the address matches the candidate's + * address. + * Returns true if the address matched, or if this was a broadcast, and + * updates the device list. Otherwise returns false. + */ + bool (*target_match)(I3CTarget *candidate, uint8_t address, bool is_read, + bool broadcast, bool in_entdaa); +}; + +struct I3CTarget { + DeviceState parent_obj; + + uint8_t address; + uint8_t static_address; + uint8_t dcr; + uint8_t bcr; + uint64_t pid; + + /* CCC State tracking. */ + I3CCCC curr_ccc; + uint8_t ccc_byte_offset; + bool in_ccc; + bool in_test_mode; +}; + +struct I3CNode { + I3CTarget *target; + QLIST_ENTRY(I3CNode) next; +}; + +typedef struct I3CNode I3CNode; + +typedef QLIST_HEAD(I3CNodeList, I3CNode) I3CNodeList; + +#define TYPE_I3C_BUS "i3c-bus" +OBJECT_DECLARE_TYPE(I3CBus, I3CBusClass, I3C_BUS) + +struct I3CBus { + BusState parent_obj; + + /* Legacy I2C. */ + I2CBus *i2c_bus; + + I3CNodeList current_devs; + bool broadcast; + uint8_t ccc; + bool in_ccc; + bool in_entdaa; + uint8_t saved_address; +}; + +struct I3CBusClass { + BusClass parent_class; + + /* Handle an incoming IBI request from a target */ + int (*ibi_handle) (I3CBus *bus, uint8_t addr, bool is_recv); + /* Receive data from an IBI request */ + int (*ibi_recv) (I3CBus *bus, uint8_t data); + /* Do anything that needs to be done, since the IBI is finished. */ + int (*ibi_finish) (I3CBus *bus); +}; + +I3CBus *i3c_init_bus(DeviceState *parent, const char *name); +I3CBus *i3c_init_bus_type(const char *type, DeviceState *parent, + const char *name); +void i3c_set_target_address(I3CTarget *dev, uint8_t address); +bool i3c_bus_busy(I3CBus *bus); + +/* + * Start a transfer on an I3C bus. + * If is_recv is known at compile-time (i.e. a device will always be sending or + * will always be receiving at a certain point), prefer to use i3c_start_recv or + * i3c_start_send instead. + * + * Returns 0 on success, non-zero on an error. + */ +int i3c_start_transfer(I3CBus *bus, uint8_t address, bool is_recv); + +/* + * Start a receive transfer on an I3C bus. + * + * Returns 0 on success, non-zero on an error + */ +int i3c_start_recv(I3CBus *bus, uint8_t address); + +/* + * Start a send transfer on an I3C bus. + * + * Returns 0 on success, non-zero on an error + */ +int i3c_start_send(I3CBus *bus, uint8_t address); + +void i3c_end_transfer(I3CBus *bus); +void i3c_nack(I3CBus *bus); +int i3c_send_byte(I3CBus *bus, uint8_t data); +int i3c_send(I3CBus *bus, const uint8_t *data, uint32_t num_to_send, + uint32_t *num_sent); +/* + * I3C receives can only NACK on a CCC. The target should NACK a CCC it does not + * support. + */ +int i3c_recv_byte(I3CBus *bus, uint8_t *data); +int i3c_recv(I3CBus *bus, uint8_t *data, uint32_t num_to_read, + uint32_t *num_read); +bool i3c_scan_bus(I3CBus *bus, uint8_t address, enum I3CEvent event); +int i3c_do_entdaa(I3CBus *bus, uint8_t address, uint64_t *pid, uint8_t *bcr, + uint8_t *dcr); +int i3c_start_device_transfer(I3CTarget *dev, int send_length); +bool i3c_target_match_and_add(I3CBus *bus, I3CTarget *target, uint8_t address, + enum I3CEvent event); +int i3c_target_send_ibi(I3CTarget *t, uint8_t addr, bool is_recv); +int i3c_target_send_ibi_bytes(I3CTarget *t, uint8_t data); +int i3c_target_ibi_finish(I3CTarget *t, uint8_t data); + +/* + * Legacy I2C functions. + * + * These are wrapper for I2C functions that take in an I3C bus instead of an I2C + * bus. Internally they use the I2C bus (and devices attached to it) that's a + * part of the I3C bus + */ +void legacy_i2c_nack(I3CBus *bus); +uint8_t legacy_i2c_recv(I3CBus *bus); +int legacy_i2c_send(I3CBus *bus, uint8_t data); +int legacy_i2c_start_transfer(I3CBus *bus, uint8_t address, bool is_recv); +int legacy_i2c_start_recv(I3CBus *bus, uint8_t address); +int legacy_i2c_start_send(I3CBus *bus, uint8_t address); +void legacy_i2c_end_transfer(I3CBus *bus); +I2CSlave *legacy_i2c_device_create_simple(I3CBus *bus, const char *name, + uint8_t addr); + +/** + * Create an I3C Target. + * + * The target returned from this function still needs to be realized. + */ +I3CTarget *i3c_target_new(const char *name, uint8_t addr, uint8_t dcr, + uint8_t bcr, uint64_t pid); + +/** + * Create and realize an I3C target. + * + * Create the target, initialize it, put it on the specified I3C bus, and + * realize it. + */ +I3CTarget *i3c_target_create_simple(I3CBus *bus, const char *name, + uint8_t addr, uint8_t dcr, uint8_t bcr, + uint64_t pid); + +/* Realize and drop the reference count on an I3C target. */ +bool i3c_target_realize_and_unref(I3CTarget *dev, I3CBus *bus, Error **errp); + +#endif /* QEMU_INCLUDE_HW_I3C_I3C_H_ */ diff --git a/hw/i3c/core.c b/hw/i3c/core.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/hw/i3c/core.c @@ -XXX,XX +XXX,XX @@ +/* + * QEMU I3C bus interface. + * + * Copyright 2025 Google LLC + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "trace.h" +#include "hw/i3c/i3c.h" +#include "hw/core/qdev-properties.h" + +/* + * In test mode (enabled by ENTTM CCC) we're supposed to send a random PID + * during ENTDAA, so we'll just send "QEMU". + */ +#define TEST_MODE_PROVISIONED_ID 0x0000554d4551ULL + +static const Property i3c_props[] = { + DEFINE_PROP_UINT8("static-address", struct I3CTarget, static_address, 0), + DEFINE_PROP_UINT8("dcr", struct I3CTarget, dcr, 0), + DEFINE_PROP_UINT8("bcr", struct I3CTarget, bcr, 0), + DEFINE_PROP_UINT64("pid", struct I3CTarget, pid, 0), +}; + +I3CBus *i3c_init_bus(DeviceState *parent, const char *name) +{ + return i3c_init_bus_type(TYPE_I3C_BUS, parent, name); +} + +I3CBus *i3c_init_bus_type(const char *type, DeviceState *parent, + const char *name) +{ + I3CBus *bus; + + bus = I3C_BUS(qbus_new(type, parent, name)); + QLIST_INIT(&bus->current_devs); + bus->broadcast = false; + bus->in_entdaa = false; + bus->in_ccc = false; + + /* I2C init. */ + g_autofree gchar *i2c_bus_name = g_strdup_printf("%s-legacy-i2c", name); + bus->i2c_bus = i2c_init_bus(parent, i2c_bus_name); + + return bus; +} + +bool i3c_bus_busy(I3CBus *bus) +{ + return !QLIST_EMPTY(&bus->current_devs); +} + +static bool i3c_target_match(I3CTarget *candidate, uint8_t address, + bool is_recv, bool broadcast, bool in_entdaa) +{ + /* Once a target has a dynamic address, it only responds to that. */ + uint8_t targ_addr = candidate->address ? candidate->address : + candidate->static_address; + + if (in_entdaa) { + if (address != I3C_BROADCAST) { + g_autofree char *path = + object_get_canonical_path(OBJECT(candidate)); + qemu_log_mask(LOG_GUEST_ERROR, "%s: I3C Address 0x%.2x sent during " + "ENTDAA instead of a broadcast address\n", + path, address); + return false; + } + + /* + * Targets should only ACK ENTDAA broadcasts if they have no dynamic + * address. + */ + return candidate->address == 0; + } + + /* Return if our addresses match, or if it's a broadcast. */ + return targ_addr == address || broadcast; +} + +bool i3c_target_match_and_add(I3CBus *bus, I3CTarget *target, uint8_t address, + enum I3CEvent event) +{ + I3CTargetClass *tc = I3C_TARGET_GET_CLASS(target); + bool matched = tc->target_match(target, address, event == I3C_START_RECV, + bus->broadcast, bus->in_entdaa); + + if (matched) { + I3CNode *node = g_new(struct I3CNode, 1); + node->target = target; + QLIST_INSERT_HEAD(&bus->current_devs, node, next); + } + return matched; +} + +bool i3c_scan_bus(I3CBus *bus, uint8_t address, enum I3CEvent event) +{ + BusChild *child; + I3CNode *node, *next; + + /* Clear out any devices from a previous (re-)START. */ + QLIST_FOREACH_SAFE(node, &bus->current_devs, next, next) { + QLIST_REMOVE(node, next); + g_free(node); + } + + QTAILQ_FOREACH(child, &bus->parent_obj.children, sibling) { + DeviceState *qdev = child->child; + I3CTarget *target = I3C_TARGET(qdev); + + if (i3c_target_match_and_add(bus, target, address, event)) { + return true; + } + } + + /* No one on the bus could respond. */ + return false; +} + +/* Class-level event handling, since we do some CCCs at the class level. */ +static int i3c_target_event(I3CTarget *t, enum I3CEvent event) +{ + I3CTargetClass *tc = I3C_TARGET_GET_CLASS(t); + trace_i3c_target_event(t->address, event); + + if (event == I3C_STOP) { + t->curr_ccc = 0; + t->ccc_byte_offset = 0; + t->in_ccc = false; + } + return tc->event(t, event); +} + +/* + * Sends a START or repeated START and the address for an I3C transaction. + * + * This function returns 0 if a device on the bus was able to respond to the + * address, and non-zero otherwise. + * A non-zero return represents a NACK. + */ +static int i3c_do_start_transfer(I3CBus *bus, uint8_t address, + enum I3CEvent event) +{ + I3CTargetClass *tc; + I3CNode *node; + + if (address == I3C_BROADCAST) { + bus->broadcast = true; + /* If we're not in ENTDAA, a broadcast is the start of a new CCC. */ + if (!bus->in_entdaa) { + bus->in_ccc = false; + } + } else { + bus->broadcast = false; + } + + /* No one responded to the address, NACK it. */ + if (!i3c_scan_bus(bus, address, event)) { + return -1; + } + + QLIST_FOREACH(node, &bus->current_devs, next) { + I3CTarget *t = node->target; + + tc = I3C_TARGET_GET_CLASS(t); + if (tc->event) { + int rv = i3c_target_event(t, event); + if (rv && !bus->broadcast) { + return rv; + } + } + } + + return 0; +} + +int i3c_start_transfer(I3CBus *bus, uint8_t address, bool is_recv) +{ + trace_i3c_start_transfer(address, is_recv); + return i3c_do_start_transfer(bus, address, is_recv + ? I3C_START_RECV + : I3C_START_SEND); +} + +int i3c_start_recv(I3CBus *bus, uint8_t address) +{ + trace_i3c_start_transfer(address, true); + return i3c_do_start_transfer(bus, address, I3C_START_RECV); +} + +int i3c_start_send(I3CBus *bus, uint8_t address) +{ + trace_i3c_start_transfer(address, false); + return i3c_do_start_transfer(bus, address, I3C_START_SEND); +} + +void i3c_end_transfer(I3CBus *bus) +{ + I3CTargetClass *tc; + I3CNode *node, *next; + + trace_i3c_end_transfer(); + + /* + * If we're in ENTDAA, we need to notify all devices when ENTDAA is done. + * This is because everyone initially participates due to the broadcast, + * but gradually drops out as they get assigned addresses. + * Since the current_devs list only stores who's currently participating, + * and not everyone who previously participated, we send the STOP to all + * children. + */ + if (bus->in_entdaa) { + BusChild *child; + + QTAILQ_FOREACH(child, &bus->parent_obj.children, sibling) { + DeviceState *qdev = child->child; + I3CTarget *t = I3C_TARGET(qdev); + tc = I3C_TARGET_GET_CLASS(t); + if (tc->event) { + i3c_target_event(t, I3C_STOP); + } + } + } else { + QLIST_FOREACH_SAFE(node, &bus->current_devs, next, next) { + I3CTarget *t = node->target; + tc = I3C_TARGET_GET_CLASS(t); + if (tc->event) { + i3c_target_event(t, I3C_STOP); + } + QLIST_REMOVE(node, next); + g_free(node); + } + } + bus->broadcast = false; + bus->in_entdaa = false; + bus->in_ccc = false; +} + +/* + * Any CCCs that are universal across all I3C devices should be handled here. + * Once they're handled, we pass the CCC up to the I3C target to do anything + * else it may want with the bytes. + */ +static int i3c_target_handle_ccc_write(I3CTarget *t, const uint8_t *data, + uint32_t num_to_send, uint32_t *num_sent) +{ + I3CTargetClass *tc = I3C_TARGET_GET_CLASS(t); + *num_sent = 0; + + /* Is this the start of a new CCC? */ + if (!t->in_ccc) { + t->curr_ccc = *data; + t->in_ccc = true; + *num_sent = 1; + trace_i3c_target_handle_ccc(t->address, t->curr_ccc); + } + + switch (t->curr_ccc) { + case I3C_CCC_ENTDAA: + /* + * This is the last byte of ENTDAA, the controller is assigning us an + * address. + */ + if (t->ccc_byte_offset == 8) { + t->address = *data; + t->in_ccc = false; + t->curr_ccc = 0; + t->ccc_byte_offset = 0; + *num_sent = 1; + } + break; + case I3C_CCCD_SETDASA: + t->address = t->static_address; + break; + case I3C_CCC_SETAASA: + t->address = t->static_address; + break; + case I3C_CCC_RSTDAA: + t->address = 0; + break; + case I3C_CCCD_SETNEWDA: + /* If this isn't the CCC byte, it's our new address. */ + if (*num_sent == 0) { + t->address = *data; + *num_sent = 1; + } + break; + case I3C_CCC_ENTTM: + /* + * If there are still more to look at, the next byte is the test mode + * byte. + */ + if (*num_sent != num_to_send) { + /* Enter test mode if the byte is non-zero. Otherwise exit. */ + t->in_test_mode = !!data[*num_sent]; + ++*num_sent; + } + break; + /* Ignore other CCCs it's better to handle on a device-by-device basis. */ + default: + break; + } + return tc->handle_ccc_write(t, data, num_to_send, num_sent); +} + +int i3c_send_byte(I3CBus *bus, uint8_t data) +{ + /* + * Ignored, the caller can determine how many were sent based on if this was + * ACKed/NACKed. + */ + uint32_t num_sent; + return i3c_send(bus, &data, 1, &num_sent); +} + +int i3c_send(I3CBus *bus, const uint8_t *data, uint32_t num_to_send, + uint32_t *num_sent) +{ + I3CTargetClass *tc; + I3CTarget *t; + I3CNode *node; + int ret = 0; + + /* If this message is a broadcast and no CCC has been found, grab it. */ + if (bus->broadcast && !bus->in_ccc) { + bus->ccc = *data; + bus->in_ccc = true; + /* + * We need to keep track if we're currently in ENTDAA. + * On any other CCC, the CCC is over on a RESTART or STOP, but ENTDAA + * is only over on a STOP. + */ + if (bus->ccc == I3C_CCC_ENTDAA) { + bus->in_entdaa = true; + } + } + + QLIST_FOREACH(node, &bus->current_devs, next) { + t = node->target; + tc = I3C_TARGET_GET_CLASS(t); + if (bus->in_ccc) { + if (!tc->handle_ccc_write) { + ret = -1; + continue; + } + ret = i3c_target_handle_ccc_write(t, data, num_to_send, num_sent); + /* Targets should only NACK on a direct CCC. */ + if (ret && !CCC_IS_DIRECT(bus->ccc)) { + ret = 0; + } + } else { + if (tc->send) { + ret = ret || tc->send(t, data, num_to_send, num_sent); + } else { + ret = -1; + } + } + } + + trace_i3c_send(*num_sent, num_to_send, ret == 0); + + return ret ? -1 : 0; +} + +static int i3c_target_handle_ccc_read(I3CTarget *t, uint8_t *data, + uint32_t num_to_read, uint32_t *num_read) +{ + I3CTargetClass *tc = I3C_TARGET_GET_CLASS(t); + uint8_t read_count = 0; + uint64_t pid; + + switch (t->curr_ccc) { + case I3C_CCC_ENTDAA: + if (t->in_test_mode) { + pid = TEST_MODE_PROVISIONED_ID; + } else { + pid = t->pid; + } + /* Return the 6-byte PID, followed by BCR then DCR. */ + while (t->ccc_byte_offset < 6) { + if (read_count >= num_to_read) { + break; + } + data[read_count] = (pid >> (t->ccc_byte_offset * 8)) & 0xff; + t->ccc_byte_offset++; + read_count++; + } + if (read_count < num_to_read) { + data[read_count] = t->bcr; + t->ccc_byte_offset++; + read_count++; + } + if (read_count < num_to_read) { + data[read_count] = t->dcr; + t->ccc_byte_offset++; + read_count++; + } + *num_read = read_count; + break; + case I3C_CCCD_GETPID: + while (t->ccc_byte_offset < 6) { + if (read_count >= num_to_read) { + break; + } + data[read_count] = (t->pid >> (t->ccc_byte_offset * 8)) & 0xff; + t->ccc_byte_offset++; + read_count++; + } + *num_read = read_count; + break; + case I3C_CCCD_GETBCR: + *data = t->bcr; + *num_read = 1; + break; + case I3C_CCCD_GETDCR: + *data = t->dcr; + *num_read = 1; + break; + default: + /* Unhandled on the I3CTarget class level. */ + break; + } + + return tc->handle_ccc_read(t, data, num_to_read, num_read); +} + +int i3c_recv_byte(I3CBus *bus, uint8_t *data) +{ + /* + * Ignored, the caller can determine how many bytes were read based on if + * this is ACKed/NACKed. + */ + uint32_t num_read; + return i3c_recv(bus, data, 1, &num_read); +} + +int i3c_recv(I3CBus *bus, uint8_t *data, uint32_t num_to_read, + uint32_t *num_read) +{ + int ret = 0; + I3CTargetClass *tc; + I3CTarget *t; + + *data = 0xff; + if (!QLIST_EMPTY(&bus->current_devs)) { + tc = I3C_TARGET_GET_CLASS(QLIST_FIRST(&bus->current_devs)->target); + t = QLIST_FIRST(&bus->current_devs)->target; + if (bus->in_ccc) { + if (!tc->handle_ccc_read) { + return -1; + } + ret = i3c_target_handle_ccc_read(t, data, num_to_read, num_read); + } else { + if (tc->recv) { + /* + * Targets cannot NACK on a direct transfer, so the data + * is returned directly. + */ + *num_read = tc->recv(t, data, num_to_read); + } + } + } + + trace_i3c_recv(*num_read, num_to_read, ret == 0); + + return ret; +} + +void i3c_nack(I3CBus *bus) +{ + I3CTargetClass *tc; + I3CNode *node; + + if (QLIST_EMPTY(&bus->current_devs)) { + return; + } + + QLIST_FOREACH(node, &bus->current_devs, next) { + tc = I3C_TARGET_GET_CLASS(node->target); + if (tc->event) { + i3c_target_event(node->target, I3C_NACK); + } + } +} + +int i3c_target_send_ibi(I3CTarget *t, uint8_t addr, bool is_recv) +{ + I3CBus *bus = I3C_BUS(t->parent_obj.parent_bus); + I3CBusClass *bc = I3C_BUS_GET_CLASS(bus); + trace_i3c_target_send_ibi(addr, is_recv); + return bc->ibi_handle(bus, addr, is_recv); +} + +int i3c_target_send_ibi_bytes(I3CTarget *t, uint8_t data) +{ + I3CBus *bus = I3C_BUS(t->parent_obj.parent_bus); + I3CBusClass *bc = I3C_BUS_GET_CLASS(bus); + trace_i3c_target_send_ibi_bytes(data); + return bc->ibi_recv(bus, data); +} + +int i3c_target_ibi_finish(I3CTarget *t, uint8_t data) +{ + I3CBus *bus = I3C_BUS(t->parent_obj.parent_bus); + I3CBusClass *bc = I3C_BUS_GET_CLASS(bus); + trace_i3c_target_ibi_finish(); + return bc->ibi_finish(bus); +} + +static bool i3c_addr_is_rsvd(uint8_t addr) +{ + const bool is_rsvd[255] = { + [0x00] = true, + [0x01] = true, + [0x02] = true, + [0x3e] = true, + [0x5e] = true, + [0x6e] = true, + [0x76] = true, + [0x7a] = true, + [0x7c] = true, + [0x7e] = true, + [0x7f] = true, + }; + + return is_rsvd[addr]; +} + +I3CTarget *i3c_target_new(const char *name, uint8_t addr, uint8_t dcr, + uint8_t bcr, uint64_t pid) +{ + DeviceState *dev; + + dev = qdev_new(name); + qdev_prop_set_uint8(dev, "static-address", addr); + qdev_prop_set_uint8(dev, "dcr", dcr); + qdev_prop_set_uint8(dev, "bcr", bcr); + qdev_prop_set_uint64(dev, "pid", pid); + + if (i3c_addr_is_rsvd(addr)) { + g_autofree char *path = object_get_canonical_path(OBJECT(dev)); + qemu_log_mask(LOG_GUEST_ERROR, "%s: I3C target created with reserved " + "address 0x%.2x\n", path, addr); + } + return I3C_TARGET(dev); +} + +bool i3c_target_realize_and_unref(I3CTarget *dev, I3CBus *bus, Error **errp) +{ + return qdev_realize_and_unref(&dev->parent_obj, &bus->parent_obj, errp); +} + +I3CTarget *i3c_target_create_simple(I3CBus *bus, const char *name, uint8_t addr, + uint8_t dcr, uint8_t bcr, uint64_t pid) +{ + I3CTarget *dev = i3c_target_new(name, addr, dcr, bcr, pid); + dev->address = 0; + i3c_target_realize_and_unref(dev, bus, &error_abort); + + return dev; +} + +/* Legacy I2C functions. */ +void legacy_i2c_nack(I3CBus *bus) +{ + trace_legacy_i2c_nack(); + i2c_nack(bus->i2c_bus); +} + +uint8_t legacy_i2c_recv(I3CBus *bus) +{ + uint8_t byte = i2c_recv(bus->i2c_bus); + trace_legacy_i2c_recv(byte); + return byte; +} + +int legacy_i2c_send(I3CBus *bus, uint8_t data) +{ + trace_legacy_i2c_send(data); + return i2c_send(bus->i2c_bus, data); +} + +int legacy_i2c_start_transfer(I3CBus *bus, uint8_t address, bool is_recv) +{ + trace_legacy_i2c_start_transfer(address, is_recv); + return i2c_start_transfer(bus->i2c_bus, address, is_recv); +} + +int legacy_i2c_start_recv(I3CBus *bus, uint8_t address) +{ + trace_legacy_i2c_start_transfer(address, true); + return i2c_start_transfer(bus->i2c_bus, address, /*is_recv=*/true); +} + +int legacy_i2c_start_send(I3CBus *bus, uint8_t address) +{ + trace_legacy_i2c_start_transfer(address, false); + return i2c_start_transfer(bus->i2c_bus, address, /*is_recv=*/false); +} + +void legacy_i2c_end_transfer(I3CBus *bus) +{ + trace_legacy_i2c_end_transfer(); + i2c_end_transfer(bus->i2c_bus); +} + +I2CSlave *legacy_i2c_device_create_simple(I3CBus *bus, const char *name, + uint8_t addr) +{ + I2CSlave *dev = i2c_slave_new(name, addr); + + i2c_slave_realize_and_unref(dev, bus->i2c_bus, &error_abort); + return dev; +} + +static void i3c_target_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *k = DEVICE_CLASS(klass); + I3CTargetClass *sc = I3C_TARGET_CLASS(klass); + set_bit(DEVICE_CATEGORY_MISC, k->categories); + k->bus_type = TYPE_I3C_BUS; + device_class_set_props(k, i3c_props); + sc->target_match = i3c_target_match; +} + +static const TypeInfo i3c_types[] = { + { + .name = TYPE_I3C_BUS, + .parent = TYPE_BUS, + .instance_size = sizeof(I3CBus), + .class_size = sizeof(I3CBusClass), + }, + { + .name = TYPE_I3C_TARGET, + .parent = TYPE_DEVICE, + .instance_size = sizeof(I3CTarget), + .abstract = true, + .class_size = sizeof(I3CTargetClass), + .class_init = i3c_target_class_init, + }, +}; + +DEFINE_TYPES(i3c_types) diff --git a/hw/i3c/meson.build b/hw/i3c/meson.build index XXXXXXX..XXXXXXX 100644 --- a/hw/i3c/meson.build +++ b/hw/i3c/meson.build @@ -XXX,XX +XXX,XX @@ i3c_ss = ss.source_set() +i3c_ss.add(when: 'CONFIG_I3C', if_true: files('core.c')) i3c_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_i3c.c')) system_ss.add_all(when: 'CONFIG_I3C', if_true: i3c_ss) diff --git a/hw/i3c/trace-events b/hw/i3c/trace-events index XXXXXXX..XXXXXXX 100644 --- a/hw/i3c/trace-events +++ b/hw/i3c/trace-events @@ -XXX,XX +XXX,XX @@ aspeed_i3c_read(uint64_t offset, uint64_t data) "I3C read: offset 0x%" PRIx64 " aspeed_i3c_write(uint64_t offset, uint64_t data) "I3C write: offset 0x%" PRIx64 " data 0x%" PRIx64 aspeed_i3c_device_read(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] read: offset 0x%" PRIx64 " data 0x%" PRIx64 aspeed_i3c_device_write(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] write: offset 0x%" PRIx64 " data 0x%" PRIx64 + +# core.c +i3c_target_event(uint8_t address, uint8_t event) "I3C target 0x%" PRIx8 " event 0x%" PRIx8 +i3c_target_handle_ccc(uint8_t address, uint8_t ccc) "I3C target 0x%" PRIx8 " handling CCC 0x%" PRIx8 +i3c_target_send_ibi(uint8_t address, bool is_recv) "I3C target IBI address 0x%" PRIx8 " RnW=%d" +i3c_target_send_ibi_bytes(uint8_t byte) "I3C target IBI byte 0x%" PRIx8 +i3c_target_ibi_finish(void) "I3C target IBI finish" +i3c_start_transfer(uint8_t address, bool is_recv) "I3C START with address 0x%" PRIx8 " is_recv=%d" +i3c_end_transfer(void) "I3C transfer done" +i3c_send(uint32_t num_sent, uint32_t num_to_send, bool ack) "I3C send %" PRId32 "/%" PRId32 " bytes, ack=%d" +i3c_recv(uint32_t num_read, uint32_t num_to_read, bool ack) "I3C recv %" PRId32 "/%" PRId32 " bytes, ack=%d" +legacy_i2c_nack(void) "Legacy I2C NACK" +legacy_i2c_recv(uint8_t byte) "Legacy I2C recv 0x%" PRIx8 +legacy_i2c_send(uint8_t byte) "Legacy I2C send 0x%" PRIx8 +legacy_i2c_start_transfer(uint8_t address, bool is_recv) "Legacy I2C START with address 0x%" PRIx8 " is_recv=%d" +legacy_i2c_end_transfer(void) "Legacy I2C STOP" -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> The Aspeed I3C IP block is technically an Aspeed IP block that manages 6 DW I3C controllers. To help reflect this better and to make it easier for other SoCs to use the DW I3C model, we'll split out the DW portion from the Aspeed portion. Signed-off-by: Joe Komlodi <komlodi@google.com> Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Tested-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260225021158.1586584-5-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- include/hw/i3c/aspeed_i3c.h | 17 +-- include/hw/i3c/dw-i3c.h | 33 ++++++ hw/i3c/aspeed_i3c.c | 181 +------------------------------- hw/i3c/dw-i3c.c | 202 ++++++++++++++++++++++++++++++++++++ hw/arm/Kconfig | 1 + hw/i3c/Kconfig | 3 + hw/i3c/meson.build | 1 + hw/i3c/trace-events | 6 +- 8 files changed, 250 insertions(+), 194 deletions(-) create mode 100644 include/hw/i3c/dw-i3c.h create mode 100644 hw/i3c/dw-i3c.c diff --git a/include/hw/i3c/aspeed_i3c.h b/include/hw/i3c/aspeed_i3c.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/i3c/aspeed_i3c.h +++ b/include/hw/i3c/aspeed_i3c.h @@ -XXX,XX +XXX,XX @@ #ifndef ASPEED_I3C_H #define ASPEED_I3C_H +#include "hw/i3c/dw-i3c.h" #include "hw/core/sysbus.h" #define TYPE_ASPEED_I3C "aspeed.i3c" -#define TYPE_ASPEED_I3C_DEVICE "aspeed.i3c.device" OBJECT_DECLARE_TYPE(AspeedI3CState, AspeedI3CClass, ASPEED_I3C) #define ASPEED_I3C_NR_REGS (0x70 >> 2) -#define ASPEED_I3C_DEVICE_NR_REGS (0x300 >> 2) #define ASPEED_I3C_NR_DEVICES 6 -OBJECT_DECLARE_SIMPLE_TYPE(AspeedI3CDevice, ASPEED_I3C_DEVICE) -struct AspeedI3CDevice { - SysBusDevice parent_obj; - - MemoryRegion mr; - qemu_irq irq; - - uint8_t id; - uint32_t regs[ASPEED_I3C_DEVICE_NR_REGS]; -}; - struct AspeedI3CState { SysBusDevice parent_obj; @@ -XXX,XX +XXX,XX @@ struct AspeedI3CState { qemu_irq irq; uint32_t regs[ASPEED_I3C_NR_REGS]; - AspeedI3CDevice devices[ASPEED_I3C_NR_DEVICES]; + DWI3C devices[ASPEED_I3C_NR_DEVICES]; + uint8_t id; }; #endif /* ASPEED_I3C_H */ diff --git a/include/hw/i3c/dw-i3c.h b/include/hw/i3c/dw-i3c.h new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/include/hw/i3c/dw-i3c.h @@ -XXX,XX +XXX,XX @@ +/* + * DesignWare I3C Controller + * + * Copyright (C) 2021 ASPEED Technology Inc. + * Copyright (C) 2025 Google, LLC. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef DW_I3C_H +#define DW_I3C_H + +#include "hw/core/sysbus.h" + +#define TYPE_DW_I3C "dw.i3c" +OBJECT_DECLARE_SIMPLE_TYPE(DWI3C, DW_I3C) + +#define DW_I3C_NR_REGS (0x300 >> 2) + +struct DWI3C { + SysBusDevice parent_obj; + + MemoryRegion mr; + qemu_irq irq; + + uint8_t id; + uint32_t regs[DW_I3C_NR_REGS]; +}; + +/* Extern for other controllers that use DesignWare I3C. */ +extern const VMStateDescription vmstate_dw_i3c; + +#endif /* DW_I3C_H */ diff --git a/hw/i3c/aspeed_i3c.c b/hw/i3c/aspeed_i3c.c index XXXXXXX..XXXXXXX 100644 --- a/hw/i3c/aspeed_i3c.c +++ b/hw/i3c/aspeed_i3c.c @@ -XXX,XX +XXX,XX @@ * ASPEED I3C Controller * * Copyright (C) 2021 ASPEED Technology Inc. + * Copyright (C) 2025 Google, LLC. * * This code is licensed under the GPL version 2 or later. See * the COPYING file in the top-level directory. @@ -XXX,XX +XXX,XX @@ REG32(I3C6_REG1, 0x64) FIELD(I3C6_REG1, I2C_MODE, 0, 1) FIELD(I3C6_REG1, SA_EN, 15, 1) -/* I3C Device Registers */ -REG32(DEVICE_CTRL, 0x00) -REG32(DEVICE_ADDR, 0x04) -REG32(HW_CAPABILITY, 0x08) -REG32(COMMAND_QUEUE_PORT, 0x0c) -REG32(RESPONSE_QUEUE_PORT, 0x10) -REG32(RX_TX_DATA_PORT, 0x14) -REG32(IBI_QUEUE_STATUS, 0x18) -REG32(IBI_QUEUE_DATA, 0x18) -REG32(QUEUE_THLD_CTRL, 0x1c) -REG32(DATA_BUFFER_THLD_CTRL, 0x20) -REG32(IBI_QUEUE_CTRL, 0x24) -REG32(IBI_MR_REQ_REJECT, 0x2c) -REG32(IBI_SIR_REQ_REJECT, 0x30) -REG32(RESET_CTRL, 0x34) -REG32(SLV_EVENT_CTRL, 0x38) -REG32(INTR_STATUS, 0x3c) -REG32(INTR_STATUS_EN, 0x40) -REG32(INTR_SIGNAL_EN, 0x44) -REG32(INTR_FORCE, 0x48) -REG32(QUEUE_STATUS_LEVEL, 0x4c) -REG32(DATA_BUFFER_STATUS_LEVEL, 0x50) -REG32(PRESENT_STATE, 0x54) -REG32(CCC_DEVICE_STATUS, 0x58) -REG32(DEVICE_ADDR_TABLE_POINTER, 0x5c) - FIELD(DEVICE_ADDR_TABLE_POINTER, DEPTH, 16, 16) - FIELD(DEVICE_ADDR_TABLE_POINTER, ADDR, 0, 16) -REG32(DEV_CHAR_TABLE_POINTER, 0x60) -REG32(VENDOR_SPECIFIC_REG_POINTER, 0x6c) -REG32(SLV_MIPI_PID_VALUE, 0x70) -REG32(SLV_PID_VALUE, 0x74) -REG32(SLV_CHAR_CTRL, 0x78) -REG32(SLV_MAX_LEN, 0x7c) -REG32(MAX_READ_TURNAROUND, 0x80) -REG32(MAX_DATA_SPEED, 0x84) -REG32(SLV_DEBUG_STATUS, 0x88) -REG32(SLV_INTR_REQ, 0x8c) -REG32(DEVICE_CTRL_EXTENDED, 0xb0) -REG32(SCL_I3C_OD_TIMING, 0xb4) -REG32(SCL_I3C_PP_TIMING, 0xb8) -REG32(SCL_I2C_FM_TIMING, 0xbc) -REG32(SCL_I2C_FMP_TIMING, 0xc0) -REG32(SCL_EXT_LCNT_TIMING, 0xc8) -REG32(SCL_EXT_TERMN_LCNT_TIMING, 0xcc) -REG32(BUS_FREE_TIMING, 0xd4) -REG32(BUS_IDLE_TIMING, 0xd8) -REG32(I3C_VER_ID, 0xe0) -REG32(I3C_VER_TYPE, 0xe4) -REG32(EXTENDED_CAPABILITY, 0xe8) -REG32(SLAVE_CONFIG, 0xec) - -static const uint32_t ast2600_i3c_device_resets[ASPEED_I3C_DEVICE_NR_REGS] = { - [R_HW_CAPABILITY] = 0x000e00bf, - [R_QUEUE_THLD_CTRL] = 0x01000101, - [R_I3C_VER_ID] = 0x3130302a, - [R_I3C_VER_TYPE] = 0x6c633033, - [R_DEVICE_ADDR_TABLE_POINTER] = 0x00080280, - [R_DEV_CHAR_TABLE_POINTER] = 0x00020200, - [A_VENDOR_SPECIFIC_REG_POINTER] = 0x000000b0, - [R_SLV_MAX_LEN] = 0x00ff00ff, -}; - -static uint64_t aspeed_i3c_device_read(void *opaque, hwaddr offset, - unsigned size) -{ - AspeedI3CDevice *s = ASPEED_I3C_DEVICE(opaque); - uint32_t addr = offset >> 2; - uint64_t value; - - switch (addr) { - case R_COMMAND_QUEUE_PORT: - value = 0; - break; - default: - value = s->regs[addr]; - break; - } - - trace_aspeed_i3c_device_read(s->id, offset, value); - - return value; -} - -static void aspeed_i3c_device_write(void *opaque, hwaddr offset, - uint64_t value, unsigned size) -{ - AspeedI3CDevice *s = ASPEED_I3C_DEVICE(opaque); - uint32_t addr = offset >> 2; - - trace_aspeed_i3c_device_write(s->id, offset, value); - - switch (addr) { - case R_HW_CAPABILITY: - case R_RESPONSE_QUEUE_PORT: - case R_IBI_QUEUE_DATA: - case R_QUEUE_STATUS_LEVEL: - case R_PRESENT_STATE: - case R_CCC_DEVICE_STATUS: - case R_DEVICE_ADDR_TABLE_POINTER: - case R_VENDOR_SPECIFIC_REG_POINTER: - case R_SLV_CHAR_CTRL: - case R_SLV_MAX_LEN: - case R_MAX_READ_TURNAROUND: - case R_I3C_VER_ID: - case R_I3C_VER_TYPE: - case R_EXTENDED_CAPABILITY: - qemu_log_mask(LOG_GUEST_ERROR, - "%s: write to readonly register[0x%02" HWADDR_PRIx - "] = 0x%08" PRIx64 "\n", - __func__, offset, value); - break; - case R_RX_TX_DATA_PORT: - break; - case R_RESET_CTRL: - break; - default: - s->regs[addr] = value; - break; - } -} - -static const VMStateDescription aspeed_i3c_device_vmstate = { - .name = TYPE_ASPEED_I3C, - .version_id = 1, - .minimum_version_id = 1, - .fields = (const VMStateField[]){ - VMSTATE_UINT32_ARRAY(regs, AspeedI3CDevice, ASPEED_I3C_DEVICE_NR_REGS), - VMSTATE_END_OF_LIST(), - } -}; - -static const MemoryRegionOps aspeed_i3c_device_ops = { - .read = aspeed_i3c_device_read, - .write = aspeed_i3c_device_write, - .endianness = DEVICE_LITTLE_ENDIAN, -}; - -static void aspeed_i3c_device_reset(DeviceState *dev) -{ - AspeedI3CDevice *s = ASPEED_I3C_DEVICE(dev); - - memcpy(s->regs, ast2600_i3c_device_resets, sizeof(s->regs)); -} - -static void aspeed_i3c_device_realize(DeviceState *dev, Error **errp) -{ - AspeedI3CDevice *s = ASPEED_I3C_DEVICE(dev); - g_autofree char *name = g_strdup_printf(TYPE_ASPEED_I3C_DEVICE ".%d", - s->id); - - sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); - - memory_region_init_io(&s->mr, OBJECT(s), &aspeed_i3c_device_ops, - s, name, ASPEED_I3C_DEVICE_NR_REGS << 2); -} - static uint64_t aspeed_i3c_read(void *opaque, hwaddr addr, unsigned int size) { AspeedI3CState *s = ASPEED_I3C(opaque); @@ -XXX,XX +XXX,XX @@ static void aspeed_i3c_instance_init(Object *obj) for (i = 0; i < ASPEED_I3C_NR_DEVICES; ++i) { object_initialize_child(obj, "device[*]", &s->devices[i], - TYPE_ASPEED_I3C_DEVICE); + TYPE_DW_I3C); } } @@ -XXX,XX +XXX,XX @@ static void aspeed_i3c_realize(DeviceState *dev, Error **errp) } -static const Property aspeed_i3c_device_properties[] = { - DEFINE_PROP_UINT8("device-id", AspeedI3CDevice, id, 0), -}; - -static void aspeed_i3c_device_class_init(ObjectClass *klass, const void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - - dc->desc = "Aspeed I3C Device"; - dc->realize = aspeed_i3c_device_realize; - device_class_set_legacy_reset(dc, aspeed_i3c_device_reset); - device_class_set_props(dc, aspeed_i3c_device_properties); -} - static const VMStateDescription vmstate_aspeed_i3c = { .name = TYPE_ASPEED_I3C, .version_id = 1, @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_aspeed_i3c = { .fields = (const VMStateField[]) { VMSTATE_UINT32_ARRAY(regs, AspeedI3CState, ASPEED_I3C_NR_REGS), VMSTATE_STRUCT_ARRAY(devices, AspeedI3CState, ASPEED_I3C_NR_DEVICES, 1, - aspeed_i3c_device_vmstate, AspeedI3CDevice), + vmstate_dw_i3c, DWI3C), VMSTATE_END_OF_LIST(), } }; @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_i3c_types[] = { .instance_size = sizeof(AspeedI3CState), .class_init = aspeed_i3c_class_init, }, - { - .name = TYPE_ASPEED_I3C_DEVICE, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(AspeedI3CDevice), - .class_init = aspeed_i3c_device_class_init, - }, }; DEFINE_TYPES(aspeed_i3c_types) diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/hw/i3c/dw-i3c.c @@ -XXX,XX +XXX,XX @@ +/* + * DesignWare I3C Controller + * + * Copyright (C) 2021 ASPEED Technology Inc. + * Copyright (C) 2025 Google, LLC + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/error-report.h" +#include "hw/i3c/i3c.h" +#include "hw/i3c/dw-i3c.h" +#include "hw/core/registerfields.h" +#include "hw/core/qdev-properties.h" +#include "qapi/error.h" +#include "migration/vmstate.h" +#include "trace.h" + +REG32(DEVICE_CTRL, 0x00) +REG32(DEVICE_ADDR, 0x04) +REG32(HW_CAPABILITY, 0x08) +REG32(COMMAND_QUEUE_PORT, 0x0c) +REG32(RESPONSE_QUEUE_PORT, 0x10) +REG32(RX_TX_DATA_PORT, 0x14) +REG32(IBI_QUEUE_STATUS, 0x18) +REG32(IBI_QUEUE_DATA, 0x18) +REG32(QUEUE_THLD_CTRL, 0x1c) +REG32(DATA_BUFFER_THLD_CTRL, 0x20) +REG32(IBI_QUEUE_CTRL, 0x24) +REG32(IBI_MR_REQ_REJECT, 0x2c) +REG32(IBI_SIR_REQ_REJECT, 0x30) +REG32(RESET_CTRL, 0x34) +REG32(SLV_EVENT_CTRL, 0x38) +REG32(INTR_STATUS, 0x3c) +REG32(INTR_STATUS_EN, 0x40) +REG32(INTR_SIGNAL_EN, 0x44) +REG32(INTR_FORCE, 0x48) +REG32(QUEUE_STATUS_LEVEL, 0x4c) +REG32(DATA_BUFFER_STATUS_LEVEL, 0x50) +REG32(PRESENT_STATE, 0x54) +REG32(CCC_DEVICE_STATUS, 0x58) +REG32(DEVICE_ADDR_TABLE_POINTER, 0x5c) + FIELD(DEVICE_ADDR_TABLE_POINTER, DEPTH, 16, 16) + FIELD(DEVICE_ADDR_TABLE_POINTER, ADDR, 0, 16) +REG32(DEV_CHAR_TABLE_POINTER, 0x60) +REG32(VENDOR_SPECIFIC_REG_POINTER, 0x6c) +REG32(SLV_MIPI_PID_VALUE, 0x70) +REG32(SLV_PID_VALUE, 0x74) +REG32(SLV_CHAR_CTRL, 0x78) +REG32(SLV_MAX_LEN, 0x7c) +REG32(MAX_READ_TURNAROUND, 0x80) +REG32(MAX_DATA_SPEED, 0x84) +REG32(SLV_DEBUG_STATUS, 0x88) +REG32(SLV_INTR_REQ, 0x8c) +REG32(DEVICE_CTRL_EXTENDED, 0xb0) +REG32(SCL_I3C_OD_TIMING, 0xb4) +REG32(SCL_I3C_PP_TIMING, 0xb8) +REG32(SCL_I2C_FM_TIMING, 0xbc) +REG32(SCL_I2C_FMP_TIMING, 0xc0) +REG32(SCL_EXT_LCNT_TIMING, 0xc8) +REG32(SCL_EXT_TERMN_LCNT_TIMING, 0xcc) +REG32(BUS_FREE_TIMING, 0xd4) +REG32(BUS_IDLE_TIMING, 0xd8) +REG32(I3C_VER_ID, 0xe0) +REG32(I3C_VER_TYPE, 0xe4) +REG32(EXTENDED_CAPABILITY, 0xe8) +REG32(SLAVE_CONFIG, 0xec) + +static const uint32_t dw_i3c_resets[DW_I3C_NR_REGS] = { + [R_HW_CAPABILITY] = 0x000e00bf, + [R_QUEUE_THLD_CTRL] = 0x01000101, + [R_I3C_VER_ID] = 0x3130302a, + [R_I3C_VER_TYPE] = 0x6c633033, + [R_DEVICE_ADDR_TABLE_POINTER] = 0x00080280, + [R_DEV_CHAR_TABLE_POINTER] = 0x00020200, + [A_VENDOR_SPECIFIC_REG_POINTER] = 0x000000b0, + [R_SLV_MAX_LEN] = 0x00ff00ff, +}; + +static uint64_t dw_i3c_read(void *opaque, hwaddr offset, unsigned size) +{ + DWI3C *s = DW_I3C(opaque); + uint32_t addr = offset >> 2; + uint64_t value; + + switch (addr) { + case R_COMMAND_QUEUE_PORT: + value = 0; + break; + default: + value = s->regs[addr]; + break; + } + + trace_dw_i3c_read(s->id, offset, value); + + return value; +} + +static void dw_i3c_write(void *opaque, hwaddr offset, uint64_t value, + unsigned size) +{ + DWI3C *s = DW_I3C(opaque); + uint32_t addr = offset >> 2; + + trace_dw_i3c_write(s->id, offset, value); + + switch (addr) { + case R_HW_CAPABILITY: + case R_RESPONSE_QUEUE_PORT: + case R_IBI_QUEUE_DATA: + case R_QUEUE_STATUS_LEVEL: + case R_PRESENT_STATE: + case R_CCC_DEVICE_STATUS: + case R_DEVICE_ADDR_TABLE_POINTER: + case R_VENDOR_SPECIFIC_REG_POINTER: + case R_SLV_CHAR_CTRL: + case R_SLV_MAX_LEN: + case R_MAX_READ_TURNAROUND: + case R_I3C_VER_ID: + case R_I3C_VER_TYPE: + case R_EXTENDED_CAPABILITY: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to readonly register[0x%02" HWADDR_PRIx + "] = 0x%08" PRIx64 "\n", + __func__, offset, value); + break; + case R_RX_TX_DATA_PORT: + break; + case R_RESET_CTRL: + break; + default: + s->regs[addr] = value; + break; + } +} + +const VMStateDescription vmstate_dw_i3c = { + .name = TYPE_DW_I3C, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]){ + VMSTATE_UINT32_ARRAY(regs, DWI3C, DW_I3C_NR_REGS), + VMSTATE_END_OF_LIST(), + } +}; + +static const MemoryRegionOps dw_i3c_ops = { + .read = dw_i3c_read, + .write = dw_i3c_write, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +static void dw_i3c_reset_enter(Object *obj, ResetType type) +{ + DWI3C *s = DW_I3C(obj); + + memcpy(s->regs, dw_i3c_resets, sizeof(s->regs)); +} + +static void dw_i3c_realize(DeviceState *dev, Error **errp) +{ + DWI3C *s = DW_I3C(dev); + g_autofree char *name = g_strdup_printf(TYPE_DW_I3C ".%d", s->id); + + sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); + + memory_region_init_io(&s->mr, OBJECT(s), &dw_i3c_ops, s, name, + DW_I3C_NR_REGS << 2); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mr); +} + +static const Property dw_i3c_properties[] = { + DEFINE_PROP_UINT8("device-id", DWI3C, id, 0), +}; + +static void dw_i3c_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); + + rc->phases.enter = dw_i3c_reset_enter; + + dc->desc = "DesignWare I3C Controller"; + dc->realize = dw_i3c_realize; + dc->vmsd = &vmstate_dw_i3c; + device_class_set_props(dc, dw_i3c_properties); +} + +static const TypeInfo dw_i3c_types[] = { + { + .name = TYPE_DW_I3C, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(DWI3C), + .class_init = dw_i3c_class_init, + }, +}; + +DEFINE_TYPES(dw_i3c_types) + diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -XXX,XX +XXX,XX @@ config ASPEED_SOC select FTGMAC100 select I2C select I3C + select DW_I3C select DPS310 select PCA9552 select PCA9554 diff --git a/hw/i3c/Kconfig b/hw/i3c/Kconfig index XXXXXXX..XXXXXXX 100644 --- a/hw/i3c/Kconfig +++ b/hw/i3c/Kconfig @@ -XXX,XX +XXX,XX @@ config I3C bool + +config DW_I3C + bool diff --git a/hw/i3c/meson.build b/hw/i3c/meson.build index XXXXXXX..XXXXXXX 100644 --- a/hw/i3c/meson.build +++ b/hw/i3c/meson.build @@ -XXX,XX +XXX,XX @@ i3c_ss = ss.source_set() i3c_ss.add(when: 'CONFIG_I3C', if_true: files('core.c')) i3c_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_i3c.c')) +i3c_ss.add(when: 'CONFIG_DW_I3C', if_true: files('dw-i3c.c')) system_ss.add_all(when: 'CONFIG_I3C', if_true: i3c_ss) diff --git a/hw/i3c/trace-events b/hw/i3c/trace-events index XXXXXXX..XXXXXXX 100644 --- a/hw/i3c/trace-events +++ b/hw/i3c/trace-events @@ -XXX,XX +XXX,XX @@ # aspeed_i3c.c aspeed_i3c_read(uint64_t offset, uint64_t data) "I3C read: offset 0x%" PRIx64 " data 0x%" PRIx64 aspeed_i3c_write(uint64_t offset, uint64_t data) "I3C write: offset 0x%" PRIx64 " data 0x%" PRIx64 -aspeed_i3c_device_read(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] read: offset 0x%" PRIx64 " data 0x%" PRIx64 -aspeed_i3c_device_write(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] write: offset 0x%" PRIx64 " data 0x%" PRIx64 + +# dw-i3c,c +dw_i3c_read(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] read: offset 0x%" PRIx64 " data 0x%" PRIx64 +dw_i3c_write(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] write: offset 0x%" PRIx64 " data 0x%" PRIx64 # core.c i3c_target_event(uint8_t address, uint8_t event) "I3C target 0x%" PRIx8 " event 0x%" PRIx8 -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> Adds the rest of the Designware register fields. Signed-off-by: Joe Komlodi <komlodi@google.com> Reviewed-by: Patrick Venture <venture@google.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Tested-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260225021158.1586584-6-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- hw/i3c/dw-i3c.c | 199 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 199 insertions(+) diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c index XXXXXXX..XXXXXXX 100644 --- a/hw/i3c/dw-i3c.c +++ b/hw/i3c/dw-i3c.c @@ -XXX,XX +XXX,XX @@ #include "trace.h" REG32(DEVICE_CTRL, 0x00) + FIELD(DEVICE_CTRL, I3C_BROADCAST_ADDR_INC, 0, 1) + FIELD(DEVICE_CTRL, I2C_SLAVE_PRESENT, 7, 1) + FIELD(DEVICE_CTRL, HOT_JOIN_ACK_NACK_CTRL, 8, 1) + FIELD(DEVICE_CTRL, IDLE_CNT_MULTIPLIER, 24, 2) + FIELD(DEVICE_CTRL, SLV_ADAPT_TO_I2C_I3C_MODE, 27, 1) + FIELD(DEVICE_CTRL, DMA_HANDSHAKE_EN, 28, 1) + FIELD(DEVICE_CTRL, I3C_ABORT, 29, 1) + FIELD(DEVICE_CTRL, I3C_RESUME, 30, 1) + FIELD(DEVICE_CTRL, I3C_EN, 31, 1) REG32(DEVICE_ADDR, 0x04) + FIELD(DEVICE_ADDR, STATIC_ADDR, 0, 7) + FIELD(DEVICE_ADDR, STATIC_ADDR_VALID, 15, 1) + FIELD(DEVICE_ADDR, DYNAMIC_ADDR, 16, 7) + FIELD(DEVICE_ADDR, DYNAMIC_ADDR_VALID, 31, 1) REG32(HW_CAPABILITY, 0x08) + FIELD(HW_CAPABILITY, DEVICE_ROLE_CONFIG, 0, 3) + FIELD(HW_CAPABILITY, HDR_DDR, 3, 1) + FIELD(HW_CAPABILITY, HDR_TS, 4, 1) REG32(COMMAND_QUEUE_PORT, 0x0c) + FIELD(COMMAND_QUEUE_PORT, CMD_ATTR, 0, 3) + /* Transfer command structure */ + FIELD(COMMAND_QUEUE_PORT, TID, 3, 4) + FIELD(COMMAND_QUEUE_PORT, CMD, 7, 8) + FIELD(COMMAND_QUEUE_PORT, CP, 15, 1) + FIELD(COMMAND_QUEUE_PORT, DEV_INDEX, 16, 5) + FIELD(COMMAND_QUEUE_PORT, SPEED, 21, 3) + FIELD(COMMAND_QUEUE_PORT, ROC, 26, 1) + FIELD(COMMAND_QUEUE_PORT, SDAP, 27, 1) + FIELD(COMMAND_QUEUE_PORT, RNW, 28, 1) + FIELD(COMMAND_QUEUE_PORT, TOC, 30, 1) + FIELD(COMMAND_QUEUE_PORT, PEC, 31, 1) + /* Transfer argument data structure */ + FIELD(COMMAND_QUEUE_PORT, DB, 8, 8) + FIELD(COMMAND_QUEUE_PORT, DL, 16, 16) + /* Short data argument data structure */ + FIELD(COMMAND_QUEUE_PORT, BYTE_STRB, 3, 3) + FIELD(COMMAND_QUEUE_PORT, BYTE0, 8, 8) + FIELD(COMMAND_QUEUE_PORT, BYTE1, 16, 8) + FIELD(COMMAND_QUEUE_PORT, BYTE2, 24, 8) + /* Address assignment command structure */ + /* + * bits 3..21 and 26..31 are the same as the transfer command structure, or + * marked as reserved. + */ + FIELD(COMMAND_QUEUE_PORT, DEV_COUNT, 21, 3) REG32(RESPONSE_QUEUE_PORT, 0x10) + FIELD(RESPONSE_QUEUE_PORT, DL, 0, 16) + FIELD(RESPONSE_QUEUE_PORT, CCCT, 16, 8) + FIELD(RESPONSE_QUEUE_PORT, TID, 24, 3) + FIELD(RESPONSE_QUEUE_PORT, ERR_STATUS, 28, 4) REG32(RX_TX_DATA_PORT, 0x14) REG32(IBI_QUEUE_STATUS, 0x18) + FIELD(IBI_QUEUE_STATUS, IBI_DATA_LEN, 0, 8) + FIELD(IBI_QUEUE_STATUS, IBI_ID, 8, 8) + FIELD(IBI_QUEUE_STATUS, LAST_STATUS, 24, 1) + FIELD(IBI_QUEUE_STATUS, ERROR, 30, 1) + FIELD(IBI_QUEUE_STATUS, IBI_STATUS, 31, 1) REG32(IBI_QUEUE_DATA, 0x18) REG32(QUEUE_THLD_CTRL, 0x1c) + FIELD(QUEUE_THLD_CTRL, CMD_BUF_EMPTY_THLD, 0, 8); + FIELD(QUEUE_THLD_CTRL, RESP_BUF_THLD, 8, 8); + FIELD(QUEUE_THLD_CTRL, IBI_DATA_THLD, 16, 5); + FIELD(QUEUE_THLD_CTRL, IBI_STATUS_THLD, 24, 8); REG32(DATA_BUFFER_THLD_CTRL, 0x20) + FIELD(DATA_BUFFER_THLD_CTRL, TX_BUF_THLD, 0, 3) + FIELD(DATA_BUFFER_THLD_CTRL, RX_BUF_THLD, 8, 3) + FIELD(DATA_BUFFER_THLD_CTRL, TX_START_THLD, 16, 3) + FIELD(DATA_BUFFER_THLD_CTRL, RX_START_THLD, 24, 3) REG32(IBI_QUEUE_CTRL, 0x24) + FIELD(IBI_QUEUE_CTRL, NOTIFY_REJECTED_HOT_JOIN, 0, 1) + FIELD(IBI_QUEUE_CTRL, NOTIFY_REJECTED_MASTER_REQ, 1, 1) + FIELD(IBI_QUEUE_CTRL, NOTIFY_REJECTED_SLAVE_IRQ, 3, 1) REG32(IBI_MR_REQ_REJECT, 0x2c) REG32(IBI_SIR_REQ_REJECT, 0x30) REG32(RESET_CTRL, 0x34) + FIELD(RESET_CTRL, CORE_RESET, 0, 1) + FIELD(RESET_CTRL, CMD_QUEUE_RESET, 1, 1) + FIELD(RESET_CTRL, RESP_QUEUE_RESET, 2, 1) + FIELD(RESET_CTRL, TX_BUF_RESET, 3, 1) + FIELD(RESET_CTRL, RX_BUF_RESET, 4, 1) + FIELD(RESET_CTRL, IBI_QUEUE_RESET, 5, 1) REG32(SLV_EVENT_CTRL, 0x38) + FIELD(SLV_EVENT_CTRL, SLV_INTERRUPT, 0, 1) + FIELD(SLV_EVENT_CTRL, MASTER_INTERRUPT, 1, 1) + FIELD(SLV_EVENT_CTRL, HOT_JOIN_INTERRUPT, 3, 1) + FIELD(SLV_EVENT_CTRL, ACTIVITY_STATE, 4, 2) + FIELD(SLV_EVENT_CTRL, MRL_UPDATED, 6, 1) + FIELD(SLV_EVENT_CTRL, MWL_UPDATED, 7, 1) REG32(INTR_STATUS, 0x3c) + FIELD(INTR_STATUS, TX_THLD, 0, 1) + FIELD(INTR_STATUS, RX_THLD, 1, 1) + FIELD(INTR_STATUS, IBI_THLD, 2, 1) + FIELD(INTR_STATUS, CMD_QUEUE_RDY, 3, 1) + FIELD(INTR_STATUS, RESP_RDY, 4, 1) + FIELD(INTR_STATUS, TRANSFER_ABORT, 5, 1) + FIELD(INTR_STATUS, CCC_UPDATED, 6, 1) + FIELD(INTR_STATUS, DYN_ADDR_ASSGN, 8, 1) + FIELD(INTR_STATUS, TRANSFER_ERR, 9, 1) + FIELD(INTR_STATUS, DEFSLV, 10, 1) + FIELD(INTR_STATUS, READ_REQ_RECV, 11, 1) + FIELD(INTR_STATUS, IBI_UPDATED, 12, 1) + FIELD(INTR_STATUS, BUSOWNER_UPDATED, 13, 1) REG32(INTR_STATUS_EN, 0x40) + FIELD(INTR_STATUS_EN, TX_THLD, 0, 1) + FIELD(INTR_STATUS_EN, RX_THLD, 1, 1) + FIELD(INTR_STATUS_EN, IBI_THLD, 2, 1) + FIELD(INTR_STATUS_EN, CMD_QUEUE_RDY, 3, 1) + FIELD(INTR_STATUS_EN, RESP_RDY, 4, 1) + FIELD(INTR_STATUS_EN, TRANSFER_ABORT, 5, 1) + FIELD(INTR_STATUS_EN, CCC_UPDATED, 6, 1) + FIELD(INTR_STATUS_EN, DYN_ADDR_ASSGN, 8, 1) + FIELD(INTR_STATUS_EN, TRANSFER_ERR, 9, 1) + FIELD(INTR_STATUS_EN, DEFSLV, 10, 1) + FIELD(INTR_STATUS_EN, READ_REQ_RECV, 11, 1) + FIELD(INTR_STATUS_EN, IBI_UPDATED, 12, 1) + FIELD(INTR_STATUS_EN, BUSOWNER_UPDATED, 13, 1) REG32(INTR_SIGNAL_EN, 0x44) + FIELD(INTR_SIGNAL_EN, TX_THLD, 0, 1) + FIELD(INTR_SIGNAL_EN, RX_THLD, 1, 1) + FIELD(INTR_SIGNAL_EN, IBI_THLD, 2, 1) + FIELD(INTR_SIGNAL_EN, CMD_QUEUE_RDY, 3, 1) + FIELD(INTR_SIGNAL_EN, RESP_RDY, 4, 1) + FIELD(INTR_SIGNAL_EN, TRANSFER_ABORT, 5, 1) + FIELD(INTR_SIGNAL_EN, CCC_UPDATED, 6, 1) + FIELD(INTR_SIGNAL_EN, DYN_ADDR_ASSGN, 8, 1) + FIELD(INTR_SIGNAL_EN, TRANSFER_ERR, 9, 1) + FIELD(INTR_SIGNAL_EN, DEFSLV, 10, 1) + FIELD(INTR_SIGNAL_EN, READ_REQ_RECV, 11, 1) + FIELD(INTR_SIGNAL_EN, IBI_UPDATED, 12, 1) + FIELD(INTR_SIGNAL_EN, BUSOWNER_UPDATED, 13, 1) REG32(INTR_FORCE, 0x48) + FIELD(INTR_FORCE, TX_THLD, 0, 1) + FIELD(INTR_FORCE, RX_THLD, 1, 1) + FIELD(INTR_FORCE, IBI_THLD, 2, 1) + FIELD(INTR_FORCE, CMD_QUEUE_RDY, 3, 1) + FIELD(INTR_FORCE, RESP_RDY, 4, 1) + FIELD(INTR_FORCE, TRANSFER_ABORT, 5, 1) + FIELD(INTR_FORCE, CCC_UPDATED, 6, 1) + FIELD(INTR_FORCE, DYN_ADDR_ASSGN, 8, 1) + FIELD(INTR_FORCE, TRANSFER_ERR, 9, 1) + FIELD(INTR_FORCE, DEFSLV, 10, 1) + FIELD(INTR_FORCE, READ_REQ_RECV, 11, 1) + FIELD(INTR_FORCE, IBI_UPDATED, 12, 1) + FIELD(INTR_FORCE, BUSOWNER_UPDATED, 13, 1) REG32(QUEUE_STATUS_LEVEL, 0x4c) + FIELD(QUEUE_STATUS_LEVEL, CMD_QUEUE_EMPTY_LOC, 0, 8) + FIELD(QUEUE_STATUS_LEVEL, RESP_BUF_BLR, 8, 8) + FIELD(QUEUE_STATUS_LEVEL, IBI_BUF_BLR, 16, 8) + FIELD(QUEUE_STATUS_LEVEL, IBI_STATUS_CNT, 24, 5) REG32(DATA_BUFFER_STATUS_LEVEL, 0x50) + FIELD(DATA_BUFFER_STATUS_LEVEL, TX_BUF_EMPTY_LOC, 0, 8) + FIELD(DATA_BUFFER_STATUS_LEVEL, RX_BUF_BLR, 16, 8) REG32(PRESENT_STATE, 0x54) + FIELD(PRESENT_STATE, SCL_LINE_SIGNAL_LEVEL, 0, 1) + FIELD(PRESENT_STATE, SDA_LINE_SIGNAL_LEVEL, 1, 1) + FIELD(PRESENT_STATE, CURRENT_MASTER, 2, 1) + FIELD(PRESENT_STATE, CM_TFR_STATUS, 8, 6) + FIELD(PRESENT_STATE, CM_TFR_ST_STATUS, 16, 6) + FIELD(PRESENT_STATE, CMD_TID, 24, 4) REG32(CCC_DEVICE_STATUS, 0x58) + FIELD(CCC_DEVICE_STATUS, PENDING_INTR, 0, 4) + FIELD(CCC_DEVICE_STATUS, PROTOCOL_ERR, 5, 1) + FIELD(CCC_DEVICE_STATUS, ACTIVITY_MODE, 6, 2) + FIELD(CCC_DEVICE_STATUS, UNDER_ERR, 8, 1) + FIELD(CCC_DEVICE_STATUS, SLV_BUSY, 9, 1) + FIELD(CCC_DEVICE_STATUS, OVERFLOW_ERR, 10, 1) + FIELD(CCC_DEVICE_STATUS, DATA_NOT_READY, 11, 1) + FIELD(CCC_DEVICE_STATUS, BUFFER_NOT_AVAIL, 12, 1) REG32(DEVICE_ADDR_TABLE_POINTER, 0x5c) FIELD(DEVICE_ADDR_TABLE_POINTER, DEPTH, 16, 16) FIELD(DEVICE_ADDR_TABLE_POINTER, ADDR, 0, 16) REG32(DEV_CHAR_TABLE_POINTER, 0x60) + FIELD(DEV_CHAR_TABLE_POINTER, P_DEV_CHAR_TABLE_START_ADDR, 0, 12) + FIELD(DEV_CHAR_TABLE_POINTER, DEV_CHAR_TABLE_DEPTH, 12, 7) + FIELD(DEV_CHAR_TABLE_POINTER, PRESENT_DEV_CHAR_TABLE_INDEX, 19, 3) REG32(VENDOR_SPECIFIC_REG_POINTER, 0x6c) + FIELD(VENDOR_SPECIFIC_REG_POINTER, P_VENDOR_REG_START_ADDR, 0, 16) REG32(SLV_MIPI_PID_VALUE, 0x70) REG32(SLV_PID_VALUE, 0x74) + FIELD(SLV_PID_VALUE, SLV_PID_DCR, 0, 12) + FIELD(SLV_PID_VALUE, SLV_INST_ID, 12, 4) + FIELD(SLV_PID_VALUE, SLV_PART_ID, 16, 16) REG32(SLV_CHAR_CTRL, 0x78) + FIELD(SLV_CHAR_CTRL, BCR, 0, 8) + FIELD(SLV_CHAR_CTRL, DCR, 8, 8) + FIELD(SLV_CHAR_CTRL, HDR_CAP, 16, 8) REG32(SLV_MAX_LEN, 0x7c) + FIELD(SLV_MAX_LEN, MWL, 0, 16) + FIELD(SLV_MAX_LEN, MRL, 16, 16) REG32(MAX_READ_TURNAROUND, 0x80) REG32(MAX_DATA_SPEED, 0x84) REG32(SLV_DEBUG_STATUS, 0x88) REG32(SLV_INTR_REQ, 0x8c) + FIELD(SLV_INTR_REQ, SIR, 0, 1) + FIELD(SLV_INTR_REQ, SIR_CTRL, 1, 2) + FIELD(SLV_INTR_REQ, MIR, 3, 1) + FIELD(SLV_INTR_REQ, TS, 4, 1) + FIELD(SLV_INTR_REQ, IBI_STS, 8, 2) +REG32(SLV_TSX_SYMBL_TIMING, 0x90) + FIELD(SLV_TSX_SYMBL_TIMING, SLV_TSX_SYMBL_CNT, 0, 6) REG32(DEVICE_CTRL_EXTENDED, 0xb0) + FIELD(DEVICE_CTRL_EXTENDED, MODE, 0, 2) + FIELD(DEVICE_CTRL_EXTENDED, REQMST_ACK_CTRL, 3, 1) REG32(SCL_I3C_OD_TIMING, 0xb4) + FIELD(SCL_I3C_OD_TIMING, I3C_OD_LCNT, 0, 8) + FIELD(SCL_I3C_OD_TIMING, I3C_OD_HCNT, 16, 8) REG32(SCL_I3C_PP_TIMING, 0xb8) + FIELD(SCL_I3C_PP_TIMING, I3C_PP_LCNT, 0, 8) + FIELD(SCL_I3C_PP_TIMING, I3C_PP_HCNT, 16, 8) REG32(SCL_I2C_FM_TIMING, 0xbc) REG32(SCL_I2C_FMP_TIMING, 0xc0) + FIELD(SCL_I2C_FMP_TIMING, I2C_FMP_LCNT, 0, 16) + FIELD(SCL_I2C_FMP_TIMING, I2C_FMP_HCNT, 16, 8) REG32(SCL_EXT_LCNT_TIMING, 0xc8) REG32(SCL_EXT_TERMN_LCNT_TIMING, 0xcc) REG32(BUS_FREE_TIMING, 0xd4) REG32(BUS_IDLE_TIMING, 0xd8) + FIELD(BUS_IDLE_TIMING, BUS_IDLE_TIME, 0, 20) REG32(I3C_VER_ID, 0xe0) REG32(I3C_VER_TYPE, 0xe4) REG32(EXTENDED_CAPABILITY, 0xe8) REG32(SLAVE_CONFIG, 0xec) +/* Device characteristic table fields */ +REG32(DEVICE_CHARACTERISTIC_TABLE_LOC1, 0x200) +REG32(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, 0x200) + FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, DYNAMIC_ADDR, 0, 8) + FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, DCR, 8, 8) + FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, BCR, 16, 8) + FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, STATIC_ADDR, 24, 8) +REG32(DEVICE_CHARACTERISTIC_TABLE_LOC2, 0x204) + FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC2, MSB_PID, 0, 16) +REG32(DEVICE_CHARACTERISTIC_TABLE_LOC3, 0x208) + FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC3, DCR, 0, 8) + FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC3, BCR, 8, 8) +REG32(DEVICE_CHARACTERISTIC_TABLE_LOC4, 0x20c) + FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC4, DEV_DYNAMIC_ADDR, 0, 8) +/* Dev addr table fields */ +REG32(DEVICE_ADDR_TABLE_LOC1, 0x280) + FIELD(DEVICE_ADDR_TABLE_LOC1, DEV_STATIC_ADDR, 0, 7) + FIELD(DEVICE_ADDR_TABLE_LOC1, IBI_PEC_EN, 11, 1) + FIELD(DEVICE_ADDR_TABLE_LOC1, IBI_WITH_DATA, 12, 1) + FIELD(DEVICE_ADDR_TABLE_LOC1, SIR_REJECT, 13, 1) + FIELD(DEVICE_ADDR_TABLE_LOC1, MR_REJECT, 14, 1) + FIELD(DEVICE_ADDR_TABLE_LOC1, DEV_DYNAMIC_ADDR, 16, 8) + FIELD(DEVICE_ADDR_TABLE_LOC1, IBI_ADDR_MASK, 24, 2) + FIELD(DEVICE_ADDR_TABLE_LOC1, DEV_NACK_RETRY_CNT, 29, 2) + FIELD(DEVICE_ADDR_TABLE_LOC1, LEGACY_I2C_DEVICE, 31, 1) static const uint32_t dw_i3c_resets[DW_I3C_NR_REGS] = { [R_HW_CAPABILITY] = 0x000e00bf, -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> Adds the rest of the Aspeed I3C controller register fields. Signed-off-by: Joe Komlodi <komlodi@google.com> Reviewed-by: Patrick Venture <venture@google.com> Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Tested-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260225021158.1586584-7-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- hw/i3c/aspeed_i3c.c | 54 +++++++++++++++++++++++++++++++++++---------- 1 file changed, 42 insertions(+), 12 deletions(-) diff --git a/hw/i3c/aspeed_i3c.c b/hw/i3c/aspeed_i3c.c index XXXXXXX..XXXXXXX 100644 --- a/hw/i3c/aspeed_i3c.c +++ b/hw/i3c/aspeed_i3c.c @@ -XXX,XX +XXX,XX @@ /* I3C Controller Registers */ REG32(I3C1_REG0, 0x10) REG32(I3C1_REG1, 0x14) - FIELD(I3C1_REG1, I2C_MODE, 0, 1) - FIELD(I3C1_REG1, SA_EN, 15, 1) + FIELD(I3C1_REG1, I2C_MODE, 0, 1) + FIELD(I3C1_REG1, SLV_TEST_MODE, 1, 1) + FIELD(I3C1_REG1, ACT_MODE, 2, 2) + FIELD(I3C1_REG1, PENDING_INT, 4, 4) + FIELD(I3C1_REG1, SA, 8, 7) + FIELD(I3C1_REG1, SA_EN, 15, 1) + FIELD(I3C1_REG1, INST_ID, 16, 4) REG32(I3C2_REG0, 0x20) REG32(I3C2_REG1, 0x24) - FIELD(I3C2_REG1, I2C_MODE, 0, 1) - FIELD(I3C2_REG1, SA_EN, 15, 1) + FIELD(I3C2_REG1, I2C_MODE, 0, 1) + FIELD(I3C2_REG1, SLV_TEST_MODE, 1, 1) + FIELD(I3C2_REG1, ACT_MODE, 2, 2) + FIELD(I3C2_REG1, PENDING_INT, 4, 4) + FIELD(I3C2_REG1, SA, 8, 7) + FIELD(I3C2_REG1, SA_EN, 15, 1) + FIELD(I3C2_REG1, INST_ID, 16, 4) REG32(I3C3_REG0, 0x30) REG32(I3C3_REG1, 0x34) - FIELD(I3C3_REG1, I2C_MODE, 0, 1) - FIELD(I3C3_REG1, SA_EN, 15, 1) + FIELD(I3C3_REG1, I2C_MODE, 0, 1) + FIELD(I3C3_REG1, SLV_TEST_MODE, 1, 1) + FIELD(I3C3_REG1, ACT_MODE, 2, 2) + FIELD(I3C3_REG1, PENDING_INT, 4, 4) + FIELD(I3C3_REG1, SA, 8, 7) + FIELD(I3C3_REG1, SA_EN, 15, 1) + FIELD(I3C3_REG1, INST_ID, 16, 4) REG32(I3C4_REG0, 0x40) REG32(I3C4_REG1, 0x44) - FIELD(I3C4_REG1, I2C_MODE, 0, 1) - FIELD(I3C4_REG1, SA_EN, 15, 1) + FIELD(I3C4_REG1, I2C_MODE, 0, 1) + FIELD(I3C4_REG1, SLV_TEST_MODE, 1, 1) + FIELD(I3C4_REG1, ACT_MODE, 2, 2) + FIELD(I3C4_REG1, PENDING_INT, 4, 4) + FIELD(I3C4_REG1, SA, 8, 7) + FIELD(I3C4_REG1, SA_EN, 15, 1) + FIELD(I3C4_REG1, INST_ID, 16, 4) REG32(I3C5_REG0, 0x50) REG32(I3C5_REG1, 0x54) - FIELD(I3C5_REG1, I2C_MODE, 0, 1) - FIELD(I3C5_REG1, SA_EN, 15, 1) + FIELD(I3C5_REG1, I2C_MODE, 0, 1) + FIELD(I3C5_REG1, SLV_TEST_MODE, 1, 1) + FIELD(I3C5_REG1, ACT_MODE, 2, 2) + FIELD(I3C5_REG1, PENDING_INT, 4, 4) + FIELD(I3C5_REG1, SA, 8, 7) + FIELD(I3C5_REG1, SA_EN, 15, 1) + FIELD(I3C5_REG1, INST_ID, 16, 4) REG32(I3C6_REG0, 0x60) REG32(I3C6_REG1, 0x64) - FIELD(I3C6_REG1, I2C_MODE, 0, 1) - FIELD(I3C6_REG1, SA_EN, 15, 1) + FIELD(I3C6_REG1, I2C_MODE, 0, 1) + FIELD(I3C6_REG1, SLV_TEST_MODE, 1, 1) + FIELD(I3C6_REG1, ACT_MODE, 2, 2) + FIELD(I3C6_REG1, PENDING_INT, 4, 4) + FIELD(I3C6_REG1, SA, 8, 7) + FIELD(I3C6_REG1, SA_EN, 15, 1) + FIELD(I3C6_REG1, INST_ID, 16, 4) static uint64_t aspeed_i3c_read(void *opaque, hwaddr addr, unsigned int size) { -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> Adds reset values for the new registers added. Signed-off-by: Joe Komlodi <komlodi@google.com> Reviewed-by: Patrick Venture <venture@google.com> Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Tested-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260225021158.1586584-8-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- hw/i3c/dw-i3c.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c index XXXXXXX..XXXXXXX 100644 --- a/hw/i3c/dw-i3c.c +++ b/hw/i3c/dw-i3c.c @@ -XXX,XX +XXX,XX @@ REG32(DEVICE_ADDR_TABLE_LOC1, 0x280) FIELD(DEVICE_ADDR_TABLE_LOC1, LEGACY_I2C_DEVICE, 31, 1) static const uint32_t dw_i3c_resets[DW_I3C_NR_REGS] = { - [R_HW_CAPABILITY] = 0x000e00bf, + /* Target mode is not supported, don't advertise it for now. */ + [R_HW_CAPABILITY] = 0x000e00b9, [R_QUEUE_THLD_CTRL] = 0x01000101, + [R_DATA_BUFFER_THLD_CTRL] = 0x01010100, + [R_SLV_EVENT_CTRL] = 0x0000000b, + [R_QUEUE_STATUS_LEVEL] = 0x00000002, + [R_DATA_BUFFER_STATUS_LEVEL] = 0x00000010, + [R_PRESENT_STATE] = 0x00000003, [R_I3C_VER_ID] = 0x3130302a, [R_I3C_VER_TYPE] = 0x6c633033, [R_DEVICE_ADDR_TABLE_POINTER] = 0x00080280, [R_DEV_CHAR_TABLE_POINTER] = 0x00020200, + [R_SLV_CHAR_CTRL] = 0x00010000, [A_VENDOR_SPECIFIC_REG_POINTER] = 0x000000b0, [R_SLV_MAX_LEN] = 0x00ff00ff, + [R_SLV_TSX_SYMBL_TIMING] = 0x0000003f, + [R_SCL_I3C_OD_TIMING] = 0x000a0010, + [R_SCL_I3C_PP_TIMING] = 0x000a000a, + [R_SCL_I2C_FM_TIMING] = 0x00100010, + [R_SCL_I2C_FMP_TIMING] = 0x00100010, + [R_SCL_EXT_LCNT_TIMING] = 0x20202020, + [R_SCL_EXT_TERMN_LCNT_TIMING] = 0x00300000, + [R_BUS_FREE_TIMING] = 0x00200020, + [R_BUS_IDLE_TIMING] = 0x00000020, + [R_EXTENDED_CAPABILITY] = 0x00000239, + [R_SLAVE_CONFIG] = 0x00000023, }; static uint64_t dw_i3c_read(void *opaque, hwaddr offset, unsigned size) -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> Adds read-only register masks for the Aspeed I3C controller registers. Signed-off-by: Joe Komlodi <komlodi@google.com> Reviewed-by: Patrick Venture <venture@google.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Tested-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260225021158.1586584-9-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- hw/i3c/aspeed_i3c.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/hw/i3c/aspeed_i3c.c b/hw/i3c/aspeed_i3c.c index XXXXXXX..XXXXXXX 100644 --- a/hw/i3c/aspeed_i3c.c +++ b/hw/i3c/aspeed_i3c.c @@ -XXX,XX +XXX,XX @@ REG32(I3C6_REG1, 0x64) FIELD(I3C6_REG1, SA_EN, 15, 1) FIELD(I3C6_REG1, INST_ID, 16, 4) +static const uint32_t ast2600_i3c_controller_ro[ASPEED_I3C_NR_REGS] = { + [R_I3C1_REG0] = 0xcc000000, + [R_I3C1_REG1] = 0xfff00000, + [R_I3C2_REG0] = 0xcc000000, + [R_I3C2_REG1] = 0xfff00000, + [R_I3C3_REG0] = 0xcc000000, + [R_I3C3_REG1] = 0xfff00000, + [R_I3C4_REG0] = 0xcc000000, + [R_I3C4_REG1] = 0xfff00000, + [R_I3C5_REG0] = 0xcc000000, + [R_I3C5_REG1] = 0xfff00000, + [R_I3C6_REG0] = 0xcc000000, + [R_I3C6_REG1] = 0xfff00000, +}; + static uint64_t aspeed_i3c_read(void *opaque, hwaddr addr, unsigned int size) { AspeedI3CState *s = ASPEED_I3C(opaque); @@ -XXX,XX +XXX,XX @@ static void aspeed_i3c_write(void *opaque, addr >>= 2; + data &= ~ast2600_i3c_controller_ro[addr]; /* I3C controller register */ switch (addr) { case R_I3C1_REG1: -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> Adds read-only register masks for the DwC I3C controller. Signed-off-by: Joe Komlodi <komlodi@google.com> Reviewed-by: Patrick Venture <venture@google.com> Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Tested-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260225021158.1586584-10-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- hw/i3c/dw-i3c.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c index XXXXXXX..XXXXXXX 100644 --- a/hw/i3c/dw-i3c.c +++ b/hw/i3c/dw-i3c.c @@ -XXX,XX +XXX,XX @@ static const uint32_t dw_i3c_resets[DW_I3C_NR_REGS] = { [R_SLAVE_CONFIG] = 0x00000023, }; +static const uint32_t dw_i3c_ro[DW_I3C_NR_REGS] = { + [R_DEVICE_CTRL] = 0x04fffe00, + [R_DEVICE_ADDR] = 0x7f807f80, + [R_HW_CAPABILITY] = 0xffffffff, + [R_IBI_QUEUE_STATUS] = 0xffffffff, + [R_DATA_BUFFER_THLD_CTRL] = 0xf8f8f8f8, + [R_IBI_QUEUE_CTRL] = 0xfffffff0, + [R_RESET_CTRL] = 0xffffffc0, + [R_SLV_EVENT_CTRL] = 0xffffff3f, + [R_INTR_STATUS] = 0xffff809f, + [R_INTR_STATUS_EN] = 0xffff8080, + [R_INTR_SIGNAL_EN] = 0xffff8080, + [R_INTR_FORCE] = 0xffff8000, + [R_QUEUE_STATUS_LEVEL] = 0xffffffff, + [R_DATA_BUFFER_STATUS_LEVEL] = 0xffffffff, + [R_PRESENT_STATE] = 0xffffffff, + [R_CCC_DEVICE_STATUS] = 0xffffffff, + [R_I3C_VER_ID] = 0xffffffff, + [R_I3C_VER_TYPE] = 0xffffffff, + [R_DEVICE_ADDR_TABLE_POINTER] = 0xffffffff, + [R_DEV_CHAR_TABLE_POINTER] = 0xffcbffff, + [R_SLV_PID_VALUE] = 0xffff0fff, + [R_SLV_CHAR_CTRL] = 0xffffffff, + [A_VENDOR_SPECIFIC_REG_POINTER] = 0xffffffff, + [R_SLV_MAX_LEN] = 0xffffffff, + [R_MAX_READ_TURNAROUND] = 0xffffffff, + [R_MAX_DATA_SPEED] = 0xffffffff, + [R_SLV_INTR_REQ] = 0xfffffff0, + [R_SLV_TSX_SYMBL_TIMING] = 0xffffffc0, + [R_DEVICE_CTRL_EXTENDED] = 0xfffffff8, + [R_SCL_I3C_OD_TIMING] = 0xff00ff00, + [R_SCL_I3C_PP_TIMING] = 0xff00ff00, + [R_SCL_I2C_FMP_TIMING] = 0xff000000, + [R_SCL_EXT_TERMN_LCNT_TIMING] = 0x0000fff0, + [R_BUS_IDLE_TIMING] = 0xfff00000, + [R_EXTENDED_CAPABILITY] = 0xffffffff, + [R_SLAVE_CONFIG] = 0xffffffff, +}; + static uint64_t dw_i3c_read(void *opaque, hwaddr offset, unsigned size) { DWI3C *s = DW_I3C(opaque); @@ -XXX,XX +XXX,XX @@ static void dw_i3c_write(void *opaque, hwaddr offset, uint64_t value, trace_dw_i3c_write(s->id, offset, value); + value &= ~dw_i3c_ro[addr]; switch (addr) { case R_HW_CAPABILITY: case R_RESPONSE_QUEUE_PORT: -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> RESET_CTRL and INTR_FORCE are write-only. Signed-off-by: Joe Komlodi <komlodi@google.com> Reviewed-by: Patrick Venture <venture@google.com> Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Tested-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260225021158.1586584-11-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- hw/i3c/dw-i3c.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c index XXXXXXX..XXXXXXX 100644 --- a/hw/i3c/dw-i3c.c +++ b/hw/i3c/dw-i3c.c @@ -XXX,XX +XXX,XX @@ static uint64_t dw_i3c_read(void *opaque, hwaddr offset, unsigned size) uint64_t value; switch (addr) { + /* RAZ */ case R_COMMAND_QUEUE_PORT: + case R_RESET_CTRL: + case R_INTR_FORCE: value = 0; break; default: -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> The registers are only 32 bits wide, so we should cast the 64-bit value passed in to only be 32 bits wide. Signed-off-by: Joe Komlodi <komlodi@google.com> Reviewed-by: Patrick Venture <venture@google.com> Reviewed-by: Titus Rwantare <titusr@google.com> Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Tested-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260225021158.1586584-12-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- hw/i3c/dw-i3c.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c index XXXXXXX..XXXXXXX 100644 --- a/hw/i3c/dw-i3c.c +++ b/hw/i3c/dw-i3c.c @@ -XXX,XX +XXX,XX @@ static void dw_i3c_write(void *opaque, hwaddr offset, uint64_t value, { DWI3C *s = DW_I3C(opaque); uint32_t addr = offset >> 2; + uint32_t val32 = (uint32_t)value; trace_dw_i3c_write(s->id, offset, value); - value &= ~dw_i3c_ro[addr]; + val32 &= ~dw_i3c_ro[addr]; switch (addr) { case R_HW_CAPABILITY: case R_RESPONSE_QUEUE_PORT: @@ -XXX,XX +XXX,XX @@ static void dw_i3c_write(void *opaque, hwaddr offset, uint64_t value, case R_RESET_CTRL: break; default: - s->regs[addr] = value; + s->regs[addr] = val32; break; } } -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Joe Komlodi <komlodi@google.com> Reviewed-by: Patrick Venture <venture@google.com> Reviewed-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Tested-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260225021158.1586584-13-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- hw/i3c/dw-i3c.c | 56 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c index XXXXXXX..XXXXXXX 100644 --- a/hw/i3c/dw-i3c.c +++ b/hw/i3c/dw-i3c.c @@ -XXX,XX +XXX,XX @@ #include "qapi/error.h" #include "migration/vmstate.h" #include "trace.h" +#include "hw/core/irq.h" REG32(DEVICE_CTRL, 0x00) FIELD(DEVICE_CTRL, I3C_BROADCAST_ADDR_INC, 0, 1) @@ -XXX,XX +XXX,XX @@ static const uint32_t dw_i3c_ro[DW_I3C_NR_REGS] = { [R_SLAVE_CONFIG] = 0xffffffff, }; +static void dw_i3c_update_irq(DWI3C *s) +{ + bool level = !!(s->regs[R_INTR_SIGNAL_EN] & s->regs[R_INTR_STATUS]); + qemu_set_irq(s->irq, level); +} + +static uint32_t dw_i3c_intr_status_r(DWI3C *s) +{ + /* Only return the status whose corresponding EN bits are set. */ + return s->regs[R_INTR_STATUS] & s->regs[R_INTR_STATUS_EN]; +} + +static void dw_i3c_intr_status_w(DWI3C *s, uint32_t val) +{ + /* INTR_STATUS[13:5] is w1c, other bits are RO. */ + val &= 0x3fe0; + s->regs[R_INTR_STATUS] &= ~val; + + dw_i3c_update_irq(s); +} + +static void dw_i3c_intr_status_en_w(DWI3C *s, uint32_t val) +{ + s->regs[R_INTR_STATUS_EN] = val; + dw_i3c_update_irq(s); +} + +static void dw_i3c_intr_signal_en_w(DWI3C *s, uint32_t val) +{ + s->regs[R_INTR_SIGNAL_EN] = val; + dw_i3c_update_irq(s); +} + +static void dw_i3c_intr_force_w(DWI3C *s, uint32_t val) +{ + /* INTR_FORCE is WO, just set the corresponding INTR_STATUS bits. */ + s->regs[R_INTR_STATUS] = val; + dw_i3c_update_irq(s); +} + static uint64_t dw_i3c_read(void *opaque, hwaddr offset, unsigned size) { DWI3C *s = DW_I3C(opaque); @@ -XXX,XX +XXX,XX @@ static uint64_t dw_i3c_read(void *opaque, hwaddr offset, unsigned size) case R_INTR_FORCE: value = 0; break; + case R_INTR_STATUS: + value = dw_i3c_intr_status_r(s); + break; default: value = s->regs[addr]; break; @@ -XXX,XX +XXX,XX @@ static void dw_i3c_write(void *opaque, hwaddr offset, uint64_t value, break; case R_RESET_CTRL: break; + case R_INTR_STATUS: + dw_i3c_intr_status_w(s, val32); + break; + case R_INTR_STATUS_EN: + dw_i3c_intr_status_en_w(s, val32); + break; + case R_INTR_SIGNAL_EN: + dw_i3c_intr_signal_en_w(s, val32); + break; + case R_INTR_FORCE: + dw_i3c_intr_force_w(s, val32); + break; default: s->regs[addr] = val32; break; -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> This adds data and CCC transmission, reception, and the associated queues required for data transmission and reception to happen. The I3C controller transmits data by the user writing into a command queue. When the queue has a command and an argument in it, the controller starts executing the command. The controller can execute 1 of 3 ways: 1. A larger data transfer that involves using the TX and RX queues. This is the most common way the controller does transactions. 2. A small data transfer that involves sending a couple bytes passed into the command queue argument. 3. An address assignment command. This is how the controller does ENTDAA. When ENTDAA succeeds in assigning an address to a target, it updates the controller's char table with the target's PID, BCR, and DCR. The controller determines what addresses to send by looking at the index in the device address table specified by the argument in the command queue. ENTDAA also uses these addresses to assign to targets on the bus. When the controller is done executing a command, it puts a response in the response queue indicating how command execution went. In order for the user to send and receive data to/from the controller, the user reads/writes to a bidirectional TX/RX port. Signed-off-by: Joe Komlodi <komlodi@google.com> Reviewed-by: Stephen Longfield <slongfield@google.com> Reviewed-by: Patrick Venture <venture@google.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Tested-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260225021158.1586584-14-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- include/hw/i3c/aspeed_i3c.h | 1 + include/hw/i3c/dw-i3c.h | 143 +++++- hw/i3c/dw-i3c.c | 882 +++++++++++++++++++++++++++++++++++- hw/i3c/trace-events | 10 + 4 files changed, 1030 insertions(+), 6 deletions(-) diff --git a/include/hw/i3c/aspeed_i3c.h b/include/hw/i3c/aspeed_i3c.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/i3c/aspeed_i3c.h +++ b/include/hw/i3c/aspeed_i3c.h @@ -XXX,XX +XXX,XX @@ * ASPEED I3C Controller * * Copyright (C) 2021 ASPEED Technology Inc. + * Copyright (C) 2023 Google, LLC * * This code is licensed under the GPL version 2 or later. See * the COPYING file in the top-level directory. diff --git a/include/hw/i3c/dw-i3c.h b/include/hw/i3c/dw-i3c.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/i3c/dw-i3c.h +++ b/include/hw/i3c/dw-i3c.h @@ -XXX,XX +XXX,XX @@ #ifndef DW_I3C_H #define DW_I3C_H +#include "qemu/fifo32.h" +#include "hw/i3c/i3c.h" #include "hw/core/sysbus.h" #define TYPE_DW_I3C "dw.i3c" OBJECT_DECLARE_SIMPLE_TYPE(DWI3C, DW_I3C) -#define DW_I3C_NR_REGS (0x300 >> 2) +/* + * Sufficiently large enough to handle configurations with large device address + * tables. + */ +#define DW_I3C_NR_REGS (0x1000 >> 2) + +/* From datasheet. */ +#define DW_I3C_CMD_ATTR_TRANSFER_CMD 0 +#define DW_I3C_CMD_ATTR_TRANSFER_ARG 1 +#define DW_I3C_CMD_ATTR_SHORT_DATA_ARG 2 +#define DW_I3C_CMD_ATTR_ADDR_ASSIGN_CMD 3 + +/* Enum values from datasheet. */ +typedef enum DWI3CRespQueueErr { + DW_I3C_RESP_QUEUE_ERR_NONE = 0, + DW_I3C_RESP_QUEUE_ERR_CRC = 1, + DW_I3C_RESP_QUEUE_ERR_PARITY = 2, + DW_I3C_RESP_QUEUE_ERR_FRAME = 3, + DW_I3C_RESP_QUEUE_ERR_BROADCAST_NACK = 4, + DW_I3C_RESP_QUEUE_ERR_DAA_NACK = 5, + DW_I3C_RESP_QUEUE_ERR_OVERFLOW = 6, + DW_I3C_RESP_QUEUE_ERR_ABORTED = 8, + DW_I3C_RESP_QUEUE_ERR_I2C_NACK = 9, +} DWI3CRespQueueErr; + +typedef enum DWI3CTransferState { + DW_I3C_TRANSFER_STATE_IDLE = 0x00, + DW_I3C_TRANSFER_STATE_START = 0x01, + DW_I3C_TRANSFER_STATE_RESTART = 0x02, + DW_I3C_TRANSFER_STATE_STOP = 0x03, + DW_I3C_TRANSFER_STATE_START_HOLD = 0x04, + DW_I3C_TRANSFER_STATE_BROADCAST_W = 0x05, + DW_I3C_TRANSFER_STATE_BROADCAST_R = 0x06, + DW_I3C_TRANSFER_STATE_DAA = 0x07, + DW_I3C_TRANSFER_STATE_DAA_GEN = 0x08, + DW_I3C_TRANSFER_STATE_CCC_BYTE = 0x0b, + DW_I3C_TRANSFER_STATE_HDR_CMD = 0x0c, + DW_I3C_TRANSFER_STATE_WRITE = 0x0d, + DW_I3C_TRANSFER_STATE_READ = 0x0e, + DW_I3C_TRANSFER_STATE_IBI_READ = 0x0f, + DW_I3C_TRANSFER_STATE_IBI_DIS = 0x10, + DW_I3C_TRANSFER_STATE_HDR_DDR_CRC = 0x11, + DW_I3C_TRANSFER_STATE_CLK_STRETCH = 0x12, + DW_I3C_TRANSFER_STATE_HALT = 0x13, +} DWI3CTransferState; + +typedef enum DWI3CTransferStatus { + DW_I3C_TRANSFER_STATUS_IDLE = 0x00, + DW_I3C_TRANSFER_STATUS_BROACAST_CCC = 0x01, + DW_I3C_TRANSFER_STATUS_DIRECT_CCC_W = 0x02, + DW_I3C_TRANSFER_STATUS_DIRECT_CCC_R = 0x03, + DW_I3C_TRANSFER_STATUS_ENTDAA = 0x04, + DW_I3C_TRANSFER_STATUS_SETDASA = 0x05, + DW_I3C_TRANSFER_STATUS_I3C_SDR_W = 0x06, + DW_I3C_TRANSFER_STATUS_I3C_SDR_R = 0x07, + DW_I3C_TRANSFER_STATUS_I2C_SDR_W = 0x08, + DW_I3C_TRANSFER_STATUS_I2C_SDR_R = 0x09, + DW_I3C_TRANSFER_STATUS_HDR_TS_W = 0x0a, + DW_I3C_TRANSFER_STATUS_HDR_TS_R = 0x0b, + DW_I3C_TRANSFER_STATUS_HDR_DDR_W = 0x0c, + DW_I3C_TRANSFER_STATUS_HDR_DDR_R = 0x0d, + DW_I3C_TRANSFER_STATUS_IBI = 0x0e, + DW_I3C_TRANSFER_STATUS_HALT = 0x0f, +} DWI3CTransferStatus; + +/* + * Transfer commands and arguments are 32-bit wide values that the user passes + * into the command queue. We interpret each 32-bit word based on the cmd_attr + * field. + */ +typedef struct DWI3CTransferCmd { + uint8_t cmd_attr:3; + uint8_t tid:4; /* Transaction ID */ + uint16_t cmd:8; + uint8_t cp:1; /* Command present */ + uint8_t dev_index:5; + uint8_t speed:3; + uint8_t resv0:1; + uint8_t dbp:1; /* Defining byte present */ + uint8_t roc:1; /* Response on completion */ + uint8_t sdap:1; /* Short data argument present */ + uint8_t rnw:1; /* Read not write */ + uint8_t resv1:1; + uint8_t toc:1; /* Termination (I3C STOP) on completion */ + uint8_t pec:1; /* Parity error check enabled */ +} DWI3CTransferCmd; + +typedef struct DWI3CTransferArg { + uint8_t cmd_attr:3; + uint8_t resv:5; + uint8_t db; /* Defining byte */ + uint16_t data_len; +} DWI3CTransferArg; + +typedef struct DWI3CShortArg { + uint8_t cmd_attr:3; + uint8_t byte_strb:3; + uint8_t resv:2; + uint8_t byte0; + uint8_t byte1; + uint8_t byte2; +} DWI3CShortArg; + +typedef struct DWI3CAddrAssignCmd { + uint8_t cmd_attr:3; + uint8_t tid:4; /* Transaction ID */ + uint16_t cmd:8; + uint8_t resv0:1; + uint8_t dev_index:5; + uint16_t dev_count:5; + uint8_t roc:1; /* Response on completion */ + uint8_t resv1:3; + uint8_t toc:1; /* Termination (I3C STOP) on completion */ + uint8_t resv2:1; +} DWI3CAddrAssignCmd; + +typedef union DWI3CCmdQueueData { + uint32_t word; + DWI3CTransferCmd transfer_cmd; + DWI3CTransferArg transfer_arg; + DWI3CShortArg short_arg; + DWI3CAddrAssignCmd addr_assign_cmd; +} DWI3CCmdQueueData; struct DWI3C { SysBusDevice parent_obj; MemoryRegion mr; qemu_irq irq; + I3CBus *bus; + + Fifo32 cmd_queue; + Fifo32 resp_queue; + Fifo32 tx_queue; + Fifo32 rx_queue; - uint8_t id; + struct { + uint8_t id; + uint8_t cmd_resp_queue_capacity_bytes; + uint16_t tx_rx_queue_capacity_bytes; + uint8_t num_addressable_devices; + uint16_t dev_addr_table_pointer; + uint16_t dev_addr_table_depth; + uint16_t dev_char_table_pointer; + uint16_t dev_char_table_depth; + } cfg; uint32_t regs[DW_I3C_NR_REGS]; }; diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c index XXXXXXX..XXXXXXX 100644 --- a/hw/i3c/dw-i3c.c +++ b/hw/i3c/dw-i3c.c @@ -XXX,XX +XXX,XX @@ static const uint32_t dw_i3c_ro[DW_I3C_NR_REGS] = { [R_SLAVE_CONFIG] = 0xffffffff, }; +static inline bool dw_i3c_has_hdr_ts(DWI3C *s) +{ + return ARRAY_FIELD_EX32(s->regs, HW_CAPABILITY, HDR_TS); +} + +static inline bool dw_i3c_has_hdr_ddr(DWI3C *s) +{ + return ARRAY_FIELD_EX32(s->regs, HW_CAPABILITY, HDR_DDR); +} + +static inline bool dw_i3c_can_transmit(DWI3C *s) +{ + /* + * We can only transmit if we're enabled and the resume bit is cleared. + * The resume bit is set on a transaction error, and software must clear it. + */ + return ARRAY_FIELD_EX32(s->regs, DEVICE_CTRL, I3C_EN) && + !ARRAY_FIELD_EX32(s->regs, DEVICE_CTRL, I3C_RESUME); +} + +static inline uint8_t dw_i3c_fifo_threshold_from_reg(uint8_t regval) +{ + return regval = regval ? (2 << regval) : 1; +} + static void dw_i3c_update_irq(DWI3C *s) { bool level = !!(s->regs[R_INTR_SIGNAL_EN] & s->regs[R_INTR_STATUS]); qemu_set_irq(s->irq, level); } +static void dw_i3c_end_transfer(DWI3C *s, bool is_i2c) +{ + if (is_i2c) { + legacy_i2c_end_transfer(s->bus); + } else { + i3c_end_transfer(s->bus); + } +} + +static int dw_i3c_send_start(DWI3C *s, uint8_t addr, bool is_recv, bool is_i2c) +{ + int ret; + + if (is_i2c) { + ret = legacy_i2c_start_transfer(s->bus, addr, is_recv); + } else { + ret = i3c_start_transfer(s->bus, addr, is_recv); + } + if (ret) { + g_autofree char *path = object_get_canonical_path(OBJECT(s)); + qemu_log_mask(LOG_GUEST_ERROR, "%s: NACKed on TX with addr 0x%.2x\n", + path, addr); + ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, + DW_I3C_TRANSFER_STATE_HALT); + ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_STATUS, + DW_I3C_TRANSFER_STATUS_HALT); + ARRAY_FIELD_DP32(s->regs, INTR_STATUS, TRANSFER_ERR, 1); + ARRAY_FIELD_DP32(s->regs, DEVICE_CTRL, I3C_RESUME, 1); + } + + return ret; +} + +static int dw_i3c_send(DWI3C *s, const uint8_t *data, uint32_t num_to_send, + uint32_t *num_sent, bool is_i2c) +{ + int ret; + uint32_t i; + + *num_sent = 0; + if (is_i2c) { + /* Legacy I2C must be byte-by-byte. */ + for (i = 0; i < num_to_send; i++) { + ret = legacy_i2c_send(s->bus, data[i]); + if (ret) { + break; + } + (*num_sent)++; + } + } else { + ret = i3c_send(s->bus, data, num_to_send, num_sent); + } + if (ret) { + g_autofree char *path = object_get_canonical_path(OBJECT(s)); + qemu_log_mask(LOG_GUEST_ERROR, "%s: NACKed sending byte 0x%.2x\n", + path, data[*num_sent]); + ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, + DW_I3C_TRANSFER_STATE_HALT); + ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_STATUS, + DW_I3C_TRANSFER_STATUS_HALT); + ARRAY_FIELD_DP32(s->regs, INTR_STATUS, TRANSFER_ERR, 1); + ARRAY_FIELD_DP32(s->regs, DEVICE_CTRL, I3C_RESUME, 1); + } + + trace_dw_i3c_send(s->cfg.id, *num_sent); + + return ret; +} + +static int dw_i3c_send_byte(DWI3C *s, uint8_t byte, bool is_i2c) +{ + /* + * Ignored, the caller will know if we sent 0 or 1 bytes depending on if + * we were ACKed/NACKed. + */ + uint32_t num_sent; + return dw_i3c_send(s, &byte, 1, &num_sent, is_i2c); +} + +static int dw_i3c_recv_data(DWI3C *s, bool is_i2c, uint8_t *data, + uint16_t num_to_read, uint32_t *num_read) +{ + int ret; + + if (is_i2c) { + for (uint16_t i = 0; i < num_to_read; i++) { + data[i] = legacy_i2c_recv(s->bus); + } + /* I2C devices can neither NACK a read, nor end transfers early. */ + *num_read = num_to_read; + trace_dw_i3c_recv_data(s->cfg.id, *num_read); + return 0; + } + /* I3C devices can NACK if the controller sends an unsupported CCC. */ + ret = i3c_recv(s->bus, data, num_to_read, num_read); + if (ret) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: NACKed receiving byte\n", + object_get_canonical_path(OBJECT(s))); + ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, + DW_I3C_TRANSFER_STATE_HALT); + ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_STATUS, + DW_I3C_TRANSFER_STATUS_HALT); + ARRAY_FIELD_DP32(s->regs, INTR_STATUS, TRANSFER_ERR, 1); + ARRAY_FIELD_DP32(s->regs, DEVICE_CTRL, I3C_RESUME, 1); + } + + trace_dw_i3c_recv_data(s->cfg.id, *num_read); + + return ret; +} + +static inline bool dw_i3c_target_is_i2c(DWI3C *s, uint16_t offset) +{ + /* / sizeof(uint32_t) because we're indexing into our 32-bit reg array. */ + uint16_t dev_index = (ARRAY_FIELD_EX32(s->regs, DEVICE_ADDR_TABLE_POINTER, + ADDR) / sizeof(uint32_t)) + offset; + return FIELD_EX32(s->regs[dev_index], DEVICE_ADDR_TABLE_LOC1, + LEGACY_I2C_DEVICE); +} + +static uint8_t dw_i3c_target_addr(DWI3C *s, uint16_t offset) +{ + if (offset > s->cfg.num_addressable_devices) { + g_autofree char *path = object_get_canonical_path(OBJECT(s)); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Device addr table offset %d out of " + "bounds\n", path, offset); + /* If we're out of bounds, return an address of 0. */ + return 0; + } + + /* / sizeof(uint32_t) because we're indexing into our 32-bit reg array. */ + uint16_t dev_index = (ARRAY_FIELD_EX32(s->regs, DEVICE_ADDR_TABLE_POINTER, + ADDR) / sizeof(uint32_t)) + offset; + /* I2C devices use a static address. */ + if (dw_i3c_target_is_i2c(s, offset)) { + return FIELD_EX32(s->regs[dev_index], DEVICE_ADDR_TABLE_LOC1, + DEV_STATIC_ADDR); + } + return FIELD_EX32(s->regs[dev_index], DEVICE_ADDR_TABLE_LOC1, + DEV_DYNAMIC_ADDR); +} + static uint32_t dw_i3c_intr_status_r(DWI3C *s) { /* Only return the status whose corresponding EN bits are set. */ @@ -XXX,XX +XXX,XX @@ static void dw_i3c_intr_force_w(DWI3C *s, uint32_t val) dw_i3c_update_irq(s); } +static uint32_t dw_i3c_pop_rx(DWI3C *s) +{ + if (fifo32_is_empty(&s->rx_queue)) { + g_autofree char *path = object_get_canonical_path(OBJECT(s)); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Tried to read RX FIFO when empty\n", + path); + return 0; + } + + uint32_t val = fifo32_pop(&s->rx_queue); + ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, RX_BUF_BLR, + fifo32_num_used(&s->rx_queue)); + + /* Threshold is 2^RX_BUF_THLD. */ + uint8_t threshold = ARRAY_FIELD_EX32(s->regs, DATA_BUFFER_THLD_CTRL, + RX_BUF_THLD); + threshold = dw_i3c_fifo_threshold_from_reg(threshold); + if (fifo32_num_used(&s->rx_queue) < threshold) { + ARRAY_FIELD_DP32(s->regs, INTR_STATUS, RX_THLD, 0); + dw_i3c_update_irq(s); + } + + trace_dw_i3c_pop_rx(s->cfg.id, val); + return val; +} + +static uint32_t dw_i3c_resp_queue_port_r(DWI3C *s) +{ + if (fifo32_is_empty(&s->resp_queue)) { + g_autofree char *path = object_get_canonical_path(OBJECT(s)); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Tried to read response FIFO when " + "empty\n", path); + return 0; + } + + uint32_t val = fifo32_pop(&s->resp_queue); + ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, RESP_BUF_BLR, + fifo32_num_used(&s->resp_queue)); + + /* Threshold is the register value + 1. */ + uint8_t threshold = ARRAY_FIELD_EX32(s->regs, QUEUE_THLD_CTRL, + RESP_BUF_THLD) + 1; + if (fifo32_num_used(&s->resp_queue) < threshold) { + ARRAY_FIELD_DP32(s->regs, INTR_STATUS, RESP_RDY, 0); + dw_i3c_update_irq(s); + } + + return val; +} + static uint64_t dw_i3c_read(void *opaque, hwaddr offset, unsigned size) { DWI3C *s = DW_I3C(opaque); @@ -XXX,XX +XXX,XX @@ static uint64_t dw_i3c_read(void *opaque, hwaddr offset, unsigned size) case R_INTR_STATUS: value = dw_i3c_intr_status_r(s); break; + case R_RX_TX_DATA_PORT: + value = dw_i3c_pop_rx(s); + break; + case R_RESPONSE_QUEUE_PORT: + value = dw_i3c_resp_queue_port_r(s); + break; default: value = s->regs[addr]; break; } - trace_dw_i3c_read(s->id, offset, value); + trace_dw_i3c_read(s->cfg.id, offset, value); return value; } +static void dw_i3c_resp_queue_push(DWI3C *s, uint8_t err, uint8_t tid, + uint8_t ccc_type, uint16_t data_len) +{ + uint32_t val = 0; + val = FIELD_DP32(val, RESPONSE_QUEUE_PORT, ERR_STATUS, err); + val = FIELD_DP32(val, RESPONSE_QUEUE_PORT, TID, tid); + val = FIELD_DP32(val, RESPONSE_QUEUE_PORT, CCCT, ccc_type); + val = FIELD_DP32(val, RESPONSE_QUEUE_PORT, DL, data_len); + if (!fifo32_is_full(&s->resp_queue)) { + trace_dw_i3c_resp_queue_push(s->cfg.id, val); + fifo32_push(&s->resp_queue, val); + } + + ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, RESP_BUF_BLR, + fifo32_num_used(&s->resp_queue)); + /* Threshold is the register value + 1. */ + uint8_t threshold = ARRAY_FIELD_EX32(s->regs, QUEUE_THLD_CTRL, + RESP_BUF_THLD) + 1; + if (fifo32_num_used(&s->resp_queue) >= threshold) { + ARRAY_FIELD_DP32(s->regs, INTR_STATUS, RESP_RDY, 1); + dw_i3c_update_irq(s); + } +} + +static void dw_i3c_push_tx(DWI3C *s, uint32_t val) +{ + if (fifo32_is_full(&s->tx_queue)) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Tried to push to TX FIFO when " + "full\n", object_get_canonical_path(OBJECT(s))); + return; + } + + trace_dw_i3c_push_tx(s->cfg.id, val); + fifo32_push(&s->tx_queue, val); + ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, TX_BUF_EMPTY_LOC, + fifo32_num_free(&s->tx_queue)); + + /* Threshold is 2^TX_BUF_THLD. */ + uint8_t empty_threshold = ARRAY_FIELD_EX32(s->regs, DATA_BUFFER_THLD_CTRL, + TX_BUF_THLD); + empty_threshold = + dw_i3c_fifo_threshold_from_reg(empty_threshold); + if (fifo32_num_free(&s->tx_queue) < empty_threshold) { + ARRAY_FIELD_DP32(s->regs, INTR_STATUS, TX_THLD, 0); + dw_i3c_update_irq(s); + } +} + +static uint32_t dw_i3c_pop_tx(DWI3C *s) +{ + if (fifo32_is_empty(&s->tx_queue)) { + g_autofree char *path = object_get_canonical_path(OBJECT(s)); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Tried to pop from TX FIFO when " + "empty\n", path); + return 0; + } + + uint32_t val = fifo32_pop(&s->tx_queue); + trace_dw_i3c_pop_tx(s->cfg.id, val); + ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, TX_BUF_EMPTY_LOC, + fifo32_num_free(&s->tx_queue)); + + /* Threshold is 2^TX_BUF_THLD. */ + uint8_t empty_threshold = ARRAY_FIELD_EX32(s->regs, DATA_BUFFER_THLD_CTRL, + TX_BUF_THLD); + empty_threshold = + dw_i3c_fifo_threshold_from_reg(empty_threshold); + if (fifo32_num_free(&s->tx_queue) >= empty_threshold) { + ARRAY_FIELD_DP32(s->regs, INTR_STATUS, TX_THLD, 1); + dw_i3c_update_irq(s); + } + return val; +} + +static void dw_i3c_push_rx(DWI3C *s, uint32_t val) +{ + if (fifo32_is_full(&s->rx_queue)) { + g_autofree char *path = object_get_canonical_path(OBJECT(s)); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Tried to push to RX FIFO when " + "full\n", path); + return; + } + trace_dw_i3c_push_rx(s->cfg.id, val); + fifo32_push(&s->rx_queue, val); + + ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, RX_BUF_BLR, + fifo32_num_used(&s->rx_queue)); + /* Threshold is 2^RX_BUF_THLD. */ + uint8_t threshold = ARRAY_FIELD_EX32(s->regs, DATA_BUFFER_THLD_CTRL, + RX_BUF_THLD); + threshold = dw_i3c_fifo_threshold_from_reg(threshold); + if (fifo32_num_used(&s->rx_queue) >= threshold) { + ARRAY_FIELD_DP32(s->regs, INTR_STATUS, RX_THLD, 1); + dw_i3c_update_irq(s); + } +} + +static void dw_i3c_short_transfer(DWI3C *s, DWI3CTransferCmd cmd, + DWI3CShortArg arg) +{ + uint8_t err = DW_I3C_RESP_QUEUE_ERR_NONE; + uint8_t addr = dw_i3c_target_addr(s, cmd.dev_index); + bool is_i2c = dw_i3c_target_is_i2c(s, cmd.dev_index); + uint8_t data[4]; /* Max we can send on a short transfer is 4 bytes. */ + uint8_t len = 0; + uint32_t bytes_sent; /* Ignored on short transfers. */ + + /* Can't do reads on a short transfer. */ + if (cmd.rnw) { + g_autofree char *path = object_get_canonical_path(OBJECT(s)); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Cannot do a read on a short " + "transfer\n", path); + return; + } + + if (dw_i3c_send_start(s, addr, /*is_recv=*/false, is_i2c)) { + err = DW_I3C_RESP_QUEUE_ERR_I2C_NACK; + goto transfer_done; + } + + /* Are we sending a command? */ + if (cmd.cp) { + data[len] = cmd.cmd; + len++; + /* + * byte0 is the defining byte for a command, and is only sent if a + * command is present and if the command has a defining byte present. + * (byte_strb & 0x01) is always treated as set by the controller, and is + * ignored. + */ + if (cmd.dbp) { + data[len] += arg.byte0; + len++; + } + } + + /* Send the bytes passed in the argument. */ + if (arg.byte_strb & 0x02) { + data[len] = arg.byte1; + len++; + } + if (arg.byte_strb & 0x04) { + data[len] = arg.byte2; + len++; + } + + if (dw_i3c_send(s, data, len, &bytes_sent, is_i2c)) { + err = DW_I3C_RESP_QUEUE_ERR_I2C_NACK; + } else { + /* Only go to an idle state on a successful transfer. */ + ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, + DW_I3C_TRANSFER_STATE_IDLE); + } + +transfer_done: + if (cmd.toc) { + dw_i3c_end_transfer(s, is_i2c); + } + if (cmd.roc) { + /* + * ccc_type is always 0 in controller mode, data_len is 0 in short + * transfers. + */ + dw_i3c_resp_queue_push(s, err, cmd.tid, /*ccc_type=*/0, + /*data_len=*/0); + } +} + +/* Returns number of bytes transmitted. */ +static uint16_t dw_i3c_tx(DWI3C *s, uint16_t num, bool is_i2c) +{ + uint16_t bytes_sent = 0; + union { + uint8_t b[sizeof(uint32_t)]; + uint32_t val; + } val32; + + while (bytes_sent < num) { + val32.val = dw_i3c_pop_tx(s); + for (uint8_t i = 0; i < sizeof(val32.val); i++) { + if (dw_i3c_send_byte(s, val32.b[i], is_i2c)) { + return bytes_sent; + } + bytes_sent++; + + /* We're not sending the full 32-bits, break early. */ + if (bytes_sent >= num) { + break; + } + } + } + + return bytes_sent; +} + +/* Returns number of bytes received. */ +static uint16_t dw_i3c_rx(DWI3C *s, uint16_t num, bool is_i2c) +{ + /* + * Allocate a temporary buffer to read data from the target. + * Zero it and word-align it as well in case we're reading unaligned data. + */ + g_autofree uint8_t *data = g_new0(uint8_t, num + (4 - (num & 0x03))); + uint32_t *data32 = (uint32_t *)data; + /* + * 32-bits since the I3C API wants a 32-bit number, even though the + * controller can only do 16-bit transfers. + */ + uint32_t num_read = 0; + + /* Can NACK if the target receives an unsupported CCC. */ + if (dw_i3c_recv_data(s, is_i2c, data, num, &num_read)) { + return 0; + } + + for (uint16_t i = 0; i < num_read / 4; i++) { + dw_i3c_push_rx(s, *data32); + data32++; + } + /* + * If we're pushing data that isn't 32-bit aligned, push what's left. + * It's software's responsibility to know what bits are valid in the partial + * data. + */ + if (num_read & 0x03) { + dw_i3c_push_rx(s, *data32); + } + + return num_read; +} + +static int dw_i3c_transfer_ccc(DWI3C *s, DWI3CTransferCmd cmd, + DWI3CTransferArg arg) +{ + /* CCC start is always a write. CCCs cannot be done on I2C devices. */ + if (dw_i3c_send_start(s, I3C_BROADCAST, /*is_recv=*/false, + /*is_i2c=*/false)) { + return DW_I3C_RESP_QUEUE_ERR_BROADCAST_NACK; + } + trace_dw_i3c_transfer_ccc(s->cfg.id, cmd.cmd); + if (dw_i3c_send_byte(s, cmd.cmd, /*is_i2c=*/false)) { + return DW_I3C_RESP_QUEUE_ERR_I2C_NACK; + } + + /* On a direct CCC, we do a restart and then send the target's address. */ + if (CCC_IS_DIRECT(cmd.cmd)) { + bool is_recv = cmd.rnw; + uint8_t addr = dw_i3c_target_addr(s, cmd.dev_index); + if (dw_i3c_send_start(s, addr, is_recv, /*is_i2c=*/false)) { + return DW_I3C_RESP_QUEUE_ERR_BROADCAST_NACK; + } + } + + return DW_I3C_RESP_QUEUE_ERR_NONE; +} + +static void dw_i3c_transfer(DWI3C *s, DWI3CTransferCmd cmd, + DWI3CTransferArg arg) +{ + bool is_recv = cmd.rnw; + uint8_t err = DW_I3C_RESP_QUEUE_ERR_NONE; + uint8_t addr = dw_i3c_target_addr(s, cmd.dev_index); + bool is_i2c = dw_i3c_target_is_i2c(s, cmd.dev_index); + uint16_t bytes_transferred = 0; + + if (cmd.cp) { + /* We're sending a CCC. */ + err = dw_i3c_transfer_ccc(s, cmd, arg); + if (err != DW_I3C_RESP_QUEUE_ERR_NONE) { + goto transfer_done; + } + } else { + if (ARRAY_FIELD_EX32(s->regs, DEVICE_CTRL, I3C_BROADCAST_ADDR_INC) && + is_i2c == false) { + if (dw_i3c_send_start(s, I3C_BROADCAST, + /*is_recv=*/false, is_i2c)) { + err = DW_I3C_RESP_QUEUE_ERR_I2C_NACK; + goto transfer_done; + } + } + /* Otherwise we're doing a private transfer. */ + if (dw_i3c_send_start(s, addr, is_recv, is_i2c)) { + err = DW_I3C_RESP_QUEUE_ERR_I2C_NACK; + goto transfer_done; + } + } + + if (is_recv) { + bytes_transferred = dw_i3c_rx(s, arg.data_len, is_i2c); + } else { + bytes_transferred = dw_i3c_tx(s, arg.data_len, is_i2c); + } + + ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, + DW_I3C_TRANSFER_STATE_IDLE); + +transfer_done: + if (cmd.toc) { + dw_i3c_end_transfer(s, is_i2c); + } + if (cmd.roc) { + /* + * data_len is the number of bytes that still need to be TX'd, or the + * number of bytes RX'd. + */ + uint16_t data_len = is_recv ? bytes_transferred : arg.data_len - + bytes_transferred; + /* CCCT is always 0 in controller mode. */ + dw_i3c_resp_queue_push(s, err, cmd.tid, /*ccc_type=*/0, + data_len); + } + + dw_i3c_update_irq(s); +} + +static void dw_i3c_transfer_cmd(DWI3C *s, DWI3CTransferCmd cmd, + DWI3CCmdQueueData arg) +{ + uint8_t arg_attr = FIELD_EX32(arg.word, COMMAND_QUEUE_PORT, CMD_ATTR); + + ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CMD_TID, cmd.tid); + + /* User is trying to do HDR transfers, see if we can do them. */ + if (cmd.speed == 0x06 && !dw_i3c_has_hdr_ddr(s)) { + g_autofree char *path = object_get_canonical_path(OBJECT(s)); + qemu_log_mask(LOG_GUEST_ERROR, "%s: HDR DDR is not supported\n", path); + ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, + DW_I3C_TRANSFER_STATE_HALT); + return; + } + if (cmd.speed == 0x05 && !dw_i3c_has_hdr_ts(s)) { + g_autofree char *path = object_get_canonical_path(OBJECT(s)); + qemu_log_mask(LOG_GUEST_ERROR, "%s: HDR TS is not supported\n", path); + ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, + DW_I3C_TRANSFER_STATE_HALT); + return; + } + + if (arg_attr == DW_I3C_CMD_ATTR_TRANSFER_ARG) { + dw_i3c_transfer(s, cmd, arg.transfer_arg); + } else if (arg_attr == DW_I3C_CMD_ATTR_SHORT_DATA_ARG) { + dw_i3c_short_transfer(s, cmd, arg.short_arg); + } else { + g_autofree char *path = object_get_canonical_path(OBJECT(s)); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Unknown command queue cmd_attr 0x%x" + "\n", path, arg_attr); + ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, + DW_I3C_TRANSFER_STATE_HALT); + } +} + +static void dw_i3c_update_char_table(DWI3C *s, uint8_t offset, uint64_t pid, + uint8_t bcr, uint8_t dcr, uint8_t addr) +{ + if (offset > s->cfg.num_addressable_devices) { + g_autofree char *path = object_get_canonical_path(OBJECT(s)); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Device char table offset %d out of " + "bounds\n", path, offset); + /* If we're out of bounds, do nothing. */ + return; + } + + /* + * Each device offset is 128 bits apart in the table, since each device gets + * 4 * 32-bits of entries in the table. + * / sizeof(uint32_t) because we're indexing into our 32-bit reg array. + */ + uint16_t dev_index = (ARRAY_FIELD_EX32(s->regs, DEV_CHAR_TABLE_POINTER, + P_DEV_CHAR_TABLE_START_ADDR) / + sizeof(uint32_t)) + + (offset * sizeof(uint32_t)); + s->regs[dev_index] = pid & 0xffffffff; + pid >>= 32; + s->regs[dev_index + 1] = FIELD_DP32(s->regs[dev_index + 1], + DEVICE_CHARACTERISTIC_TABLE_LOC2, + MSB_PID, pid); + s->regs[dev_index + 2] = FIELD_DP32(s->regs[dev_index + 2], + DEVICE_CHARACTERISTIC_TABLE_LOC3, DCR, + dcr); + s->regs[dev_index + 2] = FIELD_DP32(s->regs[dev_index + 2], + DEVICE_CHARACTERISTIC_TABLE_LOC3, BCR, + bcr); + s->regs[dev_index + 3] = FIELD_DP32(s->regs[dev_index + 3], + DEVICE_CHARACTERISTIC_TABLE_LOC4, + DEV_DYNAMIC_ADDR, addr); + + /* Increment PRESENT_DEV_CHAR_TABLE_INDEX. */ + uint8_t idx = ARRAY_FIELD_EX32(s->regs, DEV_CHAR_TABLE_POINTER, + PRESENT_DEV_CHAR_TABLE_INDEX); + /* Increment and rollover. */ + idx++; + if (idx >= ARRAY_FIELD_EX32(s->regs, DEV_CHAR_TABLE_POINTER, + DEV_CHAR_TABLE_DEPTH) / 4) { + idx = 0; + } + ARRAY_FIELD_DP32(s->regs, DEV_CHAR_TABLE_POINTER, + PRESENT_DEV_CHAR_TABLE_INDEX, idx); +} + +static void dw_i3c_addr_assign_cmd(DWI3C *s, DWI3CAddrAssignCmd cmd) +{ + uint8_t i = 0; + uint8_t err = DW_I3C_RESP_QUEUE_ERR_NONE; + + /* Tell everyone to ENTDAA. If these error, no one is on the bus. */ + if (dw_i3c_send_start(s, I3C_BROADCAST, /*is_recv=*/false, + /*is_i2c=*/false)) { + err = DW_I3C_RESP_QUEUE_ERR_BROADCAST_NACK; + goto transfer_done; + } + if (dw_i3c_send_byte(s, cmd.cmd, /*is_i2c=*/false)) { + err = DW_I3C_RESP_QUEUE_ERR_BROADCAST_NACK; + goto transfer_done; + } + + /* Go through each device in the table and assign it an address. */ + for (i = 0; i < cmd.dev_count; i++) { + uint8_t addr = dw_i3c_target_addr(s, cmd.dev_index + i); + union { + uint64_t pid:48; + uint8_t bcr; + uint8_t dcr; + uint32_t w[2]; + uint8_t b[8]; + } target_info; + + /* If this fails, there was no one left to ENTDAA. */ + if (dw_i3c_send_start(s, I3C_BROADCAST, /*is_recv=*/false, + /*is_i2c=*/false)) { + err = DW_I3C_RESP_QUEUE_ERR_BROADCAST_NACK; + break; + } + + /* + * In ENTDAA, we read 8 bytes from the target, which will be the + * target's PID, BCR, and DCR. After that, we send it the dynamic + * address. + * Don't bother checking the number of bytes received, it must send 8 + * bytes during ENTDAA. + */ + uint32_t num_read; + if (dw_i3c_recv_data(s, /*is_i2c=*/false, target_info.b, + I3C_ENTDAA_SIZE, &num_read)) { + g_autofree char *path = object_get_canonical_path(OBJECT(s)); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Target NACKed ENTDAA CCC\n", + path); + err = DW_I3C_RESP_QUEUE_ERR_DAA_NACK; + goto transfer_done; + } + if (dw_i3c_send_byte(s, addr, /*is_i2c=*/false)) { + g_autofree char *path = object_get_canonical_path(OBJECT(s)); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Target NACKed addr 0x%.2x " + "during ENTDAA\n", path, addr); + err = DW_I3C_RESP_QUEUE_ERR_DAA_NACK; + break; + } + dw_i3c_update_char_table(s, cmd.dev_index + i, + target_info.pid, target_info.bcr, + target_info.dcr, addr); + + /* Push the PID, BCR, and DCR to the RX queue. */ + dw_i3c_push_rx(s, target_info.w[0]); + dw_i3c_push_rx(s, target_info.w[1]); + } + +transfer_done: + /* Do we send a STOP? */ + if (cmd.toc) { + dw_i3c_end_transfer(s, /*is_i2c=*/false); + } + /* + * For addr assign commands, the length field is the number of devices + * left to assign. CCCT is always 0 in controller mode. + */ + if (cmd.roc) { + dw_i3c_resp_queue_push(s, err, cmd.tid, /*ccc_type=*/0, + cmd.dev_count - i); + } +} + +static uint32_t dw_i3c_cmd_queue_pop(DWI3C *s) +{ + if (fifo32_is_empty(&s->cmd_queue)) { + g_autofree char *path = object_get_canonical_path(OBJECT(s)); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Tried to dequeue command queue " + "when it was empty\n", path); + return 0; + } + uint32_t val = fifo32_pop(&s->cmd_queue); + + uint8_t empty_threshold = ARRAY_FIELD_EX32(s->regs, QUEUE_THLD_CTRL, + CMD_BUF_EMPTY_THLD); + uint8_t cmd_queue_empty_loc = ARRAY_FIELD_EX32(s->regs, + QUEUE_STATUS_LEVEL, + CMD_QUEUE_EMPTY_LOC); + cmd_queue_empty_loc++; + ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, CMD_QUEUE_EMPTY_LOC, + cmd_queue_empty_loc); + if (cmd_queue_empty_loc >= empty_threshold) { + ARRAY_FIELD_DP32(s->regs, INTR_STATUS, CMD_QUEUE_RDY, 1); + dw_i3c_update_irq(s); + } + + return val; +} + +static void dw_i3c_cmd_queue_execute(DWI3C *s) +{ + ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, + DW_I3C_TRANSFER_STATE_IDLE); + if (!dw_i3c_can_transmit(s)) { + return; + } + + /* + * We only start executing when a command is passed into the FIFO. + * We expect there to be a multiple of 2 items in the queue. The first item + * should be an argument to a command, and the command should be the second + * item. + */ + if (fifo32_num_used(&s->cmd_queue) & 1) { + return; + } + + while (!fifo32_is_empty(&s->cmd_queue)) { + DWI3CCmdQueueData arg; + arg.word = dw_i3c_cmd_queue_pop(s); + DWI3CCmdQueueData cmd; + cmd.word = dw_i3c_cmd_queue_pop(s); + trace_dw_i3c_cmd_queue_execute(s->cfg.id, cmd.word, arg.word); + + uint8_t cmd_attr = FIELD_EX32(cmd.word, COMMAND_QUEUE_PORT, CMD_ATTR); + switch (cmd_attr) { + case DW_I3C_CMD_ATTR_TRANSFER_CMD: + dw_i3c_transfer_cmd(s, cmd.transfer_cmd, arg); + break; + case DW_I3C_CMD_ATTR_ADDR_ASSIGN_CMD: + /* Arg is discarded for addr assign commands. */ + dw_i3c_addr_assign_cmd(s, cmd.addr_assign_cmd); + break; + case DW_I3C_CMD_ATTR_TRANSFER_ARG: + case DW_I3C_CMD_ATTR_SHORT_DATA_ARG: + { + g_autofree char *path = object_get_canonical_path(OBJECT(s)); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Command queue received " + "argument packet when it expected a command " + "packet\n", path); + } + break; + default: + /* + * The caller's check before queueing an item should prevent this + * from happening. + */ + g_assert_not_reached(); + break; + } + } +} + +static void dw_i3c_cmd_queue_push(DWI3C *s, uint32_t val) +{ + if (fifo32_is_full(&s->cmd_queue)) { + g_autofree char *path = object_get_canonical_path(OBJECT(s)); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Command queue received packet when " + "already full\n", path); + return; + } + trace_dw_i3c_cmd_queue_push(s->cfg.id, val); + fifo32_push(&s->cmd_queue, val); + + uint8_t empty_threshold = ARRAY_FIELD_EX32(s->regs, QUEUE_THLD_CTRL, + CMD_BUF_EMPTY_THLD); + uint8_t cmd_queue_empty_loc = ARRAY_FIELD_EX32(s->regs, + QUEUE_STATUS_LEVEL, + CMD_QUEUE_EMPTY_LOC); + if (cmd_queue_empty_loc) { + cmd_queue_empty_loc--; + ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, CMD_QUEUE_EMPTY_LOC, + cmd_queue_empty_loc); + } + if (cmd_queue_empty_loc < empty_threshold) { + ARRAY_FIELD_DP32(s->regs, INTR_STATUS, CMD_QUEUE_RDY, 0); + dw_i3c_update_irq(s); + } +} + +static void dw_i3c_cmd_queue_port_w(DWI3C *s, uint32_t val) +{ + uint8_t cmd_attr = FIELD_EX32(val, COMMAND_QUEUE_PORT, CMD_ATTR); + + switch (cmd_attr) { + /* If a command is received we can start executing it. */ + case DW_I3C_CMD_ATTR_TRANSFER_CMD: + case DW_I3C_CMD_ATTR_ADDR_ASSIGN_CMD: + dw_i3c_cmd_queue_push(s, val); + dw_i3c_cmd_queue_execute(s); + break; + /* If we get an argument just push it. */ + case DW_I3C_CMD_ATTR_TRANSFER_ARG: + case DW_I3C_CMD_ATTR_SHORT_DATA_ARG: + dw_i3c_cmd_queue_push(s, val); + break; + default: + { + g_autofree char *path = object_get_canonical_path(OBJECT(s)); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Command queue received packet " + "with unknown cmd attr 0x%x\n", path, cmd_attr); + } + break; + } +} + static void dw_i3c_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { @@ -XXX,XX +XXX,XX @@ static void dw_i3c_write(void *opaque, hwaddr offset, uint64_t value, uint32_t addr = offset >> 2; uint32_t val32 = (uint32_t)value; - trace_dw_i3c_write(s->id, offset, value); + trace_dw_i3c_write(s->cfg.id, offset, value); val32 &= ~dw_i3c_ro[addr]; switch (addr) { @@ -XXX,XX +XXX,XX @@ static void dw_i3c_write(void *opaque, hwaddr offset, uint64_t value, __func__, offset, value); break; case R_RX_TX_DATA_PORT: + dw_i3c_push_tx(s, val32); + break; + case R_COMMAND_QUEUE_PORT: + dw_i3c_cmd_queue_port_w(s, val32); break; case R_RESET_CTRL: break; @@ -XXX,XX +XXX,XX @@ static void dw_i3c_reset_enter(Object *obj, ResetType type) DWI3C *s = DW_I3C(obj); memcpy(s->regs, dw_i3c_resets, sizeof(s->regs)); + /* + * The user config for these may differ from our resets array, set them + * manually. + */ + ARRAY_FIELD_DP32(s->regs, DEVICE_ADDR_TABLE_POINTER, ADDR, + s->cfg.dev_addr_table_pointer); + ARRAY_FIELD_DP32(s->regs, DEVICE_ADDR_TABLE_POINTER, DEPTH, + s->cfg.dev_addr_table_depth); + ARRAY_FIELD_DP32(s->regs, DEV_CHAR_TABLE_POINTER, + P_DEV_CHAR_TABLE_START_ADDR, + s->cfg.dev_char_table_pointer); + ARRAY_FIELD_DP32(s->regs, DEV_CHAR_TABLE_POINTER, DEV_CHAR_TABLE_DEPTH, + s->cfg.dev_char_table_depth); } static void dw_i3c_realize(DeviceState *dev, Error **errp) { DWI3C *s = DW_I3C(dev); - g_autofree char *name = g_strdup_printf(TYPE_DW_I3C ".%d", s->id); + g_autofree char *name = g_strdup_printf(TYPE_DW_I3C ".%d", s->cfg.id); sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); memory_region_init_io(&s->mr, OBJECT(s), &dw_i3c_ops, s, name, DW_I3C_NR_REGS << 2); sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mr); + + fifo32_create(&s->cmd_queue, s->cfg.cmd_resp_queue_capacity_bytes); + fifo32_create(&s->resp_queue, s->cfg.cmd_resp_queue_capacity_bytes); + fifo32_create(&s->tx_queue, s->cfg.tx_rx_queue_capacity_bytes); + fifo32_create(&s->rx_queue, s->cfg.tx_rx_queue_capacity_bytes); + + s->bus = i3c_init_bus(DEVICE(s), name); } static const Property dw_i3c_properties[] = { - DEFINE_PROP_UINT8("device-id", DWI3C, id, 0), + DEFINE_PROP_UINT8("device-id", DWI3C, cfg.id, 0), + DEFINE_PROP_UINT8("command-response-queue-capacity-bytes", DWI3C, + cfg.cmd_resp_queue_capacity_bytes, 0x10), + DEFINE_PROP_UINT16("tx-rx-queue-capacity-bytes", DWI3C, + cfg.tx_rx_queue_capacity_bytes, 0x40), + DEFINE_PROP_UINT8("num-addressable-devices", DWI3C, + cfg.num_addressable_devices, 8), + DEFINE_PROP_UINT16("dev-addr-table-pointer", DWI3C, + cfg.dev_addr_table_pointer, 0x280), + DEFINE_PROP_UINT16("dev-addr-table-depth", DWI3C, + cfg.dev_addr_table_depth, 0x08), + DEFINE_PROP_UINT16("dev-char-table-pointer", DWI3C, + cfg.dev_char_table_pointer, 0x200), + DEFINE_PROP_UINT16("dev-char-table-depth", DWI3C, + cfg.dev_char_table_depth, 0x20), }; static void dw_i3c_class_init(ObjectClass *klass, const void *data) diff --git a/hw/i3c/trace-events b/hw/i3c/trace-events index XXXXXXX..XXXXXXX 100644 --- a/hw/i3c/trace-events +++ b/hw/i3c/trace-events @@ -XXX,XX +XXX,XX @@ aspeed_i3c_write(uint64_t offset, uint64_t data) "I3C write: offset 0x%" PRIx64 # dw-i3c,c dw_i3c_read(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] read: offset 0x%" PRIx64 " data 0x%" PRIx64 dw_i3c_write(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] write: offset 0x%" PRIx64 " data 0x%" PRIx64 +dw_i3c_send(uint32_t deviceid, uint32_t num_bytes) "I3C Dev[%u] send %" PRId32 " bytes to bus" +dw_i3c_recv_data(uint32_t deviceid, uint32_t num_bytes) "I3C Dev[%u] recv %" PRId32 " bytes from bus" +dw_i3c_pop_rx(uint32_t deviceid, uint32_t data) "I3C Dev[%u] pop 0x%" PRIx32 " from RX FIFO" +dw_i3c_resp_queue_push(uint32_t deviceid, uint32_t data) "I3C Dev[%u] push 0x%" PRIx32 " to response queue" +dw_i3c_push_tx(uint32_t deviceid, uint32_t data) "I3C Dev[%u] push 0x%" PRIx32 " to TX FIFO" +dw_i3c_pop_tx(uint32_t deviceid, uint32_t data) "I3C Dev[%u] pop 0x%" PRIx32 " from TX FIFO" +dw_i3c_push_rx(uint32_t deviceid, uint32_t data) "I3C Dev[%u] push 0x%" PRIx32 " to RX FIFO" +dw_i3c_transfer_ccc(uint32_t deviceid, uint8_t ccc) "I3C Dev[%u] transfer CCC 0x%" PRIx8 +dw_i3c_cmd_queue_execute(uint32_t deviceid, uint32_t cmd, uint32_t arg) "I3C Dev[%u] execute command 0x%" PRIx32 " arg 0x%" PRIx32 +dw_i3c_cmd_queue_push(uint32_t deviceid, uint32_t data) "I3C Dev[%u] push 0x%" PRIx32 " to cmd queue" # core.c i3c_target_event(uint8_t address, uint8_t event) "I3C target 0x%" PRIx8 " event 0x%" PRIx8 -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> Adds handling for different IBI events that the controller can receive. This includes: - Handling a hot-join from a target - Handling a secondary controller on the bus requesting to be the primary bus controller - Handling an interrupt request from a target. When receiving an IBI, the controller sets an interrupt to notify software about what happened. When the IBI is finished being serviced, the controller pushes the result of the IBI and any data received from the target into the IBI queue. Signed-off-by: Joe Komlodi <komlodi@google.com> Reviewed-by: Patrick Venture <venture@google.com> Reviewed-by: Stephen Longfield <slongfield@google.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Tested-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260225021158.1586584-15-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- include/hw/i3c/dw-i3c.h | 27 ++++ hw/i3c/dw-i3c.c | 317 ++++++++++++++++++++++++++++++++++++++++ hw/i3c/trace-events | 2 + 3 files changed, 346 insertions(+) diff --git a/include/hw/i3c/dw-i3c.h b/include/hw/i3c/dw-i3c.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/i3c/dw-i3c.h +++ b/include/hw/i3c/dw-i3c.h @@ -XXX,XX +XXX,XX @@ typedef union DWI3CCmdQueueData { DWI3CAddrAssignCmd addr_assign_cmd; } DWI3CCmdQueueData; +/* + * When we receive an IBI with data, we need to store it temporarily until + * the target is finished sending data. Then we can set the IBI queue status + * appropriately. + */ +typedef struct DWI3CIBIData { + /* Do we notify the user that an IBI was NACKed? */ + bool notify_ibi_nack; + /* Intermediate storage of IBI_QUEUE_STATUS. */ + uint32_t ibi_queue_status; + /* Temporary buffer to store IBI data from the target. */ + Fifo8 ibi_intermediate_queue; + /* The address we should send a CCC_DISEC to. */ + uint8_t disec_addr; + /* The byte we should send along with the CCC_DISEC. */ + uint8_t disec_byte; + /* Should we send a direct DISEC CCC? (As opposed to global). */ + bool send_direct_disec; + /* Was this IBI NACKed? */ + bool ibi_nacked; +} DWI3CIBIData; + struct DWI3C { SysBusDevice parent_obj; @@ -XXX,XX +XXX,XX @@ struct DWI3C { Fifo32 resp_queue; Fifo32 tx_queue; Fifo32 rx_queue; + Fifo32 ibi_queue; + + /* Temporary storage for IBI data. */ + DWI3CIBIData ibi_data; struct { uint8_t id; uint8_t cmd_resp_queue_capacity_bytes; uint16_t tx_rx_queue_capacity_bytes; + uint8_t ibi_queue_capacity_bytes; uint8_t num_addressable_devices; uint16_t dev_addr_table_pointer; uint16_t dev_addr_table_depth; diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c index XXXXXXX..XXXXXXX 100644 --- a/hw/i3c/dw-i3c.c +++ b/hw/i3c/dw-i3c.c @@ -XXX,XX +XXX,XX @@ #include "trace.h" #include "hw/core/irq.h" +/* + * Disable event command values. sent along with a DISEC CCC to disable certain + * events on targets. + */ +#define DISEC_HJ 0x08 +#define DISEC_CR 0x02 +#define DISEC_INT 0x01 + REG32(DEVICE_CTRL, 0x00) FIELD(DEVICE_CTRL, I3C_BROADCAST_ADDR_INC, 0, 1) FIELD(DEVICE_CTRL, I2C_SLAVE_PRESENT, 7, 1) @@ -XXX,XX +XXX,XX @@ static inline bool dw_i3c_can_transmit(DWI3C *s) !ARRAY_FIELD_EX32(s->regs, DEVICE_CTRL, I3C_RESUME); } +static inline uint8_t dw_i3c_ibi_slice_size(DWI3C *s) +{ + uint8_t ibi_slice_size = ARRAY_FIELD_EX32(s->regs, QUEUE_THLD_CTRL, + IBI_DATA_THLD); + /* The minimum supported slice size is 4 bytes. */ + if (ibi_slice_size == 0) { + ibi_slice_size = 1; + } + ibi_slice_size *= sizeof(uint32_t); + /* maximum supported size is 63 bytes. */ + if (ibi_slice_size >= 64) { + ibi_slice_size = 63; + } + + return ibi_slice_size; +} + static inline uint8_t dw_i3c_fifo_threshold_from_reg(uint8_t regval) { return regval = regval ? (2 << regval) : 1; @@ -XXX,XX +XXX,XX @@ static uint8_t dw_i3c_target_addr(DWI3C *s, uint16_t offset) DEV_DYNAMIC_ADDR); } +static int dw_i3c_addr_table_index_from_addr(DWI3C *s, uint8_t addr) +{ + uint8_t table_size = ARRAY_FIELD_EX32(s->regs, DEVICE_ADDR_TABLE_POINTER, + DEPTH); + for (uint8_t i = 0; i < table_size; i++) { + if (dw_i3c_target_addr(s, i) == addr) { + return i; + } + } + return -1; +} + +static void dw_i3c_send_disec(DWI3C *s) +{ + uint8_t ccc = I3C_CCC_DISEC; + if (s->ibi_data.send_direct_disec) { + ccc = I3C_CCCD_DISEC; + } + + dw_i3c_send_start(s, I3C_BROADCAST, /*is_recv=*/false, + /*is_i2c=*/false); + dw_i3c_send_byte(s, ccc, /*is_i2c=*/false); + if (s->ibi_data.send_direct_disec) { + dw_i3c_send_start(s, s->ibi_data.disec_addr, + /*is_recv=*/false, /*is_i2c=*/false); + } + dw_i3c_send_byte(s, s->ibi_data.disec_byte, /*is_i2c=*/false); +} + +static int dw_i3c_handle_hj(DWI3C *s) +{ + if (ARRAY_FIELD_EX32(s->regs, IBI_QUEUE_CTRL, NOTIFY_REJECTED_HOT_JOIN)) { + s->ibi_data.notify_ibi_nack = true; + } + + bool nack_and_disable = ARRAY_FIELD_EX32(s->regs, DEVICE_CTRL, + HOT_JOIN_ACK_NACK_CTRL); + if (nack_and_disable) { + s->ibi_data.ibi_queue_status = FIELD_DP32(s->ibi_data.ibi_queue_status, + IBI_QUEUE_STATUS, + IBI_STATUS, 1); + s->ibi_data.ibi_nacked = true; + s->ibi_data.disec_byte = DISEC_HJ; + return -1; + } + return 0; +} + +static int dw_i3c_handle_ctlr_req(DWI3C *s, uint8_t addr) +{ + if (ARRAY_FIELD_EX32(s->regs, IBI_QUEUE_CTRL, NOTIFY_REJECTED_MASTER_REQ)) { + s->ibi_data.notify_ibi_nack = true; + } + + int table_offset = dw_i3c_addr_table_index_from_addr(s, addr); + /* Doesn't exist in the table, NACK it, don't DISEC. */ + if (table_offset < 0) { + return -1; + } + + /* / sizeof(uint32_t) because we're indexing into our 32-bit reg array. */ + table_offset += (ARRAY_FIELD_EX32(s->regs, DEVICE_ADDR_TABLE_POINTER, + ADDR) / sizeof(uint32_t)); + if (FIELD_EX32(s->regs[table_offset], DEVICE_ADDR_TABLE_LOC1, MR_REJECT)) { + s->ibi_data.ibi_queue_status = FIELD_DP32(s->ibi_data.ibi_queue_status, + IBI_QUEUE_STATUS, + IBI_STATUS, 1); + s->ibi_data.ibi_nacked = true; + s->ibi_data.disec_addr = addr; + /* Tell the requester to disable controller role requests. */ + s->ibi_data.disec_byte = DISEC_CR; + s->ibi_data.send_direct_disec = true; + return -1; + } + return 0; +} + +static int dw_i3c_handle_targ_irq(DWI3C *s, uint8_t addr) +{ + if (ARRAY_FIELD_EX32(s->regs, IBI_QUEUE_CTRL, NOTIFY_REJECTED_SLAVE_IRQ)) { + s->ibi_data.notify_ibi_nack = true; + } + + int table_offset = dw_i3c_addr_table_index_from_addr(s, addr); + /* Doesn't exist in the table, NACK it, don't DISEC. */ + if (table_offset < 0) { + return -1; + } + + /* / sizeof(uint32_t) because we're indexing into our 32-bit reg array. */ + table_offset += (ARRAY_FIELD_EX32(s->regs, DEVICE_ADDR_TABLE_POINTER, + ADDR) / sizeof(uint32_t)); + if (FIELD_EX32(s->regs[table_offset], DEVICE_ADDR_TABLE_LOC1, SIR_REJECT)) { + s->ibi_data.ibi_queue_status = FIELD_DP32(s->ibi_data.ibi_queue_status, + IBI_QUEUE_STATUS, + IBI_STATUS, 1); + s->ibi_data.ibi_nacked = true; + s->ibi_data.disec_addr = addr; + /* Tell the requester to disable interrupts. */ + s->ibi_data.disec_byte = DISEC_INT; + s->ibi_data.send_direct_disec = true; + return -1; + } + return 0; +} + +static int dw_i3c_ibi_handle(I3CBus *bus, uint8_t addr, bool is_recv) +{ + DWI3C *s = DW_I3C(bus->parent_obj.parent); + + trace_dw_i3c_ibi_handle(s->cfg.id, addr, is_recv); + s->ibi_data.ibi_queue_status = FIELD_DP32(s->ibi_data.ibi_queue_status, + IBI_QUEUE_STATUS, IBI_ID, + (addr << 1) | is_recv); + /* Is this a hot join request? */ + if (addr == I3C_HJ_ADDR) { + return dw_i3c_handle_hj(s); + } + /* Is secondary controller requesting access? */ + if (!is_recv) { + return dw_i3c_handle_ctlr_req(s, addr); + } + /* Is this a target IRQ? */ + if (is_recv) { + return dw_i3c_handle_targ_irq(s, addr); + } + + /* At this point the IBI should have been ACKed or NACKed. */ + g_assert_not_reached(); + return -1; +} + +static int dw_i3c_ibi_recv(I3CBus *bus, uint8_t data) +{ + DWI3C *s = DW_I3C(bus->parent_obj.parent); + if (fifo8_is_full(&s->ibi_data.ibi_intermediate_queue)) { + return -1; + } + + fifo8_push(&s->ibi_data.ibi_intermediate_queue, data); + trace_dw_i3c_ibi_recv(s->cfg.id, data); + return 0; +} + +static void dw_i3c_ibi_queue_push(DWI3C *s) +{ + /* Stored value is in 32-bit chunks, convert it to byte chunks. */ + uint8_t ibi_slice_size = dw_i3c_ibi_slice_size(s); + uint8_t num_slices = (fifo8_num_used(&s->ibi_data.ibi_intermediate_queue) / + ibi_slice_size) + + ((fifo8_num_used(&s->ibi_data.ibi_intermediate_queue) % + ibi_slice_size) ? 1 : 0); + uint8_t ibi_status_count = num_slices; + union { + uint8_t b[sizeof(uint32_t)]; + uint32_t val32; + } ibi_data = { + .val32 = 0 + }; + + /* The report was suppressed, do nothing. */ + if (s->ibi_data.ibi_nacked && !s->ibi_data.notify_ibi_nack) { + ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, + DW_I3C_TRANSFER_STATE_IDLE); + ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_STATUS, + DW_I3C_TRANSFER_STATUS_IDLE); + return; + } + + /* If we don't have any slices to push, just push the status. */ + if (num_slices == 0) { + s->ibi_data.ibi_queue_status = + FIELD_DP32(s->ibi_data.ibi_queue_status, IBI_QUEUE_STATUS, + LAST_STATUS, 1); + fifo32_push(&s->ibi_queue, s->ibi_data.ibi_queue_status); + ibi_status_count = 1; + } + + for (uint8_t i = 0; i < num_slices; i++) { + /* If this is the last slice, set LAST_STATUS. */ + if (fifo8_num_used(&s->ibi_data.ibi_intermediate_queue) < + ibi_slice_size) { + s->ibi_data.ibi_queue_status = + FIELD_DP32(s->ibi_data.ibi_queue_status, IBI_QUEUE_STATUS, + IBI_DATA_LEN, + fifo8_num_used(&s->ibi_data.ibi_intermediate_queue)); + s->ibi_data.ibi_queue_status = + FIELD_DP32(s->ibi_data.ibi_queue_status, IBI_QUEUE_STATUS, + LAST_STATUS, 1); + } else { + s->ibi_data.ibi_queue_status = + FIELD_DP32(s->ibi_data.ibi_queue_status, IBI_QUEUE_STATUS, + IBI_DATA_LEN, ibi_slice_size); + } + + /* Push the IBI status header. */ + fifo32_push(&s->ibi_queue, s->ibi_data.ibi_queue_status); + /* Move each IBI byte into a 32-bit word and push it into the queue. */ + for (uint8_t j = 0; j < ibi_slice_size; ++j) { + if (fifo8_is_empty(&s->ibi_data.ibi_intermediate_queue)) { + break; + } + + ibi_data.b[j & 3] = fifo8_pop(&s->ibi_data.ibi_intermediate_queue); + /* We have 32-bits, push it to the IBI FIFO. */ + if ((j & 0x03) == 0x03) { + fifo32_push(&s->ibi_queue, ibi_data.val32); + ibi_data.val32 = 0; + } + } + /* If the data isn't 32-bit aligned, push the leftover bytes. */ + if (ibi_slice_size & 0x03) { + fifo32_push(&s->ibi_queue, ibi_data.val32); + } + + /* Clear out the data length for the next iteration. */ + s->ibi_data.ibi_queue_status = FIELD_DP32(s->ibi_data.ibi_queue_status, + IBI_QUEUE_STATUS, IBI_DATA_LEN, 0); + } + + ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, IBI_BUF_BLR, + fifo32_num_used(&s->ibi_queue)); + ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, IBI_STATUS_CNT, + ibi_status_count); + /* Threshold is the register value + 1. */ + uint8_t threshold = ARRAY_FIELD_EX32(s->regs, QUEUE_THLD_CTRL, + IBI_STATUS_THLD) + 1; + if (fifo32_num_used(&s->ibi_queue) >= threshold) { + ARRAY_FIELD_DP32(s->regs, INTR_STATUS, IBI_THLD, 1); + dw_i3c_update_irq(s); + } + + /* State update. */ + ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, + DW_I3C_TRANSFER_STATE_IDLE); + ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_STATUS, + DW_I3C_TRANSFER_STATUS_IDLE); +} + +static int dw_i3c_ibi_finish(I3CBus *bus) +{ + DWI3C *s = DW_I3C(bus->parent_obj.parent); + bool nack_and_disable_hj = ARRAY_FIELD_EX32(s->regs, DEVICE_CTRL, + HOT_JOIN_ACK_NACK_CTRL); + if (nack_and_disable_hj || s->ibi_data.send_direct_disec) { + dw_i3c_send_disec(s); + } + dw_i3c_ibi_queue_push(s); + + /* Clear out the intermediate values. */ + s->ibi_data.ibi_queue_status = 0; + s->ibi_data.disec_addr = 0; + s->ibi_data.disec_byte = 0; + s->ibi_data.send_direct_disec = false; + s->ibi_data.notify_ibi_nack = false; + s->ibi_data.ibi_nacked = false; + + return 0; +} + static uint32_t dw_i3c_intr_status_r(DWI3C *s) { /* Only return the status whose corresponding EN bits are set. */ @@ -XXX,XX +XXX,XX @@ static uint32_t dw_i3c_pop_rx(DWI3C *s) return val; } +static uint32_t dw_i3c_ibi_queue_r(DWI3C *s) +{ + if (fifo32_is_empty(&s->ibi_queue)) { + return 0; + } + + uint32_t val = fifo32_pop(&s->ibi_queue); + ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, IBI_BUF_BLR, + fifo32_num_used(&s->ibi_queue)); + /* Threshold is the register value + 1. */ + uint8_t threshold = ARRAY_FIELD_EX32(s->regs, QUEUE_THLD_CTRL, + IBI_STATUS_THLD) + 1; + if (fifo32_num_used(&s->ibi_queue) < threshold) { + ARRAY_FIELD_DP32(s->regs, INTR_STATUS, IBI_THLD, 0); + dw_i3c_update_irq(s); + } + return val; +} + static uint32_t dw_i3c_resp_queue_port_r(DWI3C *s) { if (fifo32_is_empty(&s->resp_queue)) { @@ -XXX,XX +XXX,XX @@ static uint64_t dw_i3c_read(void *opaque, hwaddr offset, unsigned size) case R_INTR_FORCE: value = 0; break; + case R_IBI_QUEUE_DATA: + value = dw_i3c_ibi_queue_r(s); + break; case R_INTR_STATUS: value = dw_i3c_intr_status_r(s); break; @@ -XXX,XX +XXX,XX @@ static void dw_i3c_realize(DeviceState *dev, Error **errp) fifo32_create(&s->resp_queue, s->cfg.cmd_resp_queue_capacity_bytes); fifo32_create(&s->tx_queue, s->cfg.tx_rx_queue_capacity_bytes); fifo32_create(&s->rx_queue, s->cfg.tx_rx_queue_capacity_bytes); + fifo32_create(&s->ibi_queue, s->cfg.ibi_queue_capacity_bytes); + /* Arbitrarily large enough to not be an issue. */ + fifo8_create(&s->ibi_data.ibi_intermediate_queue, + s->cfg.ibi_queue_capacity_bytes * 8); s->bus = i3c_init_bus(DEVICE(s), name); + I3CBusClass *bc = I3C_BUS_GET_CLASS(s->bus); + bc->ibi_handle = dw_i3c_ibi_handle; + bc->ibi_recv = dw_i3c_ibi_recv; + bc->ibi_finish = dw_i3c_ibi_finish; } static const Property dw_i3c_properties[] = { @@ -XXX,XX +XXX,XX @@ static const Property dw_i3c_properties[] = { cfg.cmd_resp_queue_capacity_bytes, 0x10), DEFINE_PROP_UINT16("tx-rx-queue-capacity-bytes", DWI3C, cfg.tx_rx_queue_capacity_bytes, 0x40), + DEFINE_PROP_UINT8("ibi-queue-capacity-bytes", DWI3C, + cfg.ibi_queue_capacity_bytes, 0x10), DEFINE_PROP_UINT8("num-addressable-devices", DWI3C, cfg.num_addressable_devices, 8), DEFINE_PROP_UINT16("dev-addr-table-pointer", DWI3C, diff --git a/hw/i3c/trace-events b/hw/i3c/trace-events index XXXXXXX..XXXXXXX 100644 --- a/hw/i3c/trace-events +++ b/hw/i3c/trace-events @@ -XXX,XX +XXX,XX @@ dw_i3c_read(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] read dw_i3c_write(uint32_t deviceid, uint64_t offset, uint64_t data) "I3C Dev[%u] write: offset 0x%" PRIx64 " data 0x%" PRIx64 dw_i3c_send(uint32_t deviceid, uint32_t num_bytes) "I3C Dev[%u] send %" PRId32 " bytes to bus" dw_i3c_recv_data(uint32_t deviceid, uint32_t num_bytes) "I3C Dev[%u] recv %" PRId32 " bytes from bus" +dw_i3c_ibi_recv(uint32_t deviceid, uint8_t ibi_byte) "I3C Dev[%u] recv IBI byte 0x%" PRIx8 +dw_i3c_ibi_handle(uint32_t deviceid, uint8_t addr, bool rnw) "I3C Dev[%u] handle IBI from address 0x%" PRIx8 " RnW=%d" dw_i3c_pop_rx(uint32_t deviceid, uint32_t data) "I3C Dev[%u] pop 0x%" PRIx32 " from RX FIFO" dw_i3c_resp_queue_push(uint32_t deviceid, uint32_t data) "I3C Dev[%u] push 0x%" PRIx32 " to response queue" dw_i3c_push_tx(uint32_t deviceid, uint32_t data) "I3C Dev[%u] push 0x%" PRIx32 " to TX FIFO" -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> Adds functionality to the CTRL register. Signed-off-by: Joe Komlodi <komlodi@google.com> Reviewed-by: Titus Rwantare <titusr@google.com> Reviewed-by: Patrick Venture <venture@google.com> Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Tested-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260225021158.1586584-16-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- hw/i3c/dw-i3c.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c index XXXXXXX..XXXXXXX 100644 --- a/hw/i3c/dw-i3c.c +++ b/hw/i3c/dw-i3c.c @@ -XXX,XX +XXX,XX @@ static const uint32_t dw_i3c_ro[DW_I3C_NR_REGS] = { [R_SLAVE_CONFIG] = 0xffffffff, }; +static void dw_i3c_cmd_queue_execute(DWI3C *s); + static inline bool dw_i3c_has_hdr_ts(DWI3C *s) { return ARRAY_FIELD_EX32(s->regs, HW_CAPABILITY, HDR_TS); @@ -XXX,XX +XXX,XX @@ static int dw_i3c_recv_data(DWI3C *s, bool is_i2c, uint8_t *data, return ret; } +static void dw_i3c_ctrl_w(DWI3C *s, uint32_t val) +{ + /* + * If the user is setting I3C_RESUME, the controller was halted. + * Try and resume execution and leave the bit cleared. + */ + if (FIELD_EX32(val, DEVICE_CTRL, I3C_RESUME)) { + dw_i3c_cmd_queue_execute(s); + val = FIELD_DP32(val, DEVICE_CTRL, I3C_RESUME, 0); + } + /* + * I3C_ABORT being set sends an I3C STOP. It's cleared when the STOP is + * sent. + */ + if (FIELD_EX32(val, DEVICE_CTRL, I3C_ABORT)) { + dw_i3c_end_transfer(s, /*is_i2c=*/true); + dw_i3c_end_transfer(s, /*is_i2c=*/false); + val = FIELD_DP32(val, DEVICE_CTRL, I3C_ABORT, 0); + ARRAY_FIELD_DP32(s->regs, INTR_STATUS, TRANSFER_ABORT, 1); + dw_i3c_update_irq(s); + } + /* Update present state. */ + ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, + DW_I3C_TRANSFER_STATE_IDLE); + ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_STATUS, + DW_I3C_TRANSFER_STATUS_IDLE); + + s->regs[R_DEVICE_CTRL] = val; +} + static inline bool dw_i3c_target_is_i2c(DWI3C *s, uint16_t offset) { /* / sizeof(uint32_t) because we're indexing into our 32-bit reg array. */ @@ -XXX,XX +XXX,XX @@ static void dw_i3c_write(void *opaque, hwaddr offset, uint64_t value, "] = 0x%08" PRIx64 "\n", __func__, offset, value); break; + case R_DEVICE_CTRL: + dw_i3c_ctrl_w(s, val32); + break; case R_RX_TX_DATA_PORT: dw_i3c_push_tx(s, val32); break; -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> Adds behavior to the device reset register. Signed-off-by: Joe Komlodi <komlodi@google.com> Reviewed-by: Patrick Venture <venture@google.com> Reviewed-by: Stephen Longfield <slongfield@google.com> Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Tested-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260225021158.1586584-17-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- hw/i3c/dw-i3c.c | 117 ++++++++++++++++++++++++++++++++++++++++++++ hw/i3c/trace-events | 1 + 2 files changed, 118 insertions(+) diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c index XXXXXXX..XXXXXXX 100644 --- a/hw/i3c/dw-i3c.c +++ b/hw/i3c/dw-i3c.c @@ -XXX,XX +XXX,XX @@ static void dw_i3c_intr_force_w(DWI3C *s, uint32_t val) dw_i3c_update_irq(s); } +static void dw_i3c_cmd_queue_reset(DWI3C *s) +{ + fifo32_reset(&s->cmd_queue); + + ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, CMD_QUEUE_EMPTY_LOC, + fifo32_num_free(&s->cmd_queue)); + uint8_t empty_threshold = ARRAY_FIELD_EX32(s->regs, QUEUE_THLD_CTRL, + CMD_BUF_EMPTY_THLD); + if (fifo32_num_free(&s->cmd_queue) >= empty_threshold) { + ARRAY_FIELD_DP32(s->regs, INTR_STATUS, CMD_QUEUE_RDY, 1); + dw_i3c_update_irq(s); + }; +} + +static void dw_i3c_resp_queue_reset(DWI3C *s) +{ + fifo32_reset(&s->resp_queue); + + ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, RESP_BUF_BLR, + fifo32_num_used(&s->resp_queue)); + /* + * This interrupt will always be cleared because the threshold is a minimum + * of 1 and the queue size is 0. + */ + ARRAY_FIELD_DP32(s->regs, INTR_STATUS, RESP_RDY, 0); + dw_i3c_update_irq(s); +} + +static void dw_i3c_ibi_queue_reset(DWI3C *s) +{ + fifo32_reset(&s->ibi_queue); + + ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, IBI_BUF_BLR, + fifo32_num_used(&s->resp_queue)); + /* + * This interrupt will always be cleared because the threshold is a minimum + * of 1 and the queue size is 0. + */ + ARRAY_FIELD_DP32(s->regs, INTR_STATUS, IBI_THLD, 0); + dw_i3c_update_irq(s); +} + +static void dw_i3c_tx_queue_reset(DWI3C *s) +{ + fifo32_reset(&s->tx_queue); + + ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, TX_BUF_EMPTY_LOC, + fifo32_num_free(&s->tx_queue)); + /* TX buf is empty, so this interrupt will always be set. */ + ARRAY_FIELD_DP32(s->regs, INTR_STATUS, TX_THLD, 1); + dw_i3c_update_irq(s); +} + +static void dw_i3c_rx_queue_reset(DWI3C *s) +{ + fifo32_reset(&s->rx_queue); + + ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, RX_BUF_BLR, + fifo32_num_used(&s->resp_queue)); + /* + * This interrupt will always be cleared because the threshold is a minimum + * of 1 and the queue size is 0. + */ + ARRAY_FIELD_DP32(s->regs, INTR_STATUS, RX_THLD, 0); + dw_i3c_update_irq(s); +} + +static void dw_i3c_reset(DeviceState *dev) +{ + DWI3C *s = DW_I3C(dev); + trace_dw_i3c_reset(s->cfg.id); + + memcpy(s->regs, dw_i3c_resets, sizeof(s->regs)); + /* + * The user config for these may differ from our resets array, set them + * manually. + */ + ARRAY_FIELD_DP32(s->regs, DEVICE_ADDR_TABLE_POINTER, ADDR, + s->cfg.dev_addr_table_pointer); + ARRAY_FIELD_DP32(s->regs, DEVICE_ADDR_TABLE_POINTER, DEPTH, + s->cfg.dev_addr_table_depth); + ARRAY_FIELD_DP32(s->regs, DEV_CHAR_TABLE_POINTER, + P_DEV_CHAR_TABLE_START_ADDR, + s->cfg.dev_char_table_pointer); + ARRAY_FIELD_DP32(s->regs, DEV_CHAR_TABLE_POINTER, DEV_CHAR_TABLE_DEPTH, + s->cfg.dev_char_table_depth); + + dw_i3c_cmd_queue_reset(s); + dw_i3c_resp_queue_reset(s); + dw_i3c_ibi_queue_reset(s); + dw_i3c_tx_queue_reset(s); + dw_i3c_rx_queue_reset(s); +} + +static void dw_i3c_reset_ctrl_w(DWI3C *s, uint32_t val) +{ + if (FIELD_EX32(val, RESET_CTRL, CORE_RESET)) { + dw_i3c_reset(DEVICE(s)); + } + if (FIELD_EX32(val, RESET_CTRL, CMD_QUEUE_RESET)) { + dw_i3c_cmd_queue_reset(s); + } + if (FIELD_EX32(val, RESET_CTRL, RESP_QUEUE_RESET)) { + dw_i3c_resp_queue_reset(s); + } + if (FIELD_EX32(val, RESET_CTRL, TX_BUF_RESET)) { + dw_i3c_tx_queue_reset(s); + } + if (FIELD_EX32(val, RESET_CTRL, RX_BUF_RESET)) { + dw_i3c_rx_queue_reset(s); + } + if (FIELD_EX32(val, RESET_CTRL, IBI_QUEUE_RESET)) { + dw_i3c_ibi_queue_reset(s); + } +} + static uint32_t dw_i3c_pop_rx(DWI3C *s) { if (fifo32_is_empty(&s->rx_queue)) { @@ -XXX,XX +XXX,XX @@ static void dw_i3c_write(void *opaque, hwaddr offset, uint64_t value, dw_i3c_cmd_queue_port_w(s, val32); break; case R_RESET_CTRL: + dw_i3c_reset_ctrl_w(s, val32); break; case R_INTR_STATUS: dw_i3c_intr_status_w(s, val32); diff --git a/hw/i3c/trace-events b/hw/i3c/trace-events index XXXXXXX..XXXXXXX 100644 --- a/hw/i3c/trace-events +++ b/hw/i3c/trace-events @@ -XXX,XX +XXX,XX @@ dw_i3c_send(uint32_t deviceid, uint32_t num_bytes) "I3C Dev[%u] send %" PRId32 " dw_i3c_recv_data(uint32_t deviceid, uint32_t num_bytes) "I3C Dev[%u] recv %" PRId32 " bytes from bus" dw_i3c_ibi_recv(uint32_t deviceid, uint8_t ibi_byte) "I3C Dev[%u] recv IBI byte 0x%" PRIx8 dw_i3c_ibi_handle(uint32_t deviceid, uint8_t addr, bool rnw) "I3C Dev[%u] handle IBI from address 0x%" PRIx8 " RnW=%d" +dw_i3c_reset(uint32_t deviceid) "I3C Dev[%u] reset" dw_i3c_pop_rx(uint32_t deviceid, uint32_t data) "I3C Dev[%u] pop 0x%" PRIx32 " from RX FIFO" dw_i3c_resp_queue_push(uint32_t deviceid, uint32_t data) "I3C Dev[%u] push 0x%" PRIx32 " to response queue" dw_i3c_push_tx(uint32_t deviceid, uint32_t data) "I3C Dev[%u] push 0x%" PRIx32 " to TX FIFO" -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> To retrieve the I3C bus object normally, the order is Aspeed I3C -> DW I3C[n] -> bus object, so make a nice wrapper for people to use. Signed-off-by: Joe Komlodi <komlodi@google.com> Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Tested-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260225021158.1586584-18-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- include/hw/i3c/aspeed_i3c.h | 3 +++ hw/i3c/aspeed_i3c.c | 9 +++++++++ 2 files changed, 12 insertions(+) diff --git a/include/hw/i3c/aspeed_i3c.h b/include/hw/i3c/aspeed_i3c.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/i3c/aspeed_i3c.h +++ b/include/hw/i3c/aspeed_i3c.h @@ -XXX,XX +XXX,XX @@ struct AspeedI3CState { DWI3C devices[ASPEED_I3C_NR_DEVICES]; uint8_t id; }; + +I3CBus *aspeed_i3c_get_bus(AspeedI3CState *s, uint8_t bus_num); + #endif /* ASPEED_I3C_H */ diff --git a/hw/i3c/aspeed_i3c.c b/hw/i3c/aspeed_i3c.c index XXXXXXX..XXXXXXX 100644 --- a/hw/i3c/aspeed_i3c.c +++ b/hw/i3c/aspeed_i3c.c @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_i3c_ops = { } }; +I3CBus *aspeed_i3c_get_bus(AspeedI3CState *s, uint8_t bus_num) +{ + if (bus_num < ARRAY_SIZE(s->devices)) { + return s->devices[bus_num].bus; + } + /* Developer error, fail fast. */ + g_assert_not_reached(); +} + static void aspeed_i3c_reset(DeviceState *dev) { AspeedI3CState *s = ASPEED_I3C(dev); -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> Adds a simple i3c device to be used for testing in lieu of a real device. The mock target supports the following features: - A buffer that users can read and write to. - CCC support for commonly used CCCs when probing devices on an I3C bus. - IBI sending upon receiving a user-defined byte. Signed-off-by: Joe Komlodi <komlodi@google.com> Reviewed-by: Titus Rwantare <titusr@google.com> Reviewed-by: Patrick Venture <venture@google.com> Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Tested-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260225021158.1586584-19-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- include/hw/i3c/mock-i3c-target.h | 52 ++++++ hw/i3c/mock-i3c-target.c | 298 +++++++++++++++++++++++++++++++ hw/i3c/Kconfig | 10 ++ hw/i3c/meson.build | 1 + hw/i3c/trace-events | 10 ++ 5 files changed, 371 insertions(+) create mode 100644 include/hw/i3c/mock-i3c-target.h create mode 100644 hw/i3c/mock-i3c-target.c diff --git a/include/hw/i3c/mock-i3c-target.h b/include/hw/i3c/mock-i3c-target.h new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/include/hw/i3c/mock-i3c-target.h @@ -XXX,XX +XXX,XX @@ +#ifndef MOCK_I3C_TARGET_H_ +#define MOCK_I3C_TARGET_H_ + +/* + * Mock I3C Device + * + * Copyright (c) 2025 Google LLC + * + * The mock I3C device can be thought of as a simple EEPROM. It has a buffer, + * and the pointer in the buffer is reset to 0 on an I3C STOP. + * To write to the buffer, issue a private write and send data. + * To read from the buffer, issue a private read. + * + * The mock target also supports sending target interrupt IBIs. + * To issue an IBI, set the 'ibi-magic-num' property to a non-zero number, and + * send that number in a private transaction. The mock target will issue an IBI + * after 1 second. + * + * It also supports a handful of CCCs that are typically used when probing I3C + * devices. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/timer.h" +#include "hw/i3c/i3c.h" + +#define TYPE_MOCK_I3C_TARGET "mock-i3c-target" +OBJECT_DECLARE_SIMPLE_TYPE(MockI3cTargetState, MOCK_I3C_TARGET) + +struct MockI3cTargetState { + I3CTarget parent_obj; + + /* General device state */ + bool can_ibi; + QEMUTimer qtimer; + size_t p_buf; + uint8_t *buf; + + /* For Handing CCCs. */ + bool in_ccc; + I3CCCC curr_ccc; + uint8_t ccc_byte_offset; + + struct { + uint32_t buf_size; + uint8_t ibi_magic; + } cfg; +}; + +#endif diff --git a/hw/i3c/mock-i3c-target.c b/hw/i3c/mock-i3c-target.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/hw/i3c/mock-i3c-target.c @@ -XXX,XX +XXX,XX @@ +/* + * Mock I3C Device + * + * Copyright (c) 2025 Google LLC + * + * The mock I3C device can be thought of as a simple EEPROM. It has a buffer, + * and the pointer in the buffer is reset to 0 on an I3C STOP. + * To write to the buffer, issue a private write and send data. + * To read from the buffer, issue a private read. + * + * The mock target also supports sending target interrupt IBIs. + * To issue an IBI, set the 'ibi-magic-num' property to a non-zero number, and + * send that number in a private transaction. The mock target will issue an IBI + * after 1 second. + * + * It also supports a handful of CCCs that are typically used when probing I3C + * devices. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "trace.h" +#include "hw/i3c/i3c.h" +#include "hw/i3c/mock-i3c-target.h" +#include "hw/core/irq.h" +#include "hw/core/qdev-properties.h" +#include "qapi/error.h" +#include "qemu/module.h" + +#define IBI_DELAY_NS (1 * 1000 * 1000) + +static uint32_t mock_i3c_target_rx(I3CTarget *i3c, uint8_t *data, + uint32_t num_to_read) +{ + MockI3cTargetState *s = MOCK_I3C_TARGET(i3c); + uint32_t i; + + /* Bounds check. */ + if (s->p_buf == s->cfg.buf_size) { + return 0; + } + + for (i = 0; i < num_to_read; i++) { + data[i] = s->buf[s->p_buf]; + trace_mock_i3c_target_rx(data[i]); + s->p_buf++; + if (s->p_buf == s->cfg.buf_size) { + break; + } + } + + /* Return the number of bytes we're sending to the controller. */ + return i; +} + +static void mock_i3c_target_ibi_timer_start(MockI3cTargetState *s) +{ + int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + timer_mod(&s->qtimer, now + IBI_DELAY_NS); +} + +static int mock_i3c_target_tx(I3CTarget *i3c, const uint8_t *data, + uint32_t num_to_send, uint32_t *num_sent) +{ + MockI3cTargetState *s = MOCK_I3C_TARGET(i3c); + int ret; + uint32_t to_write; + + if (s->cfg.ibi_magic && num_to_send == 1 && s->cfg.ibi_magic == *data) { + mock_i3c_target_ibi_timer_start(s); + return 0; + } + + /* Bounds check. */ + if (num_to_send + s->p_buf > s->cfg.buf_size) { + to_write = s->cfg.buf_size - s->p_buf; + ret = -1; + } else { + to_write = num_to_send; + ret = 0; + } + for (uint32_t i = 0; i < to_write; i++) { + trace_mock_i3c_target_tx(data[i]); + s->buf[s->p_buf] = data[i]; + s->p_buf++; + } + return ret; +} + +static int mock_i3c_target_event(I3CTarget *i3c, enum I3CEvent event) +{ + MockI3cTargetState *s = MOCK_I3C_TARGET(i3c); + + trace_mock_i3c_target_event(event); + if (event == I3C_STOP) { + s->in_ccc = false; + s->curr_ccc = 0; + s->ccc_byte_offset = 0; + s->p_buf = 0; + } + + return 0; +} + +static int mock_i3c_target_handle_ccc_read(I3CTarget *i3c, uint8_t *data, + uint32_t num_to_read, + uint32_t *num_read) +{ + MockI3cTargetState *s = MOCK_I3C_TARGET(i3c); + + switch (s->curr_ccc) { + case I3C_CCCD_GETMXDS: + /* Default data rate for I3C. */ + while (s->ccc_byte_offset < num_to_read) { + if (s->ccc_byte_offset >= 2) { + break; + } + data[s->ccc_byte_offset] = 0; + *num_read = s->ccc_byte_offset; + s->ccc_byte_offset++; + } + break; + case I3C_CCCD_GETCAPS: + /* Support I3C version 1.1.x, no other features. */ + while (s->ccc_byte_offset < num_to_read) { + if (s->ccc_byte_offset >= 2) { + break; + } + if (s->ccc_byte_offset == 0) { + data[s->ccc_byte_offset] = 0; + } else { + data[s->ccc_byte_offset] = 0x01; + } + *num_read = s->ccc_byte_offset; + s->ccc_byte_offset++; + } + break; + case I3C_CCCD_GETMWL: + case I3C_CCCD_GETMRL: + /* MWL/MRL is MSB first. */ + while (s->ccc_byte_offset < num_to_read) { + if (s->ccc_byte_offset >= 2) { + break; + } + data[s->ccc_byte_offset] = (s->cfg.buf_size & + (0xff00 >> (s->ccc_byte_offset * 8))) >> + (8 - (s->ccc_byte_offset * 8)); + s->ccc_byte_offset++; + *num_read = num_to_read; + } + break; + case I3C_CCC_ENTDAA: + case I3C_CCCD_GETPID: + case I3C_CCCD_GETBCR: + case I3C_CCCD_GETDCR: + /* Nothing to do. */ + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "Unhandled CCC 0x%.2x\n", s->curr_ccc); + return -1; + } + + trace_mock_i3c_target_handle_ccc_read(*num_read, num_to_read); + return 0; +} + +static int mock_i3c_target_handle_ccc_write(I3CTarget *i3c, const uint8_t *data, + uint32_t num_to_send, + uint32_t *num_sent) +{ + MockI3cTargetState *s = MOCK_I3C_TARGET(i3c); + + if (!s->curr_ccc) { + s->in_ccc = true; + s->curr_ccc = *data; + trace_mock_i3c_target_new_ccc(s->curr_ccc); + } + + *num_sent = 1; + switch (s->curr_ccc) { + case I3C_CCC_ENEC: + case I3C_CCCD_ENEC: + s->can_ibi = true; + break; + case I3C_CCC_DISEC: + case I3C_CCCD_DISEC: + s->can_ibi = false; + break; + case I3C_CCC_ENTDAA: + case I3C_CCC_SETAASA: + case I3C_CCC_RSTDAA: + case I3C_CCCD_SETDASA: + case I3C_CCCD_GETPID: + case I3C_CCCD_GETBCR: + case I3C_CCCD_GETDCR: + case I3C_CCCD_GETMWL: + case I3C_CCCD_GETMRL: + case I3C_CCCD_GETMXDS: + case I3C_CCCD_GETCAPS: + /* Nothing to do. */ + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "Unhandled CCC 0x%.2x\n", s->curr_ccc); + return -1; + } + + trace_mock_i3c_target_handle_ccc_write(*num_sent, num_to_send); + return 0; +} + +static void mock_i3c_target_do_ibi(MockI3cTargetState *s) +{ + if (!s->can_ibi) { + return; + } + + trace_mock_i3c_target_do_ibi(s->parent_obj.address, true); + int nack = i3c_target_send_ibi(&s->parent_obj, s->parent_obj.address, + /*is_recv=*/true); + /* Getting NACKed isn't necessarily an error, just print it out. */ + if (nack) { + trace_mock_i3c_target_do_ibi_nack("sending"); + } + nack = i3c_target_ibi_finish(&s->parent_obj, 0x00); + if (nack) { + trace_mock_i3c_target_do_ibi_nack("finishing"); + } +} + +static void mock_i3c_target_timer_elapsed(void *opaque) +{ + MockI3cTargetState *s = MOCK_I3C_TARGET(opaque); + timer_del(&s->qtimer); + mock_i3c_target_do_ibi(s); +} + +static void mock_i3c_target_reset(I3CTarget *i3c) +{ + MockI3cTargetState *s = MOCK_I3C_TARGET(i3c); + s->can_ibi = false; +} + +static void mock_i3c_target_realize(DeviceState *dev, Error **errp) +{ + MockI3cTargetState *s = MOCK_I3C_TARGET(dev); + s->buf = g_new0(uint8_t, s->cfg.buf_size); + mock_i3c_target_reset(&s->parent_obj); +} + +static void mock_i3c_target_init(Object *obj) +{ + MockI3cTargetState *s = MOCK_I3C_TARGET(obj); + s->can_ibi = false; + + /* For IBIs. */ + timer_init_ns(&s->qtimer, QEMU_CLOCK_VIRTUAL, mock_i3c_target_timer_elapsed, + s); +} + +static const Property remote_i3c_props[] = { + /* The size of the internal buffer. */ + DEFINE_PROP_UINT32("buf-size", MockI3cTargetState, cfg.buf_size, 0x100), + /* + * If the mock target receives this number, it will issue an IBI after + * 1 second. Disabled if the IBI magic number is 0. + */ + DEFINE_PROP_UINT8("ibi-magic-num", MockI3cTargetState, cfg.ibi_magic, 0x00), +}; + +static void mock_i3c_target_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + I3CTargetClass *k = I3C_TARGET_CLASS(klass); + + dc->realize = mock_i3c_target_realize; + k->event = mock_i3c_target_event; + k->recv = mock_i3c_target_rx; + k->send = mock_i3c_target_tx; + k->handle_ccc_read = mock_i3c_target_handle_ccc_read; + k->handle_ccc_write = mock_i3c_target_handle_ccc_write; + + device_class_set_props(dc, remote_i3c_props); +} + +static const TypeInfo mock_i3c_target_types[] = { + { + .name = TYPE_MOCK_I3C_TARGET, + .parent = TYPE_I3C_TARGET, + .instance_size = sizeof(MockI3cTargetState), + .instance_init = mock_i3c_target_init, + .class_init = mock_i3c_target_class_init, + }, +}; + +DEFINE_TYPES(mock_i3c_target_types) + diff --git a/hw/i3c/Kconfig b/hw/i3c/Kconfig index XXXXXXX..XXXXXXX 100644 --- a/hw/i3c/Kconfig +++ b/hw/i3c/Kconfig @@ -XXX,XX +XXX,XX @@ config I3C config DW_I3C bool + +config I3C_DEVICES + # Device group for i3c devices which can reasonably be user-plugged to any + # board's i3c bus. + bool + +config MOCK_I3C_TARGET + bool + select I3C + default y if I3C_DEVICES diff --git a/hw/i3c/meson.build b/hw/i3c/meson.build index XXXXXXX..XXXXXXX 100644 --- a/hw/i3c/meson.build +++ b/hw/i3c/meson.build @@ -XXX,XX +XXX,XX @@ i3c_ss = ss.source_set() i3c_ss.add(when: 'CONFIG_I3C', if_true: files('core.c')) i3c_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_i3c.c')) i3c_ss.add(when: 'CONFIG_DW_I3C', if_true: files('dw-i3c.c')) +i3c_ss.add(when: 'CONFIG_MOCK_I3C_TARGET', if_true: files('mock-i3c-target.c')) system_ss.add_all(when: 'CONFIG_I3C', if_true: i3c_ss) diff --git a/hw/i3c/trace-events b/hw/i3c/trace-events index XXXXXXX..XXXXXXX 100644 --- a/hw/i3c/trace-events +++ b/hw/i3c/trace-events @@ -XXX,XX +XXX,XX @@ legacy_i2c_recv(uint8_t byte) "Legacy I2C recv 0x%" PRIx8 legacy_i2c_send(uint8_t byte) "Legacy I2C send 0x%" PRIx8 legacy_i2c_start_transfer(uint8_t address, bool is_recv) "Legacy I2C START with address 0x%" PRIx8 " is_recv=%d" legacy_i2c_end_transfer(void) "Legacy I2C STOP" + +# mock-target.c +mock_i3c_target_rx(uint8_t byte) "I3C mock target read 0x%" PRIx8 +mock_i3c_target_tx(uint8_t byte) "I3C mock target write 0x%" PRIx8 +mock_i3c_target_event(uint8_t event) "I3C mock target event 0x%" PRIx8 +mock_i3c_target_handle_ccc_read(uint32_t num_read, uint32_t num_to_read) "I3C mock target read %" PRId32 "/%" PRId32 " bytes" +mock_i3c_target_new_ccc(uint8_t ccc) "I3C mock target handle CCC 0x%" PRIx8 +mock_i3c_target_handle_ccc_write(uint32_t num_sent, uint32_t num_to_send) "I3C mock target send %" PRId32 "/%" PRId32 " bytes" +mock_i3c_target_do_ibi(uint8_t address, bool is_recv) "I3C mock target IBI with address 0x%" PRIx8 " RnW=%d" +mock_i3c_target_do_ibi_nack(const char *reason) "NACKed from controller when %s target interrupt" -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> Allows us to attach the mock I3C target Signed-off-by: Joe Komlodi <komlodi@google.com> Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Tested-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260225021158.1586584-20-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- hw/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -XXX,XX +XXX,XX @@ config ASPEED_SOC select I2C select I3C select DW_I3C + select I3C_DEVICES select DPS310 select PCA9552 select PCA9554 -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> This adds support for hotplugging in I3C. Conceptually this can be thought of as an I3C target being physically socketed onto a board. It is then the target's responsibility to go through the hot-join and DAA process so it can participate on the bus. Signed-off-by: Joe Komlodi <komlodi@google.com> Reviewed-by: Patrick Venture <venture@google.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Tested-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260225021158.1586584-21-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- hw/i3c/core.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/hw/i3c/core.c b/hw/i3c/core.c index XXXXXXX..XXXXXXX 100644 --- a/hw/i3c/core.c +++ b/hw/i3c/core.c @@ -XXX,XX +XXX,XX @@ #include "qapi/error.h" #include "trace.h" #include "hw/i3c/i3c.h" +#include "hw/core/hotplug.h" #include "hw/core/qdev-properties.h" /* @@ -XXX,XX +XXX,XX @@ static const Property i3c_props[] = { DEFINE_PROP_UINT64("pid", struct I3CTarget, pid, 0), }; +static void i3c_realize(BusState *bus, Error **errp) +{ + qbus_set_bus_hotplug_handler(bus); +} + +static void i3c_class_init(ObjectClass *klass, const void *data) +{ + BusClass *k = BUS_CLASS(klass); + k->realize = i3c_realize; +} + I3CBus *i3c_init_bus(DeviceState *parent, const char *name) { return i3c_init_bus_type(TYPE_I3C_BUS, parent, name); @@ -XXX,XX +XXX,XX @@ static const TypeInfo i3c_types[] = { .parent = TYPE_BUS, .instance_size = sizeof(I3CBus), .class_size = sizeof(I3CBusClass), + .class_init = i3c_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_HOTPLUG_HANDLER }, + { } + } }, { .name = TYPE_I3C_TARGET, -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Tested-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260225021158.1586584-22-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- tests/functional/arm/test_aspeed_ast2600_sdk.py | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/tests/functional/arm/test_aspeed_ast2600_sdk.py b/tests/functional/arm/test_aspeed_ast2600_sdk.py index XXXXXXX..XXXXXXX 100755 --- a/tests/functional/arm/test_aspeed_ast2600_sdk.py +++ b/tests/functional/arm/test_aspeed_ast2600_sdk.py @@ -XXX,XX +XXX,XX @@ def do_ast2600_pcie_test(self): 'ip addr show dev eth4', 'inet 10.0.2.15/24') + def do_ast2600_i3c_test(self): + exec_command_and_wait_for_pattern(self, + 'i3ctransfer -d /dev/bus/i3c/5-1234567890ab' + ' -w 0x12,0x34,0x56,0x78,0x90,0xab,0xcd,0xef', + 'Success on message 0') + exec_command_and_wait_for_pattern(self, + 'i3ctransfer -d /dev/bus/i3c/5-1234567890ab -r 8 | grep 0x | xargs', + '0x12 0x34 0x56 0x78 0x90 0xab 0xcd 0xef') + def test_arm_ast2600_evb_sdk(self): self.set_machine('ast2600-evb') self.require_netdev('user') @@ -XXX,XX +XXX,XX @@ def test_arm_ast2600_evb_sdk(self): 'ds1338,bus=aspeed.i2c.bus.5,address=0x32') self.vm.add_args('-device', 'e1000e,netdev=net1,bus=pcie.0') self.vm.add_args('-netdev', 'user,id=net1') + self.vm.add_args('-device', + 'mock-i3c-target,bus=dw.i3c.5,pid=0xab9078563412') self.do_test_arm_aspeed_sdk_start( self.scratch_file("ast2600-default", "image-bmc")) @@ -XXX,XX +XXX,XX @@ def test_arm_ast2600_evb_sdk(self): exec_command_and_wait_for_pattern(self, '/sbin/hwclock -f /dev/rtc1', year) self.do_ast2600_pcie_test() + self.do_ast2600_i3c_test() if __name__ == '__main__': -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> Add a new I3C section to the MAINTAINERS file. List Joe Komlodi, Cédric Le Goater and Jamin Lin as maintainers, and Nabih Estefan as the reviewer, covering the I3C core and related files under hw/i3c/ and include/hw/i3c/. Signed-off-by: Nabih Estefan <nabihestefan@google.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Tested-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260225021158.1586584-23-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- MAINTAINERS | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index XXXXXXX..XXXXXXX 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -XXX,XX +XXX,XX @@ F: include/hw/i2c/smbus_master.h F: include/hw/i2c/smbus_slave.h F: include/hw/i2c/smbus_eeprom.h +I3C +M: Joe Komlodi <komlodi@google.com> +M: Cédric Le Goater <clg@kaod.org> +M: Jamin Lin <jamin_lin@aspeedtech.com> +R: Nabih Estefan <nabihestefan@google.com> +S: Maintained +F: hw/i3c/*.c +F: hw/i3c/.h +F: hw/i3c/Kconfig +F: hw/i3c/meson.build +F: hw/i3c/trace-events +F: include/hw/i3c/*.h + PMBus M: Titus Rwantare <titusr@google.com> S: Maintained -- 2.53.0 The size of the is_rsvd lookup table in i3c_addr_is_rsvd() is 255 but should be 256 to cover all possible uint8_t address values and avoid potential out-of-bounds access. The array should be static too as it's a constant lookup table. Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Nabih Estefan <nabihestefan@google.com> Link: https://lore.kernel.org/qemu-devel/20260302193931.382228-1-clg@redhat.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- hw/i3c/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/i3c/core.c b/hw/i3c/core.c index XXXXXXX..XXXXXXX 100644 --- a/hw/i3c/core.c +++ b/hw/i3c/core.c @@ -XXX,XX +XXX,XX @@ int i3c_target_ibi_finish(I3CTarget *t, uint8_t data) static bool i3c_addr_is_rsvd(uint8_t addr) { - const bool is_rsvd[255] = { + static const bool is_rsvd[256] = { [0x00] = true, [0x01] = true, [0x02] = true, -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> The RX temporary buffer allocation manually aligned the size using: num + (4 - (num & 0x03)) Replace this with ROUND_UP(num, 4) for better readability and consistency with common QEMU coding style. No functional change. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260303013322.1297499-2-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- hw/i3c/dw-i3c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c index XXXXXXX..XXXXXXX 100644 --- a/hw/i3c/dw-i3c.c +++ b/hw/i3c/dw-i3c.c @@ -XXX,XX +XXX,XX @@ static uint16_t dw_i3c_rx(DWI3C *s, uint16_t num, bool is_i2c) * Allocate a temporary buffer to read data from the target. * Zero it and word-align it as well in case we're reading unaligned data. */ - g_autofree uint8_t *data = g_new0(uint8_t, num + (4 - (num & 0x03))); + g_autofree uint8_t *data = g_new0(uint8_t, ROUND_UP(num, 4)); uint32_t *data32 = (uint32_t *)data; /* * 32-bits since the I3C API wants a 32-bit number, even though the -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> mock_i3c_target_tx() did not update *num_sent before returning. Although some callers may not directly use this value, i3c_send() passes num_sent to trace_i3c_send(). If the target TX callback does not initialize *num_sent, the trace output may report an incorrect or uninitialized value, leading to confusing debugging information. For example, the following trace was observed: mock_i3c_target_tx I3C mock target write 0x12 i3c_send I3C send 0/1 bytes, ack=1 (expected 1/1 bytes) This happens because *num_sent was never set by the TX callback. Fix this by setting *num_sent in all return paths, including the IBI magic handling case, to accurately reflect the number of bytes consumed. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260303013322.1297499-3-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- hw/i3c/mock-i3c-target.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/i3c/mock-i3c-target.c b/hw/i3c/mock-i3c-target.c index XXXXXXX..XXXXXXX 100644 --- a/hw/i3c/mock-i3c-target.c +++ b/hw/i3c/mock-i3c-target.c @@ -XXX,XX +XXX,XX @@ static int mock_i3c_target_tx(I3CTarget *i3c, const uint8_t *data, if (s->cfg.ibi_magic && num_to_send == 1 && s->cfg.ibi_magic == *data) { mock_i3c_target_ibi_timer_start(s); + *num_sent = 1; return 0; } @@ -XXX,XX +XXX,XX @@ static int mock_i3c_target_tx(I3CTarget *i3c, const uint8_t *data, s->buf[s->p_buf] = data[i]; s->p_buf++; } + *num_sent = to_write; return ret; } -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> i3c_send_byte() declared num_sent without initializing it before passing its address to i3c_send(). Although i3c_send_byte() itself ignores num_sent after the call, i3c_send() forwards it to trace_i3c_send(). If the target send callback does not set *num_sent, the trace may print an uninitialized value, leading to misleading or garbage output. Example concern from review: trace_i3c_send(*num_sent, num_to_send, ret == 0); If *num_sent is not written by the callback, this trace can report an incorrect number of transmitted bytes. Initialize num_sent to 0 to ensure deterministic and predictable trace output, even if the callback fails to update it. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260303013322.1297499-4-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- hw/i3c/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/i3c/core.c b/hw/i3c/core.c index XXXXXXX..XXXXXXX 100644 --- a/hw/i3c/core.c +++ b/hw/i3c/core.c @@ -XXX,XX +XXX,XX @@ int i3c_send_byte(I3CBus *bus, uint8_t data) * Ignored, the caller can determine how many were sent based on if this was * ACKed/NACKed. */ - uint32_t num_sent; + uint32_t num_sent = 0; return i3c_send(bus, &data, 1, &num_sent); } -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> The GETMRL handling logic extracted MSB/LSB bytes from s->cfg.buf_size using a mask-and-shift expression: (buf_size & (0xff00 >> (offset * 8))) >> (8 - (offset * 8)) While functionally correct, the expression is difficult to read and obscures the intent, which is simply to return a 16-bit value in MSB-first order. Replace the mask/shift formula with explicit MSB/LSB extraction: offset == 0 -> buf_size >> 8 offset == 1 -> buf_size & 0xff This makes the code clearer and easier to review without altering behavior or data ordering. No functional change. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com> Link: https://lore.kernel.org/qemu-devel/20260303013322.1297499-5-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- hw/i3c/mock-i3c-target.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/hw/i3c/mock-i3c-target.c b/hw/i3c/mock-i3c-target.c index XXXXXXX..XXXXXXX 100644 --- a/hw/i3c/mock-i3c-target.c +++ b/hw/i3c/mock-i3c-target.c @@ -XXX,XX +XXX,XX @@ static int mock_i3c_target_handle_ccc_read(I3CTarget *i3c, uint8_t *data, if (s->ccc_byte_offset >= 2) { break; } - data[s->ccc_byte_offset] = (s->cfg.buf_size & - (0xff00 >> (s->ccc_byte_offset * 8))) >> - (8 - (s->ccc_byte_offset * 8)); + if (s->ccc_byte_offset == 0) { + data[s->ccc_byte_offset] = (uint8_t)(s->cfg.buf_size >> 8); + } else { + data[s->ccc_byte_offset] = (uint8_t)s->cfg.buf_size; + } + s->ccc_byte_offset++; *num_read = num_to_read; } -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Tested-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260303063930.2878300-2-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- tests/functional/arm/test_aspeed_ast1030.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/tests/functional/arm/test_aspeed_ast1030.py b/tests/functional/arm/test_aspeed_ast1030.py index XXXXXXX..XXXXXXX 100755 --- a/tests/functional/arm/test_aspeed_ast1030.py +++ b/tests/functional/arm/test_aspeed_ast1030.py @@ -XXX,XX +XXX,XX @@ class AST1030Machine(AspeedTest): - ASSET_ZEPHYR_3_05 = Asset( + ASSET_ZEPHYR_3_06 = Asset( ('https://github.com/AspeedTech-BMC' - '/zephyr/releases/download/v00.03.05/ast1030-evb-demo.zip'), - '057528d343490b1fbb5a721e91084b4f04fec60dc114bd65e724554f9c217f4b') + '/zephyr/releases/download/v00.03.06/ast1030-evb-demo.zip'), + '056f37fcd9f165308cedca3a08f2bed37ed40c0a1402c4fa515613b80a369f38') - def test_arm_ast1030_zephyros_3_05(self): + def test_arm_ast1030_zephyros_3_06(self): self.set_machine('ast1030-evb') kernel_name = "ast1030-evb-demo/zephyr.elf" kernel_file = self.archive_extract( - self.ASSET_ZEPHYR_3_05, member=kernel_name) + self.ASSET_ZEPHYR_3_06, member=kernel_name) self.vm.set_console() self.vm.add_args('-kernel', kernel_file, '-nographic') @@ -XXX,XX +XXX,XX @@ def test_arm_ast1030_otp_blockdev_device(self): self.vm.set_machine("ast1030-evb") kernel_name = "ast1030-evb-demo/zephyr.elf" - kernel_file = self.archive_extract(self.ASSET_ZEPHYR_3_05, + kernel_file = self.archive_extract(self.ASSET_ZEPHYR_3_06, member=kernel_name) otp_img = self.generate_otpmem_image() -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Tested-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260303063930.2878300-3-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- tests/functional/arm/test_aspeed_ast1060.py | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/tests/functional/arm/test_aspeed_ast1060.py b/tests/functional/arm/test_aspeed_ast1060.py index XXXXXXX..XXXXXXX 100755 --- a/tests/functional/arm/test_aspeed_ast1060.py +++ b/tests/functional/arm/test_aspeed_ast1060.py @@ -XXX,XX +XXX,XX @@ class AST1060Machine(AspeedTest): - ASSET_ASPEED_AST1060_PROT_3_04 = Asset( + ASSET_ASPEED_AST1060_PROT_3_05 = Asset( ('https://github.com/AspeedTech-BMC' - '/aspeed-zephyr-project/releases/download/v03.04' - '/ast1060_prot_v03.04.tgz'), - 'c0319df55f5b7a547efefc5a6ba374b881223d5fe1a776bfdd36f97fd1f31d50') + '/aspeed-zephyr-project/releases/download/v03.05' + '/ast1060_prot_v03.05.tgz'), + '63b36d7420290726ca80477de254474b7cb79539a42819bb1fe2665d598dadb5') - def test_arm_ast1060_prot_3_04(self): + def test_arm_ast1060_prot_3_05(self): self.set_machine('ast1060-evb') kernel_name = "ast1060_prot/zephyr.bin" kernel_file = self.archive_extract( - self.ASSET_ASPEED_AST1060_PROT_3_04, member=kernel_name) + self.ASSET_ASPEED_AST1060_PROT_3_05, member=kernel_name) self.vm.set_console() self.vm.add_args('-kernel', kernel_file, '-nographic') @@ -XXX,XX +XXX,XX @@ def test_arm_ast1060_otp_blockdev_device(self): self.vm.set_machine("ast1060-evb") kernel_name = "ast1060_prot/zephyr.bin" - kernel_file = self.archive_extract(self.ASSET_ASPEED_AST1060_PROT_3_04, + kernel_file = self.archive_extract(self.ASSET_ASPEED_AST1060_PROT_3_05, member=kernel_name) otp_img = self.generate_otpmem_image() -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Tested-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260303063930.2878300-4-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- tests/functional/arm/test_aspeed_ast2500_sdk.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tests/functional/arm/test_aspeed_ast2500_sdk.py b/tests/functional/arm/test_aspeed_ast2500_sdk.py index XXXXXXX..XXXXXXX 100755 --- a/tests/functional/arm/test_aspeed_ast2500_sdk.py +++ b/tests/functional/arm/test_aspeed_ast2500_sdk.py @@ -XXX,XX +XXX,XX @@ class AST2500Machine(AspeedTest): - ASSET_SDK_V1000_AST2500 = Asset( - 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v10.00/ast2500-default-obmc.tar.gz', - '7d71a3f71d5f4d9f3451f59a73bf9baf8fd9f6a24107eb504a3216151a8b2b5b') + ASSET_SDK_V1101_AST2500 = Asset( + 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.01/ast2500-default-obmc.tar.gz', + '3faa1188198da2216837be4b53861c483a58c3ad63784089720bf8421e157da1') def test_arm_ast2500_evb_sdk(self): self.set_machine('ast2500-evb') - self.archive_extract(self.ASSET_SDK_V1000_AST2500) + self.archive_extract(self.ASSET_SDK_V1101_AST2500) self.do_test_arm_aspeed_sdk_start( self.scratch_file("ast2500-default", "image-bmc")) -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Tested-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260303063930.2878300-5-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- tests/functional/arm/test_aspeed_ast2500_sdk_515.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tests/functional/arm/test_aspeed_ast2500_sdk_515.py b/tests/functional/arm/test_aspeed_ast2500_sdk_515.py index XXXXXXX..XXXXXXX 100755 --- a/tests/functional/arm/test_aspeed_ast2500_sdk_515.py +++ b/tests/functional/arm/test_aspeed_ast2500_sdk_515.py @@ -XXX,XX +XXX,XX @@ class AST2500Machine(AspeedTest): - ASSET_SDK_V1100_AST2500_515 = Asset( - 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.00/ast2500-default-515-obmc.tar.gz', - '5732255d4617d98b76bbbc116d331d6ac89906fa212969eb8213fdc4aea86451') + ASSET_SDK_V1101_AST2500_515 = Asset( + 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.01/ast2500-default-515-obmc.tar.gz', + 'b848ff620d2e9c83e2fb4736b4d1c39b82fdb041058cd42be42c3b177bf38eb9') def test_arm_ast2500_evb_sdk_515(self): self.set_machine('ast2500-evb') - self.archive_extract(self.ASSET_SDK_V1100_AST2500_515) + self.archive_extract(self.ASSET_SDK_V1101_AST2500_515) self.do_test_arm_aspeed_sdk_start( self.scratch_file("ast2500-default-515", "image-bmc")) -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Tested-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260303063930.2878300-6-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- tests/functional/arm/test_aspeed_ast2600_sdk.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/tests/functional/arm/test_aspeed_ast2600_sdk.py b/tests/functional/arm/test_aspeed_ast2600_sdk.py index XXXXXXX..XXXXXXX 100755 --- a/tests/functional/arm/test_aspeed_ast2600_sdk.py +++ b/tests/functional/arm/test_aspeed_ast2600_sdk.py @@ -XXX,XX +XXX,XX @@ class AST2600Machine(AspeedTest): - ASSET_SDK_V1100_AST2600 = Asset( - 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.00/ast2600-default-obmc.tar.gz', - '64d8926a7d01b649168be96c986603b5690f06391286c438a3a772c8c7039e93') + ASSET_SDK_V1101_AST2600 = Asset( + 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.01/ast2600-default-image.tar.gz', + '3c5b4d4ccf27b0d208a073f98426db54cd751b96143180cd15df1a83978f832c') def do_ast2600_pcie_test(self): exec_command_and_wait_for_pattern(self, @@ -XXX,XX +XXX,XX @@ def test_arm_ast2600_evb_sdk(self): self.set_machine('ast2600-evb') self.require_netdev('user') - self.archive_extract(self.ASSET_SDK_V1100_AST2600) + self.archive_extract(self.ASSET_SDK_V1101_AST2600) self.vm.add_args('-device', 'tmp105,bus=aspeed.i2c.bus.5,address=0x4d,id=tmp-test') @@ -XXX,XX +XXX,XX @@ def test_arm_ast2600_evb_sdk(self): self.vm.add_args('-device', 'mock-i3c-target,bus=dw.i3c.5,pid=0xab9078563412') self.do_test_arm_aspeed_sdk_start( - self.scratch_file("ast2600-default", "image-bmc")) + self.scratch_file("ast2600-default-image", "image-bmc")) self.wait_for_console_pattern('ast2600-default login:') -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Tested-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260303063930.2878300-7-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- tests/functional/arm/test_aspeed_ast2600_sdk_otp.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/tests/functional/arm/test_aspeed_ast2600_sdk_otp.py b/tests/functional/arm/test_aspeed_ast2600_sdk_otp.py index XXXXXXX..XXXXXXX 100755 --- a/tests/functional/arm/test_aspeed_ast2600_sdk_otp.py +++ b/tests/functional/arm/test_aspeed_ast2600_sdk_otp.py @@ -XXX,XX +XXX,XX @@ class AST2600Machine(AspeedTest): - ASSET_SDK_V1100_AST2600 = Asset( - 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.00/ast2600-default-obmc.tar.gz', - '64d8926a7d01b649168be96c986603b5690f06391286c438a3a772c8c7039e93') + ASSET_SDK_V1101_AST2600 = Asset( + 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.01/ast2600-default-image.tar.gz', + '3c5b4d4ccf27b0d208a073f98426db54cd751b96143180cd15df1a83978f832c') def test_arm_ast2600_otp_blockdev_device(self): self.vm.set_machine("ast2600-evb") self.require_netdev('user') - image_path = self.archive_extract(self.ASSET_SDK_V1100_AST2600) + image_path = self.archive_extract(self.ASSET_SDK_V1101_AST2600) otp_img = self.generate_otpmem_image() self.vm.set_console() @@ -XXX,XX +XXX,XX @@ def test_arm_ast2600_otp_blockdev_device(self): "-global", "aspeed-otp.drive=otp", ) self.vm.add_args('-drive', 'file=' + - self.scratch_file("ast2600-default", "image-bmc") + + self.scratch_file("ast2600-default-image", "image-bmc") + ',if=mtd,format=raw', '-net', 'nic', '-net', 'user', '-snapshot') self.vm.launch() -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Tested-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260303063930.2878300-8-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- tests/functional/arm/test_aspeed_ast2600_sdk_515.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/tests/functional/arm/test_aspeed_ast2600_sdk_515.py b/tests/functional/arm/test_aspeed_ast2600_sdk_515.py index XXXXXXX..XXXXXXX 100755 --- a/tests/functional/arm/test_aspeed_ast2600_sdk_515.py +++ b/tests/functional/arm/test_aspeed_ast2600_sdk_515.py @@ -XXX,XX +XXX,XX @@ class AST2600Machine(AspeedTest): - ASSET_SDK_V1100_AST2600_515 = Asset( - 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.00/ast2600-default-515-obmc.tar.gz', - 'ece1a934095378929780f03e7d092e562f4b33b2841b80ad7c3d12a85744c0f6') + ASSET_SDK_V1101_AST2600_515 = Asset( + 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.01/ast2600-default-515-image.tar.gz', + 'f3ccf1c08db71cf891637fc73131b80b2c0c0e005c06d5dcae0cf74fc458b43c') def test_arm_ast2600_evb_sdk_515(self): self.set_machine('ast2600-evb') - self.archive_extract(self.ASSET_SDK_V1100_AST2600_515) + self.archive_extract(self.ASSET_SDK_V1101_AST2600_515) self.do_test_arm_aspeed_sdk_start( - self.scratch_file("ast2600-default-515", "image-bmc")) + self.scratch_file("ast2600-default-515-image", "image-bmc")) self.wait_for_console_pattern('ast2600-default-515 login:') -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Tested-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260303063930.2878300-9-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- .../aarch64/test_aspeed_ast2700a1.py | 30 +++++++++---------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/tests/functional/aarch64/test_aspeed_ast2700a1.py b/tests/functional/aarch64/test_aspeed_ast2700a1.py index XXXXXXX..XXXXXXX 100755 --- a/tests/functional/aarch64/test_aspeed_ast2700a1.py +++ b/tests/functional/aarch64/test_aspeed_ast2700a1.py @@ -XXX,XX +XXX,XX @@ def verify_openbmc_boot_and_login(self, name, enable_pcie=True): exec_command_and_wait_for_pattern(self, 'root', 'Password:') exec_command_and_wait_for_pattern(self, '0penBmc', f'root@{name}:~#') - ASSET_SDK_V1100_AST2700A1 = Asset( - 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.00/ast2700-a1-obmc.tar.gz', - 'd5ceed511cd0dfefbb102fff2d731159e0472948a28066dc0d90bcd54be76525') + ASSET_SDK_V1101_AST2700A1 = Asset( + 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.01/ast2700-a1-image.tar.gz', + '859808828531a51931aad3b4e70b28143eebb3cde1838ba7d8e7a2b844c8a1ab') - ASSET_SDK_V1100_AST2700A1_DCSCM = Asset( - 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.00/ast2700-a1-dcscm-obmc.tar.gz', - '4f8778be176ece1b57d33c4aee13bb989be114c3e4703150eaeb6f996bd5587f') + ASSET_SDK_V1101_AST2700A1_DCSCM = Asset( + 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.01/ast2700-a1-dcscm-image.tar.gz', + '4654eabad75da3fd33635cd6d29b7635181daefee7294b68feb124b9d4c24116') def do_ast2700_i2c_test(self, bus_id): bus_str = str(bus_id) @@ -XXX,XX +XXX,XX @@ def start_ast2700_test_vbootrom(self, name, bus_id): self.do_test_aarch64_aspeed_sdk_start( self.scratch_file(name, 'image-bmc'), bus_id) - def test_aarch64_ast2700a1_evb_sdk_v11_00(self): + def test_aarch64_ast2700a1_evb_sdk_v11_01(self): self.set_machine('ast2700a1-evb') self.require_netdev('user') - self.archive_extract(self.ASSET_SDK_V1100_AST2700A1) + self.archive_extract(self.ASSET_SDK_V1101_AST2700A1) self.vm.add_args('-device', 'e1000e,netdev=net1,bus=pcie.2') self.vm.add_args('-netdev', 'user,id=net1') - self.start_ast2700_test('ast2700-a1', 1) + self.start_ast2700_test('ast2700-a1-image', 1) self.verify_openbmc_boot_and_login('ast2700-a1') self.do_ast2700_i2c_test(1) self.do_ast2700_pcie_test() - def test_aarch64_ast2700a1_evb_sdk_vbootrom_v11_00(self): + def test_aarch64_ast2700a1_evb_sdk_vbootrom_v11_01(self): self.set_machine('ast2700a1-evb') self.require_netdev('user') - self.archive_extract(self.ASSET_SDK_V1100_AST2700A1) + self.archive_extract(self.ASSET_SDK_V1101_AST2700A1) self.vm.add_args('-device', 'e1000e,netdev=net1,bus=pcie.2') self.vm.add_args('-netdev', 'user,id=net1') - self.start_ast2700_test_vbootrom('ast2700-a1', 1) + self.start_ast2700_test_vbootrom('ast2700-a1-image', 1) self.verify_vbootrom_firmware_flow() self.verify_openbmc_boot_start() - def test_aarch64_ast2700a1_evb_ioexp_v11_00(self): + def test_aarch64_ast2700a1_evb_ioexp_v11_01(self): self.set_machine('ast2700a1-evb') self.require_netdev('user') - self.archive_extract(self.ASSET_SDK_V1100_AST2700A1_DCSCM) + self.archive_extract(self.ASSET_SDK_V1101_AST2700A1_DCSCM) self.vm.set_machine('ast2700a1-evb,fmc-model=w25q512jv') self.vm.add_args('-device', 'tmp105,bus=ioexp0.0,address=0x4d,id=tmp-test-16') - self.start_ast2700_test('ast2700-a1-dcscm', 8) + self.start_ast2700_test('ast2700-a1-dcscm-image', 8) self.verify_openbmc_boot_and_login('ast2700-a1-dcscm', False) self.do_ast2700_i2c_test(8) self.do_ast2700_i2c_test(16) -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Tested-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260303063930.2878300-10-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- .../aarch64/test_aspeed_ast2700a2.py | 30 +++++++++---------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/tests/functional/aarch64/test_aspeed_ast2700a2.py b/tests/functional/aarch64/test_aspeed_ast2700a2.py index XXXXXXX..XXXXXXX 100755 --- a/tests/functional/aarch64/test_aspeed_ast2700a2.py +++ b/tests/functional/aarch64/test_aspeed_ast2700a2.py @@ -XXX,XX +XXX,XX @@ def verify_openbmc_boot_and_login(self, name, enable_pcie=True): exec_command_and_wait_for_pattern(self, 'root', 'Password:') exec_command_and_wait_for_pattern(self, '0penBmc', f'root@{name}:~#') - ASSET_SDK_V1100_AST2700A2 = Asset( - 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.00/ast2700-default-obmc.tar.gz', - 'e2b8f043fe8063dd3b6ded93422e38bd41914dc9c3202199507652df024de4dc') + ASSET_SDK_V1101_AST2700A2 = Asset( + 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.01/ast2700-default-image.tar.gz', + 'ce89dcd995cf284d41a6a4bd17a1b97d59939f0277bfe54fdaaf30e741ce7487') - ASSET_SDK_V1100_AST2700A2_DCSCM = Asset( - 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.00/ast2700-dcscm-obmc.tar.gz', - '0e93f7976139da71fab9df7952a58bdd80650e23e7abf5853b0eb6695deb02d0') + ASSET_SDK_V1101_AST2700A2_DCSCM = Asset( + 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.01/ast2700-dcscm-image.tar.gz', + 'b92ece9ca733dfd7a20193a12582f743b77f1898116b6d6f1abe57ac8db01c56') def do_ast2700_i2c_test(self, bus_id): bus_str = str(bus_id) @@ -XXX,XX +XXX,XX @@ def start_ast2700_test_vbootrom(self, name, bus_id): self.do_test_aarch64_aspeed_sdk_start( self.scratch_file(name, 'image-bmc'), bus_id) - def test_aarch64_ast2700a2_evb_sdk_v11_00(self): + def test_aarch64_ast2700a2_evb_sdk_v11_01(self): self.set_machine('ast2700a2-evb') self.require_netdev('user') - self.archive_extract(self.ASSET_SDK_V1100_AST2700A2) + self.archive_extract(self.ASSET_SDK_V1101_AST2700A2) self.vm.add_args('-device', 'e1000e,netdev=net1,bus=pcie.2') self.vm.add_args('-netdev', 'user,id=net1') - self.start_ast2700_test('ast2700-default', 1) + self.start_ast2700_test('ast2700-default-image', 1) self.verify_openbmc_boot_and_login('ast2700-default') self.do_ast2700_i2c_test(1) self.do_ast2700_pcie_test() - def test_aarch64_ast2700a2_evb_sdk_vbootrom_v11_00(self): + def test_aarch64_ast2700a2_evb_sdk_vbootrom_v11_01(self): self.set_machine('ast2700a2-evb') self.require_netdev('user') - self.archive_extract(self.ASSET_SDK_V1100_AST2700A2) + self.archive_extract(self.ASSET_SDK_V1101_AST2700A2) self.vm.add_args('-device', 'e1000e,netdev=net1,bus=pcie.2') self.vm.add_args('-netdev', 'user,id=net1') - self.start_ast2700_test_vbootrom('ast2700-default', 1) + self.start_ast2700_test_vbootrom('ast2700-default-image', 1) self.verify_vbootrom_firmware_flow() self.verify_openbmc_boot_start() - def test_aarch64_ast2700a2_evb_ioexp_v11_00(self): + def test_aarch64_ast2700a2_evb_ioexp_v11_01(self): self.set_machine('ast2700a2-evb') self.require_netdev('user') - self.archive_extract(self.ASSET_SDK_V1100_AST2700A2_DCSCM) + self.archive_extract(self.ASSET_SDK_V1101_AST2700A2_DCSCM) self.vm.set_machine('ast2700a2-evb,fmc-model=w25q512jv') self.vm.add_args('-device', 'tmp105,bus=ioexp0.0,address=0x4d,id=tmp-test-16') - self.start_ast2700_test('ast2700-dcscm', 8) + self.start_ast2700_test('ast2700-dcscm-image', 8) self.verify_openbmc_boot_and_login('ast2700-dcscm', False) self.do_ast2700_i2c_test(8) self.do_ast2700_i2c_test(16) -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Tested-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260303063930.2878300-11-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- .../aarch64/test_aspeed_ast2700fc.py | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/tests/functional/aarch64/test_aspeed_ast2700fc.py b/tests/functional/aarch64/test_aspeed_ast2700fc.py index XXXXXXX..XXXXXXX 100755 --- a/tests/functional/aarch64/test_aspeed_ast2700fc.py +++ b/tests/functional/aarch64/test_aspeed_ast2700fc.py @@ -XXX,XX +XXX,XX @@ def load_ast2700fc_coprocessor(self, name): self.vm.add_args('-device', f'loader,file={file},cpu-num={cpu_num}') - ASSET_SDK_V1100_AST2700 = Asset( - 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.00/ast2700-default-obmc.tar.gz', - 'e2b8f043fe8063dd3b6ded93422e38bd41914dc9c3202199507652df024de4dc') + ASSET_SDK_V1101_AST2700 = Asset( + 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.01/ast2700-default-image.tar.gz', + 'ce89dcd995cf284d41a6a4bd17a1b97d59939f0277bfe54fdaaf30e741ce7487') def do_ast2700_i2c_test(self): exec_command_and_wait_for_pattern(self, @@ -XXX,XX +XXX,XX @@ def start_ast2700fc_test_vbootrom(self, name): self.do_test_aarch64_aspeed_sdk_start( self.scratch_file(name, 'image-bmc')) - def test_aarch64_ast2700fc_sdk_v11_00(self): + def test_aarch64_ast2700fc_sdk_v11_01(self): self.set_machine('ast2700fc') self.require_netdev('user') - self.archive_extract(self.ASSET_SDK_V1100_AST2700) - self.start_ast2700fc_test('ast2700-default') + self.archive_extract(self.ASSET_SDK_V1101_AST2700) + self.start_ast2700fc_test('ast2700-default-image') self.verify_openbmc_boot_and_login('ast2700-default') self.do_ast2700_i2c_test() self.do_ast2700_pcie_test() self.do_ast2700fc_ssp_test() self.do_ast2700fc_tsp_test() - def test_aarch64_ast2700fc_sdk_vbootrom_v11_00(self): + def test_aarch64_ast2700fc_sdk_vbootrom_v11_01(self): self.set_machine('ast2700fc') - self.archive_extract(self.ASSET_SDK_V1100_AST2700) - self.start_ast2700fc_test_vbootrom('ast2700-default') + self.archive_extract(self.ASSET_SDK_V1101_AST2700) + self.start_ast2700fc_test_vbootrom('ast2700-default-image') self.verify_openbmc_boot_and_login('ast2700-default') self.do_ast2700fc_ssp_test() self.do_ast2700fc_tsp_test() -- 2.53.0