The following changes since commit c77283dd5d79149f4e7e9edd00f65416c648ee59: Merge tag 'pull-request-2025-07-02' of https://gitlab.com/thuth/qemu into staging (2025-07-03 06:01:41 -0400) are available in the Git repository at: https://github.com/legoater/qemu/ tags/pull-aspeed-20250704 for you to fetch changes up to 3a34dad2c0d25cebafed40696bbbdeb7ff4b9c7d: tests/functional: Add gb200 tests (2025-07-03 17:36:45 +0200) ---------------------------------------------------------------- aspeed queue: * Improved AST2700 SoC modeling (SDMC, SCU) * Fixed hardware strapping of 'bletchley-bmc' machine * Added new Meta 'catalina-bmc' machine and functional test using OpenBMC * Improved AST2600 SCU protection key modeling * Introduced AST2600 SCU unit tests * Deprecated 'ast2700a0-evb' machine * Added new NVIDIA 'gb200-bmc' machine and functional test using OpenBMC ---------------------------------------------------------------- Ed Tanous (4): hw/arm/aspeed: Add second SPI chip to Aspeed model docs: add support for gb200-bmc hw/arm/aspeed: Add GB200 BMC target tests/functional: Add gb200 tests Jamin Lin (3): hw/misc/aspeed_sdmc: Skipping dram_init in u-boot for AST2700 hw/misc/aspeed_scu: Support the Frequency Counter Control register for AST2700 aspeed: Deprecate the ast2700a0-evb machine Patrick Williams (2): hw/arm/aspeed: bletchley: update hw strap values hw/arm/aspeed: add Catalina machine type Tan Siewert (2): hw/misc/aspeed_scu: Handle AST2600 protection key registers correctly tests/qtest: Add test for ASPEED SCU docs/about/deprecated.rst | 8 + docs/system/arm/aspeed.rst | 4 +- hw/arm/aspeed_eeprom.h | 3 + include/hw/arm/aspeed.h | 2 + hw/arm/aspeed.c | 285 ++++++++++++++++++++++- hw/arm/aspeed_eeprom.c | 21 ++ hw/misc/aspeed_scu.c | 22 +- hw/misc/aspeed_sdmc.c | 3 + tests/qtest/aspeed_scu-test.c | 231 ++++++++++++++++++ hw/arm/Kconfig | 1 + tests/functional/aspeed.py | 9 +- tests/functional/meson.build | 4 + tests/functional/test_arm_aspeed_catalina.py | 25 ++ tests/functional/test_arm_aspeed_gb200nvl_bmc.py | 26 +++ tests/qtest/meson.build | 1 + 15 files changed, 636 insertions(+), 9 deletions(-) create mode 100644 tests/qtest/aspeed_scu-test.c create mode 100755 tests/functional/test_arm_aspeed_catalina.py create mode 100644 tests/functional/test_arm_aspeed_gb200nvl_bmc.py From: Jamin Lin <jamin_lin@aspeedtech.com> On AST2700 SoC, QEMU now sets BIT6 in VGA0 SCRATCH register to indicate that DDR training has completed, thus skipping the dram_init(). To align with the recent U-Boot changes, where the Main Control Register's BIT16 is checked to skip the dram_init() process, this patch sets BIT16 in the SDMC Main Control Register at reset time. This allows both the main U-Boot stage to correctly detect and bypass DRAM initialization when running under QEMU. Reference: - QEMU: https://github.com/qemu/qemu/commit/2d082fea485ee455a70ed3e963cdf9a70f34858a - U-Boot: https://github.com/AspeedTech-BMC/u-boot/commit/94e5435504fb0d8888f5c1bfd3fa284cdd6aaf9b Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250618080006.846355-2-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- hw/misc/aspeed_sdmc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c index XXXXXXX..XXXXXXX 100644 --- a/hw/misc/aspeed_sdmc.c +++ b/hw/misc/aspeed_sdmc.c @@ -XXX,XX +XXX,XX @@ static void aspeed_2700_sdmc_reset(DeviceState *dev) /* Set ram size bit and defaults values */ s->regs[R_MAIN_CONF] = asc->compute_conf(s, 0); + /* Skipping dram init */ + s->regs[R_MAIN_CONTROL] = BIT(16); + if (s->unlocked) { s->regs[R_2700_PROT] = PROT_UNLOCKED; } -- 2.50.0 From: Jamin Lin <jamin_lin@aspeedtech.com> According to the datasheet: BIT[1] (SCU_FREQ_OSC_EN) enables the oscillator frequency measurement counter. BIT[6] (SCU_FREQ_DONE) indicates the measurement is finished. Firmware polls BIT[6] to determine when measurement is complete. The flag can be cleared by writing BIT[1] to 0. To simulate this hardware behavior in QEMU: If BIT[1] is set to 1, BIT[6] is immediately set to 1 to avoid firmware hanging during polling. If BIT[1] is cleared to 0, BIT[6] is also cleared to 0 to match hardware semantics. The initial value of this register is initialized to 0x80, reflecting the default value confirmed from an EVB register dump. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250618080006.846355-3-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- hw/misc/aspeed_scu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index XXXXXXX..XXXXXXX 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -XXX,XX +XXX,XX @@ #define AST2700_SCUIO_UARTCLK_GEN TO_REG(0x330) #define AST2700_SCUIO_HUARTCLK_GEN TO_REG(0x334) #define AST2700_SCUIO_CLK_DUTY_MEAS_RST TO_REG(0x388) +#define AST2700_SCUIO_FREQ_CNT_CTL TO_REG(0x3A0) #define SCU_IO_REGION_SIZE 0x1000 @@ -XXX,XX +XXX,XX @@ static void aspeed_ast2700_scuio_write(void *opaque, hwaddr offset, s->regs[reg - 1] ^= data; updated = true; break; + case AST2700_SCUIO_FREQ_CNT_CTL: + s->regs[reg] = deposit32(s->regs[reg], 6, 1, !!(data & BIT(1))); + updated = true; + break; default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Unhandled write at offset 0x%" HWADDR_PRIx "\n", @@ -XXX,XX +XXX,XX @@ static const uint32_t ast2700_a0_resets_io[ASPEED_AST2700_SCU_NR_REGS] = { [AST2700_SCUIO_UARTCLK_GEN] = 0x00014506, [AST2700_SCUIO_HUARTCLK_GEN] = 0x000145c0, [AST2700_SCUIO_CLK_DUTY_MEAS_RST] = 0x0c9100d2, + [AST2700_SCUIO_FREQ_CNT_CTL] = 0x00000080, }; static void aspeed_2700_scuio_class_init(ObjectClass *klass, const void *data) -- 2.50.0 From: Patrick Williams <patrick@stwcx.xyz> Update the Bletchley hardware strap register values per actual hardware: ``` root@bmc:~# devmem 0x1e6e2500 0x00002000 root@bmc:~# devmem 0x1e6e2510 0x00000801 ``` Signed-off-by: Patrick Williams <patrick@stwcx.xyz> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250619035850.2682690-1-patrick@stwcx.xyz Signed-off-by: Cédric Le Goater <clg@redhat.com> --- hw/arm/aspeed.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -XXX,XX +XXX,XX @@ struct AspeedMachineState { #define FUJI_BMC_HW_STRAP2 0x00000000 /* Bletchley hardware value */ -/* TODO: Leave same as EVB for now. */ -#define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1 -#define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2 +#define BLETCHLEY_BMC_HW_STRAP1 0x00002000 +#define BLETCHLEY_BMC_HW_STRAP2 0x00000801 /* Qualcomm DC-SCM hardware value */ #define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000 -- 2.50.0 From: Patrick Williams <patrick@stwcx.xyz> Add the 'catalina-bmc' machine type based on the kernel DTS[1] as of 6.16-rc2. The i2c model is as complete as the current QEMU models support, but in some cases I substituted devices that are close enough for present functionality. Strap registers are were verified with hardware. This has been tested with an openbmc image built from [2]. Add a functional test in line with Bletchley, pointing at an image obtained from the OpenBMC Jenkins server. [1]: https://github.com/torvalds/linux/blob/v6.16-rc2/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-catalina.dts [2]: https://github.com/openbmc/openbmc/commit/5bc73ec261f981d5e586bda5ac78eb0cbd5f92b0 Signed-off-by: Patrick Williams <patrick@stwcx.xyz> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250619151458.2831859-1-patrick@stwcx.xyz Signed-off-by: Cédric Le Goater <clg@redhat.com> --- hw/arm/aspeed.c | 200 +++++++++++++++++++ hw/arm/Kconfig | 1 + tests/functional/meson.build | 2 + tests/functional/test_arm_aspeed_catalina.py | 25 +++ 4 files changed, 228 insertions(+) create mode 100755 tests/functional/test_arm_aspeed_catalina.py diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -XXX,XX +XXX,XX @@ #include "hw/i2c/i2c_mux_pca954x.h" #include "hw/i2c/smbus_eeprom.h" #include "hw/gpio/pca9552.h" +#include "hw/gpio/pca9554.h" #include "hw/nvram/eeprom_at24c.h" #include "hw/sensor/tmp105.h" #include "hw/misc/led.h" @@ -XXX,XX +XXX,XX @@ static void fuji_bmc_i2c_init(AspeedMachineState *bmc) } #define TYPE_TMP421 "tmp421" +#define TYPE_DS1338 "ds1338" + +/* Catalina hardware value */ +#define CATALINA_BMC_HW_STRAP1 0x00002002 +#define CATALINA_BMC_HW_STRAP2 0x00000800 + +#define CATALINA_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) + +static void catalina_bmc_i2c_init(AspeedMachineState *bmc) +{ + /* Reference from v6.16-rc2 aspeed-bmc-facebook-catalina.dts */ + + AspeedSoCState *soc = bmc->soc; + I2CBus *i2c[16] = {}; + I2CSlave *i2c_mux; + + /* busses 0-15 are all used. */ + for (int i = 0; i < ARRAY_SIZE(i2c); i++) { + i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); + } + + /* &i2c0 */ + /* i2c-mux@71 (PCA9546) on i2c0 */ + i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x71); + + /* i2c-mux@72 (PCA9546) on i2c0 */ + i2c_mux = i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x72); + + /* i2c0mux1ch1 */ + /* io_expander7 - pca9535@20 */ + i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 1), + TYPE_PCA9552, 0x20); + /* eeprom@50 */ + at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x50, 8 * KiB); + + /* i2c-mux@73 (PCA9546) on i2c0 */ + i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x73); + + /* i2c-mux@75 (PCA9546) on i2c0 */ + i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x75); + + /* i2c-mux@76 (PCA9546) on i2c0 */ + i2c_mux = i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x76); + + /* i2c0mux4ch1 */ + /* io_expander8 - pca9535@21 */ + i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 1), + TYPE_PCA9552, 0x21); + /* eeprom@50 */ + at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x50, 8 * KiB); + + /* i2c-mux@77 (PCA9546) on i2c0 */ + i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x77); + + + /* &i2c1 */ + /* i2c-mux@70 (PCA9548) on i2c1 */ + i2c_mux = i2c_slave_create_simple(i2c[1], TYPE_PCA9548, 0x70); + /* i2c1mux0ch0 */ + /* ina238@41 - no model */ + /* ina238@42 - no model */ + /* ina238@44 - no model */ + /* i2c1mux0ch1 */ + /* ina238@41 - no model */ + /* ina238@43 - no model */ + /* i2c1mux0ch4 */ + /* ltc4287@42 - no model */ + /* ltc4287@43 - no model */ + + /* i2c1mux0ch5 */ + /* eeprom@54 */ + at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 5), 0x54, 8 * KiB); + /* tpm75@4f */ + i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 5), TYPE_TMP75, 0x4f); + + /* i2c1mux0ch6 */ + /* io_expander5 - pca9554@27 */ + i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 6), + TYPE_PCA9554, 0x27); + /* io_expander6 - pca9555@25 */ + i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 6), + TYPE_PCA9552, 0x25); + /* eeprom@51 */ + at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 6), 0x51, 8 * KiB); + + /* i2c1mux0ch7 */ + /* eeprom@53 */ + at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 7), 0x53, 8 * KiB); + /* temperature-sensor@4b - tmp75 */ + i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 7), TYPE_TMP75, 0x4b); + + /* &i2c2 */ + /* io_expander0 - pca9555@20 */ + i2c_slave_create_simple(i2c[2], TYPE_PCA9552, 0x20); + /* io_expander0 - pca9555@21 */ + i2c_slave_create_simple(i2c[2], TYPE_PCA9552, 0x21); + /* io_expander0 - pca9555@27 */ + i2c_slave_create_simple(i2c[2], TYPE_PCA9552, 0x27); + /* eeprom@50 */ + at24c_eeprom_init(i2c[2], 0x50, 8 * KiB); + /* eeprom@51 */ + at24c_eeprom_init(i2c[2], 0x51, 8 * KiB); + + /* &i2c5 */ + /* i2c-mux@70 (PCA9548) on i2c5 */ + i2c_mux = i2c_slave_create_simple(i2c[5], TYPE_PCA9548, 0x70); + /* i2c5mux0ch6 */ + /* eeprom@52 */ + at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 6), 0x52, 8 * KiB); + /* i2c5mux0ch7 */ + /* ina230@40 - no model */ + /* ina230@41 - no model */ + /* ina230@44 - no model */ + /* ina230@45 - no model */ + + /* &i2c6 */ + /* io_expander3 - pca9555@21 */ + i2c_slave_create_simple(i2c[6], TYPE_PCA9552, 0x21); + /* rtc@6f - nct3018y */ + i2c_slave_create_simple(i2c[6], TYPE_DS1338, 0x6f); + + /* &i2c9 */ + /* io_expander4 - pca9555@4f */ + i2c_slave_create_simple(i2c[9], TYPE_PCA9552, 0x4f); + /* temperature-sensor@4b - tpm75 */ + i2c_slave_create_simple(i2c[9], TYPE_TMP75, 0x4b); + /* eeprom@50 */ + at24c_eeprom_init(i2c[9], 0x50, 8 * KiB); + /* eeprom@56 */ + at24c_eeprom_init(i2c[9], 0x56, 8 * KiB); + + /* &i2c10 */ + /* temperature-sensor@1f - tpm421 */ + i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x1f); + /* eeprom@50 */ + at24c_eeprom_init(i2c[10], 0x50, 8 * KiB); + + /* &i2c11 */ + /* ssif-bmc@10 - no model */ + + /* &i2c12 */ + /* eeprom@50 */ + at24c_eeprom_init(i2c[12], 0x50, 8 * KiB); + + /* &i2c13 */ + /* eeprom@50 */ + at24c_eeprom_init(i2c[13], 0x50, 8 * KiB); + /* eeprom@54 */ + at24c_eeprom_init(i2c[13], 0x54, 256); + /* eeprom@55 */ + at24c_eeprom_init(i2c[13], 0x55, 256); + /* eeprom@57 */ + at24c_eeprom_init(i2c[13], 0x57, 256); + + /* &i2c14 */ + /* io_expander9 - pca9555@10 */ + i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x10); + /* io_expander10 - pca9555@11 */ + i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x11); + /* io_expander11 - pca9555@12 */ + i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x12); + /* io_expander12 - pca9555@13 */ + i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x13); + /* io_expander13 - pca9555@14 */ + i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x14); + /* io_expander14 - pca9555@15 */ + i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x15); + + /* &i2c15 */ + /* temperature-sensor@1f - tmp421 */ + i2c_slave_create_simple(i2c[15], TYPE_TMP421, 0x1f); + /* eeprom@52 */ + at24c_eeprom_init(i2c[15], 0x52, 8 * KiB); +} static void bletchley_bmc_i2c_init(AspeedMachineState *bmc) { @@ -XXX,XX +XXX,XX @@ static void aspeed_machine_bletchley_class_init(ObjectClass *oc, aspeed_machine_class_init_cpus_defaults(mc); } +static void aspeed_machine_catalina_class_init(ObjectClass *oc, + const void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); + + mc->desc = "Facebook Catalina BMC (Cortex-A7)"; + amc->soc_name = "ast2600-a3"; + amc->hw_strap1 = CATALINA_BMC_HW_STRAP1; + amc->hw_strap2 = CATALINA_BMC_HW_STRAP2; + amc->fmc_model = "w25q01jvq"; + amc->spi_model = NULL; + amc->num_cs = 2; + amc->macs_mask = ASPEED_MAC2_ON; + amc->i2c_init = catalina_bmc_i2c_init; + mc->auto_create_sdcard = true; + mc->default_ram_size = CATALINA_BMC_RAM_SIZE; + aspeed_machine_class_init_cpus_defaults(mc); + aspeed_machine_ast2600_class_emmc_init(oc); +} + static void fby35_reset(MachineState *state, ResetType type) { AspeedMachineState *bmc = ASPEED_MACHINE(state); @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_machine_types[] = { .name = MACHINE_TYPE_NAME("bletchley-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_bletchley_class_init, + }, { + .name = MACHINE_TYPE_NAME("catalina-bmc"), + .parent = TYPE_ASPEED_MACHINE, + .class_init = aspeed_machine_catalina_class_init, }, { .name = MACHINE_TYPE_NAME("fby35-bmc"), .parent = MACHINE_TYPE_NAME("ast2600-evb"), diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -XXX,XX +XXX,XX @@ config ASPEED_SOC select I2C select DPS310 select PCA9552 + select PCA9554 select SERIAL_MM select SMBUS_EEPROM select PCA954X diff --git a/tests/functional/meson.build b/tests/functional/meson.build index XXXXXXX..XXXXXXX 100644 --- a/tests/functional/meson.build +++ b/tests/functional/meson.build @@ -XXX,XX +XXX,XX @@ test_timeouts = { 'arm_aspeed_ast2500' : 720, 'arm_aspeed_ast2600' : 1200, 'arm_aspeed_bletchley' : 480, + 'arm_aspeed_catalina' : 480, 'arm_aspeed_rainier' : 480, 'arm_bpim2u' : 500, 'arm_collie' : 180, @@ -XXX,XX +XXX,XX @@ tests_arm_system_thorough = [ 'arm_aspeed_ast2500', 'arm_aspeed_ast2600', 'arm_aspeed_bletchley', + 'arm_aspeed_catalina', 'arm_aspeed_rainier', 'arm_bpim2u', 'arm_canona1100', diff --git a/tests/functional/test_arm_aspeed_catalina.py b/tests/functional/test_arm_aspeed_catalina.py new file mode 100755 index XXXXXXX..XXXXXXX --- /dev/null +++ b/tests/functional/test_arm_aspeed_catalina.py @@ -XXX,XX +XXX,XX @@ +#!/usr/bin/env python3 +# +# Functional test that boots the ASPEED machines +# +# SPDX-License-Identifier: GPL-2.0-or-later + +from qemu_test import Asset +from aspeed import AspeedTest + + +class CatalinaMachine(AspeedTest): + + ASSET_CATALINA_FLASH = Asset( + 'https://github.com/legoater/qemu-aspeed-boot/raw/a866feb5ef81245b4827a214584bf6bcc72939f6/images/catalina-bmc/obmc-phosphor-image-catalina-20250619123021.static.mtd.xz', + '287402e1ba021991e06be1d098f509444a02a3d81a73a932f66528b159e864f9') + + def test_arm_ast2600_catalina_openbmc(self): + image_path = self.uncompress(self.ASSET_CATALINA_FLASH) + + self.do_test_arm_aspeed_openbmc('catalina-bmc', image=image_path, + uboot='2019.04', cpu_id='0xf00', + soc='AST2600 rev A3') + +if __name__ == '__main__': + AspeedTest.main() -- 2.50.0 From: Tan Siewert <tan@siewert.io> The AST2600 SCU has two protection key registers (0x00 and 0x10) that both need to be unlocked. (Un-)locking 0x00 modifies both protection key registers, while modifying 0x10 only modifies itself. This commit updates the SCU write logic to reject writes unless both protection key registers are unlocked, matching the behaviour of real hardware. Signed-off-by: Tan Siewert <tan@siewert.io> Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Link: https://lore.kernel.org/qemu-devel/20250619085329.42125-1-tan@siewert.io Signed-off-by: Cédric Le Goater <clg@redhat.com> --- hw/misc/aspeed_scu.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index XXXXXXX..XXXXXXX 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -XXX,XX +XXX,XX @@ #define BMC_DEV_ID TO_REG(0x1A4) #define AST2600_PROT_KEY TO_REG(0x00) +#define AST2600_PROT_KEY2 TO_REG(0x10) #define AST2600_SILICON_REV TO_REG(0x04) #define AST2600_SILICON_REV2 TO_REG(0x14) #define AST2600_SYS_RST_CTRL TO_REG(0x40) @@ -XXX,XX +XXX,XX @@ static void aspeed_ast2600_scu_write(void *opaque, hwaddr offset, int reg = TO_REG(offset); /* Truncate here so bitwise operations below behave as expected */ uint32_t data = data64; + bool prot_data_state = data == ASPEED_SCU_PROT_KEY; + bool unlocked = s->regs[AST2600_PROT_KEY] && s->regs[AST2600_PROT_KEY2]; if (reg >= ASPEED_AST2600_SCU_NR_REGS) { qemu_log_mask(LOG_GUEST_ERROR, @@ -XXX,XX +XXX,XX @@ static void aspeed_ast2600_scu_write(void *opaque, hwaddr offset, return; } - if (reg > PROT_KEY && !s->regs[PROT_KEY]) { + if ((reg != AST2600_PROT_KEY && reg != AST2600_PROT_KEY2) && !unlocked) { qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__); + return; } trace_aspeed_scu_write(offset, size, data); switch (reg) { case AST2600_PROT_KEY: - s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0; + /* + * Writing a value to SCU000 will modify both protection + * registers to each protection register individually. + */ + s->regs[AST2600_PROT_KEY] = prot_data_state; + s->regs[AST2600_PROT_KEY2] = prot_data_state; + return; + case AST2600_PROT_KEY2: + s->regs[AST2600_PROT_KEY2] = prot_data_state; return; case AST2600_HW_STRAP1: case AST2600_HW_STRAP2: -- 2.50.0 From: Tan Siewert <tan@siewert.io> This adds basic tests for the ASPEED System Control Unit (SCU) and its protection mechanism on the AST2500 and AST2600 platforms. The tests verify: - That SCU protection registers can be unlocked and locked again - That modifying the primary protection register on AST2600 also affects the secondary one - That writes to protected SCU registers are blocked unless protection registers are unlocked explicitly These tests ensure proper emulation of hardware locking behaviour and help catch regressions in SCU access logic. Signed-off-by: Tan Siewert <tan@siewert.io> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250630112646.74944-1-tan@siewert.io [ clg: Reordered file list in meson.build ] Signed-off-by: Cédric Le Goater <clg@redhat.com> --- tests/qtest/aspeed_scu-test.c | 231 ++++++++++++++++++++++++++++++++++ tests/qtest/meson.build | 1 + 2 files changed, 232 insertions(+) create mode 100644 tests/qtest/aspeed_scu-test.c diff --git a/tests/qtest/aspeed_scu-test.c b/tests/qtest/aspeed_scu-test.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/tests/qtest/aspeed_scu-test.c @@ -XXX,XX +XXX,XX @@ +/* + * QTest testcase for the ASPEED AST2500 and AST2600 SCU. + * + * SPDX-License-Identifier: GPL-2.0-or-later + * Copyright (C) 2025 Tan Siewert + */ + +#include "qemu/osdep.h" +#include "libqtest-single.h" + +/* + * SCU base, as well as protection key are + * the same on AST2500 and 2600. + */ +#define AST_SCU_BASE 0x1E6E2000 +#define AST_SCU_PROT_LOCK_STATE 0x0 +#define AST_SCU_PROT_LOCK_VALUE 0x2 +#define AST_SCU_PROT_UNLOCK_STATE 0x1 +#define AST_SCU_PROT_UNLOCK_VALUE 0x1688A8A8 + +#define AST2500_MACHINE "-machine ast2500-evb" +#define AST2500_SCU_PROT_REG 0x00 +#define AST2500_SCU_MISC_2_CONTROL_REG 0x4C + +#define AST2600_MACHINE "-machine ast2600-evb" +/* AST2600 has two protection registers */ +#define AST2600_SCU_PROT_REG 0x000 +#define AST2600_SCU_PROT_REG2 0x010 +#define AST2600_SCU_MISC_2_CONTROL_REG 0x0C4 + +#define TEST_LOCK_ARBITRARY_VALUE 0xABCDEFAB + +/** + * Assert that a given register matches an expected value. + * + * Reads the register and checks if its value equals the expected value. + * + * @param *s - QTest machine state + * @param reg - Address of the register to be checked + * @param expected - Expected register value + */ +static inline void assert_register_eq(QTestState *s, + uint32_t reg, + uint32_t expected) +{ + uint32_t value = qtest_readl(s, reg); + g_assert_cmphex(value, ==, expected); +} + +/** + * Assert that a given register does not match a specific value. + * + * Reads the register and checks that its value is not equal to the + * provided value. + * + * @param *s - QTest machine state + * @param reg - Address of the register to be checked + * @param not_expected - Value the register must not contain + */ +static inline void assert_register_neq(QTestState *s, + uint32_t reg, + uint32_t not_expected) +{ + uint32_t value = qtest_readl(s, reg); + g_assert_cmphex(value, !=, not_expected); +} + +/** + * Test whether the SCU can be locked and unlocked correctly. + * + * When testing multiple registers, this function assumes that writing + * to the first register also affects the others. However, writing to + * any other register only affects itself. + * + * @param *machine - input machine configuration, passed directly + * to QTest + * @param regs[] - List of registers to be checked + * @param regc - amount of arguments for registers to be checked + */ +static void test_protection_register(const char *machine, + const uint32_t regs[], + const int regc) +{ + QTestState *s = qtest_init(machine); + + for (int i = 0; i < regc; i++) { + uint32_t reg = regs[i]; + + qtest_writel(s, reg, AST_SCU_PROT_UNLOCK_VALUE); + assert_register_eq(s, reg, AST_SCU_PROT_UNLOCK_STATE); + + /** + * Check that other registers are unlocked too, if more + * than one is available. + */ + if (regc > 1 && i == 0) { + /* Initialise at 1 instead of 0 to skip first */ + for (int j = 1; j < regc; j++) { + uint32_t add_reg = regs[j]; + assert_register_eq(s, add_reg, AST_SCU_PROT_UNLOCK_STATE); + } + } + + /* Lock the register again */ + qtest_writel(s, reg, AST_SCU_PROT_LOCK_VALUE); + assert_register_eq(s, reg, AST_SCU_PROT_LOCK_STATE); + + /* And the same for locked state */ + if (regc > 1 && i == 0) { + /* Initialise at 1 instead of 0 to skip first */ + for (int j = 1; j < regc; j++) { + uint32_t add_reg = regs[j]; + assert_register_eq(s, add_reg, AST_SCU_PROT_LOCK_STATE); + } + } + } + + qtest_quit(s); +} + +static void test_2500_protection_register(void) +{ + uint32_t regs[] = { AST_SCU_BASE + AST2500_SCU_PROT_REG }; + + test_protection_register(AST2500_MACHINE, + regs, + ARRAY_SIZE(regs)); +} + +static void test_2600_protection_register(void) +{ + /** + * The AST2600 has two protection registers, both + * being required to be unlocked to do any operation. + * + * Modifying SCU000 also modifies SCU010, but modifying + * SCU010 only will keep SCU000 untouched. + */ + uint32_t regs[] = { AST_SCU_BASE + AST2600_SCU_PROT_REG, + AST_SCU_BASE + AST2600_SCU_PROT_REG2 }; + + test_protection_register(AST2600_MACHINE, + regs, + ARRAY_SIZE(regs)); +} + +/** + * Test if SCU register writes are correctly allowed or blocked + * depending on the protection register state. + * + * The test first locks the protection register and verifies that + * writes to the target SCU register are rejected. It then unlocks + * the protection register and confirms that the written value is + * retained when unlocked. + * + * @param *machine - input machine configuration, passed directly + * to QTest + * @param protection_register - first SCU protection key register + * (only one for keeping it simple) + * @param test_register - Register to be used for writing arbitrary + * values + */ +static void test_write_permission_lock_state(const char *machine, + const uint32_t protection_register, + const uint32_t test_register) +{ + QTestState *s = qtest_init(machine); + + /* Arbitrary value to lock provided SCU protection register */ + qtest_writel(s, protection_register, AST_SCU_PROT_LOCK_VALUE); + + /* Ensure that the SCU is really locked */ + assert_register_eq(s, protection_register, AST_SCU_PROT_LOCK_STATE); + + /* Write a known arbitrary value to test that the write is blocked */ + qtest_writel(s, test_register, TEST_LOCK_ARBITRARY_VALUE); + + /* We do not want to have the written value to be saved */ + assert_register_neq(s, test_register, TEST_LOCK_ARBITRARY_VALUE); + + /** + * Unlock the SCU and verify that it can be written to. + * Assumes that the first SCU protection register is sufficient to + * unlock all protection registers, if multiple are present. + */ + qtest_writel(s, protection_register, AST_SCU_PROT_UNLOCK_VALUE); + assert_register_eq(s, protection_register, AST_SCU_PROT_UNLOCK_STATE); + + /* Write a known arbitrary value to test that the write works */ + qtest_writel(s, test_register, TEST_LOCK_ARBITRARY_VALUE); + + /* Ensure that the written value is retained */ + assert_register_eq(s, test_register, TEST_LOCK_ARBITRARY_VALUE); + + qtest_quit(s); +} + +static void test_2500_write_permission_lock_state(void) +{ + test_write_permission_lock_state( + AST2500_MACHINE, + AST_SCU_BASE + AST2500_SCU_PROT_REG, + AST_SCU_BASE + AST2500_SCU_MISC_2_CONTROL_REG + ); +} + +static void test_2600_write_permission_lock_state(void) +{ + test_write_permission_lock_state( + AST2600_MACHINE, + AST_SCU_BASE + AST2600_SCU_PROT_REG, + AST_SCU_BASE + AST2600_SCU_MISC_2_CONTROL_REG + ); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + qtest_add_func("/ast2500/scu/protection_register", + test_2500_protection_register); + qtest_add_func("/ast2600/scu/protection_register", + test_2600_protection_register); + + qtest_add_func("/ast2500/scu/write_permission_lock_state", + test_2500_write_permission_lock_state); + qtest_add_func("/ast2600/scu/write_permission_lock_state", + test_2600_write_permission_lock_state); + + return g_test_run(); +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index XXXXXXX..XXXXXXX 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -XXX,XX +XXX,XX @@ qtests_npcm8xx = \ qtests_aspeed = \ ['aspeed_gpio-test', 'aspeed_hace-test', + 'aspeed_scu-test', 'aspeed_smc-test'] qtests_aspeed64 = \ ['ast2700-gpio-test', -- 2.50.0 From: Jamin Lin <jamin_lin@aspeedtech.com> The ast2700a0-evb machine represents the first revision of the AST2700 and serves as the initial engineering sample rather than a production version. A newer revision, A1, is now supported, and the ast2700a1-evb should replace the older A0 version. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250703052400.2927831-1-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- docs/about/deprecated.rst | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index XXXXXXX..XXXXXXX 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -XXX,XX +XXX,XX @@ deprecated; use the new name ``dtb-randomness`` instead. The new name better reflects the way this property affects all random data within the device tree blob, not just the ``kaslr-seed`` node. +Arm ``ast2700a0-evb`` machine (since 10.1) +'''''''''''''''''''''''''''''''''''''''''' + +The ``ast2700a0-evb`` machine represents the first revision of the AST2700 +and serves as the initial engineering sample rather than a production version. +A newer revision, A1, is now supported, and the ``ast2700a1-evb`` should +replace the older A0 version. + Mips ``mipssim`` machine (since 10.0) ''''''''''''''''''''''''''''''''''''' -- 2.50.0 From: Ed Tanous <etanous@nvidia.com> Aspeed2600 has two spi lanes; Add a new struct that can mount the second SPI. Signed-off-by: Ed Tanous <etanous@nvidia.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250703144249.3348879-2-etanous@nvidia.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- include/hw/arm/aspeed.h | 2 ++ hw/arm/aspeed.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/aspeed.h +++ b/include/hw/arm/aspeed.h @@ -XXX,XX +XXX,XX @@ struct AspeedMachineClass { uint32_t hw_strap2; const char *fmc_model; const char *spi_model; + const char *spi2_model; uint32_t num_cs; + uint32_t num_cs2; uint32_t macs_mask; void (*i2c_init)(AspeedMachineState *bmc); uint32_t uart_default; diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine) aspeed_board_init_flashes(&bmc->soc->spi[0], bmc->spi_model ? bmc->spi_model : amc->spi_model, 1, amc->num_cs); + aspeed_board_init_flashes(&bmc->soc->spi[1], + amc->spi2_model, 1, amc->num_cs2); } if (machine->kernel_filename && sc->num_cpus > 1) { -- 2.50.0 From: Ed Tanous <etanous@nvidia.com> This patch updates the docs for support of gb200-bmc. Signed-off-by: Ed Tanous <etanous@nvidia.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250703144249.3348879-3-etanous@nvidia.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- docs/system/arm/aspeed.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index XXXXXXX..XXXXXXX 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -XXX,XX +XXX,XX @@ -Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``supermicrox11-bmc``, ``supermicrox11spi-bmc``, ``tiogapass-bmc``, ``witherspoon-bmc``, ``yosemitev2-bmc``) -================================================================================================================================================================================================================================================================================================================================================================================================================================= +Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``gb200nvl-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``supermicrox11-bmc``, ``supermicrox11spi-bmc``, ``tiogapass-bmc``, ``witherspoon-bmc``, ``yosemitev2-bmc``) The QEMU Aspeed machines model BMCs of various OpenPOWER systems and Aspeed evaluation boards. They are based on different releases of the @@ -XXX,XX +XXX,XX @@ AST2600 SoC based machines : - ``fuji-bmc`` Facebook Fuji BMC - ``bletchley-bmc`` Facebook Bletchley BMC - ``fby35-bmc`` Facebook fby35 BMC +- ``gb200nvl-bmc`` Nvidia GB200nvl BMC - ``qcom-dc-scm-v1-bmc`` Qualcomm DC-SCM V1 BMC - ``qcom-firework-bmc`` Qualcomm Firework BMC -- 2.50.0 From: Ed Tanous <etanous@nvidia.com> GB200nvl72 is a system for for accelerated compute. This is a model for the BMC target within the system. This is based on the device tree aspeed-bmc-nvidia-gb200nvl-bmc.dts from: [1] https://github.com/openbmc/linux/blob/dev-6.6/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts Signed-off-by: Ed Tanous <etanous@nvidia.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250703144249.3348879-4-etanous@nvidia.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- hw/arm/aspeed_eeprom.h | 3 ++ hw/arm/aspeed.c | 78 ++++++++++++++++++++++++++++++++++++++++++ hw/arm/aspeed_eeprom.c | 21 ++++++++++++ 3 files changed, 102 insertions(+) diff --git a/hw/arm/aspeed_eeprom.h b/hw/arm/aspeed_eeprom.h index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/aspeed_eeprom.h +++ b/hw/arm/aspeed_eeprom.h @@ -XXX,XX +XXX,XX @@ extern const size_t rainier_bb_fruid_len; extern const uint8_t rainier_bmc_fruid[]; extern const size_t rainier_bmc_fruid_len; +extern const uint8_t gb200nvl_bmc_fruid[]; +extern const size_t gb200nvl_bmc_fruid_len; + #endif diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -XXX,XX +XXX,XX @@ struct AspeedMachineState { #define BLETCHLEY_BMC_HW_STRAP1 0x00002000 #define BLETCHLEY_BMC_HW_STRAP2 0x00000801 +/* GB200NVL hardware value */ +#define GB200NVL_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1 +#define GB200NVL_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2 + /* Qualcomm DC-SCM hardware value */ #define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000 #define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041 @@ -XXX,XX +XXX,XX @@ static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr) TYPE_PCA9552, addr); } +static I2CSlave *create_pca9554(AspeedSoCState *soc, int bus_id, int addr) +{ + return i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id), + TYPE_PCA9554, addr); +} + static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) { AspeedSoCState *soc = bmc->soc; @@ -XXX,XX +XXX,XX @@ static void bletchley_bmc_i2c_init(AspeedMachineState *bmc) i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67); } + +static void gb200nvl_bmc_i2c_init(AspeedMachineState *bmc) +{ + AspeedSoCState *soc = bmc->soc; + I2CBus *i2c[15] = {}; + DeviceState *dev; + for (int i = 0; i < sizeof(i2c) / sizeof(i2c[0]); i++) { + if ((i == 11) || (i == 12) || (i == 13)) { + continue; + } + i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); + } + + /* Bus 5 Expander */ + create_pca9554(soc, 4, 0x21); + + /* Mux I2c Expanders */ + i2c_slave_create_simple(i2c[5], "pca9546", 0x71); + i2c_slave_create_simple(i2c[5], "pca9546", 0x72); + i2c_slave_create_simple(i2c[5], "pca9546", 0x73); + i2c_slave_create_simple(i2c[5], "pca9546", 0x75); + i2c_slave_create_simple(i2c[5], "pca9546", 0x76); + i2c_slave_create_simple(i2c[5], "pca9546", 0x77); + + /* Bus 10 */ + dev = DEVICE(create_pca9554(soc, 9, 0x20)); + + /* Set FPGA_READY */ + object_property_set_str(OBJECT(dev), "pin1", "high", &error_fatal); + + create_pca9554(soc, 9, 0x21); + at24c_eeprom_init(i2c[9], 0x50, 64 * KiB); + at24c_eeprom_init(i2c[9], 0x51, 64 * KiB); + + /* Bus 11 */ + at24c_eeprom_init_rom(i2c[10], 0x50, 256, gb200nvl_bmc_fruid, + gb200nvl_bmc_fruid_len); +} + static void fby35_i2c_init(AspeedMachineState *bmc) { AspeedSoCState *soc = bmc->soc; @@ -XXX,XX +XXX,XX @@ static void aspeed_machine_catalina_class_init(ObjectClass *oc, aspeed_machine_ast2600_class_emmc_init(oc); } +#define GB200NVL_BMC_RAM_SIZE ASPEED_RAM_SIZE(1 * GiB) + +static void aspeed_machine_gb200nvl_class_init(ObjectClass *oc, + const void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); + + mc->desc = "Nvidia GB200NVL BMC (Cortex-A7)"; + amc->soc_name = "ast2600-a3"; + amc->hw_strap1 = GB200NVL_BMC_HW_STRAP1; + amc->hw_strap2 = GB200NVL_BMC_HW_STRAP2; + amc->fmc_model = "mx66u51235f"; + amc->spi_model = "mx66u51235f"; + amc->num_cs = 2; + + amc->spi2_model = "mx66u51235f"; + amc->num_cs2 = 1; + amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; + amc->i2c_init = gb200nvl_bmc_i2c_init; + mc->default_ram_size = GB200NVL_BMC_RAM_SIZE; + aspeed_machine_class_init_cpus_defaults(mc); + aspeed_machine_ast2600_class_emmc_init(oc); +} + static void fby35_reset(MachineState *state, ResetType type) { AspeedMachineState *bmc = ASPEED_MACHINE(state); @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_machine_types[] = { .name = MACHINE_TYPE_NAME("bletchley-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_bletchley_class_init, + }, { + .name = MACHINE_TYPE_NAME("gb200nvl-bmc"), + .parent = TYPE_ASPEED_MACHINE, + .class_init = aspeed_machine_gb200nvl_class_init, }, { .name = MACHINE_TYPE_NAME("catalina-bmc"), .parent = TYPE_ASPEED_MACHINE, diff --git a/hw/arm/aspeed_eeprom.c b/hw/arm/aspeed_eeprom.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/aspeed_eeprom.c +++ b/hw/arm/aspeed_eeprom.c @@ -XXX,XX +XXX,XX @@ const uint8_t rainier_bmc_fruid[] = { 0x31, 0x50, 0x46, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, }; +const uint8_t gb200nvl_bmc_fruid[] = { + 0x01, 0x00, 0x00, 0x01, 0x0b, 0x00, 0x00, 0xf3, 0x01, 0x0a, 0x19, 0x1f, + 0x0f, 0xe6, 0xc6, 0x4e, 0x56, 0x49, 0x44, 0x49, 0x41, 0xc5, 0x50, 0x33, + 0x38, 0x30, 0x39, 0xcd, 0x31, 0x35, 0x38, 0x33, 0x33, 0x32, 0x34, 0x38, + 0x30, 0x30, 0x31, 0x35, 0x30, 0xd2, 0x36, 0x39, 0x39, 0x2d, 0x31, 0x33, + 0x38, 0x30, 0x39, 0x2d, 0x30, 0x34, 0x30, 0x34, 0x2d, 0x36, 0x30, 0x30, + 0xc0, 0x01, 0x01, 0xd6, 0x4d, 0x41, 0x43, 0x3a, 0x20, 0x33, 0x43, 0x3a, + 0x36, 0x44, 0x3a, 0x36, 0x36, 0x3a, 0x31, 0x34, 0x3a, 0x43, 0x38, 0x3a, + 0x37, 0x41, 0xc1, 0x3b, 0x01, 0x09, 0x19, 0xc6, 0x4e, 0x56, 0x49, 0x44, + 0x49, 0x41, 0xc9, 0x50, 0x33, 0x38, 0x30, 0x39, 0x2d, 0x42, 0x4d, 0x43, + 0xd2, 0x36, 0x39, 0x39, 0x2d, 0x31, 0x33, 0x38, 0x30, 0x39, 0x2d, 0x30, + 0x34, 0x30, 0x34, 0x2d, 0x36, 0x30, 0x30, 0xc4, 0x41, 0x45, 0x2e, 0x31, + 0xcd, 0x31, 0x35, 0x38, 0x33, 0x33, 0x32, 0x34, 0x38, 0x30, 0x30, 0x31, + 0x35, 0x30, 0xc0, 0xc4, 0x76, 0x30, 0x2e, 0x31, 0xc1, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xb4, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + +}; + const size_t tiogapass_bmc_fruid_len = sizeof(tiogapass_bmc_fruid); const size_t fby35_nic_fruid_len = sizeof(fby35_nic_fruid); const size_t fby35_bb_fruid_len = sizeof(fby35_bb_fruid); @@ -XXX,XX +XXX,XX @@ const size_t fby35_bmc_fruid_len = sizeof(fby35_bmc_fruid); const size_t yosemitev2_bmc_fruid_len = sizeof(yosemitev2_bmc_fruid); const size_t rainier_bb_fruid_len = sizeof(rainier_bb_fruid); const size_t rainier_bmc_fruid_len = sizeof(rainier_bmc_fruid); +const size_t gb200nvl_bmc_fruid_len = sizeof(gb200nvl_bmc_fruid); + -- 2.50.0 From: Ed Tanous <etanous@nvidia.com> To support the newly added gb200 machine, add appropriate tests and extend do_test_arm_aspeed_openbmc() to support the hostname of this new system: "gb200nvl-obmc". Signed-off-by: Ed Tanous <etanous@nvidia.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250703144249.3348879-5-etanous@nvidia.com [ clg: Adjust commit log to document do_test_arm_aspeed_openbmc() change ] Signed-off-by: Cédric Le Goater <clg@redhat.com> --- tests/functional/aspeed.py | 9 +++++-- tests/functional/meson.build | 2 ++ .../test_arm_aspeed_gb200nvl_bmc.py | 26 +++++++++++++++++++ 3 files changed, 35 insertions(+), 2 deletions(-) create mode 100644 tests/functional/test_arm_aspeed_gb200nvl_bmc.py diff --git a/tests/functional/aspeed.py b/tests/functional/aspeed.py index XXXXXXX..XXXXXXX 100644 --- a/tests/functional/aspeed.py +++ b/tests/functional/aspeed.py @@ -XXX,XX +XXX,XX @@ class AspeedTest(LinuxKernelTest): def do_test_arm_aspeed_openbmc(self, machine, image, uboot='2019.04', - cpu_id='0x0', soc='AST2500 rev A1'): - hostname = machine.removesuffix('-bmc') + cpu_id='0x0', soc='AST2500 rev A1', + image_hostname=None): + # Allow for the image hostname to not end in "-bmc" + if image_hostname is not None: + hostname = image_hostname + else: + hostname = machine.removesuffix('-bmc') self.set_machine(machine) self.vm.set_console() diff --git a/tests/functional/meson.build b/tests/functional/meson.build index XXXXXXX..XXXXXXX 100644 --- a/tests/functional/meson.build +++ b/tests/functional/meson.build @@ -XXX,XX +XXX,XX @@ test_timeouts = { 'arm_aspeed_ast2600' : 1200, 'arm_aspeed_bletchley' : 480, 'arm_aspeed_catalina' : 480, + 'arm_aspeed_gb200nvl_bmc' : 480, 'arm_aspeed_rainier' : 480, 'arm_bpim2u' : 500, 'arm_collie' : 180, @@ -XXX,XX +XXX,XX @@ tests_arm_system_thorough = [ 'arm_aspeed_ast2600', 'arm_aspeed_bletchley', 'arm_aspeed_catalina', + 'arm_aspeed_gb200nvl_bmc', 'arm_aspeed_rainier', 'arm_bpim2u', 'arm_canona1100', diff --git a/tests/functional/test_arm_aspeed_gb200nvl_bmc.py b/tests/functional/test_arm_aspeed_gb200nvl_bmc.py new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/tests/functional/test_arm_aspeed_gb200nvl_bmc.py @@ -XXX,XX +XXX,XX @@ +#!/usr/bin/env python3 +# +# Functional test that boots the ASPEED machines +# +# SPDX-License-Identifier: GPL-2.0-or-later + +from qemu_test import Asset +from aspeed import AspeedTest + + +class GB200Machine(AspeedTest): + + ASSET_GB200_FLASH = Asset( + 'https://github.com/legoater/qemu-aspeed-boot/raw/refs/heads/master/images/gb200nvl-obmc/obmc-phosphor-image-gb200nvl-obmc-20250702182348.static.mtd.xz', + 'b84819317cb3dc762895ad507705978ef000bfc77c50c33a63bdd37921db0dbc') + + def test_arm_aspeed_gb200_openbmc(self): + image_path = self.uncompress(self.ASSET_GB200_FLASH) + + self.do_test_arm_aspeed_openbmc('gb200nvl-bmc', image=image_path, + uboot='2019.04', cpu_id='0xf00', + soc='AST2600 rev A3', + image_hostname='gb200nvl-obmc') + +if __name__ == '__main__': + AspeedTest.main() -- 2.50.0 The following changes since commit 039fae56bb79af1124619daae60e01c257fcb2ee: Merge tag 'pull-request-2026-02-12v2' of https://gitlab.com/thuth/qemu into staging (2026-02-12 11:52:31 +0000) are available in the Git repository at: https://github.com/legoater/qemu/ tags/pull-aspeed-20260212 for you to fetch changes up to 1b662879513fa9823a887cac9cfc3d91b9d3f616: tests/functional/aarch64/test_aspeed_ast2700fc: Use AST2700 A2 SDK image for FC tests (2026-02-12 16:06:55 +0100) ---------------------------------------------------------------- aspeed-next queue: * Adds support for the AST2700 A2 SoC, including a new machine and a functional test * Enhances AST2600 OTP functional test * Restructures Aspeed ARM tests into separate files for better parallelism. * Includes new SDK tests with Linux 5.15. * Fixes Aspeed I2C models ---------------------------------------------------------------- Cédric Le Goater (2): tests/functional: Split Aspeed ARM tests into separate files tests/functional: Add SDK tests with Linux 5.15 Jamin Lin (13): hw/i2c/aspeed_i2c: Fix out-of-bounds read in I2C MMIO handlers hw/i2c/aspeed_i2c: Increase I2C device register size to 0xA0 hw/misc/aspeed_scu: Remove unused SoC silicon revision definitions hw/misc/aspeed_scu: Add AST2700 A2 silicon revisions hw/arm/aspeed_ast27x0: Add AST2700 A2 SoC support hw/arm/aspeed_ast27x0_evb: Add AST2700 A2 EVB machine hw/arm/aspeed_ast27x0_evb: Move ast2700-evb alias to AST2700 A2 EVB tests/qtest/ast2700-hace-test: Use ast2700-evb alias for AST2700 HACE tests tests/functional/aarch64/test_aspeed_ast2700: Rename AST2700 A1 test to reduce test runtime tests/functional/aarch64/test_aspeed_ast2700a2: Add AST2700 A2 EVB functional tests hw/arm/aspeed_ast27x0-fc: Switch AST2700 FC machine to A2 SoC hw/arm/aspeed_ast27x0-fc: Increase BMC DRAM size to 2GB for AST2700 A2 tests/functional/aarch64/test_aspeed_ast2700fc: Use AST2700 A2 SDK image for FC tests Kane Chen (1): tests/functional/arm/aspeed_ast2600: Enhance OTP test with functional validation include/hw/i2c/aspeed_i2c.h | 3 +- include/hw/misc/aspeed_scu.h | 11 +- hw/arm/aspeed_ast27x0-fc.c | 15 +- hw/arm/aspeed_ast27x0.c | 36 ++++ hw/arm/aspeed_ast27x0_evb.c | 29 +++- hw/i2c/aspeed_i2c.c | 58 +++---- hw/misc/aspeed_scu.c | 11 +- tests/qtest/ast2700-hace-test.c | 22 +-- tests/functional/aarch64/meson.build | 6 +- ..._aspeed_ast2700.py => test_aspeed_ast2700a1.py} | 0 tests/functional/aarch64/test_aspeed_ast2700a2.py | 190 +++++++++++++++++++++ tests/functional/aarch64/test_aspeed_ast2700fc.py | 16 +- tests/functional/arm/meson.build | 18 +- tests/functional/arm/test_aspeed_ast1060.py | 0 ...ast2500.py => test_aspeed_ast2500_buildroot.py} | 14 -- tests/functional/arm/test_aspeed_ast2500_sdk.py | 29 ++++ .../functional/arm/test_aspeed_ast2500_sdk_515.py | 29 ++++ .../arm/test_aspeed_ast2600_buildroot.py | 41 +---- .../arm/test_aspeed_ast2600_buildroot_tpm.py | 60 +++++++ tests/functional/arm/test_aspeed_ast2600_sdk.py | 15 -- .../functional/arm/test_aspeed_ast2600_sdk_515.py | 29 ++++ .../functional/arm/test_aspeed_ast2600_sdk_otp.py | 62 +++++++ 22 files changed, 539 insertions(+), 155 deletions(-) rename tests/functional/aarch64/{test_aspeed_ast2700.py => test_aspeed_ast2700a1.py} (100%) create mode 100755 tests/functional/aarch64/test_aspeed_ast2700a2.py mode change 100644 => 100755 tests/functional/arm/test_aspeed_ast1060.py rename tests/functional/arm/{test_aspeed_ast2500.py => test_aspeed_ast2500_buildroot.py} (74%) create mode 100755 tests/functional/arm/test_aspeed_ast2500_sdk.py create mode 100755 tests/functional/arm/test_aspeed_ast2500_sdk_515.py create mode 100755 tests/functional/arm/test_aspeed_ast2600_buildroot_tpm.py create mode 100755 tests/functional/arm/test_aspeed_ast2600_sdk_515.py create mode 100755 tests/functional/arm/test_aspeed_ast2600_sdk_otp.py Reorganize the monolithic Aspeed functional test files into separate files based on firmware type (Buildroot vs SDK) and specific test scenarios. This allows the test suite to run tests in parallel more effectively and makes it easier to identify and run specific test scenarios independently. Link: https://lore.kernel.org/qemu-devel/20260209065044.239378-2-clg@redhat.com Reviewed-by: Kane Chen <kane_chen@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@redhat.com> --- tests/functional/arm/meson.build | 14 +++-- tests/functional/arm/test_aspeed_ast1060.py | 0 ...00.py => test_aspeed_ast2500_buildroot.py} | 14 ----- .../functional/arm/test_aspeed_ast2500_sdk.py | 29 +++++++++ .../arm/test_aspeed_ast2600_buildroot.py | 41 +------------ .../arm/test_aspeed_ast2600_buildroot_tpm.py | 60 +++++++++++++++++++ .../functional/arm/test_aspeed_ast2600_sdk.py | 15 ----- .../arm/test_aspeed_ast2600_sdk_otp.py | 34 +++++++++++ 8 files changed, 134 insertions(+), 73 deletions(-) mode change 100644 => 100755 tests/functional/arm/test_aspeed_ast1060.py rename tests/functional/arm/{test_aspeed_ast2500.py => test_aspeed_ast2500_buildroot.py} (74%) create mode 100755 tests/functional/arm/test_aspeed_ast2500_sdk.py create mode 100755 tests/functional/arm/test_aspeed_ast2600_buildroot_tpm.py create mode 100755 tests/functional/arm/test_aspeed_ast2600_sdk_otp.py diff --git a/tests/functional/arm/meson.build b/tests/functional/arm/meson.build index XXXXXXX..XXXXXXX 100644 --- a/tests/functional/arm/meson.build +++ b/tests/functional/arm/meson.build @@ -XXX,XX +XXX,XX @@ test_arm_timeouts = { 'aspeed_palmetto' : 120, 'aspeed_romulus' : 120, 'aspeed_witherspoon' : 120, - 'aspeed_ast2500' : 720, - 'aspeed_ast2600_buildroot' : 720, - 'aspeed_ast2600_sdk' : 1200, + 'aspeed_ast2500_sdk' : 720, + 'aspeed_ast2500_buildroot' : 480, + 'aspeed_ast2600_buildroot' : 480, + 'aspeed_ast2600_buildroot_tpm' : 720, + 'aspeed_ast2600_sdk' : 720, + 'aspeed_ast2600_sdk_otp' : 720, 'aspeed_bletchley' : 480, 'aspeed_catalina' : 480, 'aspeed_gb200nvl_bmc' : 480, @@ -XXX,XX +XXX,XX @@ tests_arm_system_thorough = [ 'aspeed_palmetto', 'aspeed_romulus', 'aspeed_witherspoon', - 'aspeed_ast2500', + 'aspeed_ast2500_sdk', + 'aspeed_ast2500_buildroot', 'aspeed_ast2600_buildroot', + 'aspeed_ast2600_buildroot_tpm', 'aspeed_ast2600_sdk', + 'aspeed_ast2600_sdk_otp', 'aspeed_bletchley', 'aspeed_catalina', 'aspeed_gb200nvl_bmc', diff --git a/tests/functional/arm/test_aspeed_ast1060.py b/tests/functional/arm/test_aspeed_ast1060.py old mode 100644 new mode 100755 diff --git a/tests/functional/arm/test_aspeed_ast2500.py b/tests/functional/arm/test_aspeed_ast2500_buildroot.py similarity index 74% rename from tests/functional/arm/test_aspeed_ast2500.py rename to tests/functional/arm/test_aspeed_ast2500_buildroot.py index XXXXXXX..XXXXXXX 100755 --- a/tests/functional/arm/test_aspeed_ast2500.py +++ b/tests/functional/arm/test_aspeed_ast2500_buildroot.py @@ -XXX,XX +XXX,XX @@ def test_arm_ast2500_evb_buildroot(self): self.do_test_arm_aspeed_buildroot_poweroff() - ASSET_SDK_V1000_AST2500 = Asset( - 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v10.00/ast2500-default-obmc.tar.gz', - '7d71a3f71d5f4d9f3451f59a73bf9baf8fd9f6a24107eb504a3216151a8b2b5b') - - def test_arm_ast2500_evb_sdk(self): - self.set_machine('ast2500-evb') - - self.archive_extract(self.ASSET_SDK_V1000_AST2500) - - self.do_test_arm_aspeed_sdk_start( - self.scratch_file("ast2500-default", "image-bmc")) - - self.wait_for_console_pattern('ast2500-default login:') - if __name__ == '__main__': AspeedTest.main() diff --git a/tests/functional/arm/test_aspeed_ast2500_sdk.py b/tests/functional/arm/test_aspeed_ast2500_sdk.py new file mode 100755 index XXXXXXX..XXXXXXX --- /dev/null +++ b/tests/functional/arm/test_aspeed_ast2500_sdk.py @@ -XXX,XX +XXX,XX @@ +#!/usr/bin/env python3 +# +# Functional test that boots the ASPEED machines +# +# SPDX-License-Identifier: GPL-2.0-or-later + +from qemu_test import Asset +from aspeed import AspeedTest + + +class AST2500Machine(AspeedTest): + + ASSET_SDK_V1000_AST2500 = Asset( + 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v10.00/ast2500-default-obmc.tar.gz', + '7d71a3f71d5f4d9f3451f59a73bf9baf8fd9f6a24107eb504a3216151a8b2b5b') + + def test_arm_ast2500_evb_sdk(self): + self.set_machine('ast2500-evb') + + self.archive_extract(self.ASSET_SDK_V1000_AST2500) + + self.do_test_arm_aspeed_sdk_start( + self.scratch_file("ast2500-default", "image-bmc")) + + self.wait_for_console_pattern('ast2500-default login:') + + +if __name__ == '__main__': + AspeedTest.main() diff --git a/tests/functional/arm/test_aspeed_ast2600_buildroot.py b/tests/functional/arm/test_aspeed_ast2600_buildroot.py index XXXXXXX..XXXXXXX 100755 --- a/tests/functional/arm/test_aspeed_ast2600_buildroot.py +++ b/tests/functional/arm/test_aspeed_ast2600_buildroot.py @@ -XXX,XX +XXX,XX @@ from aspeed import AspeedTest from qemu_test import Asset -from qemu_test import exec_command_and_wait_for_pattern, skipIfMissingCommands +from qemu_test import exec_command_and_wait_for_pattern class AST2600Machine(AspeedTest): @@ -XXX,XX +XXX,XX @@ def test_arm_ast2600_evb_buildroot(self): '0000000 ffaa ffff ffff ffff ffff ffff ffff ffff') self.do_test_arm_aspeed_buildroot_poweroff() - ASSET_BR2_202302_AST2600_TPM_FLASH = Asset( - ('https://github.com/legoater/qemu-aspeed-boot/raw/master/' - 'images/ast2600-evb/buildroot-2023.02-tpm/flash.img'), - 'a46009ae8a5403a0826d607215e731a8c68d27c14c41e55331706b8f9c7bd997') - - def _test_arm_ast2600_evb_buildroot_tpm(self, tpmstate_dir): - image_path = self.ASSET_BR2_202302_AST2600_TPM_FLASH.fetch() - - socket = os.path.join(tpmstate_dir, 'swtpm-socket') - - # We must put the TPM state dir in /tmp/, not the build dir, - # because some distros use AppArmor to lock down swtpm and - # restrict the set of locations it can access files in. - subprocess.run(['swtpm', 'socket', '-d', '--tpm2', - '--tpmstate', f'dir={tpmstate_dir}', - '--ctrl', f'type=unixio,path={socket}'], - check=True) - - self.vm.add_args('-chardev', f'socket,id=chrtpm,path={socket}') - self.vm.add_args('-tpmdev', 'emulator,id=tpm0,chardev=chrtpm') - self.vm.add_args('-device', - 'tpm-tis-i2c,tpmdev=tpm0,bus=aspeed.i2c.bus.12,address=0x2e') - self.do_test_arm_aspeed_buildroot_start(image_path, '0xf00', 'Aspeed AST2600 EVB') - - exec_command_and_wait_for_pattern(self, - 'echo tpm_tis_i2c 0x2e > /sys/bus/i2c/devices/i2c-12/new_device', - 'tpm_tis_i2c 12-002e: 2.0 TPM (device-id 0x1, rev-id 1)') - exec_command_and_wait_for_pattern(self, - 'cat /sys/class/tpm/tpm0/pcr-sha256/0', - 'B804724EA13F52A9072BA87FE8FDCC497DFC9DF9AA15B9088694639C431688E0') - - self.do_test_arm_aspeed_buildroot_poweroff() - - @skipIfMissingCommands('swtpm') - def test_arm_ast2600_evb_buildroot_tpm(self): - self.set_machine('ast2600-evb') - with tempfile.TemporaryDirectory(prefix="qemu_") as tpmstate_dir: - self._test_arm_ast2600_evb_buildroot_tpm(tpmstate_dir) - if __name__ == '__main__': AspeedTest.main() diff --git a/tests/functional/arm/test_aspeed_ast2600_buildroot_tpm.py b/tests/functional/arm/test_aspeed_ast2600_buildroot_tpm.py new file mode 100755 index XXXXXXX..XXXXXXX --- /dev/null +++ b/tests/functional/arm/test_aspeed_ast2600_buildroot_tpm.py @@ -XXX,XX +XXX,XX @@ +#!/usr/bin/env python3 +# +# Functional test that boots the ASPEED machines +# +# SPDX-License-Identifier: GPL-2.0-or-later + +import os +import time +import tempfile +import subprocess + +from aspeed import AspeedTest +from qemu_test import Asset +from qemu_test import exec_command_and_wait_for_pattern, skipIfMissingCommands + + +class AST2600Machine(AspeedTest): + + ASSET_BR2_202302_AST2600_TPM_FLASH = Asset( + ('https://github.com/legoater/qemu-aspeed-boot/raw/master/' + 'images/ast2600-evb/buildroot-2023.02-tpm/flash.img'), + 'a46009ae8a5403a0826d607215e731a8c68d27c14c41e55331706b8f9c7bd997') + + def _test_arm_ast2600_evb_buildroot_tpm(self, tpmstate_dir): + image_path = self.ASSET_BR2_202302_AST2600_TPM_FLASH.fetch() + + socket = os.path.join(tpmstate_dir, 'swtpm-socket') + + # We must put the TPM state dir in /tmp/, not the build dir, + # because some distros use AppArmor to lock down swtpm and + # restrict the set of locations it can access files in. + subprocess.run(['swtpm', 'socket', '-d', '--tpm2', + '--tpmstate', f'dir={tpmstate_dir}', + '--ctrl', f'type=unixio,path={socket}'], + check=True) + + self.vm.add_args('-chardev', f'socket,id=chrtpm,path={socket}') + self.vm.add_args('-tpmdev', 'emulator,id=tpm0,chardev=chrtpm') + self.vm.add_args('-device', + 'tpm-tis-i2c,tpmdev=tpm0,bus=aspeed.i2c.bus.12,address=0x2e') + self.do_test_arm_aspeed_buildroot_start(image_path, '0xf00', 'Aspeed AST2600 EVB') + + exec_command_and_wait_for_pattern(self, + 'echo tpm_tis_i2c 0x2e > /sys/bus/i2c/devices/i2c-12/new_device', + 'tpm_tis_i2c 12-002e: 2.0 TPM (device-id 0x1, rev-id 1)') + exec_command_and_wait_for_pattern(self, + 'cat /sys/class/tpm/tpm0/pcr-sha256/0', + 'B804724EA13F52A9072BA87FE8FDCC497DFC9DF9AA15B9088694639C431688E0') + + self.do_test_arm_aspeed_buildroot_poweroff() + + @skipIfMissingCommands('swtpm') + def test_arm_ast2600_evb_buildroot_tpm(self): + self.set_machine('ast2600-evb') + with tempfile.TemporaryDirectory(prefix="qemu_") as tpmstate_dir: + self._test_arm_ast2600_evb_buildroot_tpm(tpmstate_dir) + + +if __name__ == '__main__': + AspeedTest.main() diff --git a/tests/functional/arm/test_aspeed_ast2600_sdk.py b/tests/functional/arm/test_aspeed_ast2600_sdk.py index XXXXXXX..XXXXXXX 100755 --- a/tests/functional/arm/test_aspeed_ast2600_sdk.py +++ b/tests/functional/arm/test_aspeed_ast2600_sdk.py @@ -XXX,XX +XXX,XX @@ def test_arm_ast2600_evb_sdk(self): '/sbin/hwclock -f /dev/rtc1', year) self.do_ast2600_pcie_test() - def test_arm_ast2600_otp_blockdev_device(self): - self.vm.set_machine("ast2600-evb") - - image_path = self.archive_extract(self.ASSET_SDK_V1100_AST2600) - otp_img = self.generate_otpmem_image() - - self.vm.set_console() - self.vm.add_args( - "-blockdev", f"driver=file,filename={otp_img},node-name=otp", - "-global", "aspeed-otp.drive=otp", - ) - self.do_test_arm_aspeed_sdk_start( - self.scratch_file("ast2600-default", "image-bmc")) - self.wait_for_console_pattern("ast2600-default login:") - if __name__ == '__main__': AspeedTest.main() diff --git a/tests/functional/arm/test_aspeed_ast2600_sdk_otp.py b/tests/functional/arm/test_aspeed_ast2600_sdk_otp.py new file mode 100755 index XXXXXXX..XXXXXXX --- /dev/null +++ b/tests/functional/arm/test_aspeed_ast2600_sdk_otp.py @@ -XXX,XX +XXX,XX @@ +#!/usr/bin/env python3 +# +# Functional test that boots the ASPEED machines +# +# SPDX-License-Identifier: GPL-2.0-or-later + +from qemu_test import Asset +from aspeed import AspeedTest + + +class AST2600Machine(AspeedTest): + + ASSET_SDK_V1100_AST2600 = Asset( + 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.00/ast2600-default-obmc.tar.gz', + '64d8926a7d01b649168be96c986603b5690f06391286c438a3a772c8c7039e93') + + def test_arm_ast2600_otp_blockdev_device(self): + self.vm.set_machine("ast2600-evb") + + image_path = self.archive_extract(self.ASSET_SDK_V1100_AST2600) + otp_img = self.generate_otpmem_image() + + self.vm.set_console() + self.vm.add_args( + "-blockdev", f"driver=file,filename={otp_img},node-name=otp", + "-global", "aspeed-otp.drive=otp", + ) + self.do_test_arm_aspeed_sdk_start( + self.scratch_file("ast2600-default", "image-bmc")) + self.wait_for_console_pattern("ast2600-default login:") + + +if __name__ == '__main__': + AspeedTest.main() -- 2.53.0 Add functional tests for AST2500 and AST2600 machines using the OpenBMC SDK v11.00 with Linux kernel 5.15. These tests complement the existing SDK tests and verify that QEMU correctly boots older kernel versions on these platforms. Link: https://lore.kernel.org/qemu-devel/20260209065044.239378-3-clg@redhat.com Reviewed-by: Kane Chen <kane_chen@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@redhat.com> --- tests/functional/arm/meson.build | 4 +++ .../arm/test_aspeed_ast2500_sdk_515.py | 29 +++++++++++++++++++ .../arm/test_aspeed_ast2600_sdk_515.py | 29 +++++++++++++++++++ 3 files changed, 62 insertions(+) create mode 100755 tests/functional/arm/test_aspeed_ast2500_sdk_515.py create mode 100755 tests/functional/arm/test_aspeed_ast2600_sdk_515.py diff --git a/tests/functional/arm/meson.build b/tests/functional/arm/meson.build index XXXXXXX..XXXXXXX 100644 --- a/tests/functional/arm/meson.build +++ b/tests/functional/arm/meson.build @@ -XXX,XX +XXX,XX @@ test_arm_timeouts = { 'aspeed_romulus' : 120, 'aspeed_witherspoon' : 120, 'aspeed_ast2500_sdk' : 720, + 'aspeed_ast2500_sdk_515' : 720, 'aspeed_ast2500_buildroot' : 480, 'aspeed_ast2600_buildroot' : 480, 'aspeed_ast2600_buildroot_tpm' : 720, 'aspeed_ast2600_sdk' : 720, + 'aspeed_ast2600_sdk_515' : 720, 'aspeed_ast2600_sdk_otp' : 720, 'aspeed_bletchley' : 480, 'aspeed_catalina' : 480, @@ -XXX,XX +XXX,XX @@ tests_arm_system_thorough = [ 'aspeed_romulus', 'aspeed_witherspoon', 'aspeed_ast2500_sdk', + 'aspeed_ast2500_sdk_515', 'aspeed_ast2500_buildroot', 'aspeed_ast2600_buildroot', 'aspeed_ast2600_buildroot_tpm', 'aspeed_ast2600_sdk', + 'aspeed_ast2600_sdk_515', 'aspeed_ast2600_sdk_otp', 'aspeed_bletchley', 'aspeed_catalina', diff --git a/tests/functional/arm/test_aspeed_ast2500_sdk_515.py b/tests/functional/arm/test_aspeed_ast2500_sdk_515.py new file mode 100755 index XXXXXXX..XXXXXXX --- /dev/null +++ b/tests/functional/arm/test_aspeed_ast2500_sdk_515.py @@ -XXX,XX +XXX,XX @@ +#!/usr/bin/env python3 +# +# Functional test that boots the ASPEED machines +# +# SPDX-License-Identifier: GPL-2.0-or-later + +from qemu_test import Asset +from aspeed import AspeedTest + + +class AST2500Machine(AspeedTest): + + ASSET_SDK_V1100_AST2500_515 = Asset( + 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.00/ast2500-default-515-obmc.tar.gz', + '5732255d4617d98b76bbbc116d331d6ac89906fa212969eb8213fdc4aea86451') + + def test_arm_ast2500_evb_sdk_515(self): + self.set_machine('ast2500-evb') + + self.archive_extract(self.ASSET_SDK_V1100_AST2500_515) + + self.do_test_arm_aspeed_sdk_start( + self.scratch_file("ast2500-default-515", "image-bmc")) + + self.wait_for_console_pattern('ast2500-default-515 login:') + + +if __name__ == '__main__': + AspeedTest.main() diff --git a/tests/functional/arm/test_aspeed_ast2600_sdk_515.py b/tests/functional/arm/test_aspeed_ast2600_sdk_515.py new file mode 100755 index XXXXXXX..XXXXXXX --- /dev/null +++ b/tests/functional/arm/test_aspeed_ast2600_sdk_515.py @@ -XXX,XX +XXX,XX @@ +#!/usr/bin/env python3 +# +# Functional test that boots the ASPEED machines +# +# SPDX-License-Identifier: GPL-2.0-or-later + +from qemu_test import Asset +from aspeed import AspeedTest + + +class AST2600Machine(AspeedTest): + + ASSET_SDK_V1100_AST2600_515 = Asset( + 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.00/ast2600-default-515-obmc.tar.gz', + 'ece1a934095378929780f03e7d092e562f4b33b2841b80ad7c3d12a85744c0f6') + + def test_arm_ast2600_evb_sdk_515(self): + self.set_machine('ast2600-evb') + + self.archive_extract(self.ASSET_SDK_V1100_AST2600_515) + + self.do_test_arm_aspeed_sdk_start( + self.scratch_file("ast2600-default-515", "image-bmc")) + + self.wait_for_console_pattern('ast2600-default-515 login:') + + +if __name__ == '__main__': + AspeedTest.main() -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> The ASPEED I2C controller exposes a per-bus MMIO window of 0x80 bytes on AST2600/AST1030/AST2700, but the backing regs[] array was sized for only 28 dwords (0x70 bytes). This allows guest reads in the range [0x70..0x7f] to index past the end of regs[]. Fix this by: - Sizing ASPEED_I2C_NEW_NUM_REG to match the 0x80-byte window (0x80 >> 2 = 32 dwords). - Avoiding an unconditional pre-read from regs[] in the legacy/new read handlers. Initialize the return value to -1 and only read regs[] for offsets that are explicitly handled/valid, leaving invalid offsets to return -1 with a guest error log. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3290 Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260210024331.3984696-2-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- include/hw/i2c/aspeed_i2c.h | 3 +-- hw/i2c/aspeed_i2c.c | 22 ++++++++++------------ 2 files changed, 11 insertions(+), 14 deletions(-) diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/i2c/aspeed_i2c.h +++ b/include/hw/i2c/aspeed_i2c.h @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(AspeedI2CState, AspeedI2CClass, ASPEED_I2C) #define ASPEED_I2C_NR_BUSSES 16 #define ASPEED_I2C_SHARE_POOL_SIZE 0x800 #define ASPEED_I2C_BUS_POOL_SIZE 0x20 -#define ASPEED_I2C_OLD_NUM_REG 11 -#define ASPEED_I2C_NEW_NUM_REG 28 +#define ASPEED_I2C_NEW_NUM_REG (0x80 >> 2) #define A_I2CD_M_STOP_CMD BIT(5) #define A_I2CD_M_RX_CMD BIT(3) diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c index XXXXXXX..XXXXXXX 100644 --- a/hw/i2c/aspeed_i2c.c +++ b/hw/i2c/aspeed_i2c.c @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_i2c_bus_old_read(AspeedI2CBus *bus, hwaddr offset, unsigned size) { AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); - uint64_t value = bus->regs[offset / sizeof(*bus->regs)]; + uint64_t value = -1; switch (offset) { case A_I2CD_FUN_CTRL: @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_i2c_bus_old_read(AspeedI2CBus *bus, hwaddr offset, case A_I2CD_DEV_ADDR: case A_I2CD_POOL_CTRL: case A_I2CD_BYTE_BUF: - /* Value is already set, don't do anything. */ + value = bus->regs[offset / sizeof(*bus->regs)]; break; case A_I2CD_CMD: value = SHARED_FIELD_DP32(value, BUS_BUSY_STS, i2c_bus_busy(bus->bus)); @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_i2c_bus_old_read(AspeedI2CBus *bus, hwaddr offset, case A_I2CD_DMA_ADDR: if (!aic->has_dma) { qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); - value = -1; break; } + value = bus->regs[offset / sizeof(*bus->regs)]; break; case A_I2CD_DMA_LEN: if (!aic->has_dma) { qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func__); - value = -1; + break; } + value = bus->regs[offset / sizeof(*bus->regs)]; break; - default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset); - value = -1; break; } @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_i2c_bus_new_read(AspeedI2CBus *bus, hwaddr offset, unsigned size) { AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); - uint64_t value = bus->regs[offset / sizeof(*bus->regs)]; + uint64_t value = -1; switch (offset) { case A_I2CC_FUN_CTRL: @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_i2c_bus_new_read(AspeedI2CBus *bus, hwaddr offset, case A_I2CS_CMD: case A_I2CS_INTR_CTRL: case A_I2CS_DMA_LEN_STS: - /* Value is already set, don't do anything. */ + case A_I2CS_INTR_STS: + value = bus->regs[offset / sizeof(*bus->regs)]; break; case A_I2CC_DMA_ADDR: value = extract64(bus->dma_dram_offset, 0, 32); break; - case A_I2CS_INTR_STS: - break; case A_I2CM_CMD: value = SHARED_FIELD_DP32(value, BUS_BUSY_STS, i2c_bus_busy(bus->bus)); break; @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_i2c_bus_new_read(AspeedI2CBus *bus, hwaddr offset, if (!aic->has_dma64) { qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA 64 bits support\n", __func__); - value = -1; + break; } + value = bus->regs[offset / sizeof(*bus->regs)]; break; default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset); - value = -1; break; } -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> According to the AST2700 A1 datasheet, the register space for each I2C device instance has been expanded from 0x80 bytes to 0xA0 bytes. Update the AST2700 I2C controller configuration to reflect the new register layout by increasing the per-device register size to 0xA0 and adjusting the register gap size accordingly. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Fixes: 4f53de2f103d6dfb5ad0498995d91a9694f40dd2 ("hw/arm/aspeed_ast27x0: Remove ast2700-a0 SOC") Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260210024331.3984696-3-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- include/hw/i2c/aspeed_i2c.h | 2 +- hw/i2c/aspeed_i2c.c | 36 ++++++++++++++++++------------------ 2 files changed, 19 insertions(+), 19 deletions(-) diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/i2c/aspeed_i2c.h +++ b/include/hw/i2c/aspeed_i2c.h @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(AspeedI2CState, AspeedI2CClass, ASPEED_I2C) #define ASPEED_I2C_NR_BUSSES 16 #define ASPEED_I2C_SHARE_POOL_SIZE 0x800 #define ASPEED_I2C_BUS_POOL_SIZE 0x20 -#define ASPEED_I2C_NEW_NUM_REG (0x80 >> 2) +#define ASPEED_I2C_NEW_NUM_REG (0xa0 >> 2) #define A_I2CD_M_STOP_CMD BIT(5) #define A_I2CD_M_RX_CMD BIT(3) diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c index XXXXXXX..XXXXXXX 100644 --- a/hw/i2c/aspeed_i2c.c +++ b/hw/i2c/aspeed_i2c.c @@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_instance_init(Object *obj) * * Address Definitions (AST2700) * 0x000 ... 0x0FF: Global Register - * 0x100 ... 0x17F: Device 0 + * 0x100 ... 0x19F: Device 0 * 0x1A0 ... 0x1BF: Device 0 buffer - * 0x200 ... 0x27F: Device 1 + * 0x200 ... 0x29F: Device 1 * 0x2A0 ... 0x2BF: Device 1 buffer - * 0x300 ... 0x37F: Device 2 + * 0x300 ... 0x39F: Device 2 * 0x3A0 ... 0x3BF: Device 2 buffer - * 0x400 ... 0x47F: Device 3 + * 0x400 ... 0x49F: Device 3 * 0x4A0 ... 0x4BF: Device 3 buffer - * 0x500 ... 0x57F: Device 4 + * 0x500 ... 0x59F: Device 4 * 0x5A0 ... 0x5BF: Device 4 buffer - * 0x600 ... 0x67F: Device 5 + * 0x600 ... 0x69F: Device 5 * 0x6A0 ... 0x6BF: Device 5 buffer - * 0x700 ... 0x77F: Device 6 + * 0x700 ... 0x79F: Device 6 * 0x7A0 ... 0x7BF: Device 6 buffer - * 0x800 ... 0x87F: Device 7 + * 0x800 ... 0x89F: Device 7 * 0x8A0 ... 0x8BF: Device 7 buffer - * 0x900 ... 0x97F: Device 8 + * 0x900 ... 0x99F: Device 8 * 0x9A0 ... 0x9BF: Device 8 buffer - * 0xA00 ... 0xA7F: Device 9 + * 0xA00 ... 0xA9F: Device 9 * 0xAA0 ... 0xABF: Device 9 buffer - * 0xB00 ... 0xB7F: Device 10 + * 0xB00 ... 0xB9F: Device 10 * 0xBA0 ... 0xBBF: Device 10 buffer - * 0xC00 ... 0xC7F: Device 11 + * 0xC00 ... 0xC9F: Device 11 * 0xCA0 ... 0xCBF: Device 11 buffer - * 0xD00 ... 0xD7F: Device 12 + * 0xD00 ... 0xD9F: Device 12 * 0xDA0 ... 0xDBF: Device 12 buffer - * 0xE00 ... 0xE7F: Device 13 + * 0xE00 ... 0xE9F: Device 13 * 0xEA0 ... 0xEBF: Device 13 buffer - * 0xF00 ... 0xF7F: Device 14 + * 0xF00 ... 0xF9F: Device 14 * 0xFA0 ... 0xFBF: Device 14 buffer - * 0x1000 ... 0x107F: Device 15 + * 0x1000 ... 0x109F: Device 15 * 0x10A0 ... 0x10BF: Device 15 buffer */ static void aspeed_i2c_realize(DeviceState *dev, Error **errp) @@ -XXX,XX +XXX,XX @@ static void aspeed_2700_i2c_class_init(ObjectClass *klass, const void *data) dc->desc = "ASPEED 2700 I2C Controller"; aic->num_busses = 16; - aic->reg_size = 0x80; - aic->reg_gap_size = 0x80; + aic->reg_size = 0xa0; + aic->reg_gap_size = 0x60; aic->gap = -1; /* no gap */ aic->bus_get_irq = aspeed_2600_i2c_bus_get_irq; aic->pool_size = 0x20; -- 2.53.0 From: Kane Chen <kane_chen@aspeedtech.com> Improve the OTP test script by adding functional verification of OTP strap registers. The test now validates that OTP modifications made in U-Boot persist through the Linux boot process and survive a subsequent reboot. Key changes: - Added interactive console commands for U-Boot and Linux. - Implemented verification for OTP register 0x30 across reboots. Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260211052326.430475-2-kane_chen@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- .../arm/test_aspeed_ast2600_sdk_otp.py | 34 +++++++++++++++++-- 1 file changed, 31 insertions(+), 3 deletions(-) diff --git a/tests/functional/arm/test_aspeed_ast2600_sdk_otp.py b/tests/functional/arm/test_aspeed_ast2600_sdk_otp.py index XXXXXXX..XXXXXXX 100755 --- a/tests/functional/arm/test_aspeed_ast2600_sdk_otp.py +++ b/tests/functional/arm/test_aspeed_ast2600_sdk_otp.py @@ -XXX,XX +XXX,XX @@ from qemu_test import Asset from aspeed import AspeedTest +from qemu_test import wait_for_console_pattern, exec_command +from qemu_test import exec_command_and_wait_for_pattern class AST2600Machine(AspeedTest): @@ -XXX,XX +XXX,XX @@ class AST2600Machine(AspeedTest): def test_arm_ast2600_otp_blockdev_device(self): self.vm.set_machine("ast2600-evb") + self.require_netdev('user') image_path = self.archive_extract(self.ASSET_SDK_V1100_AST2600) otp_img = self.generate_otpmem_image() @@ -XXX,XX +XXX,XX @@ def test_arm_ast2600_otp_blockdev_device(self): "-blockdev", f"driver=file,filename={otp_img},node-name=otp", "-global", "aspeed-otp.drive=otp", ) - self.do_test_arm_aspeed_sdk_start( - self.scratch_file("ast2600-default", "image-bmc")) - self.wait_for_console_pattern("ast2600-default login:") + self.vm.add_args('-drive', 'file=' + + self.scratch_file("ast2600-default", "image-bmc") + + ',if=mtd,format=raw', + '-net', 'nic', '-net', 'user', '-snapshot') + self.vm.launch() + + # Set OTP value via uboot command + wait_for_console_pattern(self, 'Hit any key to stop autoboot:') + exec_command_and_wait_for_pattern(self, '\012', 'ast#') + exec_command_and_wait_for_pattern(self, + 'otp pb strap o 0x30 1', 'ast#') + # Validate OTP value in uboot stage + exec_command_and_wait_for_pattern(self, + 'otp read strap 0x30', '0x30 1') + exec_command_and_wait_for_pattern(self, 'boot', + "ast2600-default login:") + exec_command_and_wait_for_pattern(self, 'root', 'Password:') + exec_command_and_wait_for_pattern(self, '0penBmc', + 'root@ast2600-default:~#') + # Validate OTP value in BMC stage + exec_command_and_wait_for_pattern(self, + 'otp read strap 0x30', '0x30 1') + exec_command_and_wait_for_pattern(self, + 'reboot', 'Hit any key to stop autoboot') + exec_command_and_wait_for_pattern(self, '\012', 'ast#') + # Validate OTP value in uboot stage + exec_command_and_wait_for_pattern(self, + 'otp read strap 0x30', '0x30 1') if __name__ == '__main__': -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> Several legacy Aspeed SoC silicon revision definitions are no longer used by any machine models or runtime logic. Remove unused silicon revision macros and corresponding entries from the silicon revision table to reduce dead code and improve maintainability. No functional change intended. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260211021527.119674-2-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- include/hw/misc/aspeed_scu.h | 10 ---------- hw/misc/aspeed_scu.c | 10 ---------- 2 files changed, 20 deletions(-) diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/misc/aspeed_scu.h +++ b/include/hw/misc/aspeed_scu.h @@ -XXX,XX +XXX,XX @@ struct AspeedSCUState { uint32_t hw_prot_key; }; -#define AST2400_A0_SILICON_REV 0x02000303U #define AST2400_A1_SILICON_REV 0x02010303U -#define AST2500_A0_SILICON_REV 0x04000303U #define AST2500_A1_SILICON_REV 0x04010303U -#define AST2600_A0_SILICON_REV 0x05000303U -#define AST2600_A1_SILICON_REV 0x05010303U -#define AST2600_A2_SILICON_REV 0x05020303U #define AST2600_A3_SILICON_REV 0x05030303U -#define AST1030_A0_SILICON_REV 0x80000000U #define AST1030_A1_SILICON_REV 0x80010000U #define AST1060_A2_SILICON_REV 0xA0030000U -#define AST2700_A0_SILICON_REV 0x06000103U -#define AST2720_A0_SILICON_REV 0x06000203U -#define AST2750_A0_SILICON_REV 0x06000003U #define AST2700_A1_SILICON_REV 0x06010103U -#define AST2750_A1_SILICON_REV 0x06010003U #define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index XXXXXXX..XXXXXXX 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -XXX,XX +XXX,XX @@ static void aspeed_scu_reset(DeviceState *dev) } static uint32_t aspeed_silicon_revs[] = { - AST2400_A0_SILICON_REV, AST2400_A1_SILICON_REV, - AST2500_A0_SILICON_REV, AST2500_A1_SILICON_REV, - AST2600_A0_SILICON_REV, - AST2600_A1_SILICON_REV, - AST2600_A2_SILICON_REV, AST2600_A3_SILICON_REV, - AST1030_A0_SILICON_REV, AST1030_A1_SILICON_REV, AST1060_A2_SILICON_REV, - AST2700_A0_SILICON_REV, - AST2720_A0_SILICON_REV, - AST2750_A0_SILICON_REV, AST2700_A1_SILICON_REV, - AST2750_A1_SILICON_REV, }; bool is_supported_silicon_rev(uint32_t silicon_rev) -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> Add silicon revision definitions for AST2700 A2, and include them in the list of supported Aspeed silicon revisions. This allows newer AST27x0 A2 silicon to be correctly identified via the SCU silicon revision register. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260211021527.119674-3-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- include/hw/misc/aspeed_scu.h | 1 + hw/misc/aspeed_scu.c | 1 + 2 files changed, 2 insertions(+) diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/misc/aspeed_scu.h +++ b/include/hw/misc/aspeed_scu.h @@ -XXX,XX +XXX,XX @@ struct AspeedSCUState { #define AST1030_A1_SILICON_REV 0x80010000U #define AST1060_A2_SILICON_REV 0xA0030000U #define AST2700_A1_SILICON_REV 0x06010103U +#define AST2700_A2_SILICON_REV 0x06020103U #define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index XXXXXXX..XXXXXXX 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_silicon_revs[] = { AST1030_A1_SILICON_REV, AST1060_A2_SILICON_REV, AST2700_A1_SILICON_REV, + AST2700_A2_SILICON_REV, }; bool is_supported_silicon_rev(uint32_t silicon_rev) -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> AST2700 A2 is functionally identical to AST2700 A1. There are no changes to the IRQ layout, memory map, or peripheral configuration. The only difference is the silicon revision. This commit introduces a dedicated AST2700 A2 SoC type by reusing the existing AST2700 A1 implementation and setting the A2 silicon revision accordingly. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Nabih Estefan <nabihestefan@google.com> Tested-by: Nabih Estefan <nabihestefan@google.com> Link: https://lore.kernel.org/qemu-devel/20260211021527.119674-4-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- hw/arm/aspeed_ast27x0.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, const void *data) sc->memmap = aspeed_soc_ast2700_memmap; } +static void aspeed_soc_ast2700a2_class_init(ObjectClass *oc, const void *data) +{ + static const char * const valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-a35"), + NULL + }; + DeviceClass *dc = DEVICE_CLASS(oc); + AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); + + /* Reason: The Aspeed SoC can only be instantiated from a board */ + dc->user_creatable = false; + dc->realize = aspeed_soc_ast2700_realize; + + sc->valid_cpu_types = valid_cpu_types; + sc->silicon_rev = AST2700_A2_SILICON_REV; + sc->sram_size = 0x20000; + sc->pcie_num = 3; + sc->spis_num = 3; + sc->sgpio_num = 2; + sc->ehcis_num = 4; + sc->wdts_num = 8; + sc->macs_num = 3; + sc->uarts_num = 13; + sc->num_cpus = 4; + sc->ioexp_num = 2; + sc->uarts_base = ASPEED_DEV_UART0; + sc->irqmap = aspeed_soc_ast2700a1_irqmap; + sc->memmap = aspeed_soc_ast2700_memmap; +} + static const TypeInfo aspeed_soc_ast27x0_types[] = { { .name = TYPE_ASPEED27X0_SOC, @@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_soc_ast27x0_types[] = { .instance_init = aspeed_soc_ast2700_init, .class_init = aspeed_soc_ast2700a1_class_init, }, + { + .name = "ast2700-a2", + .parent = TYPE_ASPEED27X0_SOC, + .instance_init = aspeed_soc_ast2700_init, + .class_init = aspeed_soc_ast2700a2_class_init, + }, }; DEFINE_TYPES(aspeed_soc_ast27x0_types) -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> Add a new AST2700 A2 EVB machine to model the newer A2 silicon. The ast2700a2-evb machine is largely identical to ast2700a1-evb. The only difference is the default DRAM size, which is increased to 2 GB. This change adds a dedicated ast2700a2-evb machine by copying the existing ast2700a1-evb configuration and updating the DRAM size accordingly. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260211021527.119674-5-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- hw/arm/aspeed_ast27x0_evb.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/hw/arm/aspeed_ast27x0_evb.c b/hw/arm/aspeed_ast27x0_evb.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/aspeed_ast27x0_evb.c +++ b/hw/arm/aspeed_ast27x0_evb.c @@ -XXX,XX +XXX,XX @@ static void aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc, aspeed_machine_class_init_cpus_defaults(mc); } +static void aspeed_machine_ast2700a2_evb_class_init(ObjectClass *oc, + const void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); + + mc->desc = "Aspeed AST2700 A2 EVB (Cortex-A35)"; + amc->soc_name = "ast2700-a2"; + amc->hw_strap1 = AST2700_EVB_HW_STRAP1; + amc->hw_strap2 = AST2700_EVB_HW_STRAP2; + amc->fmc_model = "w25q01jvq"; + amc->spi_model = "w25q512jv"; + amc->num_cs = 2; + amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON; + amc->uart_default = ASPEED_DEV_UART12; + amc->i2c_init = ast2700_evb_i2c_init; + amc->vbootrom = true; + mc->default_ram_size = 2 * GiB; + aspeed_machine_class_init_cpus_defaults(mc); +} + static const TypeInfo aspeed_ast27x0_evb_types[] = { { .name = MACHINE_TYPE_NAME("ast2700a1-evb"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_ast2700a1_evb_class_init, .interfaces = aarch64_machine_interfaces, + }, + { + .name = MACHINE_TYPE_NAME("ast2700a2-evb"), + .parent = TYPE_ASPEED_MACHINE, + .class_init = aspeed_machine_ast2700a2_evb_class_init, + .interfaces = aarch64_machine_interfaces, } }; -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> Make AST2700 A2 EVB the default ast2700-evb machine. The "ast2700-evb" machine alias is moved from the AST2700 A1 EVB to the AST2700 A2 EVB, making A2 the default evaluation board for AST2700. This ensures that users selecting "ast2700-evb" will run on the latest AST2700 silicon revision. The AST2700 A1 EVB machine remains available explicitly as "ast2700a1-evb". Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260211021527.119674-6-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- hw/arm/aspeed_ast27x0_evb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/aspeed_ast27x0_evb.c b/hw/arm/aspeed_ast27x0_evb.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/aspeed_ast27x0_evb.c +++ b/hw/arm/aspeed_ast27x0_evb.c @@ -XXX,XX +XXX,XX @@ static void aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc, MachineClass *mc = MACHINE_CLASS(oc); AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); - mc->alias = "ast2700-evb"; mc->desc = "Aspeed AST2700 A1 EVB (Cortex-A35)"; amc->soc_name = "ast2700-a1"; amc->hw_strap1 = AST2700_EVB_HW_STRAP1; @@ -XXX,XX +XXX,XX @@ static void aspeed_machine_ast2700a2_evb_class_init(ObjectClass *oc, MachineClass *mc = MACHINE_CLASS(oc); AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); + mc->alias = "ast2700-evb"; mc->desc = "Aspeed AST2700 A2 EVB (Cortex-A35)"; amc->soc_name = "ast2700-a2"; amc->hw_strap1 = AST2700_EVB_HW_STRAP1; -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> Update AST2700 HACE qtests to use the "ast2700-evb" machine alias instead of a specific silicon revision. The AST2700 A1 and A2 revisions are compatible for the HACE model, so the tests do not depend on a particular EVB revision. Using the "ast2700-evb" alias ensures the tests always run the latest supported AST2700 silicon revision. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260211021527.119674-7-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- tests/qtest/ast2700-hace-test.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/tests/qtest/ast2700-hace-test.c b/tests/qtest/ast2700-hace-test.c index XXXXXXX..XXXXXXX 100644 --- a/tests/qtest/ast2700-hace-test.c +++ b/tests/qtest/ast2700-hace-test.c @@ -XXX,XX +XXX,XX @@ static const struct AspeedMasks as2700_masks = { /* ast2700 */ static void test_md5_ast2700(void) { - aspeed_test_md5("-machine ast2700a1-evb", 0x12070000, 0x400000000); + aspeed_test_md5("-machine ast2700-evb", 0x12070000, 0x400000000); } static void test_sha256_ast2700(void) { - aspeed_test_sha256("-machine ast2700a1-evb", 0x12070000, 0x400000000); + aspeed_test_sha256("-machine ast2700-evb", 0x12070000, 0x400000000); } static void test_sha256_sg_ast2700(void) { - aspeed_test_sha256_sg("-machine ast2700a1-evb", 0x12070000, 0x400000000); + aspeed_test_sha256_sg("-machine ast2700-evb", 0x12070000, 0x400000000); } static void test_sha384_ast2700(void) { - aspeed_test_sha384("-machine ast2700a1-evb", 0x12070000, 0x400000000); + aspeed_test_sha384("-machine ast2700-evb", 0x12070000, 0x400000000); } static void test_sha384_sg_ast2700(void) { - aspeed_test_sha384_sg("-machine ast2700a1-evb", 0x12070000, 0x400000000); + aspeed_test_sha384_sg("-machine ast2700-evb", 0x12070000, 0x400000000); } static void test_sha512_ast2700(void) { - aspeed_test_sha512("-machine ast2700a1-evb", 0x12070000, 0x400000000); + aspeed_test_sha512("-machine ast2700-evb", 0x12070000, 0x400000000); } static void test_sha512_sg_ast2700(void) { - aspeed_test_sha512_sg("-machine ast2700a1-evb", 0x12070000, 0x400000000); + aspeed_test_sha512_sg("-machine ast2700-evb", 0x12070000, 0x400000000); } static void test_sha256_accum_ast2700(void) { - aspeed_test_sha256_accum("-machine ast2700a1-evb", 0x12070000, 0x400000000); + aspeed_test_sha256_accum("-machine ast2700-evb", 0x12070000, 0x400000000); } static void test_sha384_accum_ast2700(void) { - aspeed_test_sha384_accum("-machine ast2700a1-evb", 0x12070000, 0x400000000); + aspeed_test_sha384_accum("-machine ast2700-evb", 0x12070000, 0x400000000); } static void test_sha512_accum_ast2700(void) { - aspeed_test_sha512_accum("-machine ast2700a1-evb", 0x12070000, 0x400000000); + aspeed_test_sha512_accum("-machine ast2700-evb", 0x12070000, 0x400000000); } static void test_addresses_ast2700(void) { - aspeed_test_addresses("-machine ast2700a1-evb", 0x12070000, &as2700_masks); + aspeed_test_addresses("-machine ast2700-evb", 0x12070000, &as2700_masks); } int main(int argc, char **argv) -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> Adding additional test cases to test_aspeed_ast2700.py makes the test suite significantly larger and increases the overall test runtime. To keep testing efficient and better scoped, rename the existing test to test_aspeed_ast2700a1.py and dedicate it to AST2700 A1 specific tests. A new test_aspeed_ast2700.py will be introduced later to always cover the latest revision of the AST2700 SoC. No functional change. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260211021527.119674-8-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- tests/functional/aarch64/meson.build | 4 ++-- .../{test_aspeed_ast2700.py => test_aspeed_ast2700a1.py} | 0 2 files changed, 2 insertions(+), 2 deletions(-) rename tests/functional/aarch64/{test_aspeed_ast2700.py => test_aspeed_ast2700a1.py} (100%) diff --git a/tests/functional/aarch64/meson.build b/tests/functional/aarch64/meson.build index XXXXXXX..XXXXXXX 100644 --- a/tests/functional/aarch64/meson.build +++ b/tests/functional/aarch64/meson.build @@ -XXX,XX +XXX,XX @@ # SPDX-License-Identifier: GPL-2.0-or-later test_aarch64_timeouts = { - 'aspeed_ast2700' : 600, + 'aspeed_ast2700a1' : 600, 'aspeed_ast2700fc' : 600, 'device_passthrough' : 720, 'imx8mp_evk' : 240, @@ -XXX,XX +XXX,XX @@ tests_aarch64_system_quick = [ ] tests_aarch64_system_thorough = [ - 'aspeed_ast2700', + 'aspeed_ast2700a1', 'aspeed_ast2700fc', 'device_passthrough', 'hotplug_pci', diff --git a/tests/functional/aarch64/test_aspeed_ast2700.py b/tests/functional/aarch64/test_aspeed_ast2700a1.py similarity index 100% rename from tests/functional/aarch64/test_aspeed_ast2700.py rename to tests/functional/aarch64/test_aspeed_ast2700a1.py -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> Add functional coverage for the AST2700 A2 EVB machine by introducing test cases that boot and validate an OpenBMC SDK v11.00 image on "ast2700a2-evb". Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260211021527.119674-9-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- tests/functional/aarch64/meson.build | 2 + .../aarch64/test_aspeed_ast2700a2.py | 190 ++++++++++++++++++ 2 files changed, 192 insertions(+) create mode 100755 tests/functional/aarch64/test_aspeed_ast2700a2.py diff --git a/tests/functional/aarch64/meson.build b/tests/functional/aarch64/meson.build index XXXXXXX..XXXXXXX 100644 --- a/tests/functional/aarch64/meson.build +++ b/tests/functional/aarch64/meson.build @@ -XXX,XX +XXX,XX @@ test_aarch64_timeouts = { 'aspeed_ast2700a1' : 600, + 'aspeed_ast2700a2' : 600, 'aspeed_ast2700fc' : 600, 'device_passthrough' : 720, 'imx8mp_evk' : 240, @@ -XXX,XX +XXX,XX @@ tests_aarch64_system_quick = [ tests_aarch64_system_thorough = [ 'aspeed_ast2700a1', + 'aspeed_ast2700a2', 'aspeed_ast2700fc', 'device_passthrough', 'hotplug_pci', diff --git a/tests/functional/aarch64/test_aspeed_ast2700a2.py b/tests/functional/aarch64/test_aspeed_ast2700a2.py new file mode 100755 index XXXXXXX..XXXXXXX --- /dev/null +++ b/tests/functional/aarch64/test_aspeed_ast2700a2.py @@ -XXX,XX +XXX,XX @@ +#!/usr/bin/env python3 +# +# Functional test that boots the ASPEED SoCs with firmware +# +# Copyright (C) 2022 ASPEED Technology Inc +# +# SPDX-License-Identifier: GPL-2.0-or-later + +import os + +from qemu_test import QemuSystemTest, Asset +from qemu_test import wait_for_console_pattern, exec_command +from qemu_test import exec_command_and_wait_for_pattern + + +class AST2x00MachineSDK(QemuSystemTest): + + def do_test_aarch64_aspeed_sdk_start(self, image, bus_id): + bus_str = str(bus_id) + self.require_netdev('user') + self.vm.set_console() + self.vm.add_args( + '-device', + f'tmp105,' + f'bus=aspeed.i2c.bus.{bus_str},' + f'address=0x4d,' + f'id=tmp-test-{bus_str}' + ) + self.vm.add_args('-drive', 'file=' + image + ',if=mtd,format=raw', + '-net', 'nic', '-net', 'user', '-snapshot') + + self.vm.launch() + + def verify_vbootrom_firmware_flow(self): + wait_for_console_pattern(self, 'Found valid caliptra flash image') + wait_for_console_pattern(self, 'Check flash image checksum') + wait_for_console_pattern(self, 'pass') + wait_for_console_pattern(self, 'Read abb header') + wait_for_console_pattern(self, 'pass') + wait_for_console_pattern(self, 'Read soc manifest') + wait_for_console_pattern(self, 'pass') + wait_for_console_pattern(self, 'Load atf image') + wait_for_console_pattern(self, 'pass') + wait_for_console_pattern(self, 'Load optee image') + wait_for_console_pattern(self, 'pass') + wait_for_console_pattern(self, 'Load uboot image') + wait_for_console_pattern(self, 'pass') + wait_for_console_pattern(self, 'Load ssp image') + wait_for_console_pattern(self, 'pass') + wait_for_console_pattern(self, 'Load tsp image') + wait_for_console_pattern(self, 'pass') + wait_for_console_pattern(self, 'Jumping to BL31 (Trusted Firmware-A)') + + def enable_ast2700_pcie2(self): + wait_for_console_pattern(self, 'Hit any key to stop autoboot') + exec_command_and_wait_for_pattern(self, '\012', '=>') + exec_command_and_wait_for_pattern(self, + 'cp 100420000 403000000 900000', '=>') + exec_command_and_wait_for_pattern(self, + 'bootm start 403000000', '=>') + exec_command_and_wait_for_pattern(self, 'bootm loados', '=>') + exec_command_and_wait_for_pattern(self, 'bootm ramdisk', '=>') + exec_command_and_wait_for_pattern(self, 'bootm prep', '=>') + exec_command_and_wait_for_pattern(self, + 'fdt set /soc@14000000/pcie@140d0000 status "okay"', '=>') + exec_command(self, 'bootm go') + + def verify_openbmc_boot_start(self, enable_pcie=True): + wait_for_console_pattern(self, 'U-Boot 2023.10') + if enable_pcie: + self.enable_ast2700_pcie2() + wait_for_console_pattern(self, 'Linux version ') + + def verify_openbmc_boot_and_login(self, name, enable_pcie=True): + self.verify_openbmc_boot_start(enable_pcie) + + wait_for_console_pattern(self, f'{name} login:') + exec_command_and_wait_for_pattern(self, 'root', 'Password:') + exec_command_and_wait_for_pattern(self, '0penBmc', f'root@{name}:~#') + + ASSET_SDK_V1100_AST2700A2 = Asset( + 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.00/ast2700-default-obmc.tar.gz', + 'e2b8f043fe8063dd3b6ded93422e38bd41914dc9c3202199507652df024de4dc') + + ASSET_SDK_V1100_AST2700A2_DCSCM = Asset( + 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.00/ast2700-dcscm-obmc.tar.gz', + '0e93f7976139da71fab9df7952a58bdd80650e23e7abf5853b0eb6695deb02d0') + + def do_ast2700_i2c_test(self, bus_id): + bus_str = str(bus_id) + exec_command_and_wait_for_pattern(self, + 'echo lm75 0x4d > ' + f'/sys/class/i2c-dev/i2c-{bus_str}/device/new_device ', + f'i2c i2c-{bus_str}: new_device: Instantiated device lm75 at 0x4d') + exec_command_and_wait_for_pattern(self, + f'cat /sys/bus/i2c/devices/{bus_str}-004d/hwmon/hwmon*/temp1_input', + '0') + self.vm.cmd('qom-set', path=f'/machine/peripheral/tmp-test-{bus_str}', + property='temperature', value=18000) + exec_command_and_wait_for_pattern(self, + f'cat /sys/bus/i2c/devices/{bus_str}-004d/hwmon/hwmon*/temp1_input', + '18000') + + def do_ast2700_pcie_test(self): + exec_command_and_wait_for_pattern(self, + 'lspci -s 0002:00:00.0', + '0002:00:00.0 PCI bridge: ' + 'ASPEED Technology, Inc. AST1150 PCI-to-PCI Bridge') + exec_command_and_wait_for_pattern(self, + 'lspci -s 0002:01:00.0', + '0002:01:00.0 Ethernet controller: ' + 'Intel Corporation 82574L Gigabit Network Connection') + exec_command_and_wait_for_pattern(self, + 'ip addr show dev eth2', + 'inet 10.0.2.15/24') + + def start_ast2700_test(self, name, bus_id): + num_cpu = 4 + load_images_list = [ + { + 'addr': '0x400000000', + 'file': self.scratch_file(name, 'u-boot.bin') + }, + { + 'addr': '0x430000000', + 'file': self.scratch_file(name, 'bl31.bin') + }, + { + 'addr': '0x430080000', + 'file': self.scratch_file(name, 'optee', 'tee-raw.bin') + } + ] + + for load_image in load_images_list: + addr = load_image['addr'] + file = load_image['file'] + self.vm.add_args('-device', + f'loader,force-raw=on,addr={addr},file={file}') + + for i in range(num_cpu): + self.vm.add_args('-device', + f'loader,addr=0x430000000,cpu-num={i}') + + self.vm.add_args('-smp', str(num_cpu)) + self.do_test_aarch64_aspeed_sdk_start( + self.scratch_file(name, 'image-bmc'), bus_id) + + def start_ast2700_test_vbootrom(self, name, bus_id): + self.vm.add_args('-bios', 'ast27x0_bootrom.bin') + self.do_test_aarch64_aspeed_sdk_start( + self.scratch_file(name, 'image-bmc'), bus_id) + + def test_aarch64_ast2700a2_evb_sdk_v11_00(self): + self.set_machine('ast2700a2-evb') + self.require_netdev('user') + + self.archive_extract(self.ASSET_SDK_V1100_AST2700A2) + self.vm.add_args('-device', 'e1000e,netdev=net1,bus=pcie.2') + self.vm.add_args('-netdev', 'user,id=net1') + self.start_ast2700_test('ast2700-default', 1) + self.verify_openbmc_boot_and_login('ast2700-default') + self.do_ast2700_i2c_test(1) + self.do_ast2700_pcie_test() + + def test_aarch64_ast2700a2_evb_sdk_vbootrom_v11_00(self): + self.set_machine('ast2700a2-evb') + self.require_netdev('user') + + self.archive_extract(self.ASSET_SDK_V1100_AST2700A2) + self.vm.add_args('-device', 'e1000e,netdev=net1,bus=pcie.2') + self.vm.add_args('-netdev', 'user,id=net1') + self.start_ast2700_test_vbootrom('ast2700-default', 1) + self.verify_vbootrom_firmware_flow() + self.verify_openbmc_boot_start() + + def test_aarch64_ast2700a2_evb_ioexp_v11_00(self): + self.set_machine('ast2700a2-evb') + self.require_netdev('user') + + self.archive_extract(self.ASSET_SDK_V1100_AST2700A2_DCSCM) + self.vm.set_machine('ast2700a2-evb,fmc-model=w25q512jv') + self.vm.add_args('-device', + 'tmp105,bus=ioexp0.0,address=0x4d,id=tmp-test-16') + self.start_ast2700_test('ast2700-dcscm', 8) + self.verify_openbmc_boot_and_login('ast2700-dcscm', False) + self.do_ast2700_i2c_test(8) + self.do_ast2700_i2c_test(16) + +if __name__ == '__main__': + QemuSystemTest.main() -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> Update the AST2700 FC machine to use the AST2700 A2 SoC model instead of the A1-specific variant. This change removes A1-specific naming and definitions from the FC machine and aligns it with the newer AST2700 A2 silicon. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260211021527.119674-10-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- hw/arm/aspeed_ast27x0-fc.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/aspeed_ast27x0-fc.c +++ b/hw/arm/aspeed_ast27x0-fc.c @@ -XXX,XX +XXX,XX @@ #include "hw/arm/aspeed_coprocessor.h" #include "hw/arm/machines-qom.h" -#define TYPE_AST2700A1FC MACHINE_TYPE_NAME("ast2700fc") -OBJECT_DECLARE_SIMPLE_TYPE(Ast2700FCState, AST2700A1FC); +#define TYPE_AST2700FC MACHINE_TYPE_NAME("ast2700fc") +OBJECT_DECLARE_SIMPLE_TYPE(Ast2700FCState, AST2700FC); static struct arm_boot_info ast2700fc_board_info = { .board_id = -1, /* device-tree-only board */ @@ -XXX,XX +XXX,XX @@ struct Ast2700FCState { }; #define AST2700FC_BMC_RAM_SIZE (1 * GiB) -#define AST2700FC_CM4_DRAM_SIZE (32 * MiB) #define AST2700FC_HW_STRAP1 0x000000C0 #define AST2700FC_HW_STRAP2 0x00000003 @@ -XXX,XX +XXX,XX @@ struct Ast2700FCState { static bool ast2700fc_ca35_init(MachineState *machine, Error **errp) { - Ast2700FCState *s = AST2700A1FC(machine); + Ast2700FCState *s = AST2700FC(machine); AspeedSoCState *soc; AspeedSoCClass *sc; const char *bios_name = NULL; @@ -XXX,XX +XXX,XX @@ static bool ast2700fc_ca35_init(MachineState *machine, Error **errp) DeviceState *dev = NULL; uint64_t rom_size; - object_initialize_child(OBJECT(s), "ca35", &s->ca35, "ast2700-a1"); + object_initialize_child(OBJECT(s), "ca35", &s->ca35, "ast2700-a2"); soc = ASPEED_SOC(&s->ca35); sc = ASPEED_SOC_GET_CLASS(soc); @@ -XXX,XX +XXX,XX @@ static bool ast2700fc_ca35_init(MachineState *machine, Error **errp) static bool ast2700fc_ssp_init(MachineState *machine, Error **errp) { - Ast2700FCState *s = AST2700A1FC(machine); + Ast2700FCState *s = AST2700FC(machine); AspeedSoCState *psp = ASPEED_SOC(&s->ca35); s->ssp_sysclk = clock_new(OBJECT(s), "SSP_SYSCLK"); @@ -XXX,XX +XXX,XX @@ static bool ast2700fc_ssp_init(MachineState *machine, Error **errp) static bool ast2700fc_tsp_init(MachineState *machine, Error **errp) { - Ast2700FCState *s = AST2700A1FC(machine); + Ast2700FCState *s = AST2700FC(machine); AspeedSoCState *psp = ASPEED_SOC(&s->ca35); s->tsp_sysclk = clock_new(OBJECT(s), "TSP_SYSCLK"); -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> The AST2700 A1 EVB is equipped with 1GB of DRAM, while the AST2700 A2 EVB increases the DRAM size to 2GB. The ast2700fc machine is updated to support the AST2700 A2. Increase the BMC DRAM size to 2GB to match the hardware configuration of AST2700 A2. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260211021527.119674-11-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- hw/arm/aspeed_ast27x0-fc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/aspeed_ast27x0-fc.c +++ b/hw/arm/aspeed_ast27x0-fc.c @@ -XXX,XX +XXX,XX @@ struct Ast2700FCState { Aspeed27x0CoprocessorState tsp; }; -#define AST2700FC_BMC_RAM_SIZE (1 * GiB) +#define AST2700FC_BMC_RAM_SIZE (2 * GiB) #define AST2700FC_HW_STRAP1 0x000000C0 #define AST2700FC_HW_STRAP2 0x00000003 -- 2.53.0 From: Jamin Lin <jamin_lin@aspeedtech.com> Update AST2700 FC functional tests to use the AST2700 A2 SDK v11.00 image. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20260211021527.119674-12-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com> --- .../functional/aarch64/test_aspeed_ast2700fc.py | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/tests/functional/aarch64/test_aspeed_ast2700fc.py b/tests/functional/aarch64/test_aspeed_ast2700fc.py index XXXXXXX..XXXXXXX 100755 --- a/tests/functional/aarch64/test_aspeed_ast2700fc.py +++ b/tests/functional/aarch64/test_aspeed_ast2700fc.py @@ -XXX,XX +XXX,XX @@ def load_ast2700fc_coprocessor(self, name): f'loader,file={file},cpu-num={cpu_num}') ASSET_SDK_V1100_AST2700 = Asset( - 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.00/ast2700-a1-obmc.tar.gz', - 'd5ceed511cd0dfefbb102fff2d731159e0472948a28066dc0d90bcd54be76525') + 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v11.00/ast2700-default-obmc.tar.gz', + 'e2b8f043fe8063dd3b6ded93422e38bd41914dc9c3202199507652df024de4dc') def do_ast2700_i2c_test(self): exec_command_and_wait_for_pattern(self, @@ -XXX,XX +XXX,XX @@ def do_ast2700fc_ssp_test(self): exec_command_and_wait_for_pattern(self, 'version', 'Zephyr version 3.7.1') exec_command_and_wait_for_pattern(self, 'md 72c02000 1', - '[72c02000] 06010103') + '[72c02000] 06020103') def do_ast2700fc_tsp_test(self): self.vm.shutdown() @@ -XXX,XX +XXX,XX @@ def do_ast2700fc_tsp_test(self): exec_command_and_wait_for_pattern(self, 'version', 'Zephyr version 3.7.1') exec_command_and_wait_for_pattern(self, 'md 72c02000 1', - '[72c02000] 06010103') + '[72c02000] 06020103') def start_ast2700fc_test(self, name): ca35_core = 4 @@ -XXX,XX +XXX,XX @@ def test_aarch64_ast2700fc_sdk_v11_00(self): self.require_netdev('user') self.archive_extract(self.ASSET_SDK_V1100_AST2700) - self.start_ast2700fc_test('ast2700-a1') - self.verify_openbmc_boot_and_login('ast2700-a1') + self.start_ast2700fc_test('ast2700-default') + self.verify_openbmc_boot_and_login('ast2700-default') self.do_ast2700_i2c_test() self.do_ast2700_pcie_test() self.do_ast2700fc_ssp_test() @@ -XXX,XX +XXX,XX @@ def test_aarch64_ast2700fc_sdk_vbootrom_v11_00(self): self.set_machine('ast2700fc') self.archive_extract(self.ASSET_SDK_V1100_AST2700) - self.start_ast2700fc_test_vbootrom('ast2700-a1') - self.verify_openbmc_boot_and_login('ast2700-a1') + self.start_ast2700fc_test_vbootrom('ast2700-default') + self.verify_openbmc_boot_and_login('ast2700-default') self.do_ast2700fc_ssp_test() self.do_ast2700fc_tsp_test() -- 2.53.0