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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1751546266; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NIVmB9T7X9elVC/gEk8odcOfXiEnBnk9LzN+nIeRoJE=; b=K+DJp8tBjbjE/Z5POh5LUzYMf4gqxHncusNx9hGOlRtKdqWNS8RGUykeK0Uzv6KUjqKtqB mjX2BeUuUA/glHs+Tf6sCOB4T050+cJaRMDbwWalVCj+/fAmEfc5fFCn751HiJRLwcf8iH HDiGKzdCDUDCRMydKnnWaZcfRyWHuxQ= X-MC-Unique: D2W67tqeO06fwnpwi8BK0A-1 X-Mimecast-MFC-AGG-ID: D2W67tqeO06fwnpwi8BK0A_1751546262 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, imammedo@redhat.com, Jonathan.Cameron@huawei.com, gustavo.romero@linaro.org, anisinha@redhat.com, mst@redhat.com, shannon.zhaosl@gmail.com Cc: pbonzini@redhat.com, philmd@linaro.org, alex.bennee@linaro.org Subject: [PATCH v5 01/36] hw/i386/acpi-build: Make aml_pci_device_dsm() static Date: Thu, 3 Jul 2025 14:35:01 +0200 Message-ID: <20250703123728.414386-2-eric.auger@redhat.com> In-Reply-To: <20250703123728.414386-1-eric.auger@redhat.com> References: <20250703123728.414386-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 15 X-Spam_score: 1.5 X-Spam_bar: + X-Spam_report: (1.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_SBL_CSS=3.335, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.237, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1751547198877116600 No need to export aml_pci_device_dsm() as it is only used in hw/i386/acpi-build.c. Signed-off-by: Eric Auger Reviewed-by: Gustavo Romero Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Igor Mammedov Reviewed-by: Jonathan Cameron --- include/hw/acpi/pci.h | 1 - hw/i386/acpi-build.c | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/include/hw/acpi/pci.h b/include/hw/acpi/pci.h index 6359d574fd..ab0187a894 100644 --- a/include/hw/acpi/pci.h +++ b/include/hw/acpi/pci.h @@ -36,7 +36,6 @@ typedef struct AcpiMcfgInfo { =20 void build_mcfg(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *info, const char *oem_id, const char *oem_table_id); -Aml *aml_pci_device_dsm(void); =20 void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus); void build_pci_bridge_aml(AcpiDevAmlIf *adev, Aml *scope); diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 61851cc840..f59026524f 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -338,7 +338,7 @@ build_facs(GArray *table_data) g_array_append_vals(table_data, reserved, 40); /* Reserved */ } =20 -Aml *aml_pci_device_dsm(void) +static Aml *aml_pci_device_dsm(void) { Aml *method; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1751546272; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=X76P9T7rfToMdRO+4/neesROUS3j61xqlfm9Z1lq87E=; b=H2LeJz3VXH5g7PZQOfLGWzeA9g02J77XB1AuUl2KwBTMlcHqUzAOmFUmbjOdcHGMYRdwVm LL7x7MSifkyvtxRJZNIkrpNRJF8MBMGFR9IpzalE5kUs7i0sNZBBL+dOivXTjFDtMJ88NE IEsVF9Nbp0driqMxwBFCecS6XL7Vtj8= X-MC-Unique: G_PzuRr5Ma-ZSYhR0sDaxg-1 X-Mimecast-MFC-AGG-ID: G_PzuRr5Ma-ZSYhR0sDaxg_1751546267 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, imammedo@redhat.com, Jonathan.Cameron@huawei.com, gustavo.romero@linaro.org, anisinha@redhat.com, mst@redhat.com, shannon.zhaosl@gmail.com Cc: pbonzini@redhat.com, philmd@linaro.org, alex.bennee@linaro.org Subject: [PATCH v5 02/36] hw/acpi: Rename and move build_x86_acpi_pci_hotplug to pcihp Date: Thu, 3 Jul 2025 14:35:02 +0200 Message-ID: <20250703123728.414386-3-eric.auger@redhat.com> In-Reply-To: <20250703123728.414386-1-eric.auger@redhat.com> References: <20250703123728.414386-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" We plan to reuse build_x86_acpi_pci_hotplug() implementation for ARM so let's move the code to generic pcihp. Associated static aml_pci_pdsm() helper is also moved along. build_x86_acpi_pci_hotplug is renamed into build_acpi_pci_hotplug(). No code change intended. Also fix the reference to acpi_pci_hotplug.rst documentation Signed-off-by: Eric Auger Reviewed-by: Gustavo Romero Reviewed-by: Igor Mammedov Reviewed-by: Jonathan Cameron --- v1 -> v2: - s/spec/specs in reference to rst (Gustavo) - fixed double space in commit msg (Gustavo) rfc -> v1: - make build_append_pci_dsm_func0_common non static and move it to pcihp --- hw/i386/acpi-build.h | 4 - include/hw/acpi/pcihp.h | 7 ++ hw/acpi/pcihp.c | 174 ++++++++++++++++++++++++++++++++++++++- hw/i386/acpi-build.c | 176 +--------------------------------------- 4 files changed, 182 insertions(+), 179 deletions(-) diff --git a/hw/i386/acpi-build.h b/hw/i386/acpi-build.h index 275ec058a1..8ba3c33e48 100644 --- a/hw/i386/acpi-build.h +++ b/hw/i386/acpi-build.h @@ -5,10 +5,6 @@ =20 extern const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio; =20 -/* PCI Hot-plug registers' base. See docs/specs/acpi_pci_hotplug.rst */ -#define ACPI_PCIHP_SEJ_BASE 0x8 -#define ACPI_PCIHP_BNMR_BASE 0x10 - void acpi_setup(void); Object *acpi_get_i386_pci_host(void); =20 diff --git a/include/hw/acpi/pcihp.h b/include/hw/acpi/pcihp.h index cdc0cb8e43..971451e8ea 100644 --- a/include/hw/acpi/pcihp.h +++ b/include/hw/acpi/pcihp.h @@ -33,6 +33,10 @@ #define ACPI_PCIHP_IO_BASE_PROP "acpi-pcihp-io-base" #define ACPI_PCIHP_IO_LEN_PROP "acpi-pcihp-io-len" =20 +/* PCI Hot-plug registers bases. See docs/specs/acpi_pci_hotplug.rst */ +#define ACPI_PCIHP_SEJ_BASE 0x8 +#define ACPI_PCIHP_BNMR_BASE 0x10 + typedef struct AcpiPciHpPciStatus { uint32_t up; uint32_t down; @@ -69,6 +73,9 @@ void acpi_pcihp_device_unplug_request_cb(HotplugHandler *= hotplug_dev, AcpiPciHpState *s, DeviceState *d= ev, Error **errp); =20 +void build_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr); +void build_append_pci_dsm_func0_common(Aml *ctx, Aml *retvar); + /* Called on reset */ void acpi_pcihp_reset(AcpiPciHpState *s); =20 diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c index 497281ae20..cbe7e01385 100644 --- a/hw/acpi/pcihp.c +++ b/hw/acpi/pcihp.c @@ -26,7 +26,7 @@ =20 #include "qemu/osdep.h" #include "hw/acpi/pcihp.h" - +#include "hw/acpi/aml-build.h" #include "hw/pci-host/i440fx.h" #include "hw/pci/pci.h" #include "hw/pci/pci_bridge.h" @@ -513,6 +513,178 @@ void acpi_pcihp_init(Object *owner, AcpiPciHpState *s= , PCIBus *root_bus, OBJ_PROP_FLAG_READ); } =20 +void build_append_pci_dsm_func0_common(Aml *ctx, Aml *retvar) +{ + Aml *UUID, *ifctx1; + uint8_t byte_list[1] =3D { 0 }; /* nothing supported yet */ + + aml_append(ctx, aml_store(aml_buffer(1, byte_list), retvar)); + /* + * PCI Firmware Specification 3.1 + * 4.6. _DSM Definitions for PCI + */ + UUID =3D aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); + ifctx1 =3D aml_if(aml_lnot(aml_equal(aml_arg(0), UUID))); + { + /* call is for unsupported UUID, bail out */ + aml_append(ifctx1, aml_return(retvar)); + } + aml_append(ctx, ifctx1); + + ifctx1 =3D aml_if(aml_lless(aml_arg(1), aml_int(2))); + { + /* call is for unsupported REV, bail out */ + aml_append(ifctx1, aml_return(retvar)); + } + aml_append(ctx, ifctx1); +} + +static Aml *aml_pci_pdsm(void) +{ + Aml *method, *ifctx, *ifctx1; + Aml *ret =3D aml_local(0); + Aml *caps =3D aml_local(1); + Aml *acpi_index =3D aml_local(2); + Aml *zero =3D aml_int(0); + Aml *one =3D aml_int(1); + Aml *not_supp =3D aml_int(0xFFFFFFFF); + Aml *func =3D aml_arg(2); + Aml *params =3D aml_arg(4); + Aml *bnum =3D aml_derefof(aml_index(params, aml_int(0))); + Aml *sunum =3D aml_derefof(aml_index(params, aml_int(1))); + + method =3D aml_method("PDSM", 5, AML_SERIALIZED); + + /* get supported functions */ + ifctx =3D aml_if(aml_equal(func, zero)); + { + build_append_pci_dsm_func0_common(ifctx, ret); + + aml_append(ifctx, aml_store(zero, caps)); + aml_append(ifctx, + aml_store(aml_call2("AIDX", bnum, sunum), acpi_index)); + /* + * advertise function 7 if device has acpi-index + * acpi_index values: + * 0: not present (default value) + * FFFFFFFF: not supported (old QEMU without PIDX reg) + * other: device's acpi-index + */ + ifctx1 =3D aml_if(aml_lnot( + aml_or(aml_equal(acpi_index, zero), + aml_equal(acpi_index, not_supp), NULL) + )); + { + /* have supported functions */ + aml_append(ifctx1, aml_or(caps, one, caps)); + /* support for function 7 */ + aml_append(ifctx1, + aml_or(caps, aml_shiftleft(one, aml_int(7)), caps)); + } + aml_append(ifctx, ifctx1); + + aml_append(ifctx, aml_store(caps, aml_index(ret, zero))); + aml_append(ifctx, aml_return(ret)); + } + aml_append(method, ifctx); + + /* handle specific functions requests */ + /* + * PCI Firmware Specification 3.1 + * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under + * Operating Systems + */ + ifctx =3D aml_if(aml_equal(func, aml_int(7))); + { + Aml *pkg =3D aml_package(2); + + aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sunum), acpi_in= dex)); + aml_append(ifctx, aml_store(pkg, ret)); + /* + * Windows calls func=3D7 without checking if it's available, + * as workaround Microsoft has suggested to return invalid for func7 + * Package, so return 2 elements package but only initialize elemen= ts + * when acpi_index is supported and leave them uninitialized, which + * leads elements to being Uninitialized ObjectType and should trip + * Windows into discarding result as an unexpected and prevent sett= ing + * bogus 'PCI Label' on the device. + */ + ifctx1 =3D aml_if(aml_lnot(aml_lor( + aml_equal(acpi_index, zero), aml_equal(acpi_index, not= _supp) + ))); + { + aml_append(ifctx1, aml_store(acpi_index, aml_index(ret, zero))); + /* + * optional, if not impl. should return null string + */ + aml_append(ifctx1, aml_store(aml_string("%s", ""), + aml_index(ret, one))); + } + aml_append(ifctx, ifctx1); + + aml_append(ifctx, aml_return(ret)); + } + + aml_append(method, ifctx); + return method; +} + +void build_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr) +{ + Aml *scope; + Aml *field; + Aml *method; + + scope =3D aml_scope("_SB.PCI0"); + + aml_append(scope, + aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0= x08)); + field =3D aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZE= ROS); + aml_append(field, aml_named_field("PCIU", 32)); + aml_append(field, aml_named_field("PCID", 32)); + aml_append(scope, field); + + aml_append(scope, + aml_operation_region("SEJ", AML_SYSTEM_IO, + aml_int(pcihp_addr + ACPI_PCIHP_SEJ_BASE), 0x= 04)); + field =3D aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZER= OS); + aml_append(field, aml_named_field("B0EJ", 32)); + aml_append(scope, field); + + aml_append(scope, + aml_operation_region("BNMR", AML_SYSTEM_IO, + aml_int(pcihp_addr + ACPI_PCIHP_BNMR_BASE), 0= x08)); + field =3D aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZE= ROS); + aml_append(field, aml_named_field("BNUM", 32)); + aml_append(field, aml_named_field("PIDX", 32)); + aml_append(scope, field); + + aml_append(scope, aml_mutex("BLCK", 0)); + + method =3D aml_method("PCEJ", 2, AML_NOTSERIALIZED); + aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); + aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); + aml_append(method, + aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))= ); + aml_append(method, aml_release(aml_name("BLCK"))); + aml_append(method, aml_return(aml_int(0))); + aml_append(scope, method); + + method =3D aml_method("AIDX", 2, AML_NOTSERIALIZED); + aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); + aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); + aml_append(method, + aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("PIDX"))= ); + aml_append(method, aml_store(aml_name("PIDX"), aml_local(0))); + aml_append(method, aml_release(aml_name("BLCK"))); + aml_append(method, aml_return(aml_local(0))); + aml_append(scope, method); + + aml_append(scope, aml_pci_pdsm()); + + aml_append(table, scope); +} + const VMStateDescription vmstate_acpi_pcihp_pci_status =3D { .name =3D "acpi_pcihp_pci_status", .version_id =3D 1, diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index f59026524f..4f8572eebe 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -361,32 +361,6 @@ static Aml *aml_pci_device_dsm(void) return method; } =20 -static void build_append_pci_dsm_func0_common(Aml *ctx, Aml *retvar) -{ - Aml *UUID, *ifctx1; - uint8_t byte_list[1] =3D { 0 }; /* nothing supported yet */ - - aml_append(ctx, aml_store(aml_buffer(1, byte_list), retvar)); - /* - * PCI Firmware Specification 3.1 - * 4.6. _DSM Definitions for PCI - */ - UUID =3D aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); - ifctx1 =3D aml_if(aml_lnot(aml_equal(aml_arg(0), UUID))); - { - /* call is for unsupported UUID, bail out */ - aml_append(ifctx1, aml_return(retvar)); - } - aml_append(ctx, ifctx1); - - ifctx1 =3D aml_if(aml_lless(aml_arg(1), aml_int(2))); - { - /* call is for unsupported REV, bail out */ - aml_append(ifctx1, aml_return(retvar)); - } - aml_append(ctx, ifctx1); -} - static Aml *aml_pci_edsm(void) { Aml *method, *ifctx; @@ -647,96 +621,6 @@ static bool build_append_notification_callback(Aml *pa= rent_scope, return !!nr_notifiers; } =20 -static Aml *aml_pci_pdsm(void) -{ - Aml *method, *ifctx, *ifctx1; - Aml *ret =3D aml_local(0); - Aml *caps =3D aml_local(1); - Aml *acpi_index =3D aml_local(2); - Aml *zero =3D aml_int(0); - Aml *one =3D aml_int(1); - Aml *not_supp =3D aml_int(0xFFFFFFFF); - Aml *func =3D aml_arg(2); - Aml *params =3D aml_arg(4); - Aml *bnum =3D aml_derefof(aml_index(params, aml_int(0))); - Aml *sunum =3D aml_derefof(aml_index(params, aml_int(1))); - - method =3D aml_method("PDSM", 5, AML_SERIALIZED); - - /* get supported functions */ - ifctx =3D aml_if(aml_equal(func, zero)); - { - build_append_pci_dsm_func0_common(ifctx, ret); - - aml_append(ifctx, aml_store(zero, caps)); - aml_append(ifctx, - aml_store(aml_call2("AIDX", bnum, sunum), acpi_index)); - /* - * advertise function 7 if device has acpi-index - * acpi_index values: - * 0: not present (default value) - * FFFFFFFF: not supported (old QEMU without PIDX reg) - * other: device's acpi-index - */ - ifctx1 =3D aml_if(aml_lnot( - aml_or(aml_equal(acpi_index, zero), - aml_equal(acpi_index, not_supp), NULL) - )); - { - /* have supported functions */ - aml_append(ifctx1, aml_or(caps, one, caps)); - /* support for function 7 */ - aml_append(ifctx1, - aml_or(caps, aml_shiftleft(one, aml_int(7)), caps)); - } - aml_append(ifctx, ifctx1); - - aml_append(ifctx, aml_store(caps, aml_index(ret, zero))); - aml_append(ifctx, aml_return(ret)); - } - aml_append(method, ifctx); - - /* handle specific functions requests */ - /* - * PCI Firmware Specification 3.1 - * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under - * Operating Systems - */ - ifctx =3D aml_if(aml_equal(func, aml_int(7))); - { - Aml *pkg =3D aml_package(2); - - aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sunum), acpi_in= dex)); - aml_append(ifctx, aml_store(pkg, ret)); - /* - * Windows calls func=3D7 without checking if it's available, - * as workaround Microsoft has suggested to return invalid for func7 - * Package, so return 2 elements package but only initialize elemen= ts - * when acpi_index is supported and leave them uninitialized, which - * leads elements to being Uninitialized ObjectType and should trip - * Windows into discarding result as an unexpected and prevent sett= ing - * bogus 'PCI Label' on the device. - */ - ifctx1 =3D aml_if(aml_lnot(aml_lor( - aml_equal(acpi_index, zero), aml_equal(acpi_index, not= _supp) - ))); - { - aml_append(ifctx1, aml_store(acpi_index, aml_index(ret, zero))); - /* - * optional, if not impl. should return null string - */ - aml_append(ifctx1, aml_store(aml_string("%s", ""), - aml_index(ret, one))); - } - aml_append(ifctx, ifctx1); - - aml_append(ifctx, aml_return(ret)); - } - - aml_append(method, ifctx); - return method; -} - /* * build_prt - Define interrupt routing rules * @@ -1227,62 +1111,6 @@ static Aml *build_q35_dram_controller(const AcpiMcfg= Info *mcfg) return dev; } =20 -static void build_x86_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr) -{ - Aml *scope; - Aml *field; - Aml *method; - - scope =3D aml_scope("_SB.PCI0"); - - aml_append(scope, - aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0= x08)); - field =3D aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZE= ROS); - aml_append(field, aml_named_field("PCIU", 32)); - aml_append(field, aml_named_field("PCID", 32)); - aml_append(scope, field); - - aml_append(scope, - aml_operation_region("SEJ", AML_SYSTEM_IO, - aml_int(pcihp_addr + ACPI_PCIHP_SEJ_BASE), 0x= 04)); - field =3D aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZER= OS); - aml_append(field, aml_named_field("B0EJ", 32)); - aml_append(scope, field); - - aml_append(scope, - aml_operation_region("BNMR", AML_SYSTEM_IO, - aml_int(pcihp_addr + ACPI_PCIHP_BNMR_BASE), 0= x08)); - field =3D aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZE= ROS); - aml_append(field, aml_named_field("BNUM", 32)); - aml_append(field, aml_named_field("PIDX", 32)); - aml_append(scope, field); - - aml_append(scope, aml_mutex("BLCK", 0)); - - method =3D aml_method("PCEJ", 2, AML_NOTSERIALIZED); - aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); - aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); - aml_append(method, - aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ"))= ); - aml_append(method, aml_release(aml_name("BLCK"))); - aml_append(method, aml_return(aml_int(0))); - aml_append(scope, method); - - method =3D aml_method("AIDX", 2, AML_NOTSERIALIZED); - aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF)); - aml_append(method, aml_store(aml_arg(0), aml_name("BNUM"))); - aml_append(method, - aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("PIDX"))= ); - aml_append(method, aml_store(aml_name("PIDX"), aml_local(0))); - aml_append(method, aml_release(aml_name("BLCK"))); - aml_append(method, aml_return(aml_local(0))); - aml_append(scope, method); - - aml_append(scope, aml_pci_pdsm()); - - aml_append(table, scope); -} - static Aml *build_q35_osc_method(bool enable_native_pcie_hotplug) { Aml *if_ctx; @@ -1394,7 +1222,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, aml_append(dsdt, sb_scope); =20 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { - build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); + build_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); } build_piix4_pci0_int(dsdt); } else if (q35) { @@ -1438,7 +1266,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, aml_append(dsdt, sb_scope); =20 if (pm->pcihp_bridge_en) { - build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); + build_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); } build_q35_pci0_int(dsdt); } --=20 2.49.0 From nobody Sat Nov 15 12:16:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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b=Ob4RtZMUaHXWiTaDNP6e56mRvO2njEymRw2DAlZ0YKeUhtol4e2AsBdHK4/mP6XYpbZyrp K4hOzLIYQKgn8Ytg3jYJTSb8VJEjM7c0aLQ7/u73bFSb/MNv4pOOnJDeM51M0lRPPnvFWa gvV/CKsXPcXR2VmWOnwrSmmoQJl+l5w= X-MC-Unique: jeguISCNPBKyqNoaRLIkag-1 X-Mimecast-MFC-AGG-ID: jeguISCNPBKyqNoaRLIkag_1751546273 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, imammedo@redhat.com, Jonathan.Cameron@huawei.com, gustavo.romero@linaro.org, anisinha@redhat.com, mst@redhat.com, shannon.zhaosl@gmail.com Cc: pbonzini@redhat.com, philmd@linaro.org, alex.bennee@linaro.org Subject: [PATCH v5 03/36] hw/pci-host/gpex-acpi: Add native_pci_hotplug arg to acpi_dsdt_add_pci_osc Date: Thu, 3 Jul 2025 14:35:03 +0200 Message-ID: <20250703123728.414386-4-eric.auger@redhat.com> In-Reply-To: <20250703123728.414386-1-eric.auger@redhat.com> References: <20250703123728.414386-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Add a new argument to acpi_dsdt_add_pci_osc to be able to disable native pci hotplug. Signed-off-by: Eric Auger Reviewed-by: Gustavo Romero Reviewed-by: Igor Mammedov Reviewed-by: Jonathan Cameron --- rfc -> v1: - updated the "Allow OS control for all 5 features" comment --- hw/pci-host/gpex-acpi.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c index 0aba47c71c..f34b7cf25e 100644 --- a/hw/pci-host/gpex-acpi.c +++ b/hw/pci-host/gpex-acpi.c @@ -50,7 +50,7 @@ static void acpi_dsdt_add_pci_route_table(Aml *dev, uint3= 2_t irq, } } =20 -static void acpi_dsdt_add_pci_osc(Aml *dev) +static void acpi_dsdt_add_pci_osc(Aml *dev, bool enable_native_pcie_hotplu= g) { Aml *method, *UUID, *ifctx, *ifctx1, *elsectx, *buf; =20 @@ -77,11 +77,12 @@ static void acpi_dsdt_add_pci_osc(Aml *dev) aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL"))); =20 /* - * Allow OS control for all 5 features: - * PCIeHotplug SHPCHotplug PME AER PCIeCapability. + * Allow OS control for SHPCHotplug, PME, AER, PCIeCapability, + * and PCIeHotplug depending on enable_native_pcie_hotplug */ - aml_append(ifctx, aml_and(aml_name("CTRL"), aml_int(0x1F), - aml_name("CTRL"))); + aml_append(ifctx, aml_and(aml_name("CTRL"), + aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)), + aml_name("CTRL"))); =20 ifctx1 =3D aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1)))); aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x08), @@ -192,7 +193,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *= cfg) if (is_cxl) { build_cxl_osc_method(dev); } else { - acpi_dsdt_add_pci_osc(dev); + acpi_dsdt_add_pci_osc(dev, true); } =20 aml_append(scope, dev); @@ -267,7 +268,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *= cfg) } aml_append(dev, aml_name_decl("_CRS", rbuf)); =20 - acpi_dsdt_add_pci_osc(dev); + acpi_dsdt_add_pci_osc(dev, true); =20 Aml *dev_res0 =3D aml_device("%s", "RES0"); aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02"))); --=20 2.49.0 From nobody Sat Nov 15 12:16:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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b=QHcXvIOkD0u0zvfX4H+vgnRsaQHqe+1qqBNDhnipQ2ETPgPb513eI/zTtgdhBm2aM8g4xe dULabiiAX/C5WNWIECAnqWw/qK2T65BzIkuLuN6sX5C3HAnFWw0U5UvNjZPSJ2OPZMCdB2 6CfdKnxbDczGTbPxjSIDE0UazSBatoc= X-MC-Unique: dXUOKrs6P9SGqEebpwDcbw-1 X-Mimecast-MFC-AGG-ID: dXUOKrs6P9SGqEebpwDcbw_1751546278 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, imammedo@redhat.com, Jonathan.Cameron@huawei.com, gustavo.romero@linaro.org, anisinha@redhat.com, mst@redhat.com, shannon.zhaosl@gmail.com Cc: pbonzini@redhat.com, philmd@linaro.org, alex.bennee@linaro.org Subject: [PATCH v5 04/36] tests/qtest/bios-tables-test: Prepare for changes in the DSDT table Date: Thu, 3 Jul 2025 14:35:04 +0200 Message-ID: <20250703123728.414386-5-eric.auger@redhat.com> In-Reply-To: <20250703123728.414386-1-eric.auger@redhat.com> References: <20250703123728.414386-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: Gustavo Romero This commit adds DSDT blobs to the whilelist in the prospect to allow changes in the GPEX _OSC method. Signed-off-by: Gustavo Romero Signed-off-by: Eric Auger Reviewed-by: Jonathan Cameron Acked-by: Igor Mammedov --- v3 -> v4: - add missed tests/data/acpi/riscv64/virt/DSDT v2 -> v3: - fix for microvm --- tests/qtest/bios-tables-test-allowed-diff.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index dfb8523c8b..333e5acf63 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,8 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/aarch64/virt/DSDT", +"tests/data/acpi/aarch64/virt/DSDT.acpihmatvirt", +"tests/data/acpi/aarch64/virt/DSDT.memhp", +"tests/data/acpi/aarch64/virt/DSDT.pxb", +"tests/data/acpi/aarch64/virt/DSDT.topology", +"tests/data/acpi/x86/microvm/DSDT.pcie", +"tests/data/acpi/riscv64/virt/DSDT", --=20 2.49.0 From nobody Sat Nov 15 12:16:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1751546289; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=8tsfNnFgjFSMarOZ/Ey2DdHtTx77eO4HAyY+2EP63+M=; b=PzZ23hawIEKKq8Vfb4oHaVHUQWq+vq36tdxwcgIRBZjqMNTezp4MIkwv8yIHwA+zVkE5cU 6c7JpcQoyRBkCXI/BLs4+vEJie9hwKjgZFShqE/8j2FuF1wJOk5kl3ydHPK9Z1QOODo4s9 FOKClukkcKXdCmffQwcs9g6vwiwvTiY= X-MC-Unique: eX7hsATXPPK2tGvWD0_1dA-1 X-Mimecast-MFC-AGG-ID: eX7hsATXPPK2tGvWD0_1dA_1751546283 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, imammedo@redhat.com, Jonathan.Cameron@huawei.com, gustavo.romero@linaro.org, anisinha@redhat.com, mst@redhat.com, shannon.zhaosl@gmail.com Cc: pbonzini@redhat.com, philmd@linaro.org, alex.bennee@linaro.org Subject: [PATCH v5 05/36] hw/pci-host/gpex-acpi: Split host bridge OSC and DSM generation Date: Thu, 3 Jul 2025 14:35:05 +0200 Message-ID: <20250703123728.414386-6-eric.auger@redhat.com> In-Reply-To: <20250703123728.414386-1-eric.auger@redhat.com> References: <20250703123728.414386-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" acpi_dsdt_add_pci_osc() name is confusing as it gives the impression it appends the _OSC method but in fact it also appends the _DSM method for the host bridge. Let's split the function into two separate ones and let them return the method Aml pointer instead. This matches the way it is done on x86 (build_q35_osc_method). In a subsequent patch we will replace the gpex method by the q35 implementation that will become shared between ARM and x86. acpi_dsdt_add_host_bridge_methods is a new top helper that generates both the _OSC and _DSM methods. We take the opportunity to move SUPP and CTRL in the _osc method that use them. Signed-off-by: Eric Auger Reviewed-by: Jonathan Cameron Reviewed-by: Igor Mammedov --- v2 -> v3: - moved aml_append(dev, aml_name_decl("SUPP", aml_int(0))); aml_append(dev, aml_name_decl("CTRL", aml_int(0))); into the _osc function. (Jonathan) hence discarded Gustavo's and Igor's R-bs --- hw/pci-host/gpex-acpi.c | 32 +++++++++++++++++++++----------- 1 file changed, 21 insertions(+), 11 deletions(-) diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c index f34b7cf25e..80fc2bf032 100644 --- a/hw/pci-host/gpex-acpi.c +++ b/hw/pci-host/gpex-acpi.c @@ -50,14 +50,12 @@ static void acpi_dsdt_add_pci_route_table(Aml *dev, uin= t32_t irq, } } =20 -static void acpi_dsdt_add_pci_osc(Aml *dev, bool enable_native_pcie_hotplu= g) +static Aml *build_host_bridge_osc(bool enable_native_pcie_hotplug) { - Aml *method, *UUID, *ifctx, *ifctx1, *elsectx, *buf; - - /* Declare an _OSC (OS Control Handoff) method */ - aml_append(dev, aml_name_decl("SUPP", aml_int(0))); - aml_append(dev, aml_name_decl("CTRL", aml_int(0))); + Aml *method, *UUID, *ifctx, *ifctx1, *elsectx; method =3D aml_method("_OSC", 4, AML_NOTSERIALIZED); + aml_append(method, aml_name_decl("SUPP", aml_int(0))); + aml_append(method, aml_name_decl("CTRL", aml_int(0))); aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); =20 @@ -103,9 +101,13 @@ static void acpi_dsdt_add_pci_osc(Aml *dev, bool enabl= e_native_pcie_hotplug) aml_name("CDW1"))); aml_append(elsectx, aml_return(aml_arg(3))); aml_append(method, elsectx); - aml_append(dev, method); + return method; +} =20 - method =3D aml_method("_DSM", 4, AML_NOTSERIALIZED); +static Aml *build_host_bridge_dsm(void) +{ + Aml *method =3D aml_method("_DSM", 4, AML_NOTSERIALIZED); + Aml *UUID, *ifctx, *ifctx1, *buf; =20 /* PCI Firmware Specification 3.0 * 4.6.1. _DSM for PCI Express Slot Information @@ -124,7 +126,15 @@ static void acpi_dsdt_add_pci_osc(Aml *dev, bool enabl= e_native_pcie_hotplug) byte_list[0] =3D 0; buf =3D aml_buffer(1, byte_list); aml_append(method, aml_return(buf)); - aml_append(dev, method); + return method; +} + +static void acpi_dsdt_add_host_bridge_methods(Aml *dev, + bool enable_native_pcie_hotp= lug) +{ + /* Declare an _OSC (OS Control Handoff) method */ + aml_append(dev, build_host_bridge_osc(enable_native_pcie_hotplug)); + aml_append(dev, build_host_bridge_dsm()); } =20 void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) @@ -193,7 +203,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *= cfg) if (is_cxl) { build_cxl_osc_method(dev); } else { - acpi_dsdt_add_pci_osc(dev, true); + acpi_dsdt_add_host_bridge_methods(dev, true); } =20 aml_append(scope, dev); @@ -268,7 +278,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *= cfg) } aml_append(dev, aml_name_decl("_CRS", rbuf)); =20 - acpi_dsdt_add_pci_osc(dev, true); + acpi_dsdt_add_host_bridge_methods(dev, true); =20 Aml *dev_res0 =3D aml_device("%s", "RES0"); aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02"))); --=20 2.49.0 From nobody Sat Nov 15 12:16:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; 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b=IoKA2E524a/jJISffxV1dN5K2+i1jGdT0mSqgD4LgUVQ3NEQErvT9thZFAMNvZeT0bJF7y WCC4u3KJNSS0PdvfzIP2UhTeyMvv7c4wv2zt4IxeyT6DopcbX7Ry2QFr32YbWlCRaYFSJ2 8C+WUbU9BjANuUpGilkx0vi9U9xywLQ= X-MC-Unique: Xa3hcKhIM0yNroyOkmdtYA-1 X-Mimecast-MFC-AGG-ID: Xa3hcKhIM0yNroyOkmdtYA_1751546288 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, imammedo@redhat.com, Jonathan.Cameron@huawei.com, gustavo.romero@linaro.org, anisinha@redhat.com, mst@redhat.com, shannon.zhaosl@gmail.com Cc: pbonzini@redhat.com, philmd@linaro.org, alex.bennee@linaro.org Subject: [PATCH v5 06/36] hw/acpi/ged: Add a acpi-pci-hotplug-with-bridge-support property Date: Thu, 3 Jul 2025 14:35:06 +0200 Message-ID: <20250703123728.414386-7-eric.auger@redhat.com> In-Reply-To: <20250703123728.414386-1-eric.auger@redhat.com> References: <20250703123728.414386-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" A new boolean property is introduced. This will be used to turn ACPI PCI hotplug support. By default it is unset. Signed-off-by: Eric Auger Reviewed-by: Jonathan Cameron Reviewed-by: Igor Mammedov --- include/hw/acpi/generic_event_device.h | 2 ++ hw/acpi/generic_event_device.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/include/hw/acpi/generic_event_device.h b/include/hw/acpi/gener= ic_event_device.h index d2dac87b4a..f5ffa67a39 100644 --- a/include/hw/acpi/generic_event_device.h +++ b/include/hw/acpi/generic_event_device.h @@ -63,6 +63,7 @@ #include "hw/acpi/memory_hotplug.h" #include "hw/acpi/ghes.h" #include "hw/acpi/cpu.h" +#include "hw/acpi/pcihp.h" #include "qom/object.h" =20 #define ACPI_POWER_BUTTON_DEVICE "PWRB" @@ -114,6 +115,7 @@ struct AcpiGedState { MemoryRegion container_memhp; CPUHotplugState cpuhp_state; MemoryRegion container_cpuhp; + AcpiPciHpState pcihp_state; GEDState ged_state; uint32_t ged_event_bitmap; qemu_irq irq; diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c index 7a62f8d5bc..7831db412b 100644 --- a/hw/acpi/generic_event_device.c +++ b/hw/acpi/generic_event_device.c @@ -318,6 +318,8 @@ static void acpi_ged_send_event(AcpiDeviceIf *adev, Acp= iEventStatusBits ev) =20 static const Property acpi_ged_properties[] =3D { DEFINE_PROP_UINT32("ged-event", AcpiGedState, ged_event_bitmap, 0), + DEFINE_PROP_BOOL(ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, AcpiGedState, + pcihp_state.use_acpi_hotplug_bridge, 0), }; =20 static const VMStateDescription vmstate_memhp_state =3D { --=20 2.49.0 From nobody Sat Nov 15 12:16:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1751546509; cv=none; d=zohomail.com; s=zohoarc; b=mStw0JI5WYx9DbmPg51Euk4l/J70XGZBN4XZxoAtjeWOWLC1iJLgxguBy6Wz1VyonXfLc5Asjfl6N01fNVuhYpqoFm6tsWajjXj9KZwbu4B7X36JfT81BgPfEWqnd7C+VAPv4GIX6sge3++xuNaRCr+rlVDuCbDVnubBFEewTjk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751546509; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=qLaMDFzZjY+u32IAfNjad79BEhlHi5t75wvKla/0++E=; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1751546300; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qLaMDFzZjY+u32IAfNjad79BEhlHi5t75wvKla/0++E=; b=MI3H2VIDNeZGmNMNy2MQOKxwo3Se+Poj5brFi8MVZb13CJ9L2kyzZriEovivoQwouT7DTu cVXei5J68mu0Zhl7kMiqafb/o++rVgT9ETDphxR5DjFJu5dXQmNljF7AeqCHY39bmik7ri ETswqzEGxdQCXs5gkyPjVE5MPN6pBOc= X-MC-Unique: ply-y_rsNhOiy-YRWybOWQ-1 X-Mimecast-MFC-AGG-ID: ply-y_rsNhOiy-YRWybOWQ_1751546294 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, imammedo@redhat.com, Jonathan.Cameron@huawei.com, gustavo.romero@linaro.org, anisinha@redhat.com, mst@redhat.com, shannon.zhaosl@gmail.com Cc: pbonzini@redhat.com, philmd@linaro.org, alex.bennee@linaro.org Subject: [PATCH v5 07/36] hw/pci-host/gpex-acpi: Use GED acpi pcihp property Date: Thu, 3 Jul 2025 14:35:07 +0200 Message-ID: <20250703123728.414386-8-eric.auger@redhat.com> In-Reply-To: <20250703123728.414386-1-eric.auger@redhat.com> References: <20250703123728.414386-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Retrieve the acpi pcihp property value from the ged. In case this latter is not set, PCI native hotplug is used on pci0. For expander bridges we keep pci native hotplug, as done on x86 q35. Signed-off-by: Eric Auger Reviewed-by: Jonathan Cameron --- v4 -> v5: - check vms->acpi_dev v3 -> v4: - Use object_property_get_bool (Igor) - rework the commit description (Igor) v2 -> v3: - don'use the virt arm machine option anymore. --- include/hw/pci-host/gpex.h | 1 + hw/arm/virt-acpi-build.c | 9 +++++++++ hw/pci-host/gpex-acpi.c | 3 ++- 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h index 84471533af..feaf827474 100644 --- a/include/hw/pci-host/gpex.h +++ b/include/hw/pci-host/gpex.h @@ -45,6 +45,7 @@ struct GPEXConfig { MemMapEntry pio; int irq; PCIBus *bus; + bool pci_native_hotplug; }; =20 typedef struct GPEXIrq GPEXIrq; diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index cd90c47976..a2f31be9ec 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -123,12 +123,21 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMa= pEntry *memmap, uint32_t irq, VirtMachineState *vms) { int ecam_id =3D VIRT_ECAM_ID(vms->highmem_ecam); + bool acpi_pcihp =3D false; + + if (vms->acpi_dev) { + acpi_pcihp =3D object_property_get_bool(OBJECT(vms->acpi_dev), + ACPI_PM_PROP_ACPI_PCIHP_BRID= GE, + NULL); + } + struct GPEXConfig cfg =3D { .mmio32 =3D memmap[VIRT_PCIE_MMIO], .pio =3D memmap[VIRT_PCIE_PIO], .ecam =3D memmap[ecam_id], .irq =3D irq, .bus =3D vms->bus, + .pci_native_hotplug =3D !acpi_pcihp, }; =20 if (vms->highmem_mmio) { diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c index 80fc2bf032..44737a8d81 100644 --- a/hw/pci-host/gpex-acpi.c +++ b/hw/pci-host/gpex-acpi.c @@ -203,6 +203,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *= cfg) if (is_cxl) { build_cxl_osc_method(dev); } else { + /* pxb bridges do not have ACPI PCI Hot-plug enabled */ acpi_dsdt_add_host_bridge_methods(dev, true); } =20 @@ -278,7 +279,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *= cfg) } aml_append(dev, aml_name_decl("_CRS", rbuf)); =20 - acpi_dsdt_add_host_bridge_methods(dev, true); + acpi_dsdt_add_host_bridge_methods(dev, cfg->pci_native_hotplug); =20 Aml *dev_res0 =3D aml_device("%s", "RES0"); aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02"))); --=20 2.49.0 From nobody Sat Nov 15 12:16:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1751546409; cv=none; d=zohomail.com; s=zohoarc; b=UKrHCbPQ1Yv+aGR8LqAhdGig2prStJqNalMjvgwz3+zGxqLEmooxTZ3qOroFJXAfYYw/5jggwNb5FXYn7O+xHAyNa4Tbx3OuWXWy9vlhi/KKeDn9dorGWrXqOLIjWREhivE70B8DgaJSIdVeOVH1qzBsnyZM6bORDO9RfOXp4do= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751546409; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Thu, 3 Jul 2025 12:38:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1751546311; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=QM187LTqh66mz9nDTkv5Uwarxaf5Ee/ezdUTTwFgH/4=; b=S+MoSDI7jau2Rrp1RGU/+IU5ika5UBYZ8jBINR8SdLKXMjzymGO9a2WAhHXpjjd2wjVV7s 9ofbkZpuBWlY1IKXD6VJhsXh5PitZS16/LGAqXeaXcov3wp6hpOzVda1q+koKxdKCy/M6j TEGipeIkd4n6+OhPUhxOtKlDRnGdgGU= X-MC-Unique: zC0u4U4qOj-as6m25fvHyA-1 X-Mimecast-MFC-AGG-ID: zC0u4U4qOj-as6m25fvHyA_1751546299 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, imammedo@redhat.com, Jonathan.Cameron@huawei.com, gustavo.romero@linaro.org, anisinha@redhat.com, mst@redhat.com, shannon.zhaosl@gmail.com Cc: pbonzini@redhat.com, philmd@linaro.org, alex.bennee@linaro.org Subject: [PATCH v5 08/36] hw/i386/acpi-build: Turn build_q35_osc_method into a generic method Date: Thu, 3 Jul 2025 14:35:08 +0200 Message-ID: <20250703123728.414386-9-eric.auger@redhat.com> In-Reply-To: <20250703123728.414386-1-eric.auger@redhat.com> References: <20250703123728.414386-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" GPEX acpi_dsdt_add_pci_osc() does basically the same as build_q35_osc_method(). Rename build_q35_osc_method() into build_pci_host_bridge_osc_method() and move it into hw/acpi/pci.c. In a subsequent patch we will use this later in place of acpi_dsdt_add_pci_osc(). Signed-off-by: Eric Auger Reviewed-by: Jonathan Cameron Reviewed-by: Igor Mammedov --- v2 -> v3: - move to hw/acpi/pci.c instead of aml-build.c (Igor) --- include/hw/acpi/pci.h | 2 ++ hw/acpi/pci.c | 50 +++++++++++++++++++++++++++++++++++++++ hw/i386/acpi-build.c | 54 ++----------------------------------------- 3 files changed, 54 insertions(+), 52 deletions(-) diff --git a/include/hw/acpi/pci.h b/include/hw/acpi/pci.h index ab0187a894..8a328b580c 100644 --- a/include/hw/acpi/pci.h +++ b/include/hw/acpi/pci.h @@ -42,4 +42,6 @@ void build_pci_bridge_aml(AcpiDevAmlIf *adev, Aml *scope); =20 void build_srat_generic_affinity_structures(GArray *table_data); =20 +Aml *build_pci_host_bridge_osc_method(bool enable_native_pcie_hotplug); + #endif diff --git a/hw/acpi/pci.c b/hw/acpi/pci.c index d511a85029..2228f1245e 100644 --- a/hw/acpi/pci.c +++ b/hw/acpi/pci.c @@ -301,3 +301,53 @@ void build_srat_generic_affinity_structures(GArray *ta= ble_data) object_child_foreach_recursive(object_get_root(), build_acpi_generic_p= ort, table_data); } + +Aml *build_pci_host_bridge_osc_method(bool enable_native_pcie_hotplug) +{ + Aml *if_ctx; + Aml *if_ctx2; + Aml *else_ctx; + Aml *method; + Aml *a_cwd1 =3D aml_name("CDW1"); + Aml *a_ctrl =3D aml_local(0); + + method =3D aml_method("_OSC", 4, AML_NOTSERIALIZED); + aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW= 1")); + + if_ctx =3D aml_if(aml_equal( + aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); + aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW= 2")); + aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW= 3")); + + aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); + + /* + * Always allow native PME, AER (no dependencies) + * Allow SHPC (PCI bridges can have SHPC controller) + * Disable PCIe Native Hot-plug if ACPI PCI Hot-plug is enabled. + */ + aml_append(if_ctx, aml_and(a_ctrl, + aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)), a_ctrl)); + + if_ctx2 =3D aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); + /* Unknown revision */ + aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); + aml_append(if_ctx, if_ctx2); + + if_ctx2 =3D aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); + /* Capabilities bits were masked */ + aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); + aml_append(if_ctx, if_ctx2); + + /* Update DWORD3 in the buffer */ + aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); + aml_append(method, if_ctx); + + else_ctx =3D aml_else(); + /* Unrecognized UUID */ + aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); + aml_append(method, else_ctx); + + aml_append(method, aml_return(aml_arg(3))); + return method; +} diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 4f8572eebe..91945f716c 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1111,56 +1111,6 @@ static Aml *build_q35_dram_controller(const AcpiMcfg= Info *mcfg) return dev; } =20 -static Aml *build_q35_osc_method(bool enable_native_pcie_hotplug) -{ - Aml *if_ctx; - Aml *if_ctx2; - Aml *else_ctx; - Aml *method; - Aml *a_cwd1 =3D aml_name("CDW1"); - Aml *a_ctrl =3D aml_local(0); - - method =3D aml_method("_OSC", 4, AML_NOTSERIALIZED); - aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW= 1")); - - if_ctx =3D aml_if(aml_equal( - aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"))); - aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW= 2")); - aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW= 3")); - - aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl)); - - /* - * Always allow native PME, AER (no dependencies) - * Allow SHPC (PCI bridges can have SHPC controller) - * Disable PCIe Native Hot-plug if ACPI PCI Hot-plug is enabled. - */ - aml_append(if_ctx, aml_and(a_ctrl, - aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)), a_ctrl)); - - if_ctx2 =3D aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); - /* Unknown revision */ - aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1)); - aml_append(if_ctx, if_ctx2); - - if_ctx2 =3D aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl))); - /* Capabilities bits were masked */ - aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1)); - aml_append(if_ctx, if_ctx2); - - /* Update DWORD3 in the buffer */ - aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3"))); - aml_append(method, if_ctx); - - else_ctx =3D aml_else(); - /* Unrecognized UUID */ - aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1)); - aml_append(method, else_ctx); - - aml_append(method, aml_return(aml_arg(3))); - return method; -} - static void build_acpi0017(Aml *table) { Aml *dev, *scope, *method; @@ -1231,7 +1181,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))= ); - aml_append(dev, build_q35_osc_method(!pm->pcihp_bridge_en)); + aml_append(dev, build_pci_host_bridge_osc_method(!pm->pcihp_bridge= _en)); aml_append(dev, aml_pci_edsm()); aml_append(sb_scope, dev); if (mcfg_valid) { @@ -1353,7 +1303,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"= ))); =20 /* Expander bridges do not have ACPI PCI Hot-plug enabled = */ - aml_append(dev, build_q35_osc_method(true)); + aml_append(dev, build_pci_host_bridge_osc_method(true)); } else { aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"= ))); } --=20 2.49.0 From nobody Sat Nov 15 12:16:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1751547524; cv=none; d=zohomail.com; s=zohoarc; b=mLUh4JpRtJshrE8Mji4HxaiCRi+bT7GItrOvw9InjlwqiiICxd2mWEeB1/KQ4hFpdfEoRwaq8k/C1RDxBDX1emzL90V1J3Svn9LRF/tB2XTa91hVEbBVIo5vYweF1l8He7hWEjlb/torAKEAjfR9PWqMAIeDFo1d/bRwiVGubNA= ARC-Message-Signature: i=1; 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charset="utf-8" gpex build_host_bridge_osc() and x86 originated build_pci_host_bridge_osc_method() are mostly identical. In GPEX, SUPP is set to CDW2 but is not further used. CTRL is same as Local0. So let gpex code reuse build_pci_host_bridge_osc_method() and remove build_host_bridge_osc(). Also add an imply ACPI_PCI clause along with PCI_EXPRESS_GENERIC_BRIDGE to compile hw/acpi/pci.c when its dependency is resolved (ie. CONFIG_ACPI_PCI). This is requested to link qemu-system-mips64el. The disassembled DSDT difference is given below: * Original Table Header: * Signature "DSDT" - * Length 0x00001A4F (6735) + * Length 0x00001A35 (6709) * Revision 0x02 - * Checksum 0xBF + * Checksum 0xDD * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) @@ -1849,27 +1849,26 @@ DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPC = ", 0x00000001) { CreateDWordField (Arg3, 0x04, CDW2) CreateDWordField (Arg3, 0x08, CDW3) - SUPP =3D CDW2 /* \_SB_.PCI0._OSC.CDW2 */ - CTRL =3D CDW3 /* \_SB_.PCI0._OSC.CDW3 */ - CTRL &=3D 0x1F + Local0 =3D CDW3 /* \_SB_.PCI0._OSC.CDW3 */ + Local0 &=3D 0x1F If ((Arg1 !=3D One)) { CDW1 |=3D 0x08 } - If ((CDW3 !=3D CTRL)) + If ((CDW3 !=3D Local0)) { CDW1 |=3D 0x10 } - CDW3 =3D CTRL /* \_SB_.PCI0.CTRL */ - Return (Arg3) + CDW3 =3D Local0 } Else { CDW1 |=3D 0x04 - Return (Arg3) } + + Return (Arg3) } Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Meth= od Signed-off-by: Eric Auger Reviewed-by: Igor Mammedov Reviewed-by: Jonathan Cameron --- v3 -> v4: - Fix link issue: /usr/bin/ld: libsystem.a.p/hw_pci-host_gpex-acpi.c.o: in function `acpi_dsd= t_add_host_bridge_methods': ./hw/pci-host/gpex-acpi.c:83: undefined reference to `build_pci_host_bridge= _osc_method' v1 -> v2: - move in the dsdt.dsl diff in the commit message and remove useless info (Gustavo, Michael) --- hw/pci-host/gpex-acpi.c | 62 ++++------------------------------------- hw/pci-host/Kconfig | 1 + 2 files changed, 6 insertions(+), 57 deletions(-) diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c index 44737a8d81..952a0ace19 100644 --- a/hw/pci-host/gpex-acpi.c +++ b/hw/pci-host/gpex-acpi.c @@ -1,5 +1,6 @@ #include "qemu/osdep.h" #include "hw/acpi/aml-build.h" +#include "hw/acpi/pci.h" #include "hw/pci-host/gpex.h" #include "hw/arm/virt.h" #include "hw/pci/pci_bus.h" @@ -50,61 +51,7 @@ static void acpi_dsdt_add_pci_route_table(Aml *dev, uint= 32_t irq, } } =20 -static Aml *build_host_bridge_osc(bool enable_native_pcie_hotplug) -{ - Aml *method, *UUID, *ifctx, *ifctx1, *elsectx; - method =3D aml_method("_OSC", 4, AML_NOTSERIALIZED); - aml_append(method, aml_name_decl("SUPP", aml_int(0))); - aml_append(method, aml_name_decl("CTRL", aml_int(0))); - aml_append(method, - aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); - - /* PCI Firmware Specification 3.0 - * 4.5.1. _OSC Interface for PCI Host Bridge Devices - * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is - * identified by the Universal Unique IDentifier (UUID) - * 33DB4D5B-1FF7-401C-9657-7441C03DD766 - */ - UUID =3D aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"); - ifctx =3D aml_if(aml_equal(aml_arg(0), UUID)); - aml_append(ifctx, - aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); - aml_append(ifctx, - aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); - aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP"))); - aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL"))); - - /* - * Allow OS control for SHPCHotplug, PME, AER, PCIeCapability, - * and PCIeHotplug depending on enable_native_pcie_hotplug - */ - aml_append(ifctx, aml_and(aml_name("CTRL"), - aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)), - aml_name("CTRL"))); - - ifctx1 =3D aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1)))); - aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x08), - aml_name("CDW1"))); - aml_append(ifctx, ifctx1); - - ifctx1 =3D aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL"= )))); - aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x10), - aml_name("CDW1"))); - aml_append(ifctx, ifctx1); - - aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3"))); - aml_append(ifctx, aml_return(aml_arg(3))); - aml_append(method, ifctx); - - elsectx =3D aml_else(); - aml_append(elsectx, aml_or(aml_name("CDW1"), aml_int(4), - aml_name("CDW1"))); - aml_append(elsectx, aml_return(aml_arg(3))); - aml_append(method, elsectx); - return method; -} - -static Aml *build_host_bridge_dsm(void) +static Aml *build_pci_host_bridge_dsm_method(void) { Aml *method =3D aml_method("_DSM", 4, AML_NOTSERIALIZED); Aml *UUID, *ifctx, *ifctx1, *buf; @@ -133,8 +80,9 @@ static void acpi_dsdt_add_host_bridge_methods(Aml *dev, bool enable_native_pcie_hotp= lug) { /* Declare an _OSC (OS Control Handoff) method */ - aml_append(dev, build_host_bridge_osc(enable_native_pcie_hotplug)); - aml_append(dev, build_host_bridge_dsm()); + aml_append(dev, + build_pci_host_bridge_osc_method(enable_native_pcie_hotplug= )); + aml_append(dev, build_pci_host_bridge_dsm_method()); } =20 void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) diff --git a/hw/pci-host/Kconfig b/hw/pci-host/Kconfig index 35c0415242..9824fa188d 100644 --- a/hw/pci-host/Kconfig +++ b/hw/pci-host/Kconfig @@ -54,6 +54,7 @@ config PCI_EXPRESS_Q35 config PCI_EXPRESS_GENERIC_BRIDGE bool select PCI_EXPRESS + imply ACPI_PCI =20 config PCI_EXPRESS_XILINX bool --=20 2.49.0 From nobody Sat Nov 15 12:16:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1751546409; cv=none; d=zohomail.com; s=zohoarc; b=bfMTZkZu5ehTDMNccvHd6fKIq1sl8FYWNbDwVPYLhr2YYG3nlvCyOroLmG/M+lDwZwnO+eTbvpLbnhzBFcm5gBXXSFCFdDBGvGMJyu3vI27P7vSyvCp7idV8oLLoS4/w4fqHKlxTa7ZmGCuuhEG42uketzFPKHWi3R+PFWvVUFY= ARC-Message-Signature: i=1; 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charset="utf-8" Update the reference DSDT blobs after GPEX _OSC change. The _OSC change affects the aarch64 'virt' and the x86 'microvm' machines. DSDT diff is the same for all the machines/tests: * Original Table Header: * Signature "DSDT" - * Length 0x00001A4F (6735) + * Length 0x00001A35 (6709) * Revision 0x02 - * Checksum 0xBF + * Checksum 0xDD * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) @@ -1849,27 +1849,26 @@ DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPC = ", 0x00000001) { CreateDWordField (Arg3, 0x04, CDW2) CreateDWordField (Arg3, 0x08, CDW3) - SUPP =3D CDW2 /* \_SB_.PCI0._OSC.CDW2 */ - CTRL =3D CDW3 /* \_SB_.PCI0._OSC.CDW3 */ - CTRL &=3D 0x1F + Local0 =3D CDW3 /* \_SB_.PCI0._OSC.CDW3 */ + Local0 &=3D 0x1F If ((Arg1 !=3D One)) { CDW1 |=3D 0x08 } - If ((CDW3 !=3D CTRL)) + If ((CDW3 !=3D Local0)) { CDW1 |=3D 0x10 } - CDW3 =3D CTRL /* \_SB_.PCI0.CTRL */ - Return (Arg3) + CDW3 =3D Local0 } Else { CDW1 |=3D 0x04 - Return (Arg3) } + + Return (Arg3) } Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Meth= od Signed-off-by: Eric Auger Signed-off-by: Gustavo Romero Reviewed-by: Jonathan Cameron --- v3 -> v4 - fix the commit msg: dsl reverse diff (Jonathan) --- tests/qtest/bios-tables-test-allowed-diff.h | 7 ------- tests/data/acpi/aarch64/virt/DSDT | Bin 5196 -> 5158 bytes .../data/acpi/aarch64/virt/DSDT.acpihmatvirt | Bin 5282 -> 5244 bytes tests/data/acpi/aarch64/virt/DSDT.memhp | Bin 6557 -> 6519 bytes tests/data/acpi/aarch64/virt/DSDT.pxb | Bin 7679 -> 7603 bytes tests/data/acpi/aarch64/virt/DSDT.topology | Bin 5398 -> 5360 bytes tests/data/acpi/riscv64/virt/DSDT | Bin 3576 -> 3538 bytes tests/data/acpi/x86/microvm/DSDT.pcie | Bin 3023 -> 2985 bytes 8 files changed, 7 deletions(-) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index 333e5acf63..dfb8523c8b 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,8 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/aarch64/virt/DSDT", -"tests/data/acpi/aarch64/virt/DSDT.acpihmatvirt", -"tests/data/acpi/aarch64/virt/DSDT.memhp", -"tests/data/acpi/aarch64/virt/DSDT.pxb", -"tests/data/acpi/aarch64/virt/DSDT.topology", -"tests/data/acpi/x86/microvm/DSDT.pcie", -"tests/data/acpi/riscv64/virt/DSDT", diff --git a/tests/data/acpi/aarch64/virt/DSDT b/tests/data/acpi/aarch64/vi= rt/DSDT index 36d3e5d5a5e47359b6dcb3706f98b4f225677591..acab6e65febbc210158d4c39be0= 680bbb90250f5 100644 GIT binary patch delta 114 zcmX@3u}p)@CDC8kfX{JVpjp}Y(OkR^V=3DX2?C2#NTx$NL96vvg%MIJ<-! zF7RWWyjw`i#5kckflEGNfxx86nT)j{87>a6yzr#S&Mx7`2@o*>kXS(iNMs?;W@BMV FMgSUfAKd@| delta 152 zcmZ3caYlp7CDL29`;z&gYx bO@^t12n&FO3qXoN;!Cm@@@?i7mSh9~5Tq&5 diff --git a/tests/data/acpi/aarch64/virt/DSDT.acpihmatvirt b/tests/data/ac= pi/aarch64/virt/DSDT.acpihmatvirt index e6154d0355f84fdcc51387b4db8f9ee63acae4e9..54c27e7d95b4956ed1b5dee0d29= 9ccb08dc2a73e 100644 GIT binary patch delta 114 zcmZ3a`A37xCDa6yzr#S&Mx7`2@o*>kXS(iNMs?;=3D1yTr FMgUJNAb|h? delta 152 zcmeyPu}G84CDNm0%wFq=3D=3DX{M&B8`a&on7k%!&gatO5EAiWkM|FDX6ediaCQkd zT;Rt#dAE?3iE%=3D80+)Qk0)a`BGZ||^GF%*BdErTuon69>6Ch#&AhCi3kjO%w&Bnr6 FYyg6XAvXX3 delta 152 zcmexvG}oBRCDi~V&gatOkmCpr4G3W1a1IIbVGwcS zjQ06Ch#&AhCi3kjO%w$t?mg51 delta 282 zcmdmN{ok6)CD}EVLcA|TR*v9$aeB|nL7Yd7E^Zs diff --git a/tests/data/acpi/aarch64/virt/DSDT.topology b/tests/data/acpi/a= arch64/virt/DSDT.topology index 029d03eecc4efddc001e5377e85ac8e831294362..969b4f6560d3ae39f5b7e0064b7= 122905476fce8 100644 GIT binary patch delta 114 zcmbQH^+A)%CDa6yzr#S&Mx7`2@o*>kXS(iNMs?;=3DD)&{ Fi~vUbAmso6 delta 152 zcmeyMIZcbpCDha)H34$(f9`Ahlc^U>#zU bCd1T0gatst1t7&B@g>;{`8Hn{mSh9~yBaCk diff --git a/tests/data/acpi/riscv64/virt/DSDT b/tests/data/acpi/riscv64/vi= rt/DSDT index 6a33f5647ddd6de3a0f000f718b58f6fff44f0fd..527f239dab13a00ad42e5a70b8d= c2b89f12aa84a 100644 GIT binary patch delta 113 zcmew%eMy?jCDMXEN4;WVkrM^1_oQJG+D%CqTpmKwp#T5? delta 151 zcmca4{X?3|CDNm0%wvzEYgaCD#&HG5Ji`+{YxqAtd6%9`7IQ%+i(3;Or7^ zxWJEf@*XZN6XS&H1TMLR1p<>MXEN4;WVkrM^1_oQJG+D%CqTpmKwpn4BhW?qd?*kmCpr4G3W1a1IIbVGwcS zjQ0|Z0pAkq&fwN1vF-TQ4h~Sb3kqZPSP0nPj1*zrY0P7H& aG#RE2A}jzBE&wS8i7&}s$Tyjfdo}=3D5#47aw --=20 2.49.0 From nobody Sat Nov 15 12:16:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1751546320; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dPBzy9CsJVFt5NIIFLm3SKgobSoPadimXomCtIYommM=; b=iSjLCymtyogg+gIm6cy00epj0ZCMjnETdZa8FEg917C9rb+FmjfiWAv29IvQWDQlGPZN0w Ki2HVoNDFK25wAZFa1FPEc4vaHGJSLzdNfpMsBgIOjwSauD32Io54BshVXMPupEZzU84zl 22bv73BzBaVAQZajRQS9vOpCUIwTiFA= X-MC-Unique: GcIaQgQnOXWizg6XZLCZdQ-1 X-Mimecast-MFC-AGG-ID: GcIaQgQnOXWizg6XZLCZdQ_1751546316 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, imammedo@redhat.com, Jonathan.Cameron@huawei.com, gustavo.romero@linaro.org, anisinha@redhat.com, mst@redhat.com, shannon.zhaosl@gmail.com Cc: pbonzini@redhat.com, philmd@linaro.org, alex.bennee@linaro.org Subject: [PATCH v5 11/36] hw/i386/acpi-build: Introduce build_append_pcihp_resources() helper Date: Thu, 3 Jul 2025 14:35:11 +0200 Message-ID: <20250703123728.414386-12-eric.auger@redhat.com> In-Reply-To: <20250703123728.414386-1-eric.auger@redhat.com> References: <20250703123728.414386-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Extract the code that reserves resources for ACPI PCI hotplug into a new helper named build_append_pcihp_resources() and move it to pcihp.c. We will reuse it on ARM. Signed-off-by: Eric Auger Reviewed-by: Gustavo Romero Reviewed-by: Igor Mammedov Reviewed-by: Jonathan Cameron --- v2 -> v3: - fixed indent (Jonathan) --- include/hw/acpi/pcihp.h | 2 ++ hw/acpi/pcihp.c | 18 ++++++++++++++++++ hw/i386/acpi-build.c | 15 ++------------- 3 files changed, 22 insertions(+), 13 deletions(-) diff --git a/include/hw/acpi/pcihp.h b/include/hw/acpi/pcihp.h index 971451e8ea..8a46a414cc 100644 --- a/include/hw/acpi/pcihp.h +++ b/include/hw/acpi/pcihp.h @@ -75,6 +75,8 @@ void acpi_pcihp_device_unplug_request_cb(HotplugHandler *= hotplug_dev, =20 void build_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr); void build_append_pci_dsm_func0_common(Aml *ctx, Aml *retvar); +void build_append_pcihp_resources(Aml *table, + uint64_t io_addr, uint64_t io_len); =20 /* Called on reset */ void acpi_pcihp_reset(AcpiPciHpState *s); diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c index cbe7e01385..5ca36c8619 100644 --- a/hw/acpi/pcihp.c +++ b/hw/acpi/pcihp.c @@ -685,6 +685,24 @@ void build_acpi_pci_hotplug(Aml *table, uint64_t pcihp= _addr) aml_append(table, scope); } =20 +/* Reserve PCIHP resources */ +void build_append_pcihp_resources(Aml *scope /* \\_SB.PCI0 */, + uint64_t io_addr, uint64_t io_len) +{ + Aml *dev, *crs; + + dev =3D aml_device("PHPR"); + aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); + aml_append(dev, + aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); + /* device present, functioning, decoding, not shown in UI */ + aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); + crs =3D aml_resource_template(); + aml_append(crs, aml_io(AML_DECODE16, io_addr, io_addr, 1, io_len)); + aml_append(dev, aml_name_decl("_CRS", crs)); + aml_append(scope, dev); +} + const VMStateDescription vmstate_acpi_pcihp_pci_status =3D { .name =3D "acpi_pcihp_pci_status", .version_id =3D 1, diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 91945f716c..52cef834ed 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1432,19 +1432,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, =20 /* reserve PCIHP resources */ if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { - dev =3D aml_device("PHPR"); - aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); - aml_append(dev, - aml_name_decl("_UID", aml_string("PCI Hotplug resources"))); - /* device present, functioning, decoding, not shown in UI */ - aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); - crs =3D aml_resource_template(); - aml_append(crs, - aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1, - pm->pcihp_io_len) - ); - aml_append(dev, aml_name_decl("_CRS", crs)); - aml_append(scope, dev); + build_append_pcihp_resources(scope, + pm->pcihp_io_base, pm->pcihp_io_len); } aml_append(dsdt, scope); =20 --=20 2.49.0 From nobody Sat Nov 15 12:16:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1751546418; cv=none; d=zohomail.com; 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charset="utf-8" On ARM we will put the operation regions in AML_SYSTEM_MEMORY. So let's allow this configuration. Signed-off-by: Eric Auger Reviewed-by: Gustavo Romero Reviewed-by: Igor Mammedov Reviewed-by: Jonathan Cameron --- include/hw/acpi/pcihp.h | 3 ++- hw/acpi/pcihp.c | 8 ++++---- hw/i386/acpi-build.c | 4 ++-- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/include/hw/acpi/pcihp.h b/include/hw/acpi/pcihp.h index 8a46a414cc..253ac6e483 100644 --- a/include/hw/acpi/pcihp.h +++ b/include/hw/acpi/pcihp.h @@ -28,6 +28,7 @@ #define HW_ACPI_PCIHP_H =20 #include "hw/acpi/acpi.h" +#include "hw/acpi/aml-build.h" #include "hw/hotplug.h" =20 #define ACPI_PCIHP_IO_BASE_PROP "acpi-pcihp-io-base" @@ -73,7 +74,7 @@ void acpi_pcihp_device_unplug_request_cb(HotplugHandler *= hotplug_dev, AcpiPciHpState *s, DeviceState *d= ev, Error **errp); =20 -void build_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr); +void build_acpi_pci_hotplug(Aml *table, AmlRegionSpace rs, uint64_t pcihp_= addr); void build_append_pci_dsm_func0_common(Aml *ctx, Aml *retvar); void build_append_pcihp_resources(Aml *table, uint64_t io_addr, uint64_t io_len); diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c index 5ca36c8619..afa3ec5f4d 100644 --- a/hw/acpi/pcihp.c +++ b/hw/acpi/pcihp.c @@ -629,7 +629,7 @@ static Aml *aml_pci_pdsm(void) return method; } =20 -void build_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr) +void build_acpi_pci_hotplug(Aml *table, AmlRegionSpace rs, uint64_t pcihp_= addr) { Aml *scope; Aml *field; @@ -638,21 +638,21 @@ void build_acpi_pci_hotplug(Aml *table, uint64_t pcih= p_addr) scope =3D aml_scope("_SB.PCI0"); =20 aml_append(scope, - aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0= x08)); + aml_operation_region("PCST", rs, aml_int(pcihp_addr), 0x08)); field =3D aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZE= ROS); aml_append(field, aml_named_field("PCIU", 32)); aml_append(field, aml_named_field("PCID", 32)); aml_append(scope, field); =20 aml_append(scope, - aml_operation_region("SEJ", AML_SYSTEM_IO, + aml_operation_region("SEJ", rs, aml_int(pcihp_addr + ACPI_PCIHP_SEJ_BASE), 0x= 04)); field =3D aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZER= OS); aml_append(field, aml_named_field("B0EJ", 32)); aml_append(scope, field); =20 aml_append(scope, - aml_operation_region("BNMR", AML_SYSTEM_IO, + aml_operation_region("BNMR", rs, aml_int(pcihp_addr + ACPI_PCIHP_BNMR_BASE), 0= x08)); field =3D aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZE= ROS); aml_append(field, aml_named_field("BNUM", 32)); diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 52cef834ed..6ca2b34ef8 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1172,7 +1172,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, aml_append(dsdt, sb_scope); =20 if (pm->pcihp_bridge_en || pm->pcihp_root_en) { - build_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); + build_acpi_pci_hotplug(dsdt, AML_SYSTEM_IO, pm->pcihp_io_base); } build_piix4_pci0_int(dsdt); } else if (q35) { @@ -1216,7 +1216,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, aml_append(dsdt, sb_scope); =20 if (pm->pcihp_bridge_en) { - build_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); + build_acpi_pci_hotplug(dsdt, AML_SYSTEM_IO, pm->pcihp_io_base); } build_q35_pci0_int(dsdt); } --=20 2.49.0 From nobody Sat Nov 15 12:16:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1751546653; cv=none; d=zohomail.com; s=zohoarc; b=Rpv+HfRZ5av6N5SPpot5OGjhNJD9bDyUSiwO02wrw5OFn+T2JInkbCSIrDDG36jNjTt4KWoP2UD1jkxpLYwlGhLuGhM25WFLpXTnqZvfrtJr3qB7ZQ3K5wxM47Vbh0bnCD6TsNnzWrmJNazJlRquIfoE2+bb7ELZ9BFfNQNZEgo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751546653; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Thu, 3 Jul 2025 12:38:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1751546330; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ztOHQuRdZU6Ia6/9fdzeOkwFogOl4LLzWMJKwr7hjGI=; b=M4r/2PZsVzw0v+xkR1eeGqpTBNdbITGISSM6q2g60boPHVe/g1AXiYD1LgmuM5KWUKrKM4 f0ek222FK+vU3BHreqQjjHPMWDtSZ0DUjNkuE9YLHWzLQcTu1Os3mEQ+5TAGijp7K1Pt0e crllUjSafxTGSIltRPOgjyUjTKjTX2c= X-MC-Unique: 1ELgZuimP12AlPtu-3IrMw-1 X-Mimecast-MFC-AGG-ID: 1ELgZuimP12AlPtu-3IrMw_1751546326 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, imammedo@redhat.com, Jonathan.Cameron@huawei.com, gustavo.romero@linaro.org, anisinha@redhat.com, mst@redhat.com, shannon.zhaosl@gmail.com Cc: pbonzini@redhat.com, philmd@linaro.org, alex.bennee@linaro.org Subject: [PATCH v5 13/36] hw/i386/acpi-build: Move build_append_notification_callback to pcihp Date: Thu, 3 Jul 2025 14:35:13 +0200 Message-ID: <20250703123728.414386-14-eric.auger@redhat.com> In-Reply-To: <20250703123728.414386-1-eric.auger@redhat.com> References: <20250703123728.414386-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" We plan to reuse build_append_notification_callback() on ARM so let's move it to pcihp.c. No functional change intended. Signed-off-by: Eric Auger Reviewed-by: Gustavo Romero Reviewed-by: Igor Mammedov Reviewed-by: Jonathan Cameron --- include/hw/acpi/pcihp.h | 1 + hw/acpi/pcihp.c | 58 +++++++++++++++++++++++++++++++++++++++++ hw/i386/acpi-build.c | 58 ----------------------------------------- 3 files changed, 59 insertions(+), 58 deletions(-) diff --git a/include/hw/acpi/pcihp.h b/include/hw/acpi/pcihp.h index 253ac6e483..f4fd44cb32 100644 --- a/include/hw/acpi/pcihp.h +++ b/include/hw/acpi/pcihp.h @@ -78,6 +78,7 @@ void build_acpi_pci_hotplug(Aml *table, AmlRegionSpace rs= , uint64_t pcihp_addr); void build_append_pci_dsm_func0_common(Aml *ctx, Aml *retvar); void build_append_pcihp_resources(Aml *table, uint64_t io_addr, uint64_t io_len); +bool build_append_notification_callback(Aml *parent_scope, const PCIBus *b= us); =20 /* Called on reset */ void acpi_pcihp_reset(AcpiPciHpState *s); diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c index afa3ec5f4d..b64d06afc9 100644 --- a/hw/acpi/pcihp.c +++ b/hw/acpi/pcihp.c @@ -39,6 +39,7 @@ #include "migration/vmstate.h" #include "qapi/error.h" #include "qom/qom-qobject.h" +#include "qobject/qnum.h" #include "trace.h" =20 #define ACPI_PCIHP_SIZE 0x0018 @@ -703,6 +704,63 @@ void build_append_pcihp_resources(Aml *scope /* \\_SB.= PCI0 */, aml_append(scope, dev); } =20 +bool build_append_notification_callback(Aml *parent_scope, const PCIBus *b= us) +{ + Aml *method; + PCIBus *sec; + QObject *bsel; + int nr_notifiers =3D 0; + GQueue *pcnt_bus_list =3D g_queue_new(); + + QLIST_FOREACH(sec, &bus->child, sibling) { + Aml *br_scope =3D aml_scope("S%.02X", sec->parent_dev->devfn); + if (pci_bus_is_root(sec)) { + continue; + } + nr_notifiers =3D nr_notifiers + + build_append_notification_callback(br_scope, sec); + /* + * add new child scope to parent + * and keep track of bus that have PCNT, + * bus list is used later to call children PCNTs from this level P= CNT + */ + if (nr_notifiers) { + g_queue_push_tail(pcnt_bus_list, sec); + aml_append(parent_scope, br_scope); + } + } + + /* + * Append PCNT method to notify about events on local and child buses. + * ps: hostbridge might not have hotplug (bsel) enabled but might have + * child bridges that do have bsel. + */ + method =3D aml_method("PCNT", 0, AML_NOTSERIALIZED); + + /* If bus supports hotplug select it and notify about local events */ + bsel =3D object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL= , NULL); + if (bsel) { + uint64_t bsel_val =3D qnum_get_uint(qobject_to(QNum, bsel)); + + aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); + aml_append(method, aml_call2("DVNT", aml_name("PCIU"), + aml_int(1))); /* Device Check */ + aml_append(method, aml_call2("DVNT", aml_name("PCID"), + aml_int(3))); /* Eject Request */ + nr_notifiers++; + } + + /* Notify about child bus events in any case */ + while ((sec =3D g_queue_pop_head(pcnt_bus_list))) { + aml_append(method, aml_name("^S%.02X.PCNT", sec->parent_dev->devfn= )); + } + + aml_append(parent_scope, method); + qobject_unref(bsel); + g_queue_free(pcnt_bus_list); + return !!nr_notifiers; +} + const VMStateDescription vmstate_acpi_pcihp_pci_status =3D { .name =3D "acpi_pcihp_pci_status", .version_id =3D 1, diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 6ca2b34ef8..3275675e60 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -563,64 +563,6 @@ void build_append_pci_bus_devices(Aml *parent_scope, P= CIBus *bus) } } =20 -static bool build_append_notification_callback(Aml *parent_scope, - const PCIBus *bus) -{ - Aml *method; - PCIBus *sec; - QObject *bsel; - int nr_notifiers =3D 0; - GQueue *pcnt_bus_list =3D g_queue_new(); - - QLIST_FOREACH(sec, &bus->child, sibling) { - Aml *br_scope =3D aml_scope("S%.02X", sec->parent_dev->devfn); - if (pci_bus_is_root(sec)) { - continue; - } - nr_notifiers =3D nr_notifiers + - build_append_notification_callback(br_scope, sec); - /* - * add new child scope to parent - * and keep track of bus that have PCNT, - * bus list is used later to call children PCNTs from this level P= CNT - */ - if (nr_notifiers) { - g_queue_push_tail(pcnt_bus_list, sec); - aml_append(parent_scope, br_scope); - } - } - - /* - * Append PCNT method to notify about events on local and child buses. - * ps: hostbridge might not have hotplug (bsel) enabled but might have - * child bridges that do have bsel. - */ - method =3D aml_method("PCNT", 0, AML_NOTSERIALIZED); - - /* If bus supports hotplug select it and notify about local events */ - bsel =3D object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL= , NULL); - if (bsel) { - uint64_t bsel_val =3D qnum_get_uint(qobject_to(QNum, bsel)); - - aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM"))); - aml_append(method, aml_call2("DVNT", aml_name("PCIU"), - aml_int(1))); /* Device Check */ - aml_append(method, aml_call2("DVNT", aml_name("PCID"), - aml_int(3))); /* Eject Request */ - nr_notifiers++; - } - - /* Notify about child bus events in any case */ - while ((sec =3D g_queue_pop_head(pcnt_bus_list))) { - aml_append(method, aml_name("^S%.02X.PCNT", sec->parent_dev->devfn= )); - } - - aml_append(parent_scope, method); - qobject_unref(bsel); - g_queue_free(pcnt_bus_list); - return !!nr_notifiers; -} - /* * build_prt - Define interrupt routing rules * --=20 2.49.0 From nobody Sat Nov 15 12:16:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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b=VK0szO95+E6/7yaF9XWPHdpCWxisrJe0HH+/Myl4eJbHDiPf2K48hFxoEv6VFETym4W9Ad C4ZajEBiPgAiNB7p17lTKxxJB0SO/2MgsOwoxEWBERwZmaDUDcza1gH+yP2aN2ypNglTuj VVHvEBnlcC4Rp7tNuX7eYque4sqwsac= X-MC-Unique: gfzsuWSePASa0cCbC-0n7A-1 X-Mimecast-MFC-AGG-ID: gfzsuWSePASa0cCbC-0n7A_1751546331 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, imammedo@redhat.com, Jonathan.Cameron@huawei.com, gustavo.romero@linaro.org, anisinha@redhat.com, mst@redhat.com, shannon.zhaosl@gmail.com Cc: pbonzini@redhat.com, philmd@linaro.org, alex.bennee@linaro.org Subject: [PATCH v5 14/36] hw/i386/acpi-build: Move build_append_pci_bus_devices/pcihp_slots to pcihp Date: Thu, 3 Jul 2025 14:35:14 +0200 Message-ID: <20250703123728.414386-15-eric.auger@redhat.com> In-Reply-To: <20250703123728.414386-1-eric.auger@redhat.com> References: <20250703123728.414386-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" We intend to reuse build_append_pci_bus_devices and build_append_pcihp_slots on ARM. So let's move them to hw/acpi/pcihp.c as well as all static helpers they use. No functional change intended. Signed-off-by: Eric Auger Reviewed-by: Gustavo Romero Reviewed-by: Igor Mammedov Reviewed-by: Jonathan Cameron --- v2 -> v3: - changed the layout of the commit message - reordered the moved functions to match the original ordering (Jonathan) --- include/hw/acpi/pci.h | 1 - include/hw/acpi/pcihp.h | 2 + hw/acpi/pcihp.c | 173 ++++++++++++++++++++++++++++++++++++++++ hw/i386/acpi-build.c | 172 --------------------------------------- 4 files changed, 175 insertions(+), 173 deletions(-) diff --git a/include/hw/acpi/pci.h b/include/hw/acpi/pci.h index 8a328b580c..69bae95eac 100644 --- a/include/hw/acpi/pci.h +++ b/include/hw/acpi/pci.h @@ -37,7 +37,6 @@ typedef struct AcpiMcfgInfo { void build_mcfg(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *info, const char *oem_id, const char *oem_table_id); =20 -void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus); void build_pci_bridge_aml(AcpiDevAmlIf *adev, Aml *scope); =20 void build_srat_generic_affinity_structures(GArray *table_data); diff --git a/include/hw/acpi/pcihp.h b/include/hw/acpi/pcihp.h index f4fd44cb32..5506a58862 100644 --- a/include/hw/acpi/pcihp.h +++ b/include/hw/acpi/pcihp.h @@ -80,6 +80,8 @@ void build_append_pcihp_resources(Aml *table, uint64_t io_addr, uint64_t io_len); bool build_append_notification_callback(Aml *parent_scope, const PCIBus *b= us); =20 +void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus); + /* Called on reset */ void acpi_pcihp_reset(AcpiPciHpState *s); =20 diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c index b64d06afc9..2c76edeb15 100644 --- a/hw/acpi/pcihp.c +++ b/hw/acpi/pcihp.c @@ -27,6 +27,7 @@ #include "qemu/osdep.h" #include "hw/acpi/pcihp.h" #include "hw/acpi/aml-build.h" +#include "hw/acpi/acpi_aml_interface.h" #include "hw/pci-host/i440fx.h" #include "hw/pci/pci.h" #include "hw/pci/pci_bridge.h" @@ -761,6 +762,178 @@ bool build_append_notification_callback(Aml *parent_s= cope, const PCIBus *bus) return !!nr_notifiers; } =20 +static Aml *aml_pci_device_dsm(void) +{ + Aml *method; + + method =3D aml_method("_DSM", 4, AML_SERIALIZED); + { + Aml *params =3D aml_local(0); + Aml *pkg =3D aml_package(2); + aml_append(pkg, aml_int(0)); + aml_append(pkg, aml_int(0)); + aml_append(method, aml_store(pkg, params)); + aml_append(method, + aml_store(aml_name("BSEL"), aml_index(params, aml_int(0)))); + aml_append(method, + aml_store(aml_name("ASUN"), aml_index(params, aml_int(1)))); + aml_append(method, + aml_return(aml_call5("PDSM", aml_arg(0), aml_arg(1), + aml_arg(2), aml_arg(3), params)) + ); + } + return method; +} + +static Aml *aml_pci_static_endpoint_dsm(PCIDevice *pdev) +{ + Aml *method; + + g_assert(pdev->acpi_index !=3D 0); + method =3D aml_method("_DSM", 4, AML_SERIALIZED); + { + Aml *params =3D aml_local(0); + Aml *pkg =3D aml_package(1); + aml_append(pkg, aml_int(pdev->acpi_index)); + aml_append(method, aml_store(pkg, params)); + aml_append(method, + aml_return(aml_call5("EDSM", aml_arg(0), aml_arg(1), + aml_arg(2), aml_arg(3), params)) + ); + } + return method; +} + +static void build_append_pcihp_notify_entry(Aml *method, int slot) +{ + Aml *if_ctx; + int32_t devfn =3D PCI_DEVFN(slot, 0); + + if_ctx =3D aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); + aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); + aml_append(method, if_ctx); +} + +static bool is_devfn_ignored_generic(const int devfn, const PCIBus *bus) +{ + const PCIDevice *pdev =3D bus->devices[devfn]; + + if (PCI_FUNC(devfn)) { + if (IS_PCI_BRIDGE(pdev)) { + /* + * Ignore only hotplugged PCI bridges on !0 functions, but + * allow describing cold plugged bridges on all functions + */ + if (DEVICE(pdev)->hotplugged) { + return true; + } + } + } + return false; +} + +static bool is_devfn_ignored_hotplug(const int devfn, const PCIBus *bus) +{ + PCIDevice *pdev =3D bus->devices[devfn]; + if (pdev) { + return is_devfn_ignored_generic(devfn, bus) || + !DEVICE_GET_CLASS(pdev)->hotpluggable || + /* Cold plugged bridges aren't themselves hot-pluggable */ + (IS_PCI_BRIDGE(pdev) && !DEVICE(pdev)->hotplugged); + } else { /* non populated slots */ + /* + * hotplug is supported only for non-multifunction device + * so generate device description only for function 0 + */ + if (PCI_FUNC(devfn) || + (pci_bus_is_express(bus) && PCI_SLOT(devfn) > 0)) { + return true; + } + } + return false; +} + +void build_append_pcihp_slots(Aml *parent_scope, PCIBus *bus) +{ + int devfn; + Aml *dev, *notify_method =3D NULL, *method; + QObject *bsel =3D object_property_get_qobject(OBJECT(bus), + ACPI_PCIHP_PROP_BSEL, NULL); + uint64_t bsel_val =3D qnum_get_uint(qobject_to(QNum, bsel)); + qobject_unref(bsel); + + aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); + notify_method =3D aml_method("DVNT", 2, AML_NOTSERIALIZED); + + for (devfn =3D 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { + int slot =3D PCI_SLOT(devfn); + int adr =3D slot << 16 | PCI_FUNC(devfn); + + if (is_devfn_ignored_hotplug(devfn, bus)) { + continue; + } + + if (bus->devices[devfn]) { + dev =3D aml_scope("S%.02X", devfn); + } else { + dev =3D aml_device("S%.02X", devfn); + aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); + } + + /* + * Can't declare _SUN here for every device as it changes 'slot' + * enumeration order in linux kernel, so use another variable for = it + */ + aml_append(dev, aml_name_decl("ASUN", aml_int(slot))); + aml_append(dev, aml_pci_device_dsm()); + + aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); + /* add _EJ0 to make slot hotpluggable */ + method =3D aml_method("_EJ0", 1, AML_NOTSERIALIZED); + aml_append(method, + aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) + ); + aml_append(dev, method); + + build_append_pcihp_notify_entry(notify_method, slot); + + /* device descriptor has been composed, add it into parent context= */ + aml_append(parent_scope, dev); + } + aml_append(parent_scope, notify_method); +} + +void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus) +{ + int devfn; + Aml *dev; + + for (devfn =3D 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { + /* ACPI spec: 1.0b: Table 6-2 _ADR Object Bus Types, PCI type */ + int adr =3D PCI_SLOT(devfn) << 16 | PCI_FUNC(devfn); + PCIDevice *pdev =3D bus->devices[devfn]; + + if (!pdev || is_devfn_ignored_generic(devfn, bus)) { + continue; + } + + /* start to compose PCI device descriptor */ + dev =3D aml_device("S%.02X", devfn); + aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); + + call_dev_aml_func(DEVICE(bus->devices[devfn]), dev); + /* add _DSM if device has acpi-index set */ + if (pdev->acpi_index && + !object_property_get_bool(OBJECT(pdev), "hotpluggable", + &error_abort)) { + aml_append(dev, aml_pci_static_endpoint_dsm(pdev)); + } + + /* device descriptor has been composed, add it into parent context= */ + aml_append(parent_scope, dev); + } +} + const VMStateDescription vmstate_acpi_pcihp_pci_status =3D { .name =3D "acpi_pcihp_pci_status", .version_id =3D 1, diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 3275675e60..fe8bc62c03 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -338,29 +338,6 @@ build_facs(GArray *table_data) g_array_append_vals(table_data, reserved, 40); /* Reserved */ } =20 -static Aml *aml_pci_device_dsm(void) -{ - Aml *method; - - method =3D aml_method("_DSM", 4, AML_SERIALIZED); - { - Aml *params =3D aml_local(0); - Aml *pkg =3D aml_package(2); - aml_append(pkg, aml_int(0)); - aml_append(pkg, aml_int(0)); - aml_append(method, aml_store(pkg, params)); - aml_append(method, - aml_store(aml_name("BSEL"), aml_index(params, aml_int(0)))); - aml_append(method, - aml_store(aml_name("ASUN"), aml_index(params, aml_int(1)))); - aml_append(method, - aml_return(aml_call5("PDSM", aml_arg(0), aml_arg(1), - aml_arg(2), aml_arg(3), params)) - ); - } - return method; -} - static Aml *aml_pci_edsm(void) { Aml *method, *ifctx; @@ -414,155 +391,6 @@ static Aml *aml_pci_edsm(void) return method; } =20 -static Aml *aml_pci_static_endpoint_dsm(PCIDevice *pdev) -{ - Aml *method; - - g_assert(pdev->acpi_index !=3D 0); - method =3D aml_method("_DSM", 4, AML_SERIALIZED); - { - Aml *params =3D aml_local(0); - Aml *pkg =3D aml_package(1); - aml_append(pkg, aml_int(pdev->acpi_index)); - aml_append(method, aml_store(pkg, params)); - aml_append(method, - aml_return(aml_call5("EDSM", aml_arg(0), aml_arg(1), - aml_arg(2), aml_arg(3), params)) - ); - } - return method; -} - -static void build_append_pcihp_notify_entry(Aml *method, int slot) -{ - Aml *if_ctx; - int32_t devfn =3D PCI_DEVFN(slot, 0); - - if_ctx =3D aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL)); - aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1))); - aml_append(method, if_ctx); -} - -static bool is_devfn_ignored_generic(const int devfn, const PCIBus *bus) -{ - const PCIDevice *pdev =3D bus->devices[devfn]; - - if (PCI_FUNC(devfn)) { - if (IS_PCI_BRIDGE(pdev)) { - /* - * Ignore only hotplugged PCI bridges on !0 functions, but - * allow describing cold plugged bridges on all functions - */ - if (DEVICE(pdev)->hotplugged) { - return true; - } - } - } - return false; -} - -static bool is_devfn_ignored_hotplug(const int devfn, const PCIBus *bus) -{ - PCIDevice *pdev =3D bus->devices[devfn]; - if (pdev) { - return is_devfn_ignored_generic(devfn, bus) || - !DEVICE_GET_CLASS(pdev)->hotpluggable || - /* Cold plugged bridges aren't themselves hot-pluggable */ - (IS_PCI_BRIDGE(pdev) && !DEVICE(pdev)->hotplugged); - } else { /* non populated slots */ - /* - * hotplug is supported only for non-multifunction device - * so generate device description only for function 0 - */ - if (PCI_FUNC(devfn) || - (pci_bus_is_express(bus) && PCI_SLOT(devfn) > 0)) { - return true; - } - } - return false; -} - -void build_append_pcihp_slots(Aml *parent_scope, PCIBus *bus) -{ - int devfn; - Aml *dev, *notify_method =3D NULL, *method; - QObject *bsel =3D object_property_get_qobject(OBJECT(bus), - ACPI_PCIHP_PROP_BSEL, NULL); - uint64_t bsel_val =3D qnum_get_uint(qobject_to(QNum, bsel)); - qobject_unref(bsel); - - aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val))); - notify_method =3D aml_method("DVNT", 2, AML_NOTSERIALIZED); - - for (devfn =3D 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { - int slot =3D PCI_SLOT(devfn); - int adr =3D slot << 16 | PCI_FUNC(devfn); - - if (is_devfn_ignored_hotplug(devfn, bus)) { - continue; - } - - if (bus->devices[devfn]) { - dev =3D aml_scope("S%.02X", devfn); - } else { - dev =3D aml_device("S%.02X", devfn); - aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); - } - - /* - * Can't declare _SUN here for every device as it changes 'slot' - * enumeration order in linux kernel, so use another variable for = it - */ - aml_append(dev, aml_name_decl("ASUN", aml_int(slot))); - aml_append(dev, aml_pci_device_dsm()); - - aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); - /* add _EJ0 to make slot hotpluggable */ - method =3D aml_method("_EJ0", 1, AML_NOTSERIALIZED); - aml_append(method, - aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN")) - ); - aml_append(dev, method); - - build_append_pcihp_notify_entry(notify_method, slot); - - /* device descriptor has been composed, add it into parent context= */ - aml_append(parent_scope, dev); - } - aml_append(parent_scope, notify_method); -} - -void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus) -{ - int devfn; - Aml *dev; - - for (devfn =3D 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { - /* ACPI spec: 1.0b: Table 6-2 _ADR Object Bus Types, PCI type */ - int adr =3D PCI_SLOT(devfn) << 16 | PCI_FUNC(devfn); - PCIDevice *pdev =3D bus->devices[devfn]; - - if (!pdev || is_devfn_ignored_generic(devfn, bus)) { - continue; - } - - /* start to compose PCI device descriptor */ - dev =3D aml_device("S%.02X", devfn); - aml_append(dev, aml_name_decl("_ADR", aml_int(adr))); - - call_dev_aml_func(DEVICE(bus->devices[devfn]), dev); - /* add _DSM if device has acpi-index set */ - if (pdev->acpi_index && - !object_property_get_bool(OBJECT(pdev), "hotpluggable", - &error_abort)) { - aml_append(dev, aml_pci_static_endpoint_dsm(pdev)); - } - - /* device descriptor has been composed, add it into parent context= */ - aml_append(parent_scope, dev); - } -} - /* * build_prt - Define interrupt routing rules * --=20 2.49.0 From nobody Sat Nov 15 12:16:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1751546341; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=hOnk6tUF8BEtgoK/DOmMaR/Km0pJrk/2ZiEFOx7CRQU=; b=NC0Fq1DNkx4Us3K/fLPl4+iU77PrNxDTKWxhSnZu63+m0uyR7njIuxEd6mM8wxzy19Wx23 0r8lvlEs7nKO/Z0QtJUdEHDZDeaRjD5Y0BZlbuXR8S3vwMSQ66tR+b7L4OewFgUpBZmMYk LlNi0mWH0DqRrvIuRTpO/gMKoZUf6xw= X-MC-Unique: k_7hvxCjNz29U4_dmSkw0Q-1 X-Mimecast-MFC-AGG-ID: k_7hvxCjNz29U4_dmSkw0Q_1751546336 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, imammedo@redhat.com, Jonathan.Cameron@huawei.com, gustavo.romero@linaro.org, anisinha@redhat.com, mst@redhat.com, shannon.zhaosl@gmail.com Cc: pbonzini@redhat.com, philmd@linaro.org, alex.bennee@linaro.org Subject: [PATCH v5 15/36] hw/i386/acpi-build: Use AcpiPciHpState::root in acpi_set_pci_info Date: Thu, 3 Jul 2025 14:35:15 +0200 Message-ID: <20250703123728.414386-16-eric.auger@redhat.com> In-Reply-To: <20250703123728.414386-1-eric.auger@redhat.com> References: <20250703123728.414386-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" pcihp acpi_set_pci_info() generic code currently uses acpi_get_i386_pci_host() to retrieve the pci host bridge. To make it work also on ARM we get rid of that call and directly use AcpiPciHpState::root. Signed-off-by: Eric Auger Suggested-by: Igor Mammedov Reviewed-by: Igor Mammedov Reviewed-by: Jonathan Cameron --- v2 -> v3: - Use AcpiPciHpState::root v1 -> v2 - described the fact we changed the implementation of acpi_get_pci_host() in the commit msg. --- hw/acpi/pcihp.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c index 2c76edeb15..2db2f16940 100644 --- a/hw/acpi/pcihp.c +++ b/hw/acpi/pcihp.c @@ -99,10 +99,10 @@ static void *acpi_set_bsel(PCIBus *bus, void *opaque) return info; } =20 -static void acpi_set_pci_info(bool has_bridge_hotplug) +static void acpi_set_pci_info(AcpiPciHpState *s) { static bool bsel_is_set; - Object *host =3D acpi_get_i386_pci_host(); + bool has_bridge_hotplug =3D s->use_acpi_hotplug_bridge; PCIBus *bus; BSELInfo info =3D { .bsel_alloc =3D ACPI_PCIHP_BSEL_DEFAULT, .has_bridge_hotplug =3D has_bridge_hotplug }; @@ -112,11 +112,8 @@ static void acpi_set_pci_info(bool has_bridge_hotplug) } bsel_is_set =3D true; =20 - if (!host) { - return; - } =20 - bus =3D PCI_HOST_BRIDGE(host)->bus; + bus =3D s->root; if (bus) { /* Scan all PCI buses. Set property to enable acpi based hotplug. = */ pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &info); @@ -266,7 +263,7 @@ static void acpi_pcihp_update(AcpiPciHpState *s) =20 void acpi_pcihp_reset(AcpiPciHpState *s) { - acpi_set_pci_info(s->use_acpi_hotplug_bridge); + acpi_set_pci_info(s); acpi_pcihp_update(s); } =20 --=20 2.49.0 From nobody Sat Nov 15 12:16:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1751546650; cv=none; d=zohomail.com; s=zohoarc; b=KNkiMO3tff4ty/HGAJV1QmSz4UD0AIljVtOX2DoYiPSEvDHdfXLuQByqoyKnQSYzJWXsUKKpbcLecVk8jDNjOpGhaXP73KIr5J487X6oywuypOlWS2TZf/qeCGneEiq4LCDm35AAZqtEZC6fJdz8K3n+6/E5J5jjiqipEwV2Twk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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charset="utf-8" Move aml_pci_edsm to pci-bridge.c since we want to reuse that for ARM and acpi-index support. Also rename it into build_pci_bridge_edsm. Signed-off-by: Eric Auger Reviewed-by: Jonathan Cameron --- v3->v4: - renamed into build_pci_bridge_edsm() (Jonathan, Igor) v2 -> v3: - move to pci-bridge.c instead of pcihp.c (Igor) --- include/hw/acpi/pci.h | 1 + hw/acpi/pci-bridge.c | 54 ++++++++++++++++++++++++++++++++++++++++ hw/i386/acpi-build.c | 57 ++----------------------------------------- 3 files changed, 57 insertions(+), 55 deletions(-) diff --git a/include/hw/acpi/pci.h b/include/hw/acpi/pci.h index 69bae95eac..20b672575f 100644 --- a/include/hw/acpi/pci.h +++ b/include/hw/acpi/pci.h @@ -42,5 +42,6 @@ void build_pci_bridge_aml(AcpiDevAmlIf *adev, Aml *scope); void build_srat_generic_affinity_structures(GArray *table_data); =20 Aml *build_pci_host_bridge_osc_method(bool enable_native_pcie_hotplug); +Aml *build_pci_bridge_edsm(void); =20 #endif diff --git a/hw/acpi/pci-bridge.c b/hw/acpi/pci-bridge.c index 7baa7034a1..394a919479 100644 --- a/hw/acpi/pci-bridge.c +++ b/hw/acpi/pci-bridge.c @@ -35,3 +35,57 @@ void build_pci_bridge_aml(AcpiDevAmlIf *adev, Aml *scope) } } } + +Aml *build_pci_bridge_edsm(void) +{ + Aml *method, *ifctx; + Aml *zero =3D aml_int(0); + Aml *func =3D aml_arg(2); + Aml *ret =3D aml_local(0); + Aml *aidx =3D aml_local(1); + Aml *params =3D aml_arg(4); + + method =3D aml_method("EDSM", 5, AML_SERIALIZED); + + /* get supported functions */ + ifctx =3D aml_if(aml_equal(func, zero)); + { + /* 1: have supported functions */ + /* 7: support for function 7 */ + const uint8_t caps =3D 1 | BIT(7); + build_append_pci_dsm_func0_common(ifctx, ret); + aml_append(ifctx, aml_store(aml_int(caps), aml_index(ret, zero))); + aml_append(ifctx, aml_return(ret)); + } + aml_append(method, ifctx); + + /* handle specific functions requests */ + /* + * PCI Firmware Specification 3.1 + * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under + * Operating Systems + */ + ifctx =3D aml_if(aml_equal(func, aml_int(7))); + { + Aml *pkg =3D aml_package(2); + aml_append(pkg, zero); + /* optional, if not impl. should return null string */ + aml_append(pkg, aml_string("%s", "")); + aml_append(ifctx, aml_store(pkg, ret)); + + /* + * IASL is fine when initializing Package with computational data, + * however it makes guest unhappy /it fails to process such AML/. + * So use runtime assignment to set acpi-index after initializer + * to make OSPM happy. + */ + aml_append(ifctx, + aml_store(aml_derefof(aml_index(params, aml_int(0))), aidx)); + aml_append(ifctx, aml_store(aidx, aml_index(ret, zero))); + aml_append(ifctx, aml_return(ret)); + } + aml_append(method, ifctx); + + return method; +} + diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index fe8bc62c03..423c4959fe 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -338,59 +338,6 @@ build_facs(GArray *table_data) g_array_append_vals(table_data, reserved, 40); /* Reserved */ } =20 -static Aml *aml_pci_edsm(void) -{ - Aml *method, *ifctx; - Aml *zero =3D aml_int(0); - Aml *func =3D aml_arg(2); - Aml *ret =3D aml_local(0); - Aml *aidx =3D aml_local(1); - Aml *params =3D aml_arg(4); - - method =3D aml_method("EDSM", 5, AML_SERIALIZED); - - /* get supported functions */ - ifctx =3D aml_if(aml_equal(func, zero)); - { - /* 1: have supported functions */ - /* 7: support for function 7 */ - const uint8_t caps =3D 1 | BIT(7); - build_append_pci_dsm_func0_common(ifctx, ret); - aml_append(ifctx, aml_store(aml_int(caps), aml_index(ret, zero))); - aml_append(ifctx, aml_return(ret)); - } - aml_append(method, ifctx); - - /* handle specific functions requests */ - /* - * PCI Firmware Specification 3.1 - * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under - * Operating Systems - */ - ifctx =3D aml_if(aml_equal(func, aml_int(7))); - { - Aml *pkg =3D aml_package(2); - aml_append(pkg, zero); - /* optional, if not impl. should return null string */ - aml_append(pkg, aml_string("%s", "")); - aml_append(ifctx, aml_store(pkg, ret)); - - /* - * IASL is fine when initializing Package with computational data, - * however it makes guest unhappy /it fails to process such AML/. - * So use runtime assignment to set acpi-index after initializer - * to make OSPM happy. - */ - aml_append(ifctx, - aml_store(aml_derefof(aml_index(params, aml_int(0))), aidx)); - aml_append(ifctx, aml_store(aidx, aml_index(ret, zero))); - aml_append(ifctx, aml_return(ret)); - } - aml_append(method, ifctx); - - return method; -} - /* * build_prt - Define interrupt routing rules * @@ -937,7 +884,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, dev =3D aml_device("PCI0"); aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))= ); - aml_append(dev, aml_pci_edsm()); + aml_append(dev, build_pci_bridge_edsm()); aml_append(sb_scope, dev); aml_append(dsdt, sb_scope); =20 @@ -952,7 +899,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid))= ); aml_append(dev, build_pci_host_bridge_osc_method(!pm->pcihp_bridge= _en)); - aml_append(dev, aml_pci_edsm()); + aml_append(dev, build_pci_bridge_edsm()); aml_append(sb_scope, dev); if (mcfg_valid) { aml_append(sb_scope, build_q35_dram_controller(&mcfg)); --=20 2.49.0 From nobody Sat Nov 15 12:16:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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b=Drtw5v9egekJd3luB6SvJhbVwYl18GpQl6gZp0HeUOtkre2ASD7I7avoSXEuPyufeVwYQl tLZlJJtdpLaWFp74TBu+Z/kU5T7DEAGfrizFf4w39a3N8zoTUwbEml2sWTw7UyvTDYCqmO u0U+ngKSAIb5c4tu8//fZX08pUyJ8AY= X-MC-Unique: JHG7LUgnNhGG7rxeiYBP3w-1 X-Mimecast-MFC-AGG-ID: JHG7LUgnNhGG7rxeiYBP3w_1751546346 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, imammedo@redhat.com, Jonathan.Cameron@huawei.com, gustavo.romero@linaro.org, anisinha@redhat.com, mst@redhat.com, shannon.zhaosl@gmail.com Cc: pbonzini@redhat.com, philmd@linaro.org, alex.bennee@linaro.org Subject: [PATCH v5 17/36] qtest/bios-tables-test: Prepare for fixing the aarch64 viot test Date: Thu, 3 Jul 2025 14:35:17 +0200 Message-ID: <20250703123728.414386-18-eric.auger@redhat.com> In-Reply-To: <20250703123728.414386-1-eric.auger@redhat.com> References: <20250703123728.414386-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" The test misses a variant and this puts the mess on subsequent rebuild-expected-aml.sh where a first DSDT reference blob is overriden by another one. Signed-off-by: Eric Auger Reviewed-by: Jonathan Cameron --- tests/qtest/bios-tables-test-allowed-diff.h | 1 + tests/data/acpi/aarch64/virt/DSDT.viot | 0 2 files changed, 1 insertion(+) create mode 100644 tests/data/acpi/aarch64/virt/DSDT.viot diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index dfb8523c8b..7a74beab3d 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,2 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/aarch64/virt/DSDT.viot", diff --git a/tests/data/acpi/aarch64/virt/DSDT.viot b/tests/data/acpi/aarch= 64/virt/DSDT.viot new file mode 100644 index 0000000000..e69de29bb2 --=20 2.49.0 From nobody Sat Nov 15 12:16:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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b=SUcRUhqvlA52BnoSUXhHv4eSf9PUwxtf3p/nOruUdymL7PEwjbC8cxV+8jTNe8uWo0EDXO tH+vvmzhHOuu2ae6vbLu02KDFMViYRgbNgTZmPDetZsOXvEBZ+69XU9z93/pSOuZ4SSkoZ LMl2HWuU0niFmRt0Zrks20+3RbcAnE0= X-MC-Unique: rkDMllXtOcWVCqK4g6-yqQ-1 X-Mimecast-MFC-AGG-ID: rkDMllXtOcWVCqK4g6-yqQ_1751546351 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, imammedo@redhat.com, Jonathan.Cameron@huawei.com, gustavo.romero@linaro.org, anisinha@redhat.com, mst@redhat.com, shannon.zhaosl@gmail.com Cc: pbonzini@redhat.com, philmd@linaro.org, alex.bennee@linaro.org Subject: [PATCH v5 18/36] qtest/bios-tables-test: Add a variant to the aarch64 viot test Date: Thu, 3 Jul 2025 14:35:18 +0200 Message-ID: <20250703123728.414386-19-eric.auger@redhat.com> In-Reply-To: <20250703123728.414386-1-eric.auger@redhat.com> References: <20250703123728.414386-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Signed-off-by: Eric Auger --- tests/qtest/bios-tables-test.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index 4dbc07ec5e..357bcefd37 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -2237,6 +2237,7 @@ static void test_acpi_aarch64_virt_viot(void) test_data data =3D { .machine =3D "virt", .arch =3D "aarch64", + .variant =3D ".viot", .tcg_only =3D true, .uefi_fl1 =3D "pc-bios/edk2-aarch64-code.fd", .uefi_fl2 =3D "pc-bios/edk2-arm-vars.fd", --=20 2.49.0 From nobody Sat Nov 15 12:16:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1751546757; cv=none; d=zohomail.com; s=zohoarc; b=fCFF9yV2u2P9eC8Vp434TBNjzZfu/MJE9dHMfuZOtlfdI7sd3Btms28Ki3FyVNBZW8r73sL4be7xhmSFhYYonUTsTHtbVV5fhgS0i69rLoeu0PiS82hUoFk+bzwHRpioo71JRGlkaDU7G+uFmXVx8+nm7ZYQADbRbUzNMQklt+A= ARC-Message-Signature: i=1; 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charset="utf-8" Use a specific DSDT.viot reference blob instead of relying on the default DSDT blob. The context has not changed. Signed-off-by: Eric Auger --- tests/qtest/bios-tables-test-allowed-diff.h | 1 - tests/data/acpi/aarch64/virt/DSDT.viot | Bin 0 -> 5158 bytes 2 files changed, 1 deletion(-) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index 7a74beab3d..dfb8523c8b 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,2 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/aarch64/virt/DSDT.viot", diff --git a/tests/data/acpi/aarch64/virt/DSDT.viot b/tests/data/acpi/aarch= 64/virt/DSDT.viot index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..acab6e65febbc210158d4c39be0= 680bbb90250f5 100644 GIT binary patch literal 5158 zcmZvg%WoT16o=3D2)6MH;|y)ALqOG8=3DsMmZ^!NIT`CYo z{%G$y+itD>`OvA=3DYBi0B)V=3Dz)p54~&Pu%uod|Y;H+cqZKy-vF2412b1uahyk+w0Ky z_`0(@2**Z)ZQHKbgE3>`jNEM5EIv<=3D0w%~J`Y}eDc7ceV(D-;`bKlwYxu10hcWv8l zkTG%hT4vIiI8ICR5m__iBO-}X5ZTi2jlwPUcSgImZLgg#JBvJD+@wgbxXlrDe|1Et zW#2$V7@{5^+G-aK31LPghRzrb&S;8^sKkgdMw2tHhzwm~7>sd+GuA}LoWw90V~sPe zij0`VNHNA$&R7>2afy*(jCIb~5E+KVuoz>5Gp>n@gv7`(#x=3D&M2QLSvm}yFk0%Kg~ z3^7gdB?(h~kug5z3^`9z(mqOzaf37DJWWfCGGpB23^`9T5~IQxw>U%2(|L)p${3$; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1751546367; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ygV87S2dsgtc2njtsuKJl/dqXurPzUNwHztllmOt+EI=; b=BJfVXAhhDEevdABMiN04Ye+oH9pMuXNiB71l/uslQeALo3gDR1d9mrCsK8Hrd5hQH+G7D5 KI1xDhGV2PocdrAXtS1cEDgznS4FTnddU035HHspF2SUsn0MI5FBbkBJKV0YQZ1wWzsVXp OQQ4i4p8P1OUB/8X6DyebFG1V2vTcMg= X-MC-Unique: 6XitAmLWP46S3Cn6jqhvdA-1 X-Mimecast-MFC-AGG-ID: 6XitAmLWP46S3Cn6jqhvdA_1751546362 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, imammedo@redhat.com, Jonathan.Cameron@huawei.com, gustavo.romero@linaro.org, anisinha@redhat.com, mst@redhat.com, shannon.zhaosl@gmail.com Cc: pbonzini@redhat.com, philmd@linaro.org, alex.bennee@linaro.org Subject: [PATCH v5 20/36] tests/qtest/bios-tables-test: Prepare for changes in the arm virt DSDT table Date: Thu, 3 Jul 2025 14:35:20 +0200 Message-ID: <20250703123728.414386-21-eric.auger@redhat.com> In-Reply-To: <20250703123728.414386-1-eric.auger@redhat.com> References: <20250703123728.414386-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: Gustavo Romero This commit adds DSDT blobs to the whilelist in the prospect to allow changes in the arm virt DSDT method. Signed-off-by: Gustavo Romero Signed-off-by: Eric Auger Reviewed-by: Jonathan Cameron --- --- tests/qtest/bios-tables-test-allowed-diff.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index dfb8523c8b..023fbc6059 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,7 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/aarch64/virt/DSDT", +"tests/data/acpi/aarch64/virt/DSDT.acpihmatvirt", +"tests/data/acpi/aarch64/virt/DSDT.memhp", +"tests/data/acpi/aarch64/virt/DSDT.pxb", +"tests/data/acpi/aarch64/virt/DSDT.topology", +"tests/data/acpi/aarch64/virt/DSDT.viot", --=20 2.49.0 From nobody Sat Nov 15 12:16:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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b=iFUw0QaJoBOx1aOcbmPCdsatgUqtwVxq+eVw3nC4iUu6m0WrgmAeZ7eg8HdbR5hrv2ZVrB NtJ1BQzkDphERdztljJRvOW3TOOmis2yEwDEp8ZXOVnw4mbQdVq9Znt1L9SGxBTS2wFicB fMQu5k81i6YaxSXhdYj7ZFdwg/sjtXA= X-MC-Unique: 1kmE7PvZMZ2Dz1eNpcU0nA-1 X-Mimecast-MFC-AGG-ID: 1kmE7PvZMZ2Dz1eNpcU0nA_1751546367 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, imammedo@redhat.com, Jonathan.Cameron@huawei.com, gustavo.romero@linaro.org, anisinha@redhat.com, mst@redhat.com, shannon.zhaosl@gmail.com Cc: pbonzini@redhat.com, philmd@linaro.org, alex.bennee@linaro.org Subject: [PATCH v5 21/36] hw/arm/virt-acpi-build: Let non hotplug ports support static acpi-index Date: Thu, 3 Jul 2025 14:35:21 +0200 Message-ID: <20250703123728.414386-22-eric.auger@redhat.com> In-Reply-To: <20250703123728.414386-1-eric.auger@redhat.com> References: <20250703123728.414386-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" hw/arm/virt-acpi-build: Let non hotplug ports support static acpi-index Add the requested ACPI bits requested to support static acpi-index for non hotplug ports. Signed-off-by: Eric Auger Reviewed-by: Jonathan Cameron --- hw/arm/virt-acpi-build.c | 12 ++++++++++++ hw/arm/Kconfig | 2 ++ 2 files changed, 14 insertions(+) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index a2f31be9ec..1f936516b3 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -34,6 +34,7 @@ #include "hw/core/cpu.h" #include "hw/acpi/acpi-defs.h" #include "hw/acpi/acpi.h" +#include "hw/acpi/pcihp.h" #include "hw/nvram/fw_cfg_acpi.h" #include "hw/acpi/bios-linker-loader.h" #include "hw/acpi/aml-build.h" @@ -883,6 +884,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) const int *irqmap =3D vms->irqmap; AcpiTable table =3D { .sig =3D "DSDT", .rev =3D 2, .oem_id =3D vms->oe= m_id, .oem_table_id =3D vms->oem_table_id }; + Aml *pci0_scope; =20 acpi_table_begin(&table, table_data); dsdt =3D init_aml_allocator(); @@ -936,6 +938,16 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, Vir= tMachineState *vms) =20 aml_append(dsdt, scope); =20 + pci0_scope =3D aml_scope("\\_SB.PCI0"); + + aml_append(pci0_scope, build_pci_bridge_edsm()); + build_append_pci_bus_devices(pci0_scope, vms->bus); + if (object_property_find(OBJECT(vms->bus), ACPI_PCIHP_PROP_BSEL)) { + build_append_pcihp_slots(pci0_scope, vms->bus); + } + + aml_append(dsdt, pci0_scope); + /* copy AML table into ACPI tables blob */ g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); =20 diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index f543d944c3..dee4d6dd25 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -34,6 +34,8 @@ config ARM_VIRT select ACPI_HW_REDUCED select ACPI_APEI select ACPI_VIOT + select ACPI_PCIHP + select ACPI_PCI_BRIDGE select VIRTIO_MEM_SUPPORTED select ACPI_CXL select ACPI_HMAT --=20 2.49.0 From nobody Sat Nov 15 12:16:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 03 Jul 2025 08:39:33 -0400 Received: from mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.111]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 5267D1808984; Thu, 3 Jul 2025 12:39:32 +0000 (UTC) Received: from laptop.redhat.com (unknown [10.44.32.16]) by mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id CFBA918046C3; Thu, 3 Jul 2025 12:39:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1751546377; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=QHc3Q09Dqigb/sMudrL+aWhQqpvZQb0rLxzCywU8qmM=; b=KGQal9ZU3gFkhZberovpdOmBP4slI43VRyJBmQ8W+AnMt9/r/mTLNnTmwUzXxGW6T2vfGt UDJ28+/kDYtB6zB1woJlc0mxT4nFsr1+iku8jOHUPcQj6ElPAoU56A5meWG/KvPbCuMt9E pWsxLJvuruPlZxknrWxRrq0cxjEzt9c= X-MC-Unique: KN4jHzLkPtGrqItv1J7z9Q-1 X-Mimecast-MFC-AGG-ID: KN4jHzLkPtGrqItv1J7z9Q_1751546372 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, imammedo@redhat.com, Jonathan.Cameron@huawei.com, gustavo.romero@linaro.org, anisinha@redhat.com, mst@redhat.com, shannon.zhaosl@gmail.com Cc: pbonzini@redhat.com, philmd@linaro.org, alex.bennee@linaro.org Subject: [PATCH v5 22/36] tests/qtest/bios-tables-test: Update ARM DSDT reference blobs Date: Thu, 3 Jul 2025 14:35:22 +0200 Message-ID: <20250703123728.414386-23-eric.auger@redhat.com> In-Reply-To: <20250703123728.414386-1-eric.auger@redhat.com> References: <20250703123728.414386-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Changes relate to the introduction of pieces related to acpi-index static support along with root ports with no hotplug. + + Scope (\_SB.PCI0) + { + Method (EDSM, 5, Serialized) + { + If ((Arg2 =3D=3D Zero)) + { + Local0 =3D Buffer (One) + { + 0x00 = // . + } + If ((Arg0 !=3D ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c343= 4d") /* Device Labeling Interface */)) + { + Return (Local0) + } + + If ((Arg1 < 0x02)) + { + Return (Local0) + } + + Local0 [Zero] =3D 0x81 + Return (Local0) + } + + If ((Arg2 =3D=3D 0x07)) + { + Local0 =3D Package (0x02) + { + Zero, + "" + } + Local1 =3D DerefOf (Arg4 [Zero]) + Local0 [Zero] =3D Local1 + Return (Local0) + } + } + + Device (S00) + { + Name (_ADR, Zero) // _ADR: Address + } + + Device (S08) + { + Name (_ADR, 0x00010000) // _ADR: Address + } + + Device (S10) + { + Name (_ADR, 0x00020000) // _ADR: Address + } + } } Signed-off-by: Eric Auger --- tests/qtest/bios-tables-test-allowed-diff.h | 6 ------ tests/data/acpi/aarch64/virt/DSDT | Bin 5158 -> 5293 bytes .../data/acpi/aarch64/virt/DSDT.acpihmatvirt | Bin 5244 -> 5379 bytes tests/data/acpi/aarch64/virt/DSDT.memhp | Bin 6519 -> 6654 bytes tests/data/acpi/aarch64/virt/DSDT.pxb | Bin 7603 -> 7768 bytes tests/data/acpi/aarch64/virt/DSDT.topology | Bin 5360 -> 5495 bytes tests/data/acpi/aarch64/virt/DSDT.viot | Bin 5158 -> 5310 bytes 7 files changed, 6 deletions(-) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index 023fbc6059..dfb8523c8b 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,7 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/aarch64/virt/DSDT", -"tests/data/acpi/aarch64/virt/DSDT.acpihmatvirt", -"tests/data/acpi/aarch64/virt/DSDT.memhp", -"tests/data/acpi/aarch64/virt/DSDT.pxb", -"tests/data/acpi/aarch64/virt/DSDT.topology", -"tests/data/acpi/aarch64/virt/DSDT.viot", diff --git a/tests/data/acpi/aarch64/virt/DSDT b/tests/data/acpi/aarch64/vi= rt/DSDT index acab6e65febbc210158d4c39be0680bbb90250f5..18d97e8f22979411a528705c0e3= 14acb424bbfa5 100644 GIT binary patch delta 156 zcmZ3cu~w7ICDM6Gl delta 19 acmZ3hxlDu0CDC8qh84&E4EZYD8 delta 19 acmexo{N0GlCDFq|YTuA^&WCm0K diff --git a/tests/data/acpi/aarch64/virt/DSDT.pxb b/tests/data/acpi/aarch6= 4/virt/DSDT.pxb index 7fdbc03e2bf9fb7d35704779253de36e362f0bf9..c2779882494e16920787b8ab7b4= cb3c3b70f224b 100644 GIT binary patch delta 168 zcmdmNeZz*!CD2+L6)WZd delta 19 acmca%v)P)HJ2nXCn0iZX7Xs@xe~<0nVNVBHpa7F2TOM3(O{GF%$?g zGcqJBkeW0(Lr|DY;DY(dr@^LGz7xe?`AQyk_Fa;&fPHEv7t@l20M6GC8qh84& (p=quarantine dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1751546646207368.53244422148896; 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Thu, 3 Jul 2025 12:39:37 +0000 (UTC) Received: from laptop.redhat.com (unknown [10.44.32.16]) by mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id D637818046C7; Thu, 3 Jul 2025 12:39:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1751546383; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=/5nu6NuITo203ftGtrA2lpVLlTccJCwkIpBLYxqRRHk=; b=X/Y+ylZNnYb3RFBoqFj5Nunxf8qzgmTzLNlFqxoR4xJtmIBJeG2B7Hs2lrRAwIFBlnZA/n mg494gDcXv4NDegjJpiEuwXuRUPS2tVkYO/VLaxrlCRTGlCykfvYwZdJsb/SpKbdjdx0px 1ssGvhMhsHKUEaU1uGUeMaSch0JangU= X-MC-Unique: sa5SmMAUM1GPP3xwbw5XxQ-1 X-Mimecast-MFC-AGG-ID: sa5SmMAUM1GPP3xwbw5XxQ_1751546377 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, imammedo@redhat.com, Jonathan.Cameron@huawei.com, gustavo.romero@linaro.org, anisinha@redhat.com, mst@redhat.com, shannon.zhaosl@gmail.com Cc: pbonzini@redhat.com, philmd@linaro.org, alex.bennee@linaro.org Subject: [PATCH v5 23/36] hw/arm/virt-acpi-build: Modify the DSDT ACPI table to enable ACPI PCI hotplug Date: Thu, 3 Jul 2025 14:35:23 +0200 Message-ID: <20250703123728.414386-24-eric.auger@redhat.com> In-Reply-To: <20250703123728.414386-1-eric.auger@redhat.com> References: <20250703123728.414386-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Modify the DSDT ACPI table to enable ACPI PCI hotplug. Signed-off-by: Eric Auger Reviewed-by: Jonathan Cameron --- v4 -> v5: - protect the access to the ged property by an acpi_dev check v3 -> v4: - use property accessor - removed ACPI_PCIHP_SIZE which is already in the header - make addition of EDSM unconditional v2 -> v3: - use ACPI_PCIHP_SIZE instead of 0x1000 (Igor) - use cihp_state->use_acpi_hotplug_bridge --- include/hw/acpi/pcihp.h | 2 ++ include/hw/arm/virt.h | 1 + hw/acpi/pcihp.c | 1 - hw/arm/virt-acpi-build.c | 17 +++++++++++++++++ hw/arm/virt.c | 2 ++ 5 files changed, 22 insertions(+), 1 deletion(-) diff --git a/include/hw/acpi/pcihp.h b/include/hw/acpi/pcihp.h index 5506a58862..9ff548650b 100644 --- a/include/hw/acpi/pcihp.h +++ b/include/hw/acpi/pcihp.h @@ -38,6 +38,8 @@ #define ACPI_PCIHP_SEJ_BASE 0x8 #define ACPI_PCIHP_BNMR_BASE 0x10 =20 +#define ACPI_PCIHP_SIZE 0x0018 + typedef struct AcpiPciHpPciStatus { uint32_t up; uint32_t down; diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 9a1b0f53d2..0ed2e6b732 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -79,6 +79,7 @@ enum { VIRT_ACPI_GED, VIRT_NVDIMM_ACPI, VIRT_PVTIME, + VIRT_ACPI_PCIHP, VIRT_LOWMEMMAP_LAST, }; =20 diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c index 2db2f16940..f1594e664a 100644 --- a/hw/acpi/pcihp.c +++ b/hw/acpi/pcihp.c @@ -43,7 +43,6 @@ #include "qobject/qnum.h" #include "trace.h" =20 -#define ACPI_PCIHP_SIZE 0x0018 #define PCI_UP_BASE 0x0000 #define PCI_DOWN_BASE 0x0004 #define PCI_EJ_BASE 0x0008 diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 1f936516b3..14eb775b0c 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -946,6 +946,23 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, Vir= tMachineState *vms) build_append_pcihp_slots(pci0_scope, vms->bus); } =20 + if (vms->acpi_dev) { + bool acpi_pcihp; + + acpi_pcihp =3D object_property_get_bool(OBJECT(vms->acpi_dev), + ACPI_PM_PROP_ACPI_PCIHP_BRID= GE, + NULL); + + if (acpi_pcihp) { + build_acpi_pci_hotplug(dsdt, AML_SYSTEM_MEMORY, + memmap[VIRT_ACPI_PCIHP].base); + build_append_pcihp_resources(pci0_scope, + memmap[VIRT_ACPI_PCIHP].base, + memmap[VIRT_ACPI_PCIHP].size); + + build_append_notification_callback(pci0_scope, vms->bus); + } + } aml_append(dsdt, pci0_scope); =20 /* copy AML table into ACPI tables blob */ diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 3bcdf92e2f..8024a0b6b3 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -75,6 +75,7 @@ #include "standard-headers/linux/input.h" #include "hw/arm/smmuv3.h" #include "hw/acpi/acpi.h" +#include "hw/acpi/pcihp.h" #include "target/arm/cpu-qom.h" #include "target/arm/internals.h" #include "target/arm/multiprocessing.h" @@ -183,6 +184,7 @@ static const MemMapEntry base_memmap[] =3D { [VIRT_NVDIMM_ACPI] =3D { 0x09090000, NVDIMM_ACPI_IO_LEN}, [VIRT_PVTIME] =3D { 0x090a0000, 0x00010000 }, [VIRT_SECURE_GPIO] =3D { 0x090b0000, 0x00001000 }, + [VIRT_ACPI_PCIHP] =3D { 0x090c0000, ACPI_PCIHP_SIZE }, [VIRT_MMIO] =3D { 0x0a000000, 0x00000200 }, /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that siz= e */ [VIRT_PLATFORM_BUS] =3D { 0x0c000000, 0x02000000 }, --=20 2.49.0 From nobody Sat Nov 15 12:16:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1751546387; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gui6+S19PIPTP0HqJYWTL54xHSgeFPP1n+ZMQjEgGiQ=; b=Va0zMMjysE439AzLXfXZVQAZGxTKdHVQcxC3nPnS7WKdNSH9Yj9ByMW7ZJfcB1+bSmitnL 5FEY5rYjN1CLNZs3BMZVUjO8EwKhivptM37R8IeBHmwiXqKefuoGZ/L8+WI8pUeH4JdPfG 5QyC0hYkazrgJWhehdHFGP2sXJTMghs= X-MC-Unique: s7LHlYcxPsWGAwPJTR7idw-1 X-Mimecast-MFC-AGG-ID: s7LHlYcxPsWGAwPJTR7idw_1751546382 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, imammedo@redhat.com, Jonathan.Cameron@huawei.com, gustavo.romero@linaro.org, anisinha@redhat.com, mst@redhat.com, shannon.zhaosl@gmail.com Cc: pbonzini@redhat.com, philmd@linaro.org, alex.bennee@linaro.org Subject: [PATCH v5 24/36] hw/acpi/ged: Add a bus link property Date: Thu, 3 Jul 2025 14:35:24 +0200 Message-ID: <20250703123728.414386-25-eric.auger@redhat.com> In-Reply-To: <20250703123728.414386-1-eric.auger@redhat.com> References: <20250703123728.414386-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" This property will be set by the machine code on the object creation. It will be used by acpi pcihp hotplug code. Signed-off-by: Eric Auger Reviewed-by: Igor Mammedov Reviewed-by: Jonathan Cameron --- hw/acpi/generic_event_device.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c index 7831db412b..ef1c1ec51f 100644 --- a/hw/acpi/generic_event_device.c +++ b/hw/acpi/generic_event_device.c @@ -13,6 +13,7 @@ #include "qapi/error.h" #include "hw/acpi/acpi.h" #include "hw/acpi/generic_event_device.h" +#include "hw/pci/pci.h" #include "hw/irq.h" #include "hw/mem/pc-dimm.h" #include "hw/mem/nvdimm.h" @@ -320,6 +321,8 @@ static const Property acpi_ged_properties[] =3D { DEFINE_PROP_UINT32("ged-event", AcpiGedState, ged_event_bitmap, 0), DEFINE_PROP_BOOL(ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, AcpiGedState, pcihp_state.use_acpi_hotplug_bridge, 0), + DEFINE_PROP_LINK("bus", AcpiGedState, pcihp_state.root, + TYPE_PCI_BUS, PCIBus *), }; =20 static const VMStateDescription vmstate_memhp_state =3D { --=20 2.49.0 From nobody Sat Nov 15 12:16:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1751546392; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=VIeycjAWB5Y3e/OsAKShYgyRoeDu8FNvB+cY9/fz4GA=; b=K7iRejc8Y9Ukc9NbgoDSzWb8LgKyU44Nb1nCwr8XaxjjcwBsb1ZhvJvII6AScPX7hM9dTL RYzOmJ96yFaZ2ahMCENSzq5KLcvdz4jDw1HJl/TWLJDVnpHKtiwlhbYnPA/vdDR7ejSm2l o46Wm1fBAHzJ1MPlbemHXTeqxI//83c= X-MC-Unique: Kr2yfSAtNgu7CS-346mANg-1 X-Mimecast-MFC-AGG-ID: Kr2yfSAtNgu7CS-346mANg_1751546387 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, imammedo@redhat.com, Jonathan.Cameron@huawei.com, gustavo.romero@linaro.org, anisinha@redhat.com, mst@redhat.com, shannon.zhaosl@gmail.com Cc: pbonzini@redhat.com, philmd@linaro.org, alex.bennee@linaro.org Subject: [PATCH v5 25/36] hw/arm/virt: Pass the bus on the ged creation Date: Thu, 3 Jul 2025 14:35:25 +0200 Message-ID: <20250703123728.414386-26-eric.auger@redhat.com> In-Reply-To: <20250703123728.414386-1-eric.auger@redhat.com> References: <20250703123728.414386-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" The bus will be needed on ged realize for acpi pci hp setup. Signed-off-by: Eric Auger Reviewed-by: Jonathan Cameron --- hw/arm/virt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 8024a0b6b3..34a3831530 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -696,6 +696,7 @@ static inline DeviceState *create_acpi_ged(VirtMachineS= tate *vms) =20 dev =3D qdev_new(TYPE_ACPI_GED); qdev_prop_set_uint32(dev, "ged-event", event); + object_property_set_link(OBJECT(dev), "bus", OBJECT(vms->bus), &error_= abort); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); =20 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].bas= e); --=20 2.49.0 From nobody Sat Nov 15 12:16:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; 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charset="utf-8" Add PCI device related code in the TYPE_HOTPLUG_HANDLER implementation. For a PCI device hotplug/hotunplug event, the code routes to acpi_pcihp_device callbacks (pre_plug_cb, plug_cb, unplug_request_cb, unplug_cb). Signed-off-by: Eric Auger Reviewed-by: Igor Mammedov Reviewed-by: Jonathan Cameron --- v2 -> v4: moved before "hw/acpi/ged: Prepare the device to react to PCI hotplug events" (Igor) v2 -> v3: - remove else block in acpi_ged_device_pre_plug_cb --- hw/acpi/generic_event_device.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c index ef1c1ec51f..92b931758f 100644 --- a/hw/acpi/generic_event_device.c +++ b/hw/acpi/generic_event_device.c @@ -17,6 +17,7 @@ #include "hw/irq.h" #include "hw/mem/pc-dimm.h" #include "hw/mem/nvdimm.h" +#include "hw/pci/pci_device.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" #include "qemu/error-report.h" @@ -228,6 +229,14 @@ static const MemoryRegionOps ged_regs_ops =3D { }, }; =20 +static void acpi_ged_device_pre_plug_cb(HotplugHandler *hotplug_dev, + DeviceState *dev, Error **errp) +{ + if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { + acpi_pcihp_device_pre_plug_cb(hotplug_dev, dev, errp); + } +} + static void acpi_ged_device_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp) { @@ -241,6 +250,8 @@ static void acpi_ged_device_plug_cb(HotplugHandler *hot= plug_dev, } } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { acpi_cpu_plug_cb(hotplug_dev, &s->cpuhp_state, dev, errp); + } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { + acpi_pcihp_device_plug_cb(hotplug_dev, &s->pcihp_state, dev, errp); } else { error_setg(errp, "virt: device plug request for unsupported device" " type: %s", object_get_typename(OBJECT(dev))); @@ -257,6 +268,9 @@ static void acpi_ged_unplug_request_cb(HotplugHandler *= hotplug_dev, acpi_memory_unplug_request_cb(hotplug_dev, &s->memhp_state, dev, e= rrp); } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { acpi_cpu_unplug_request_cb(hotplug_dev, &s->cpuhp_state, dev, errp= ); + } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { + acpi_pcihp_device_unplug_request_cb(hotplug_dev, &s->pcihp_state, + dev, errp); } else { error_setg(errp, "acpi: device unplug request for unsupported devi= ce" " type: %s", object_get_typename(OBJECT(dev))); @@ -272,6 +286,8 @@ static void acpi_ged_unplug_cb(HotplugHandler *hotplug_= dev, acpi_memory_unplug_cb(&s->memhp_state, dev, errp); } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { acpi_cpu_unplug_cb(&s->cpuhp_state, dev, errp); + } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { + acpi_pcihp_device_unplug_cb(hotplug_dev, &s->pcihp_state, dev, err= p); } else { error_setg(errp, "acpi: device unplug for unsupported device" " type: %s", object_get_typename(OBJECT(dev))); @@ -485,6 +501,7 @@ static void acpi_ged_class_init(ObjectClass *class, con= st void *data) dc->vmsd =3D &vmstate_acpi_ged; dc->realize =3D acpi_ged_realize; =20 + hc->pre_plug =3D acpi_ged_device_pre_plug_cb; hc->plug =3D acpi_ged_device_plug_cb; hc->unplug_request =3D acpi_ged_unplug_request_cb; hc->unplug =3D acpi_ged_unplug_cb; --=20 2.49.0 From nobody Sat Nov 15 12:16:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1751546405; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qykNbq9Z1KR/RSUyv3WPhqM899KG4p1hewVkFgNUlDM=; b=iaaRnoVvoE+DVEDW4CwKjW8+qQy2z5ATfObcAPxN/Ct1JL+MLiKiJ9qGXca/XEG8UNx4WX fpWYlpESpDYFx12fvav6zywMWGubbuMaSrm9n2HogWTKRfA3lcUoMQ5SMaXAUJB8mih7Fp ky6ft1hL0ZC/HUwv37+ipF1EyMidN0Q= X-MC-Unique: 0qgx4O3_Op6RVLD_Q77E_A-1 X-Mimecast-MFC-AGG-ID: 0qgx4O3_Op6RVLD_Q77E_A_1751546398 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, imammedo@redhat.com, Jonathan.Cameron@huawei.com, gustavo.romero@linaro.org, anisinha@redhat.com, mst@redhat.com, shannon.zhaosl@gmail.com Cc: pbonzini@redhat.com, philmd@linaro.org, alex.bennee@linaro.org Subject: [PATCH v5 27/36] hw/acpi/pcihp: Remove root arg in acpi_pcihp_init Date: Thu, 3 Jul 2025 14:35:27 +0200 Message-ID: <20250703123728.414386-28-eric.auger@redhat.com> In-Reply-To: <20250703123728.414386-1-eric.auger@redhat.com> References: <20250703123728.414386-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Let pass the root bus to ich9 and piix4 through a property link instead of through an argument passed to acpi_pcihp_init(). Also make sure the root bus is set at the entry of acpi_pcihp_init(). The rationale of that change is to be consistent with the forecoming ARM implementation where the machine passes the root bus (steming from GPEX) to the GED device through a link property. Signed-off-by: Eric Auger Suggested-by: Igor Mammedov Reviewed-by: Jonathan Cameron --- include/hw/acpi/pcihp.h | 2 +- hw/acpi/acpi-pci-hotplug-stub.c | 2 +- hw/acpi/ich9.c | 7 ++++++- hw/acpi/pcihp.c | 4 ++-- hw/acpi/piix4.c | 5 ++++- 5 files changed, 14 insertions(+), 6 deletions(-) diff --git a/include/hw/acpi/pcihp.h b/include/hw/acpi/pcihp.h index 9ff548650b..ca6a258825 100644 --- a/include/hw/acpi/pcihp.h +++ b/include/hw/acpi/pcihp.h @@ -62,7 +62,7 @@ typedef struct AcpiPciHpState { bool use_acpi_root_pci_hotplug; } AcpiPciHpState; =20 -void acpi_pcihp_init(Object *owner, AcpiPciHpState *, PCIBus *root, +void acpi_pcihp_init(Object *owner, AcpiPciHpState *, MemoryRegion *io, uint16_t io_base); =20 bool acpi_pcihp_is_hotpluggable_bus(AcpiPciHpState *s, BusState *bus); diff --git a/hw/acpi/acpi-pci-hotplug-stub.c b/hw/acpi/acpi-pci-hotplug-stu= b.c index b7bc6e40a1..d58ea726a8 100644 --- a/hw/acpi/acpi-pci-hotplug-stub.c +++ b/hw/acpi/acpi-pci-hotplug-stub.c @@ -4,7 +4,7 @@ =20 const VMStateDescription vmstate_acpi_pcihp_pci_status; =20 -void acpi_pcihp_init(Object *owner, AcpiPciHpState *s, PCIBus *root_bus, +void acpi_pcihp_init(Object *owner, AcpiPciHpState *s, MemoryRegion *address_space_io, uint16_t io_base) { } diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c index 967b67485e..2b3b493c01 100644 --- a/hw/acpi/ich9.c +++ b/hw/acpi/ich9.c @@ -322,9 +322,10 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *p= m, qemu_irq sci_irq) } =20 if (pm->acpi_pci_hotplug.use_acpi_hotplug_bridge) { + object_property_set_link(OBJECT(lpc_pci), "bus", + OBJECT(pci_get_bus(lpc_pci)), &error_abor= t); acpi_pcihp_init(OBJECT(lpc_pci), &pm->acpi_pci_hotplug, - pci_get_bus(lpc_pci), pci_address_space_io(lpc_pci), ACPI_PCIHP_ADDR_ICH9); =20 @@ -428,6 +429,10 @@ void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs= *pm) =20 object_property_add_uint32_ptr(obj, ACPI_PM_PROP_PM_IO_BASE, &pm->pm_io_base, OBJ_PROP_FLAG_READ); + object_property_add_link(obj, "bus", TYPE_PCI_BUS, + (Object **)&pm->acpi_pci_hotplug.root, + object_property_allow_set_link, + OBJ_PROP_LINK_STRONG); object_property_add(obj, ACPI_PM_PROP_GPE0_BLK, "uint32", ich9_pm_get_gpe0_blk, NULL, NULL, pm); diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c index f1594e664a..4922bbc778 100644 --- a/hw/acpi/pcihp.c +++ b/hw/acpi/pcihp.c @@ -493,13 +493,13 @@ static const MemoryRegionOps acpi_pcihp_io_ops =3D { }, }; =20 -void acpi_pcihp_init(Object *owner, AcpiPciHpState *s, PCIBus *root_bus, +void acpi_pcihp_init(Object *owner, AcpiPciHpState *s, MemoryRegion *io, uint16_t io_base) { s->io_len =3D ACPI_PCIHP_SIZE; s->io_base =3D io_base; =20 - s->root =3D root_bus; + assert(s->root); =20 memory_region_init_io(&s->io, owner, &acpi_pcihp_io_ops, s, "acpi-pci-hotplug", s->io_len); diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index d98b80df6d..7a18f18dda 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -567,7 +567,8 @@ static void piix4_acpi_system_hot_add_init(MemoryRegion= *parent, =20 if (s->acpi_pci_hotplug.use_acpi_hotplug_bridge || s->acpi_pci_hotplug.use_acpi_root_pci_hotplug) { - acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent, + object_property_set_link(OBJECT(s), "bus", OBJECT(bus), &error_abo= rt); + acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, parent, ACPI_PCIHP_ADDR_PIIX4); qbus_set_hotplug_handler(BUS(pci_get_bus(PCI_DEVICE(s))), OBJECT(s= )); } @@ -611,6 +612,8 @@ static const Property piix4_pm_properties[] =3D { acpi_pci_hotplug.use_acpi_hotplug_bridge, true), DEFINE_PROP_BOOL(ACPI_PM_PROP_ACPI_PCI_ROOTHP, PIIX4PMState, acpi_pci_hotplug.use_acpi_root_pci_hotplug, true), + DEFINE_PROP_LINK("bus", PIIX4PMState, acpi_pci_hotplug.root, + TYPE_PCI_BUS, PCIBus *), DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState, acpi_memory_hotplug.is_enabled, true), DEFINE_PROP_BOOL("smm-compat", PIIX4PMState, smm_compat, false), --=20 2.49.0 From nobody Sat Nov 15 12:16:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; 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b=cD/5ekDEdUigNpbmrZtuM9/MCEuTIZT1/8ppyPzGHPAWIQUi6LzXe2Md5AJ8JHZtxTwhji 6twjcHysIJMgXRIeezHjDjVvzHCgoxY8cvEfak8SdfhmZZYjbwgbnFPmZmdAmCLtj9qkLz c7olsTR7EYqQmGPHIMaIuN3OMx7jl00= X-MC-Unique: 77xcClk3NgipRJbb6uy5Xw-1 X-Mimecast-MFC-AGG-ID: 77xcClk3NgipRJbb6uy5Xw_1751546404 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, imammedo@redhat.com, Jonathan.Cameron@huawei.com, gustavo.romero@linaro.org, anisinha@redhat.com, mst@redhat.com, shannon.zhaosl@gmail.com Cc: pbonzini@redhat.com, philmd@linaro.org, alex.bennee@linaro.org Subject: [PATCH v5 28/36] hw/acpi/ged: Prepare the device to react to PCI hotplug events Date: Thu, 3 Jul 2025 14:35:28 +0200 Message-ID: <20250703123728.414386-29-eric.auger@redhat.com> In-Reply-To: <20250703123728.414386-1-eric.auger@redhat.com> References: <20250703123728.414386-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" QEMU will notify the OS about PCI hotplug/hotunplug events through GED interrupts. Let the GED device handle a new PCI hotplug event. On its occurrence it calls the \\_SB.PCI0.PCNT method with the BLCK mutex held. The GED device uses a dedicated MMIO region that will be mapped by the machine code. At this point the GED still does not support PCI device hotplug in its TYPE_HOTPLUG_HANDLER implementation. This will come in a subsequent patch. Signed-off-by: Eric Auger --- v4 -> v5: - Get rid of legacy reset API v3 -> v4: - add qbus_set_hotplug_handler - root bus is not passed in acpi_pcihp_init arg v2 -> v3: - pcihp_init and reset are put in ged code instead of machine code (Igor) - Add ACPI_GED_PCI_HOTPLUG_EVT event depending on use_acpi_hotplug_bridge (Igor) v1 -> v2: - Introduce ACPI_PCIHP_REGION_NAME --- include/hw/acpi/generic_event_device.h | 14 ++++++++++- hw/acpi/generic_event_device.c | 35 ++++++++++++++++++++++++++ 2 files changed, 48 insertions(+), 1 deletion(-) diff --git a/include/hw/acpi/generic_event_device.h b/include/hw/acpi/gener= ic_event_device.h index f5ffa67a39..d56adaa626 100644 --- a/include/hw/acpi/generic_event_device.h +++ b/include/hw/acpi/generic_event_device.h @@ -69,7 +69,7 @@ #define ACPI_POWER_BUTTON_DEVICE "PWRB" =20 #define TYPE_ACPI_GED "acpi-ged" -OBJECT_DECLARE_SIMPLE_TYPE(AcpiGedState, ACPI_GED) +OBJECT_DECLARE_TYPE(AcpiGedState, AcpiGedClass, ACPI_GED) =20 #define ACPI_GED_EVT_SEL_OFFSET 0x0 #define ACPI_GED_EVT_SEL_LEN 0x4 @@ -102,6 +102,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(AcpiGedState, ACPI_GED) #define ACPI_GED_PWR_DOWN_EVT 0x2 #define ACPI_GED_NVDIMM_HOTPLUG_EVT 0x4 #define ACPI_GED_CPU_HOTPLUG_EVT 0x8 +#define ACPI_GED_PCI_HOTPLUG_EVT 0x10 =20 typedef struct GEDState { MemoryRegion evt; @@ -109,6 +110,8 @@ typedef struct GEDState { uint32_t sel; } GEDState; =20 +#define ACPI_PCIHP_REGION_NAME "pcihp container" + struct AcpiGedState { SysBusDevice parent_obj; MemHotplugState memhp_state; @@ -116,12 +119,21 @@ struct AcpiGedState { CPUHotplugState cpuhp_state; MemoryRegion container_cpuhp; AcpiPciHpState pcihp_state; + MemoryRegion container_pcihp; GEDState ged_state; uint32_t ged_event_bitmap; qemu_irq irq; AcpiGhesState ghes_state; }; =20 +typedef struct AcpiGedClass { + /* */ + SysBusDeviceClass parent_class; + + /*< public >*/ + ResettablePhases parent_phases; +} AcpiGedClass; + void build_ged_aml(Aml *table, const char* name, HotplugHandler *hotplug_d= ev, uint32_t ged_irq, AmlRegionSpace rs, hwaddr ged_base); void acpi_dsdt_add_power_button(Aml *scope); diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c index 92b931758f..7535d07737 100644 --- a/hw/acpi/generic_event_device.c +++ b/hw/acpi/generic_event_device.c @@ -12,6 +12,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "hw/acpi/acpi.h" +#include "hw/acpi/pcihp.h" #include "hw/acpi/generic_event_device.h" #include "hw/pci/pci.h" #include "hw/irq.h" @@ -28,6 +29,7 @@ static const uint32_t ged_supported_events[] =3D { ACPI_GED_PWR_DOWN_EVT, ACPI_GED_NVDIMM_HOTPLUG_EVT, ACPI_GED_CPU_HOTPLUG_EVT, + ACPI_GED_PCI_HOTPLUG_EVT, }; =20 /* @@ -123,6 +125,12 @@ void build_ged_aml(Aml *table, const char *name, Hotpl= ugHandler *hotplug_dev, aml_notify(aml_name("\\_SB.NVDR"), aml_int(0x80))); break; + case ACPI_GED_PCI_HOTPLUG_EVT: + aml_append(if_ctx, + aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF= )); + aml_append(if_ctx, aml_call0("\\_SB.PCI0.PCNT")); + aml_append(if_ctx, aml_release(aml_name("\\_SB.PCI0.BLCK")= )); + break; default: /* * Please make sure all the events in ged_supported_events= [] @@ -316,6 +324,8 @@ static void acpi_ged_send_event(AcpiDeviceIf *adev, Acp= iEventStatusBits ev) sel =3D ACPI_GED_NVDIMM_HOTPLUG_EVT; } else if (ev & ACPI_CPU_HOTPLUG_STATUS) { sel =3D ACPI_GED_CPU_HOTPLUG_EVT; + } else if (ev & ACPI_PCI_HOTPLUG_STATUS) { + sel =3D ACPI_GED_PCI_HOTPLUG_EVT; } else { /* Unknown event. Return without generating interrupt. */ warn_report("GED: Unsupported event %d. No irq injected", ev); @@ -427,9 +437,13 @@ static void acpi_ged_realize(DeviceState *dev, Error *= *errp) { SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); AcpiGedState *s =3D ACPI_GED(dev); + AcpiPciHpState *pcihp_state =3D &s->pcihp_state; uint32_t ged_events; int i; =20 + if (pcihp_state->use_acpi_hotplug_bridge) { + s->ged_event_bitmap |=3D ACPI_GED_PCI_HOTPLUG_EVT; + } ged_events =3D ctpop32(s->ged_event_bitmap); =20 for (i =3D 0; i < ARRAY_SIZE(ged_supported_events) && ged_events; i++)= { @@ -449,6 +463,13 @@ static void acpi_ged_realize(DeviceState *dev, Error *= *errp) cpu_hotplug_hw_init(&s->container_cpuhp, OBJECT(dev), &s->cpuhp_state, 0); break; + case ACPI_GED_PCI_HOTPLUG_EVT: + memory_region_init(&s->container_pcihp, OBJECT(dev), + ACPI_PCIHP_REGION_NAME, ACPI_PCIHP_SIZE); + sysbus_init_mmio(sbd, &s->container_pcihp); + acpi_pcihp_init(OBJECT(s), &s->pcihp_state, + &s->container_pcihp, 0); + qbus_set_hotplug_handler(BUS(s->pcihp_state.root), OBJECT(dev)= ); } ged_events--; } @@ -490,11 +511,22 @@ static void acpi_ged_initfn(Object *obj) sysbus_init_mmio(sbd, &ged_st->regs); } =20 +static void ged_reset_hold(Object *obj, ResetType type) +{ + AcpiGedState *s =3D ACPI_GED(obj); + + if (s->pcihp_state.use_acpi_hotplug_bridge) { + acpi_pcihp_reset(&s->pcihp_state); + } +} + static void acpi_ged_class_init(ObjectClass *class, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(class); HotplugHandlerClass *hc =3D HOTPLUG_HANDLER_CLASS(class); AcpiDeviceIfClass *adevc =3D ACPI_DEVICE_IF_CLASS(class); + ResettableClass *rc =3D RESETTABLE_CLASS(class); + AcpiGedClass *gedc =3D ACPI_GED_CLASS(class); =20 dc->desc =3D "ACPI Generic Event Device"; device_class_set_props(dc, acpi_ged_properties); @@ -505,6 +537,8 @@ static void acpi_ged_class_init(ObjectClass *class, con= st void *data) hc->plug =3D acpi_ged_device_plug_cb; hc->unplug_request =3D acpi_ged_unplug_request_cb; hc->unplug =3D acpi_ged_unplug_cb; + resettable_class_set_parent_phases(rc, NULL, ged_reset_hold, NULL, + &gedc->parent_phases); =20 adevc->ospm_status =3D acpi_ged_ospm_status; adevc->send_event =3D acpi_ged_send_event; @@ -516,6 +550,7 @@ static const TypeInfo acpi_ged_info =3D { .instance_size =3D sizeof(AcpiGedState), .instance_init =3D acpi_ged_initfn, .class_init =3D acpi_ged_class_init, + .class_size =3D sizeof(AcpiGedClass), .interfaces =3D (const InterfaceInfo[]) { { TYPE_HOTPLUG_HANDLER }, { TYPE_ACPI_DEVICE_IF }, --=20 2.49.0 From nobody Sat Nov 15 12:16:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1751547473; cv=none; d=zohomail.com; s=zohoarc; b=EvfvdQXx5hJEP2C8CldgBHxo0o9ctEvVCoaIUfgdD0DnzxxJ/VWXMMrsMvS7H/EGnUt3pyddFXfrnHnHBJaCQk8+nj5plezxq5o/x5eatwBVNfndRItZkiT5pTLOEOwqEsCjOhwAOyn7bmb0c5F/R/PzpFIRnVmpbXpp8kIx8ZI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751547473; 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charset="utf-8" Add a subsection to migrate the AcpiPciHpState state. Signed-off-by: Eric Auger Reviewed-by: Igor Mammedov Reviewed-by: Jonathan Cameron --- hw/acpi/generic_event_device.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c index 7535d07737..95682b79a2 100644 --- a/hw/acpi/generic_event_device.c +++ b/hw/acpi/generic_event_device.c @@ -417,6 +417,25 @@ static const VMStateDescription vmstate_ghes_state =3D= { } }; =20 +static bool pcihp_needed(void *opaque) +{ + AcpiGedState *s =3D opaque; + return s->pcihp_state.use_acpi_hotplug_bridge; +} + +static const VMStateDescription vmstate_pcihp_state =3D { + .name =3D "acpi-ged/pcihp", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D pcihp_needed, + .fields =3D (const VMStateField[]) { + VMSTATE_PCI_HOTPLUG(pcihp_state, + AcpiGedState, + NULL, NULL), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_acpi_ged =3D { .name =3D "acpi-ged", .version_id =3D 1, @@ -429,6 +448,7 @@ static const VMStateDescription vmstate_acpi_ged =3D { &vmstate_memhp_state, &vmstate_cpuhp_state, &vmstate_ghes_state, + &vmstate_pcihp_state, NULL } }; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1751546418; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Pzj2MFtdQnbxUAQCssC7SV9aCXwj2DU+ao42ErCzUmI=; b=bPcQwDQVhunHiGNijQBnr+ChHRA7HsIOzmjEs8IBGO0KoQItPKcTG81aSOdrr7N/J8FBi1 0A5v2AokoPOnwxvE+OzrBaoLG8KTyBoiCj41X0D3w9eu0zr0Spa0ThK5wjKqZDDL3oxEkk 1tuLMLUTEZUqP+BTVOO37lIH/8gWL80= X-MC-Unique: M3q2el7SM5-bNxbbMYkp3g-1 X-Mimecast-MFC-AGG-ID: M3q2el7SM5-bNxbbMYkp3g_1751546414 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, imammedo@redhat.com, Jonathan.Cameron@huawei.com, gustavo.romero@linaro.org, anisinha@redhat.com, mst@redhat.com, shannon.zhaosl@gmail.com Cc: pbonzini@redhat.com, philmd@linaro.org, alex.bennee@linaro.org Subject: [PATCH v5 30/36] hw/core/sysbus: Introduce sysbus_mmio_map_name() helper Date: Thu, 3 Jul 2025 14:35:30 +0200 Message-ID: <20250703123728.414386-31-eric.auger@redhat.com> In-Reply-To: <20250703123728.414386-1-eric.auger@redhat.com> References: <20250703123728.414386-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Some sysbus devices have conditional mmio regions. This happens for instance with the hw/acpi/ged device. In that case it becomes difficult to predict which index a specific MMIO region corresponds to when one needs to mmio map the region. Introduce a new helper that takes the name of the region instead of its index. If the region is not found this returns -1. Otherwise it maps the corresponding index and returns this latter. Signed-off-by: Eric Auger Reviewed-by: Jonathan Cameron --- include/hw/sysbus.h | 1 + hw/core/sysbus.c | 11 +++++++++++ 2 files changed, 12 insertions(+) diff --git a/include/hw/sysbus.h b/include/hw/sysbus.h index 7dc88aaa27..18fde8a7b4 100644 --- a/include/hw/sysbus.h +++ b/include/hw/sysbus.h @@ -82,6 +82,7 @@ void sysbus_connect_irq(SysBusDevice *dev, int n, qemu_ir= q irq); bool sysbus_is_irq_connected(SysBusDevice *dev, int n); qemu_irq sysbus_get_connected_irq(SysBusDevice *dev, int n); void sysbus_mmio_map(SysBusDevice *dev, int n, hwaddr addr); +int sysbus_mmio_map_name(SysBusDevice *dev, const char*name, hwaddr addr); void sysbus_mmio_map_overlap(SysBusDevice *dev, int n, hwaddr addr, int priority); =20 diff --git a/hw/core/sysbus.c b/hw/core/sysbus.c index e71367adfb..ec69e877a2 100644 --- a/hw/core/sysbus.c +++ b/hw/core/sysbus.c @@ -151,6 +151,17 @@ void sysbus_mmio_map(SysBusDevice *dev, int n, hwaddr = addr) sysbus_mmio_map_common(dev, n, addr, false, 0); } =20 +int sysbus_mmio_map_name(SysBusDevice *dev, const char *name, hwaddr addr) +{ + for (int i =3D 0; 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Thu, 3 Jul 2025 12:40:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1751546425; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=QxwfYEvRpYO+ysfGn4l7Ic5LE5Wsaju89hTYULgExAg=; b=R/fZBJZlurHRqEcKc9OIr11Rn6OrkT5+ZmN/fbwJ/HVR6/1zYZ6QAI74umm8kADHUFxMNn gbNUTSibDTTcjQDrdAQtt0jE1ix5W5cWVYFJdP2nYxmc4iQ/U2fGSR3DacEQ4LR9fM6TUs FFadRBuXozeFs59pXVEmk+KB7etNfgw= X-MC-Unique: Vu89Ro_SNlGaz_DNGnChpw-1 X-Mimecast-MFC-AGG-ID: Vu89Ro_SNlGaz_DNGnChpw_1751546419 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, imammedo@redhat.com, Jonathan.Cameron@huawei.com, gustavo.romero@linaro.org, anisinha@redhat.com, mst@redhat.com, shannon.zhaosl@gmail.com Cc: pbonzini@redhat.com, philmd@linaro.org, alex.bennee@linaro.org Subject: [PATCH v5 31/36] hw/arm/virt: Minor code reshuffling in create_acpi_ged Date: Thu, 3 Jul 2025 14:35:31 +0200 Message-ID: <20250703123728.414386-32-eric.auger@redhat.com> In-Reply-To: <20250703123728.414386-1-eric.auger@redhat.com> References: <20250703123728.414386-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Use a local SysBusDevice handle. Also use the newly introduced sysbus_mmio_map_name which brings better readability about the region being mapped. GED device has regions which exist depending on some external properties and it becomes difficult to guess the index of a region. Better refer to a region by its name. Signed-off-by: Eric Auger Reviewed-by: Jonathan Cameron --- include/hw/acpi/generic_event_device.h | 1 + hw/arm/virt.c | 11 +++++++---- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/include/hw/acpi/generic_event_device.h b/include/hw/acpi/gener= ic_event_device.h index d56adaa626..2c5b055327 100644 --- a/include/hw/acpi/generic_event_device.h +++ b/include/hw/acpi/generic_event_device.h @@ -111,6 +111,7 @@ typedef struct GEDState { } GEDState; =20 #define ACPI_PCIHP_REGION_NAME "pcihp container" +#define ACPI_MEMHP_REGION_NAME "memhp container" =20 struct AcpiGedState { SysBusDevice parent_obj; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 34a3831530..7b247ad30c 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -683,6 +683,7 @@ static inline DeviceState *create_acpi_ged(VirtMachineS= tate *vms) { DeviceState *dev; MachineState *ms =3D MACHINE(vms); + SysBusDevice *sbdev; int irq =3D vms->irqmap[VIRT_ACPI_GED]; uint32_t event =3D ACPI_GED_PWR_DOWN_EVT; =20 @@ -697,11 +698,13 @@ static inline DeviceState *create_acpi_ged(VirtMachin= eState *vms) dev =3D qdev_new(TYPE_ACPI_GED); qdev_prop_set_uint32(dev, "ged-event", event); object_property_set_link(OBJECT(dev), "bus", OBJECT(vms->bus), &error_= abort); - sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sbdev =3D SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(sbdev, &error_fatal); =20 - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].bas= e); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].= base); - sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, = irq)); + sysbus_mmio_map_name(sbdev, TYPE_ACPI_GED, vms->memmap[VIRT_ACPI_GED].= base); + sysbus_mmio_map_name(sbdev, ACPI_MEMHP_REGION_NAME, + vms->memmap[VIRT_PCDIMM_ACPI].base); + sysbus_connect_irq(sbdev, 0, qdev_get_gpio_in(vms->gic, irq)); =20 return dev; } --=20 2.49.0 From nobody Sat Nov 15 12:16:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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b=A6ac9a1b/TxBBy6+fO63hIfcdoOTk4Q1qF25mMN7XM8PX3kUKm5kt8uzsVvkg9CzZ6wztx ZhP+ympsBb9eUxEfI20KLGYR06V8+6B4ZnGtve2Xw5ddAqrIcXdjZr+9+nm67OLXr/R1W/ 8wjYba7bfQsXBdgUAPV1dbYMNAG1HPg= X-MC-Unique: YacpWBbyMqKWyBI4UfuuqA-1 X-Mimecast-MFC-AGG-ID: YacpWBbyMqKWyBI4UfuuqA_1751546424 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, imammedo@redhat.com, Jonathan.Cameron@huawei.com, gustavo.romero@linaro.org, anisinha@redhat.com, mst@redhat.com, shannon.zhaosl@gmail.com Cc: pbonzini@redhat.com, philmd@linaro.org, alex.bennee@linaro.org Subject: [PATCH v5 32/36] hw/arm/virt: Let virt support pci hotplug/unplug GED event Date: Thu, 3 Jul 2025 14:35:32 +0200 Message-ID: <20250703123728.414386-33-eric.auger@redhat.com> In-Reply-To: <20250703123728.414386-1-eric.auger@redhat.com> References: <20250703123728.414386-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Set up the IO registers used to communicate between QEMU and ACPI. Signed-off-by: Eric Auger --- v2 -> v3: - remove acpi_ged_state->pcihp_state.use_acpi_hotplug_bridge =3D true; - use sysbus_mmio_map_name for all regs (Igor) - create_pcie left at its original place v1 -> v2: - use ACPI_PCIHP_REGION_NAME --- hw/arm/virt.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 7b247ad30c..4f6fe16675 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -686,6 +686,7 @@ static inline DeviceState *create_acpi_ged(VirtMachineS= tate *vms) SysBusDevice *sbdev; int irq =3D vms->irqmap[VIRT_ACPI_GED]; uint32_t event =3D ACPI_GED_PWR_DOWN_EVT; + bool acpi_pcihp; =20 if (ms->ram_slots) { event |=3D ACPI_GED_MEM_HOTPLUG_EVT; @@ -704,6 +705,18 @@ static inline DeviceState *create_acpi_ged(VirtMachine= State *vms) sysbus_mmio_map_name(sbdev, TYPE_ACPI_GED, vms->memmap[VIRT_ACPI_GED].= base); sysbus_mmio_map_name(sbdev, ACPI_MEMHP_REGION_NAME, vms->memmap[VIRT_PCDIMM_ACPI].base); + + acpi_pcihp =3D object_property_get_bool(OBJECT(dev), + ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, = NULL); + + if (acpi_pcihp) { + int pcihp_region_index; + + pcihp_region_index =3D sysbus_mmio_map_name(sbdev, ACPI_PCIHP_REGI= ON_NAME, + vms->memmap[VIRT_ACPI_PC= IHP].base); + assert(pcihp_region_index >=3D 0); + } + sysbus_connect_irq(sbdev, 0, qdev_get_gpio_in(vms->gic, irq)); =20 return dev; --=20 2.49.0 From nobody Sat Nov 15 12:16:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1751547172; cv=none; d=zohomail.com; s=zohoarc; b=Kj15aotN17utW7hSsxVdjpXTjhpvZt8hCKAjjfqNinkXBGv+XIHh6UDQR0NyITFuWcZaLm5kIwbZ1CS5eOQyvES9CqD/kcxSX5PMQMGNFhHach4bHXbbzlEtmcpr8vi8QW0z0fjiz7Im2RvqJbBTVC8vsLcDB30PR9BULcqY2JM= ARC-Message-Signature: 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(mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.111]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-04.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 6E52619560AD; Thu, 3 Jul 2025 12:40:29 +0000 (UTC) Received: from laptop.redhat.com (unknown [10.44.32.16]) by mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id CAA66180045B; Thu, 3 Jul 2025 12:40:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1751546434; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=KsfUkLon/+WAZ1K8J1yMGAMyGCY2Z1dhM4JRzV9aVSE=; b=JNeuAcgPUXXQ6erxb/4E31G0krwp6xisL9PvxXyfC804YVWqaeF20LuGeRPOj503riU5Im 2g4WyNVYuOye5/rApE3hVzVOWEt+vPPvR1kPqg48EngXobgQKRXnhYCypB5a4iG9JmT0if UgjS/Gi8OfrgjIYOrGWgLxJpmoHu87E= X-MC-Unique: W0Nb-Q2JP12wPRUbdXJ3vQ-1 X-Mimecast-MFC-AGG-ID: W0Nb-Q2JP12wPRUbdXJ3vQ_1751546429 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, imammedo@redhat.com, Jonathan.Cameron@huawei.com, gustavo.romero@linaro.org, anisinha@redhat.com, mst@redhat.com, shannon.zhaosl@gmail.com Cc: pbonzini@redhat.com, philmd@linaro.org, alex.bennee@linaro.org Subject: [PATCH v5 33/36] tests/qtest/bios-tables-test: Prepare for addition of acpi pci hp tests Date: Thu, 3 Jul 2025 14:35:33 +0200 Message-ID: <20250703123728.414386-34-eric.auger@redhat.com> In-Reply-To: <20250703123728.414386-1-eric.auger@redhat.com> References: <20250703123728.414386-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 15 X-Spam_score: 1.5 X-Spam_bar: + X-Spam_report: (1.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_SBL_CSS=3.335, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.237, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1751547174601116600 Content-Type: text/plain; charset="utf-8" From: Gustavo Romero Soon we will introduce new tests related to ACPI PCI hotplug and acpi-index that will use a new reference blob: tests/data/acpi/aarch64/virt/DSDT.acpipcihp tests/data/acpi/aarch64/virt/DSDT.hpoffacpiindex Signed-off-by: Gustavo Romero Signed-off-by: Eric Auger Reviewed-by: Jonathan Cameron --- v3 -> v4: - switch Sign-off's (Jonathan) --- tests/qtest/bios-tables-test-allowed-diff.h | 2 ++ tests/data/acpi/aarch64/virt/DSDT.acpipcihp | 0 tests/data/acpi/aarch64/virt/DSDT.hpoffacpiindex | 0 3 files changed, 2 insertions(+) create mode 100644 tests/data/acpi/aarch64/virt/DSDT.acpipcihp create mode 100644 tests/data/acpi/aarch64/virt/DSDT.hpoffacpiindex diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index dfb8523c8b..02f4f0b29f 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,3 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/aarch64/virt/DSDT.acpipcihp", +"tests/data/acpi/aarch64/virt/DSDT.hpoffacpiindex", diff --git a/tests/data/acpi/aarch64/virt/DSDT.acpipcihp b/tests/data/acpi/= aarch64/virt/DSDT.acpipcihp new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/data/acpi/aarch64/virt/DSDT.hpoffacpiindex b/tests/data/= acpi/aarch64/virt/DSDT.hpoffacpiindex new file mode 100644 index 0000000000..e69de29bb2 --=20 2.49.0 From nobody Sat Nov 15 12:16:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine 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s=mimecast20190719; t=1751546437; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7z4t23L2CEjvRbW4POxEjlHbPc7Y86a0BBQtX1AsNc0=; b=TLPJMqEChlp9mM4fmfL8ei3b23yUgT4ZcGNEb0cZafwA0pJ6C+pujCJI9MkZpjvUcPuY3a MjIfRTQZhLONtLAHjGu3dVkhaNhoAFyxoQdV4I50hl9Ll+RPkr0oDmRm+YDxNn2ObExHae fCzL/v46auYryRCEcIwzm46hjKX+Nac= X-MC-Unique: VCGK9_JxP4qRm1RqCS9Uxg-1 X-Mimecast-MFC-AGG-ID: VCGK9_JxP4qRm1RqCS9Uxg_1751546434 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, imammedo@redhat.com, Jonathan.Cameron@huawei.com, gustavo.romero@linaro.org, anisinha@redhat.com, mst@redhat.com, shannon.zhaosl@gmail.com Cc: pbonzini@redhat.com, philmd@linaro.org, alex.bennee@linaro.org Subject: [PATCH v5 34/36] tests/qtest/bios-tables-test: Add aarch64 ACPI PCI hotplug test Date: Thu, 3 Jul 2025 14:35:34 +0200 Message-ID: <20250703123728.414386-35-eric.auger@redhat.com> In-Reply-To: <20250703123728.414386-1-eric.auger@redhat.com> References: <20250703123728.414386-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 15 X-Spam_score: 1.5 X-Spam_bar: + X-Spam_report: (1.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_SBL_CSS=3.335, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.237, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1751546883812116600 Content-Type: text/plain; charset="utf-8" From: Gustavo Romero Add 2 new tests: - test_acpi_aarch64_virt_acpi_pci_hotplug tests the acpi pci hotplug using -global acpi-ged.acpi-pci-hotplug-with-bridge-support=3Don - test_acpi_aarch64_virt_pcie_root_port_hpoff tests static-acpi index on a root port with disabled hotplug Signed-off-by: Gustavo Romero Signed-off-by: Eric Auger Reviewed-by: Jonathan Cameron --- v3 -> v4: - add -device pci-testdev for the first test case - fix the chassis - add a test for static acpi-index --- tests/qtest/bios-tables-test.c | 52 ++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index 357bcefd37..1074b8d67a 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -1643,6 +1643,54 @@ static void test_acpi_aarch64_virt_tcg_memhp(void) =20 } =20 +static void test_acpi_aarch64_virt_acpi_pci_hotplug(void) +{ + test_data data =3D { + .machine =3D "virt", + .arch =3D "aarch64", + .tcg_only =3D true, + .uefi_fl1 =3D "pc-bios/edk2-aarch64-code.fd", + .uefi_fl2 =3D "pc-bios/edk2-arm-vars.fd", + .cd =3D "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.= qcow2", + .ram_start =3D 0x40000000ULL, + .scan_len =3D 256ULL * MiB, + .variant =3D ".acpipcihp", + }; + + /* Use ACPI PCI Hotplug */ + test_acpi_one(" -global acpi-ged.acpi-pci-hotplug-with-bridge-support= =3Don" + " -cpu cortex-a57" + " -device pcie-root-port,id=3Dpcie.1,bus=3Dpcie.0,chassis= =3D0,slot=3D1,addr=3D7.0" + " -device pci-testdev,bus=3Dpcie.1", + &data); + + free_test_data(&data); +} + +static void test_acpi_aarch64_virt_pcie_root_port_hpoff(void) +{ + test_data data =3D { + .machine =3D "virt", + .arch =3D "aarch64", + .tcg_only =3D true, + .uefi_fl1 =3D "pc-bios/edk2-aarch64-code.fd", + .uefi_fl2 =3D "pc-bios/edk2-arm-vars.fd", + .cd =3D "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.= qcow2", + .ram_start =3D 0x40000000ULL, + .scan_len =3D 256ULL * MiB, + .variant =3D ".hpoffacpiindex", + }; + + /* turn hotplug off on the pcie-root-port and use static acpi-index*/ + test_acpi_one(" -device pcie-root-port,id=3Dpcie.1,chassis=3D0," + "slot=3D1,hotplug=3Doff,addr=3D7= .0" + " -device pci-testdev,bus=3Dpcie.1,acpi-index=3D12" + " -cpu cortex-a57", + &data); + + free_test_data(&data); +} + static void test_acpi_microvm_prepare(test_data *data) { data->machine =3D "microvm"; @@ -2602,6 +2650,10 @@ int main(int argc, char *argv[]) qtest_add_func("acpi/virt/numamem", test_acpi_aarch64_virt_tcg_numamem); qtest_add_func("acpi/virt/memhp", test_acpi_aarch64_virt_tcg_m= emhp); + qtest_add_func("acpi/virt/acpipcihp", + test_acpi_aarch64_virt_acpi_pci_hotplug); + qtest_add_func("acpi/virt/hpoffacpiindex", + test_acpi_aarch64_virt_pcie_root_port_hpoff); qtest_add_func("acpi/virt/pxb", test_acpi_aarch64_virt_tcg_pxb= ); qtest_add_func("acpi/virt/oem-fields", test_acpi_aarch64_virt_oem_fields); --=20 2.49.0 From nobody Sat Nov 15 12:16:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1751546709; cv=none; d=zohomail.com; s=zohoarc; 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content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=TyMY/wK3HEYC3QDJ06OrdRZLREBhcdwj8DHiOhLxrrU=; b=go3hHupwmAghsb2qPTHMIyo+/BGVFnz3CdLT8KG5j1DbOjvwkUKlADHwfGpANnR2tZhioj du5QsS+9YUj6GObwkpHsoFmZEi9vxYGlZqBf+WxnMEwwJv/gNRQ/HBm3ohrz+YSZZKYtPe pFzuPyD55L0i2Wh5fJ9AX9gs5vs7kgI= X-MC-Unique: _Y8iJyw2NKmys08qXP3Upw-1 X-Mimecast-MFC-AGG-ID: _Y8iJyw2NKmys08qXP3Upw_1751546441 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, imammedo@redhat.com, Jonathan.Cameron@huawei.com, gustavo.romero@linaro.org, anisinha@redhat.com, mst@redhat.com, shannon.zhaosl@gmail.com Cc: pbonzini@redhat.com, philmd@linaro.org, alex.bennee@linaro.org Subject: [PATCH v5 35/36] qtest/bios-tables-test: Generate reference blob for DSDT.hpoffacpiindex Date: Thu, 3 Jul 2025 14:35:35 +0200 Message-ID: <20250703123728.414386-36-eric.auger@redhat.com> In-Reply-To: <20250703123728.414386-1-eric.auger@redhat.com> References: <20250703123728.414386-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 15 X-Spam_score: 1.5 X-Spam_bar: + X-Spam_report: (1.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_SBL_CSS=3.335, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.237, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1751546716096116600 Content-Type: text/plain; charset="utf-8" The disassembled DSDT table is given below * Original Table Header: * Signature "DSDT" * Length 0x000014E3 (5347) * Revision 0x02 * Checksum 0x92 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPC ", 0x00000001) { Scope (\_SB) { Device (C000) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardwa= re ID Name (_UID, Zero) // _UID: Unique ID } Device (COM0) { Name (_HID, "ARMH0011") // _HID: Hardware ID Name (_UID, Zero) // _UID: Unique ID Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x09000000, // Address Base 0x00001000, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000021, } }) } Device (FWCF) { Name (_HID, "QEMU0002") // _HID: Hardware ID Name (_STA, 0x0B) // _STA: Status Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x09020000, // Address Base 0x00000018, // Address Length ) }) } Device (VR00) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, Zero) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A000000, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000030, } }) } Device (VR01) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, One) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A000200, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000031, } }) } Device (VR02) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x02) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A000400, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000032, } }) } Device (VR03) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x03) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A000600, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000033, } }) } Device (VR04) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x04) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A000800, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000034, } }) } Device (VR05) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x05) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A000A00, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000035, } }) } Device (VR06) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x06) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A000C00, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000036, } }) } Device (VR07) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x07) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A000E00, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000037, } }) } Device (VR08) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x08) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A001000, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000038, } }) } Device (VR09) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x09) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A001200, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000039, } }) } Device (VR10) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x0A) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A001400, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x0000003A, } }) } Device (VR11) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x0B) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A001600, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x0000003B, } }) } Device (VR12) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x0C) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A001800, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x0000003C, } }) } Device (VR13) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x0D) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A001A00, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x0000003D, } }) } Device (VR14) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x0E) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A001C00, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x0000003E, } }) } Device (VR15) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x0F) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A001E00, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x0000003F, } }) } Device (VR16) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x10) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A002000, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000040, } }) } Device (VR17) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x11) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A002200, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000041, } }) } Device (VR18) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x12) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A002400, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000042, } }) } Device (VR19) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x13) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A002600, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000043, } }) } Device (VR20) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x14) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A002800, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000044, } }) } Device (VR21) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x15) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A002A00, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000045, } }) } Device (VR22) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x16) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A002C00, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000046, } }) } Device (VR23) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x17) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A002E00, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000047, } }) } Device (VR24) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x18) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A003000, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000048, } }) } Device (VR25) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x19) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A003200, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000049, } }) } Device (VR26) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x1A) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A003400, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x0000004A, } }) } Device (VR27) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x1B) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A003600, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x0000004B, } }) } Device (VR28) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x1C) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A003800, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x0000004C, } }) } Device (VR29) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x1D) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A003A00, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x0000004D, } }) } Device (VR30) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x1E) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A003C00, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x0000004E, } }) } Device (VR31) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x1F) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A003E00, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x0000004F, } }) } Device (L000) { Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID= : Hardware ID Name (_UID, Zero) // _UID: Unique ID Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Set= tings { Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000023, } }) Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000023, } }) Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings { } } Device (L001) { Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID= : Hardware ID Name (_UID, One) // _UID: Unique ID Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Set= tings { Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000024, } }) Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000024, } }) Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings { } } Device (L002) { Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID= : Hardware ID Name (_UID, 0x02) // _UID: Unique ID Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Set= tings { Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000025, } }) Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000025, } }) Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings { } } Device (L003) { Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID= : Hardware ID Name (_UID, 0x03) // _UID: Unique ID Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Set= tings { Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000026, } }) Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000026, } }) Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings { } } Device (PCI0) { Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware= ID Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID Name (_SEG, Zero) // _SEG: PCI Segment Name (_BBN, Zero) // _BBN: BIOS Bus Number Name (_UID, Zero) // _UID: Unique ID Name (_STR, Unicode ("PCIe 0 Device")) // _STR: Description St= ring Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_PRT, Package (0x80) // _PRT: PCI Routing Table { Package (0x04) { 0xFFFF, Zero, L000, Zero }, Package (0x04) { 0xFFFF, One, L001, Zero }, Package (0x04) { 0xFFFF, 0x02, L002, Zero }, Package (0x04) { 0xFFFF, 0x03, L003, Zero }, Package (0x04) { 0x0001FFFF, Zero, L001, Zero }, Package (0x04) { 0x0001FFFF, One, L002, Zero }, Package (0x04) { 0x0001FFFF, 0x02, L003, Zero }, Package (0x04) { 0x0001FFFF, 0x03, L000, Zero }, Package (0x04) { 0x0002FFFF, Zero, L002, Zero }, Package (0x04) { 0x0002FFFF, One, L003, Zero }, Package (0x04) { 0x0002FFFF, 0x02, L000, Zero }, Package (0x04) { 0x0002FFFF, 0x03, L001, Zero }, Package (0x04) { 0x0003FFFF, Zero, L003, Zero }, Package (0x04) { 0x0003FFFF, One, L000, Zero }, Package (0x04) { 0x0003FFFF, 0x02, L001, Zero }, Package (0x04) { 0x0003FFFF, 0x03, L002, Zero }, Package (0x04) { 0x0004FFFF, Zero, L000, Zero }, Package (0x04) { 0x0004FFFF, One, L001, Zero }, Package (0x04) { 0x0004FFFF, 0x02, L002, Zero }, Package (0x04) { 0x0004FFFF, 0x03, L003, Zero }, Package (0x04) { 0x0005FFFF, Zero, L001, Zero }, Package (0x04) { 0x0005FFFF, One, L002, Zero }, Package (0x04) { 0x0005FFFF, 0x02, L003, Zero }, Package (0x04) { 0x0005FFFF, 0x03, L000, Zero }, Package (0x04) { 0x0006FFFF, Zero, L002, Zero }, Package (0x04) { 0x0006FFFF, One, L003, Zero }, Package (0x04) { 0x0006FFFF, 0x02, L000, Zero }, Package (0x04) { 0x0006FFFF, 0x03, L001, Zero }, Package (0x04) { 0x0007FFFF, Zero, L003, Zero }, Package (0x04) { 0x0007FFFF, One, L000, Zero }, Package (0x04) { 0x0007FFFF, 0x02, L001, Zero }, Package (0x04) { 0x0007FFFF, 0x03, L002, Zero }, Package (0x04) { 0x0008FFFF, Zero, L000, Zero }, Package (0x04) { 0x0008FFFF, One, L001, Zero }, Package (0x04) { 0x0008FFFF, 0x02, L002, Zero }, Package (0x04) { 0x0008FFFF, 0x03, L003, Zero }, Package (0x04) { 0x0009FFFF, Zero, L001, Zero }, Package (0x04) { 0x0009FFFF, One, L002, Zero }, Package (0x04) { 0x0009FFFF, 0x02, L003, Zero }, Package (0x04) { 0x0009FFFF, 0x03, L000, Zero }, Package (0x04) { 0x000AFFFF, Zero, L002, Zero }, Package (0x04) { 0x000AFFFF, One, L003, Zero }, Package (0x04) { 0x000AFFFF, 0x02, L000, Zero }, Package (0x04) { 0x000AFFFF, 0x03, L001, Zero }, Package (0x04) { 0x000BFFFF, Zero, L003, Zero }, Package (0x04) { 0x000BFFFF, One, L000, Zero }, Package (0x04) { 0x000BFFFF, 0x02, L001, Zero }, Package (0x04) { 0x000BFFFF, 0x03, L002, Zero }, Package (0x04) { 0x000CFFFF, Zero, L000, Zero }, Package (0x04) { 0x000CFFFF, One, L001, Zero }, Package (0x04) { 0x000CFFFF, 0x02, L002, Zero }, Package (0x04) { 0x000CFFFF, 0x03, L003, Zero }, Package (0x04) { 0x000DFFFF, Zero, L001, Zero }, Package (0x04) { 0x000DFFFF, One, L002, Zero }, Package (0x04) { 0x000DFFFF, 0x02, L003, Zero }, Package (0x04) { 0x000DFFFF, 0x03, L000, Zero }, Package (0x04) { 0x000EFFFF, Zero, L002, Zero }, Package (0x04) { 0x000EFFFF, One, L003, Zero }, Package (0x04) { 0x000EFFFF, 0x02, L000, Zero }, Package (0x04) { 0x000EFFFF, 0x03, L001, Zero }, Package (0x04) { 0x000FFFFF, Zero, L003, Zero }, Package (0x04) { 0x000FFFFF, One, L000, Zero }, Package (0x04) { 0x000FFFFF, 0x02, L001, Zero }, Package (0x04) { 0x000FFFFF, 0x03, L002, Zero }, Package (0x04) { 0x0010FFFF, Zero, L000, Zero }, Package (0x04) { 0x0010FFFF, One, L001, Zero }, Package (0x04) { 0x0010FFFF, 0x02, L002, Zero }, Package (0x04) { 0x0010FFFF, 0x03, L003, Zero }, Package (0x04) { 0x0011FFFF, Zero, L001, Zero }, Package (0x04) { 0x0011FFFF, One, L002, Zero }, Package (0x04) { 0x0011FFFF, 0x02, L003, Zero }, Package (0x04) { 0x0011FFFF, 0x03, L000, Zero }, Package (0x04) { 0x0012FFFF, Zero, L002, Zero }, Package (0x04) { 0x0012FFFF, One, L003, Zero }, Package (0x04) { 0x0012FFFF, 0x02, L000, Zero }, Package (0x04) { 0x0012FFFF, 0x03, L001, Zero }, Package (0x04) { 0x0013FFFF, Zero, L003, Zero }, Package (0x04) { 0x0013FFFF, One, L000, Zero }, Package (0x04) { 0x0013FFFF, 0x02, L001, Zero }, Package (0x04) { 0x0013FFFF, 0x03, L002, Zero }, Package (0x04) { 0x0014FFFF, Zero, L000, Zero }, Package (0x04) { 0x0014FFFF, One, L001, Zero }, Package (0x04) { 0x0014FFFF, 0x02, L002, Zero }, Package (0x04) { 0x0014FFFF, 0x03, L003, Zero }, Package (0x04) { 0x0015FFFF, Zero, L001, Zero }, Package (0x04) { 0x0015FFFF, One, L002, Zero }, Package (0x04) { 0x0015FFFF, 0x02, L003, Zero }, Package (0x04) { 0x0015FFFF, 0x03, L000, Zero }, Package (0x04) { 0x0016FFFF, Zero, L002, Zero }, Package (0x04) { 0x0016FFFF, One, L003, Zero }, Package (0x04) { 0x0016FFFF, 0x02, L000, Zero }, Package (0x04) { 0x0016FFFF, 0x03, L001, Zero }, Package (0x04) { 0x0017FFFF, Zero, L003, Zero }, Package (0x04) { 0x0017FFFF, One, L000, Zero }, Package (0x04) { 0x0017FFFF, 0x02, L001, Zero }, Package (0x04) { 0x0017FFFF, 0x03, L002, Zero }, Package (0x04) { 0x0018FFFF, Zero, L000, Zero }, Package (0x04) { 0x0018FFFF, One, L001, Zero }, Package (0x04) { 0x0018FFFF, 0x02, L002, Zero }, Package (0x04) { 0x0018FFFF, 0x03, L003, Zero }, Package (0x04) { 0x0019FFFF, Zero, L001, Zero }, Package (0x04) { 0x0019FFFF, One, L002, Zero }, Package (0x04) { 0x0019FFFF, 0x02, L003, Zero }, Package (0x04) { 0x0019FFFF, 0x03, L000, Zero }, Package (0x04) { 0x001AFFFF, Zero, L002, Zero }, Package (0x04) { 0x001AFFFF, One, L003, Zero }, Package (0x04) { 0x001AFFFF, 0x02, L000, Zero }, Package (0x04) { 0x001AFFFF, 0x03, L001, Zero }, Package (0x04) { 0x001BFFFF, Zero, L003, Zero }, Package (0x04) { 0x001BFFFF, One, L000, Zero }, Package (0x04) { 0x001BFFFF, 0x02, L001, Zero }, Package (0x04) { 0x001BFFFF, 0x03, L002, Zero }, Package (0x04) { 0x001CFFFF, Zero, L000, Zero }, Package (0x04) { 0x001CFFFF, One, L001, Zero }, Package (0x04) { 0x001CFFFF, 0x02, L002, Zero }, Package (0x04) { 0x001CFFFF, 0x03, L003, Zero }, Package (0x04) { 0x001DFFFF, Zero, L001, Zero }, Package (0x04) { 0x001DFFFF, One, L002, Zero }, Package (0x04) { 0x001DFFFF, 0x02, L003, Zero }, Package (0x04) { 0x001DFFFF, 0x03, L000, Zero }, Package (0x04) { 0x001EFFFF, Zero, L002, Zero }, Package (0x04) { 0x001EFFFF, One, L003, Zero }, Package (0x04) { 0x001EFFFF, 0x02, L000, Zero }, Package (0x04) { 0x001EFFFF, 0x03, L001, Zero }, Package (0x04) { 0x001FFFFF, Zero, L003, Zero }, Package (0x04) { 0x001FFFFF, One, L000, Zero }, Package (0x04) { 0x001FFFFF, 0x02, L001, Zero }, Package (0x04) { 0x001FFFFF, 0x03, L002, Zero } }) Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Ad= dress { Return (0x0000004010000000) } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDec= ode, 0x0000, // Granularity 0x0000, // Range Minimum 0x00FF, // Range Maximum 0x0000, // Translation Offset 0x0100, // Length ,, ) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixe= d, NonCacheable, ReadWrite, 0x00000000, // Granularity 0x10000000, // Range Minimum 0x3EFEFFFF, // Range Maximum 0x00000000, // Translation Offset 0x2EFF0000, // Length ,, , AddressRangeMemory, TypeStatic) DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, E= ntireRange, 0x00000000, // Granularity 0x00000000, // Range Minimum 0x0000FFFF, // Range Maximum 0x3EFF0000, // Translation Offset 0x00010000, // Length ,, , TypeStatic, DenseTranslation) QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixe= d, NonCacheable, ReadWrite, 0x0000000000000000, // Granularity 0x0000008000000000, // Range Minimum 0x000000FFFFFFFFFF, // Range Maximum 0x0000000000000000, // Translation Offset 0x0000008000000000, // Length ,, , AddressRangeMemory, TypeStatic) }) Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capa= bilities { CreateDWordField (Arg3, Zero, CDW1) If ((Arg0 =3D=3D ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd= 766") /* PCI Host Bridge Device */)) { CreateDWordField (Arg3, 0x04, CDW2) CreateDWordField (Arg3, 0x08, CDW3) Local0 =3D CDW3 /* \_SB_.PCI0._OSC.CDW3 */ Local0 &=3D 0x1F If ((Arg1 !=3D One)) { CDW1 |=3D 0x08 } If ((CDW3 !=3D Local0)) { CDW1 |=3D 0x10 } CDW3 =3D Local0 } Else { CDW1 |=3D 0x04 } Return (Arg3) } Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { If ((Arg0 =3D=3D ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c34= 34d") /* Device Labeling Interface */)) { If ((Arg2 =3D=3D Zero)) { Return (Buffer (One) { 0x01 = // . }) } } Return (Buffer (One) { 0x00 // . }) } Device (RES0) { Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // = _HID: Hardware ID Name (_CRS, ResourceTemplate () // _CRS: Current Resource = Settings { QWordMemory (ResourceProducer, PosDecode, MinFixed, Max= Fixed, NonCacheable, ReadWrite, 0x0000000000000000, // Granularity 0x0000004010000000, // Range Minimum 0x000000401FFFFFFF, // Range Maximum 0x0000000000000000, // Translation Offset 0x0000000010000000, // Length ,, , AddressRangeMemory, TypeStatic) }) } } Device (\_SB.GED) { Name (_HID, "ACPI0013" /* Generic Event Device */) // _HID: Ha= rdware ID Name (_UID, "GED") // _UID: Unique ID Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,= , ) { 0x00000029, } }) OperationRegion (EREG, SystemMemory, 0x09080000, 0x04) Field (EREG, DWordAcc, NoLock, WriteAsZeros) { ESEL, 32 } Method (_EVT, 1, Serialized) // _EVT: Event { Local0 =3D ESEL /* \_SB_.GED_.ESEL */ If (((Local0 & 0x02) =3D=3D 0x02)) { Notify (PWRB, 0x80) // Status Change } } } Device (PWRB) { Name (_HID, "PNP0C0C" /* Power Button Device */) // _HID: Hard= ware ID Name (_UID, Zero) // _UID: Unique ID } } Scope (\_SB.PCI0) { Method (EDSM, 5, Serialized) { If ((Arg2 =3D=3D Zero)) { Local0 =3D Buffer (One) { 0x00 /= / . } If ((Arg0 !=3D ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434= d") /* Device Labeling Interface */)) { Return (Local0) } If ((Arg1 < 0x02)) { Return (Local0) } Local0 [Zero] =3D 0x81 Return (Local0) } If ((Arg2 =3D=3D 0x07)) { Local0 =3D Package (0x02) { Zero, "" } Local1 =3D DerefOf (Arg4 [Zero]) Local0 [Zero] =3D Local1 Return (Local0) } } Device (S00) { Name (_ADR, Zero) // _ADR: Address } Device (S08) { Name (_ADR, 0x00010000) // _ADR: Address } Device (S38) { Name (_ADR, 0x00070000) // _ADR: Address Device (S00) { Name (_ADR, Zero) // _ADR: Address Method (_DSM, 4, Serialized) // _DSM: Device-Specific Meth= od { Local0 =3D Package (0x01) { 0x0C } Return (EDSM (Arg0, Arg1, Arg2, Arg3, Local0)) } } } } } Signed-off-by: Eric Auger --- tests/qtest/bios-tables-test-allowed-diff.h | 1 - tests/data/acpi/aarch64/virt/DSDT.hpoffacpiindex | Bin 0 -> 5347 bytes 2 files changed, 1 deletion(-) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index 02f4f0b29f..dc3ab24d05 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,3 +1,2 @@ /* List of comma-separated changed AML files to ignore */ "tests/data/acpi/aarch64/virt/DSDT.acpipcihp", -"tests/data/acpi/aarch64/virt/DSDT.hpoffacpiindex", diff --git a/tests/data/acpi/aarch64/virt/DSDT.hpoffacpiindex b/tests/data/= acpi/aarch64/virt/DSDT.hpoffacpiindex index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..970d43f68bca060361105f70dbb= 00b3a25646db4 100644 GIT binary patch literal 5347 zcmZvgOK%!i6oAjb0K+ig;bCKAY)F$veMSTLl{8HQGuS2pn=3D(#ZiAY0KrHbt?kQ!A=3D zqe>2yk~F*8YS&cq52@5ucinZ-Wz|jpKzF6Oa|inz<;()+KF)XVH=3DL0U*KwV_zj6Sf zlg6&S?Uoy#b?tJwTvh-;+>3AX`EBKa=3DQh0ls9;-`rFq*eCt0_RG&kPk1&JJQ-j;bJYw9$3_eej9HW33A7cierzwt6M2uUQ!RP4=3D$5=3D*;PcVbe zQh|$0dK2Nh8<0@j(Z&ouPnS5x4aDdmMvc$YWsY$ZF?KM6&(jjexP=3D(I z0i&h1&kLgNPS>)n&GX`;+jG+?J>l0mm;L#&h@pMCsOR=3Dvr7uyzb_hz*2 zJ7QPC+e1*I7{S|mn_pOR#4~9*L8~TezUCHa zUZb&d{v6%CUb>_gyI?~L9zhu_D1!r!;A=3DR5&*2e(fcRxvx3`yVf2AL15^7>H0rA^_ zyjR+mRe_8l`t^`_Jkv(FZCN$QBvoTFQ9#60&RZg?3YnA~^W$n4O%Z7Yb3=3DY)^}Hn_ zr&B{R(h4F&;73kZ3Hy=3DL9fbYJ>C~`{tOSu^897}=3D^&_V{Q2og1R8>Y!H?PXb=3D_(Q8 z86ln#>KT!d(^aCxGfF(8)H6ywW5hE?JY&=3D|Mm;s+sS!_&dTP`&PCVnpGfq9@)Ke#( zI`P!0r%pW+#4|xW6Vx+7Jq_Y%5Kn`88q_mMJd?yTNj;O)Geta8#4|-bQ`B>Yc+L>d z8R|JhJx$_i5>JzQn$$B*Jk!K8O+C}pGebNx#4|%ZGt@InJhQ|zOFgsHGeN!t67l`Kq@m!#u z3)HhfJPX9LKs^i8bCGy163<2Ixkx>W#Ir~|i`277J(q~*67gK3o=3DenonRqS}&t>Yl zOg&4)vqU^g)U!18%$c6usKZ%Gocf6WH?m^cj_FTcB_U*hxF+I5d6@?=3D#9@xO%*o_G z@wZHjUVE7b#R$t5z{H-SNNe;xZXCUO$GME_IBwPW6{Ypbu1z;^a4FWBW%~;^3>MTW^^APj@nzl*Cg;mnrVWiC81{;F>sd+iE(V zJbRD_ZWU1^-D^3?t)@c?%CPdT3_Wi4npeb&8s^-=3D#OSx qYeO~+kw5*>id(zrh(UjJ`C@u5FMcp%m{Aqo7@UbcK0Y`+8vG9j4In)L literal 0 HcmV?d00001 --=20 2.49.0 From nobody Sat Nov 15 12:16:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1751546653; cv=none; d=zohomail.com; s=zohoarc; b=ROh+og+O2Oes50k0ZY+aNjxpPVFptby+TFTbseKgNOJXeLSC5i8Cu0IzUMWcoGDbqFZJBikZzAqVUX82W7FABMldaBWawwH53T6EbsdfjCYJ/ExZ60YKjmYqVzG/2Kqs1F6rKLc3jx2nK2vkq3d6LNnwjacgGa0Rvo9sx1+Zrqk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751546653; 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(identity @redhat.com) X-ZM-MESSAGEID: 1751546655135116600 Content-Type: text/plain; charset="utf-8" The disassembled DSDT table is given below. /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20210604 (64-bit version) * Copyright (c) 2000 - 2021 Intel Corporation * * Disassembling to symbolic ASL+ operators * * Disassembly of ../tests/data/acpi/aarch64/virt/DSDT.acpipcihp, Thu Jul = 3 05:16:27 2025 * * Original Table Header: * Signature "DSDT" * Length 0x0000183A (6202) * Revision 0x02 * Checksum 0x98 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPC ", 0x00000001) { Scope (\_SB) { Device (C000) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardwa= re ID Name (_UID, Zero) // _UID: Unique ID } Device (COM0) { Name (_HID, "ARMH0011") // _HID: Hardware ID Name (_UID, Zero) // _UID: Unique ID Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x09000000, // Address Base 0x00001000, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000021, } }) } Device (FWCF) { Name (_HID, "QEMU0002") // _HID: Hardware ID Name (_STA, 0x0B) // _STA: Status Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x09020000, // Address Base 0x00000018, // Address Length ) }) } Device (VR00) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, Zero) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A000000, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000030, } }) } Device (VR01) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, One) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A000200, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000031, } }) } Device (VR02) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x02) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A000400, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000032, } }) } Device (VR03) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x03) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A000600, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000033, } }) } Device (VR04) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x04) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A000800, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000034, } }) } Device (VR05) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x05) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A000A00, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000035, } }) } Device (VR06) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x06) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A000C00, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000036, } }) } Device (VR07) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x07) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A000E00, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000037, } }) } Device (VR08) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x08) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A001000, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000038, } }) } Device (VR09) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x09) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A001200, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000039, } }) } Device (VR10) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x0A) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A001400, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x0000003A, } }) } Device (VR11) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x0B) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A001600, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x0000003B, } }) } Device (VR12) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x0C) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A001800, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x0000003C, } }) } Device (VR13) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x0D) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A001A00, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x0000003D, } }) } Device (VR14) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x0E) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A001C00, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x0000003E, } }) } Device (VR15) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x0F) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A001E00, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x0000003F, } }) } Device (VR16) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x10) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A002000, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000040, } }) } Device (VR17) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x11) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A002200, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000041, } }) } Device (VR18) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x12) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A002400, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000042, } }) } Device (VR19) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x13) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A002600, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000043, } }) } Device (VR20) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x14) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A002800, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000044, } }) } Device (VR21) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x15) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A002A00, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000045, } }) } Device (VR22) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x16) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A002C00, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000046, } }) } Device (VR23) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x17) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A002E00, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000047, } }) } Device (VR24) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x18) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A003000, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000048, } }) } Device (VR25) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x19) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A003200, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000049, } }) } Device (VR26) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x1A) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A003400, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x0000004A, } }) } Device (VR27) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x1B) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A003600, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x0000004B, } }) } Device (VR28) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x1C) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A003800, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x0000004C, } }) } Device (VR29) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x1D) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A003A00, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x0000004D, } }) } Device (VR30) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x1E) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A003C00, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x0000004E, } }) } Device (VR31) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x1F) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Memory32Fixed (ReadWrite, 0x0A003E00, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x0000004F, } }) } Device (L000) { Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID= : Hardware ID Name (_UID, Zero) // _UID: Unique ID Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Set= tings { Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000023, } }) Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000023, } }) Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings { } } Device (L001) { Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID= : Hardware ID Name (_UID, One) // _UID: Unique ID Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Set= tings { Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000024, } }) Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000024, } }) Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings { } } Device (L002) { Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID= : Hardware ID Name (_UID, 0x02) // _UID: Unique ID Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Set= tings { Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000025, } }) Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000025, } }) Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings { } } Device (L003) { Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID= : Hardware ID Name (_UID, 0x03) // _UID: Unique ID Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Set= tings { Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000026, } }) Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, = ,, ) { 0x00000026, } }) Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings { } } Device (PCI0) { Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware= ID Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID Name (_SEG, Zero) // _SEG: PCI Segment Name (_BBN, Zero) // _BBN: BIOS Bus Number Name (_UID, Zero) // _UID: Unique ID Name (_STR, Unicode ("PCIe 0 Device")) // _STR: Description St= ring Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_PRT, Package (0x80) // _PRT: PCI Routing Table { Package (0x04) { 0xFFFF, Zero, L000, Zero }, Package (0x04) { 0xFFFF, One, L001, Zero }, Package (0x04) { 0xFFFF, 0x02, L002, Zero }, Package (0x04) { 0xFFFF, 0x03, L003, Zero }, Package (0x04) { 0x0001FFFF, Zero, L001, Zero }, Package (0x04) { 0x0001FFFF, One, L002, Zero }, Package (0x04) { 0x0001FFFF, 0x02, L003, Zero }, Package (0x04) { 0x0001FFFF, 0x03, L000, Zero }, Package (0x04) { 0x0002FFFF, Zero, L002, Zero }, Package (0x04) { 0x0002FFFF, One, L003, Zero }, Package (0x04) { 0x0002FFFF, 0x02, L000, Zero }, Package (0x04) { 0x0002FFFF, 0x03, L001, Zero }, Package (0x04) { 0x0003FFFF, Zero, L003, Zero }, Package (0x04) { 0x0003FFFF, One, L000, Zero }, Package (0x04) { 0x0003FFFF, 0x02, L001, Zero }, Package (0x04) { 0x0003FFFF, 0x03, L002, Zero }, Package (0x04) { 0x0004FFFF, Zero, L000, Zero }, Package (0x04) { 0x0004FFFF, One, L001, Zero }, Package (0x04) { 0x0004FFFF, 0x02, L002, Zero }, Package (0x04) { 0x0004FFFF, 0x03, L003, Zero }, Package (0x04) { 0x0005FFFF, Zero, L001, Zero }, Package (0x04) { 0x0005FFFF, One, L002, Zero }, Package (0x04) { 0x0005FFFF, 0x02, L003, Zero }, Package (0x04) { 0x0005FFFF, 0x03, L000, Zero }, Package (0x04) { 0x0006FFFF, Zero, L002, Zero }, Package (0x04) { 0x0006FFFF, One, L003, Zero }, Package (0x04) { 0x0006FFFF, 0x02, L000, Zero }, Package (0x04) { 0x0006FFFF, 0x03, L001, Zero }, Package (0x04) { 0x0007FFFF, Zero, L003, Zero }, Package (0x04) { 0x0007FFFF, One, L000, Zero }, Package (0x04) { 0x0007FFFF, 0x02, L001, Zero }, Package (0x04) { 0x0007FFFF, 0x03, L002, Zero }, Package (0x04) { 0x0008FFFF, Zero, L000, Zero }, Package (0x04) { 0x0008FFFF, One, L001, Zero }, Package (0x04) { 0x0008FFFF, 0x02, L002, Zero }, Package (0x04) { 0x0008FFFF, 0x03, L003, Zero }, Package (0x04) { 0x0009FFFF, Zero, L001, Zero }, Package (0x04) { 0x0009FFFF, One, L002, Zero }, Package (0x04) { 0x0009FFFF, 0x02, L003, Zero }, Package (0x04) { 0x0009FFFF, 0x03, L000, Zero }, Package (0x04) { 0x000AFFFF, Zero, L002, Zero }, Package (0x04) { 0x000AFFFF, One, L003, Zero }, Package (0x04) { 0x000AFFFF, 0x02, L000, Zero }, Package (0x04) { 0x000AFFFF, 0x03, L001, Zero }, Package (0x04) { 0x000BFFFF, Zero, L003, Zero }, Package (0x04) { 0x000BFFFF, One, L000, Zero }, Package (0x04) { 0x000BFFFF, 0x02, L001, Zero }, Package (0x04) { 0x000BFFFF, 0x03, L002, Zero }, Package (0x04) { 0x000CFFFF, Zero, L000, Zero }, Package (0x04) { 0x000CFFFF, One, L001, Zero }, Package (0x04) { 0x000CFFFF, 0x02, L002, Zero }, Package (0x04) { 0x000CFFFF, 0x03, L003, Zero }, Package (0x04) { 0x000DFFFF, Zero, L001, Zero }, Package (0x04) { 0x000DFFFF, One, L002, Zero }, Package (0x04) { 0x000DFFFF, 0x02, L003, Zero }, Package (0x04) { 0x000DFFFF, 0x03, L000, Zero }, Package (0x04) { 0x000EFFFF, Zero, L002, Zero }, Package (0x04) { 0x000EFFFF, One, L003, Zero }, Package (0x04) { 0x000EFFFF, 0x02, L000, Zero }, Package (0x04) { 0x000EFFFF, 0x03, L001, Zero }, Package (0x04) { 0x000FFFFF, Zero, L003, Zero }, Package (0x04) { 0x000FFFFF, One, L000, Zero }, Package (0x04) { 0x000FFFFF, 0x02, L001, Zero }, Package (0x04) { 0x000FFFFF, 0x03, L002, Zero }, Package (0x04) { 0x0010FFFF, Zero, L000, Zero }, Package (0x04) { 0x0010FFFF, One, L001, Zero }, Package (0x04) { 0x0010FFFF, 0x02, L002, Zero }, Package (0x04) { 0x0010FFFF, 0x03, L003, Zero }, Package (0x04) { 0x0011FFFF, Zero, L001, Zero }, Package (0x04) { 0x0011FFFF, One, L002, Zero }, Package (0x04) { 0x0011FFFF, 0x02, L003, Zero }, Package (0x04) { 0x0011FFFF, 0x03, L000, Zero }, Package (0x04) { 0x0012FFFF, Zero, L002, Zero }, Package (0x04) { 0x0012FFFF, One, L003, Zero }, Package (0x04) { 0x0012FFFF, 0x02, L000, Zero }, Package (0x04) { 0x0012FFFF, 0x03, L001, Zero }, Package (0x04) { 0x0013FFFF, Zero, L003, Zero }, Package (0x04) { 0x0013FFFF, One, L000, Zero }, Package (0x04) { 0x0013FFFF, 0x02, L001, Zero }, Package (0x04) { 0x0013FFFF, 0x03, L002, Zero }, Package (0x04) { 0x0014FFFF, Zero, L000, Zero }, Package (0x04) { 0x0014FFFF, One, L001, Zero }, Package (0x04) { 0x0014FFFF, 0x02, L002, Zero }, Package (0x04) { 0x0014FFFF, 0x03, L003, Zero }, Package (0x04) { 0x0015FFFF, Zero, L001, Zero }, Package (0x04) { 0x0015FFFF, One, L002, Zero }, Package (0x04) { 0x0015FFFF, 0x02, L003, Zero }, Package (0x04) { 0x0015FFFF, 0x03, L000, Zero }, Package (0x04) { 0x0016FFFF, Zero, L002, Zero }, Package (0x04) { 0x0016FFFF, One, L003, Zero }, Package (0x04) { 0x0016FFFF, 0x02, L000, Zero }, Package (0x04) { 0x0016FFFF, 0x03, L001, Zero }, Package (0x04) { 0x0017FFFF, Zero, L003, Zero }, Package (0x04) { 0x0017FFFF, One, L000, Zero }, Package (0x04) { 0x0017FFFF, 0x02, L001, Zero }, Package (0x04) { 0x0017FFFF, 0x03, L002, Zero }, Package (0x04) { 0x0018FFFF, Zero, L000, Zero }, Package (0x04) { 0x0018FFFF, One, L001, Zero }, Package (0x04) { 0x0018FFFF, 0x02, L002, Zero }, Package (0x04) { 0x0018FFFF, 0x03, L003, Zero }, Package (0x04) { 0x0019FFFF, Zero, L001, Zero }, Package (0x04) { 0x0019FFFF, One, L002, Zero }, Package (0x04) { 0x0019FFFF, 0x02, L003, Zero }, Package (0x04) { 0x0019FFFF, 0x03, L000, Zero }, Package (0x04) { 0x001AFFFF, Zero, L002, Zero }, Package (0x04) { 0x001AFFFF, One, L003, Zero }, Package (0x04) { 0x001AFFFF, 0x02, L000, Zero }, Package (0x04) { 0x001AFFFF, 0x03, L001, Zero }, Package (0x04) { 0x001BFFFF, Zero, L003, Zero }, Package (0x04) { 0x001BFFFF, One, L000, Zero }, Package (0x04) { 0x001BFFFF, 0x02, L001, Zero }, Package (0x04) { 0x001BFFFF, 0x03, L002, Zero }, Package (0x04) { 0x001CFFFF, Zero, L000, Zero }, Package (0x04) { 0x001CFFFF, One, L001, Zero }, Package (0x04) { 0x001CFFFF, 0x02, L002, Zero }, Package (0x04) { 0x001CFFFF, 0x03, L003, Zero }, Package (0x04) { 0x001DFFFF, Zero, L001, Zero }, Package (0x04) { 0x001DFFFF, One, L002, Zero }, Package (0x04) { 0x001DFFFF, 0x02, L003, Zero }, Package (0x04) { 0x001DFFFF, 0x03, L000, Zero }, Package (0x04) { 0x001EFFFF, Zero, L002, Zero }, Package (0x04) { 0x001EFFFF, One, L003, Zero }, Package (0x04) { 0x001EFFFF, 0x02, L000, Zero }, Package (0x04) { 0x001EFFFF, 0x03, L001, Zero }, Package (0x04) { 0x001FFFFF, Zero, L003, Zero }, Package (0x04) { 0x001FFFFF, One, L000, Zero }, Package (0x04) { 0x001FFFFF, 0x02, L001, Zero }, Package (0x04) { 0x001FFFFF, 0x03, L002, Zero } }) Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Ad= dress { Return (0x0000004010000000) } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDec= ode, 0x0000, // Granularity 0x0000, // Range Minimum 0x00FF, // Range Maximum 0x0000, // Translation Offset 0x0100, // Length ,, ) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixe= d, NonCacheable, ReadWrite, 0x00000000, // Granularity 0x10000000, // Range Minimum 0x3EFEFFFF, // Range Maximum 0x00000000, // Translation Offset 0x2EFF0000, // Length ,, , AddressRangeMemory, TypeStatic) DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, E= ntireRange, 0x00000000, // Granularity 0x00000000, // Range Minimum 0x0000FFFF, // Range Maximum 0x3EFF0000, // Translation Offset 0x00010000, // Length ,, , TypeStatic, DenseTranslation) QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixe= d, NonCacheable, ReadWrite, 0x0000000000000000, // Granularity 0x0000008000000000, // Range Minimum 0x000000FFFFFFFFFF, // Range Maximum 0x0000000000000000, // Translation Offset 0x0000008000000000, // Length ,, , AddressRangeMemory, TypeStatic) }) Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capa= bilities { CreateDWordField (Arg3, Zero, CDW1) If ((Arg0 =3D=3D ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd= 766") /* PCI Host Bridge Device */)) { CreateDWordField (Arg3, 0x04, CDW2) CreateDWordField (Arg3, 0x08, CDW3) Local0 =3D CDW3 /* \_SB_.PCI0._OSC.CDW3 */ Local0 &=3D 0x1E If ((Arg1 !=3D One)) { CDW1 |=3D 0x08 } If ((CDW3 !=3D Local0)) { CDW1 |=3D 0x10 } CDW3 =3D Local0 } Else { CDW1 |=3D 0x04 } Return (Arg3) } Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { If ((Arg0 =3D=3D ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c34= 34d") /* Device Labeling Interface */)) { If ((Arg2 =3D=3D Zero)) { Return (Buffer (One) { 0x01 = // . }) } } Return (Buffer (One) { 0x00 // . }) } Device (RES0) { Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // = _HID: Hardware ID Name (_CRS, ResourceTemplate () // _CRS: Current Resource = Settings { QWordMemory (ResourceProducer, PosDecode, MinFixed, Max= Fixed, NonCacheable, ReadWrite, 0x0000000000000000, // Granularity 0x0000004010000000, // Range Minimum 0x000000401FFFFFFF, // Range Maximum 0x0000000000000000, // Translation Offset 0x0000000010000000, // Length ,, , AddressRangeMemory, TypeStatic) }) } } Device (\_SB.GED) { Name (_HID, "ACPI0013" /* Generic Event Device */) // _HID: Ha= rdware ID Name (_UID, "GED") // _UID: Unique ID Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,= , ) { 0x00000029, } }) OperationRegion (EREG, SystemMemory, 0x09080000, 0x04) Field (EREG, DWordAcc, NoLock, WriteAsZeros) { ESEL, 32 } Method (_EVT, 1, Serialized) // _EVT: Event { Local0 =3D ESEL /* \_SB_.GED_.ESEL */ If (((Local0 & 0x02) =3D=3D 0x02)) { Notify (PWRB, 0x80) // Status Change } If (((Local0 & 0x10) =3D=3D 0x10)) { Acquire (\_SB.PCI0.BLCK, 0xFFFF) \_SB.PCI0.PCNT () Release (\_SB.PCI0.BLCK) } } } Device (PWRB) { Name (_HID, "PNP0C0C" /* Power Button Device */) // _HID: Hard= ware ID Name (_UID, Zero) // _UID: Unique ID } } Scope (_SB.PCI0) { OperationRegion (PCST, SystemMemory, 0x090C0000, 0x08) Field (PCST, DWordAcc, NoLock, WriteAsZeros) { PCIU, 32, PCID, 32 } OperationRegion (SEJ, SystemMemory, 0x090C0008, 0x04) Field (SEJ, DWordAcc, NoLock, WriteAsZeros) { B0EJ, 32 } OperationRegion (BNMR, SystemMemory, 0x090C0010, 0x08) Field (BNMR, DWordAcc, NoLock, WriteAsZeros) { BNUM, 32, PIDX, 32 } Mutex (BLCK, 0x00) Method (PCEJ, 2, NotSerialized) { Acquire (BLCK, 0xFFFF) BNUM =3D Arg0 B0EJ =3D (One << Arg1) Release (BLCK) Return (Zero) } Method (AIDX, 2, NotSerialized) { Acquire (BLCK, 0xFFFF) BNUM =3D Arg0 PIDX =3D (One << Arg1) Local0 =3D PIDX /* \_SB_.PCI0.PIDX */ Release (BLCK) Return (Local0) } Method (PDSM, 5, Serialized) { If ((Arg2 =3D=3D Zero)) { Local0 =3D Buffer (One) { 0x00 /= / . } If ((Arg0 !=3D ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434= d") /* Device Labeling Interface */)) { Return (Local0) } If ((Arg1 < 0x02)) { Return (Local0) } Local1 =3D Zero Local2 =3D AIDX (DerefOf (Arg4 [Zero]), DerefOf (Arg4 [One] )) If (!((Local2 =3D=3D Zero) | (Local2 =3D=3D 0xFFFFFFFF))) { Local1 |=3D One Local1 |=3D (One << 0x07) } Local0 [Zero] =3D Local1 Return (Local0) } If ((Arg2 =3D=3D 0x07)) { Local2 =3D AIDX (DerefOf (Arg4 [Zero]), DerefOf (Arg4 [One] )) Local0 =3D Package (0x02) {} If (!((Local2 =3D=3D Zero) || (Local2 =3D=3D 0xFFFFFFFF))) { Local0 [Zero] =3D Local2 Local0 [One] =3D "" } Return (Local0) } } } Scope (\_SB.PCI0) { Method (EDSM, 5, Serialized) { If ((Arg2 =3D=3D Zero)) { Local0 =3D Buffer (One) { 0x00 /= / . } If ((Arg0 !=3D ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434= d") /* Device Labeling Interface */)) { Return (Local0) } If ((Arg1 < 0x02)) { Return (Local0) } Local0 [Zero] =3D 0x81 Return (Local0) } If ((Arg2 =3D=3D 0x07)) { Local0 =3D Package (0x02) { Zero, "" } Local1 =3D DerefOf (Arg4 [Zero]) Local0 [Zero] =3D Local1 Return (Local0) } } Device (S00) { Name (_ADR, Zero) // _ADR: Address } Device (S08) { Name (_ADR, 0x00010000) // _ADR: Address } Device (S38) { Name (_ADR, 0x00070000) // _ADR: Address Device (S00) { Name (_ADR, Zero) // _ADR: Address } Name (BSEL, One) Scope (S00) { Name (ASUN, Zero) Method (_DSM, 4, Serialized) // _DSM: Device-Specific Meth= od { Local0 =3D Package (0x02) { Zero, Zero } Local0 [Zero] =3D BSEL /* \_SB_.PCI0.S38_.BSEL */ Local0 [One] =3D ASUN /* \_SB_.PCI0.S38_.S00_.ASUN */ Return (PDSM (Arg0, Arg1, Arg2, Arg3, Local0)) } Name (_SUN, Zero) // _SUN: Slot User Number Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x= =3D0-9 { PCEJ (BSEL, _SUN) } } Method (DVNT, 2, NotSerialized) { If ((Arg0 & One)) { Notify (S00, Arg1) } } } Name (BSEL, Zero) Scope (S00) { Name (ASUN, Zero) Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method { Local0 =3D Package (0x02) { Zero, Zero } Local0 [Zero] =3D BSEL /* \_SB_.PCI0.BSEL */ Local0 [One] =3D ASUN /* \_SB_.PCI0.S00_.ASUN */ Return (PDSM (Arg0, Arg1, Arg2, Arg3, Local0)) } Name (_SUN, Zero) // _SUN: Slot User Number Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=3D0-9 { PCEJ (BSEL, _SUN) } } Scope (S08) { Name (ASUN, One) Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method { Local0 =3D Package (0x02) { Zero, Zero } Local0 [Zero] =3D BSEL /* \_SB_.PCI0.BSEL */ Local0 [One] =3D ASUN /* \_SB_.PCI0.S08_.ASUN */ Return (PDSM (Arg0, Arg1, Arg2, Arg3, Local0)) } Name (_SUN, One) // _SUN: Slot User Number Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=3D0-9 { PCEJ (BSEL, _SUN) } } Method (DVNT, 2, NotSerialized) { If ((Arg0 & One)) { Notify (S00, Arg1) } If ((Arg0 & 0x02)) { Notify (S08, Arg1) } } Device (PHPR) { Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID:= Hardware ID Name (_UID, "PCI Hotplug resources") // _UID: Unique ID Name (_STA, 0x0B) // _STA: Status Name (_CRS, ResourceTemplate () // _CRS: Current Resource Sett= ings { IO (Decode16, 0x0000, // Range Minimum 0x0000, // Range Maximum 0x01, // Alignment 0x18, // Length ) }) } Scope (S38) { Method (PCNT, 0, NotSerialized) { BNUM =3D One DVNT (PCIU, One) DVNT (PCID, 0x03) } } Method (PCNT, 0, NotSerialized) { BNUM =3D Zero DVNT (PCIU, One) DVNT (PCID, 0x03) ^S38.PCNT () } } } Signed-off-by: Eric Auger --- tests/qtest/bios-tables-test-allowed-diff.h | 1 - tests/data/acpi/aarch64/virt/DSDT.acpipcihp | Bin 0 -> 6202 bytes 2 files changed, 1 deletion(-) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index dc3ab24d05..dfb8523c8b 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,2 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/aarch64/virt/DSDT.acpipcihp", diff --git a/tests/data/acpi/aarch64/virt/DSDT.acpipcihp b/tests/data/acpi/= aarch64/virt/DSDT.acpipcihp index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..8d55a877a40cb4c4dffdc703782= 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