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([187.210.107.185]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-2efd50f7d89sm3907004fac.34.2025.07.02.05.42.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Jul 2025 05:42:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751460124; x=1752064924; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=20kn4eYbxYwfStQX/tEOBcIiKRrQrxRWQALB+sLrCqM=; b=xEiD1yCdj8+UrRqy++o9frgUG0hyDsT1tNNUJPHZ6MniFhvIgJXxGYxcsXVttgotMV +EwP6YrbfVixuIGN2ctpDv9OBD8l7p1fqroMO2sk08ehtu4VYCJwCCAz12AnbAVFjhTF tq3WMoI1kIBFxVXg3QcdiKDM5YDwxhCQCR0/kmj8DP29SDPq7s1NvmGH9NrJNTHZUj9d +VAv8cGjQQp9HDlqnsrDME/OJbMX6HVIisoG3LI8nPmh3/Dj3z6cO4+3l+SQbFeZM36U 8COWry3N7Pz6Hj+sdl8MpfiaRtswZJT8xSMmVyx6bRUFv9VHPJswuP1hDezw96jaGl4o 5uTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751460124; x=1752064924; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=20kn4eYbxYwfStQX/tEOBcIiKRrQrxRWQALB+sLrCqM=; b=WsH5rTTrCxyLEtZTbirFRQ/bBB5N2CPEfqutGJQM3Q67fxFuqqC7k8lyreAkNfdzhZ ezIR1GAxEnk3AiPdvg+lrI85PIIzXMtSfdPg3eSLWbRCvgraeGX7DeZubg1XkdDeKkIa 8DvKC2p+y7d2lv2Lvr9lspgf9Isp2N6lB5vd1yV+D3/d1JpWx7hZJJq2bRtUGseFKk5V xwGoBxPXDisAnLgezGqSH/qdgmTgFatstksgHDAiH6e19uU9+QWmo/LprDHcBCilm/wm Y4XJRps0VZ+03UnjfOfjXzgWerR1SdeXCZsxnkGh836aTEnFuEMml6Hho4679zLRhGEr WmEA== X-Gm-Message-State: AOJu0Yy3IVdUh2MFa/Ao5W+Dj7yumYjOP8DUC/9GVk/xfgUCb6c4hJTP 4We/JUjv51CNGIqyqMHbYwgjIOEIaYKl/M3OtsDDJ0yaYR+xziKSous6XSPiASOtLg4IWKO7ILt lAuQBxek= X-Gm-Gg: ASbGnct57qpXSGEK4JVg9BH95Ne/5dSo3hk/o1J5UKEV5U+rvT0VjYyD+vHTTqOAMsY E3exBbSl0noxiAd3h2MBltAV7DbqVptqR/QNwwwQc5QmrrQvbmfnp8W0rcSN8lfoDCKMO/Ov3wr qXMyAnmhKVtlvDwehBeuMbsqn3wmmBMhwRttuswu3fLjbdrnTVQxmbMA2wcI3PZP82a84aYpnWN gzgqr8dPxpCqBggcUWpfRII+OjvU5w/EQ6kefBXyV7wE7aqUmiqn1tRHceFTy/d0cy1Vb/AST7N Z6oqaxYYhqbPFfxyq1fYDjCwbA510gta4/VbrjpObqMH2RMOGkgSf79VM48sUWIFf3BOjA== X-Google-Smtp-Source: AGHT+IGRyrp8Hpcb0W86klQq2+DaBkGAIEjXZaowzM1Cmc8GTwJXRrj3ZlRAKVK9sp/LoJyfdvRMjA== X-Received: by 2002:a05:6870:32d1:b0:2ee:2800:8592 with SMTP id 586e51a60fabf-2f5a8c8e296mr1883885fac.23.1751460123652; Wed, 02 Jul 2025 05:42:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 85/97] target/arm: Move ld1qq and st1qq primitives to sve_ldst_internal.h Date: Wed, 2 Jul 2025 06:33:58 -0600 Message-ID: <20250702123410.761208-86-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250702123410.761208-1-richard.henderson@linaro.org> References: <20250702123410.761208-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2d; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751461115905116600 Content-Type: text/plain; charset="utf-8" Move from sme_helper.c to the shared header. Add a comment noting the lack of atomicity. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/tcg/sve_ldst_internal.h | 63 ++++++++++++++++++++++++++++++ target/arm/tcg/sme_helper.c | 44 +++------------------ 2 files changed, 69 insertions(+), 38 deletions(-) diff --git a/target/arm/tcg/sve_ldst_internal.h b/target/arm/tcg/sve_ldst_i= nternal.h index e87beba435..c67cda9d3b 100644 --- a/target/arm/tcg/sve_ldst_internal.h +++ b/target/arm/tcg/sve_ldst_internal.h @@ -141,6 +141,69 @@ DO_LD_PRIM_3(ld1dqu_le, ld1dd_le) #define sve_st1dq_be_tlb sve_st1dd_be_tlb #define sve_st1dq_le_tlb sve_st1dd_le_tlb =20 +/* + * The ARMVectorReg elements are stored in host-endian 64-bit units. + * For 128-bit quantities, the sequence defined by the Elem[] pseudocode + * corresponds to storing the two 64-bit pieces in little-endian order. + */ +/* FIXME: Nothing in this file makes any effort at atomicity. */ + +static inline void sve_ld1qq_be_host(void *vd, intptr_t reg_off, void *hos= t) +{ + sve_ld1dd_be_host(vd, reg_off + 8, host); + sve_ld1dd_be_host(vd, reg_off, host + 8); +} + +static inline void sve_ld1qq_le_host(void *vd, intptr_t reg_off, void *hos= t) +{ + sve_ld1dd_le_host(vd, reg_off, host); + sve_ld1dd_le_host(vd, reg_off + 8, host + 8); +} + +static inline void +sve_ld1qq_be_tlb(CPUARMState *env, void *vd, intptr_t reg_off, + target_ulong addr, uintptr_t ra) +{ + sve_ld1dd_be_tlb(env, vd, reg_off + 8, addr, ra); + sve_ld1dd_be_tlb(env, vd, reg_off, addr + 8, ra); +} + +static inline void +sve_ld1qq_le_tlb(CPUARMState *env, void *vd, intptr_t reg_off, + target_ulong addr, uintptr_t ra) +{ + sve_ld1dd_le_tlb(env, vd, reg_off, addr, ra); + sve_ld1dd_le_tlb(env, vd, reg_off + 8, addr + 8, ra); +} + +static inline void sve_st1qq_be_host(void *vd, intptr_t reg_off, void *hos= t) +{ + sve_st1dd_be_host(vd, reg_off + 8, host); + sve_st1dd_be_host(vd, reg_off, host + 8); +} + +static inline void sve_st1qq_le_host(void *vd, intptr_t reg_off, void *hos= t) +{ + sve_st1dd_le_host(vd, reg_off, host); + sve_st1dd_le_host(vd, reg_off + 8, host + 8); +} + +static inline void +sve_st1qq_be_tlb(CPUARMState *env, void *vd, intptr_t reg_off, + target_ulong addr, uintptr_t ra) +{ + sve_st1dd_be_tlb(env, vd, reg_off + 8, addr, ra); + sve_st1dd_be_tlb(env, vd, reg_off, addr + 8, ra); +} + +static inline void +sve_st1qq_le_tlb(CPUARMState *env, void *vd, intptr_t reg_off, + target_ulong addr, uintptr_t ra) +{ + sve_st1dd_le_tlb(env, vd, reg_off, addr, ra); + sve_st1dd_le_tlb(env, vd, reg_off + 8, addr + 8, ra); +} + #undef DO_LD_TLB #undef DO_ST_TLB #undef DO_LD_HOST diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index 77eab68870..19c4c2efa2 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -408,54 +408,22 @@ static inline void sme_##NAME##_v_tlb(CPUARMState *en= v, void *za, \ TLB(env, useronly_clean_ptr(addr), val, ra); = \ } =20 -/* - * The ARMVectorReg elements are stored in host-endian 64-bit units. - * For 128-bit quantities, the sequence defined by the Elem[] pseudocode - * corresponds to storing the two 64-bit pieces in little-endian order. - */ -#define DO_LDQ(HNAME, VNAME, BE, HOST, TLB) = \ -static inline void HNAME##_host(void *za, intptr_t off, void *host) = \ -{ = \ - uint64_t val0 =3D HOST(host), val1 =3D HOST(host + 8); = \ - uint64_t *ptr =3D za + off; = \ - ptr[0] =3D BE ? val1 : val0, ptr[1] =3D BE ? val0 : val1; = \ -} = \ +#define DO_LDQ(HNAME, VNAME) \ static inline void VNAME##_v_host(void *za, intptr_t off, void *host) = \ { = \ HNAME##_host(za, tile_vslice_offset(off), host); = \ } = \ -static inline void HNAME##_tlb(CPUARMState *env, void *za, intptr_t off, = \ - target_ulong addr, uintptr_t ra) = \ -{ = \ - uint64_t val0 =3D TLB(env, useronly_clean_ptr(addr), ra); = \ - uint64_t val1 =3D TLB(env, useronly_clean_ptr(addr + 8), ra); = \ - uint64_t *ptr =3D za + off; = \ - ptr[0] =3D BE ? val1 : val0, ptr[1] =3D BE ? val0 : val1; = \ -} = \ static inline void VNAME##_v_tlb(CPUARMState *env, void *za, intptr_t off,= \ target_ulong addr, uintptr_t ra) = \ { = \ HNAME##_tlb(env, za, tile_vslice_offset(off), addr, ra); = \ } =20 -#define DO_STQ(HNAME, VNAME, BE, HOST, TLB) = \ -static inline void HNAME##_host(void *za, intptr_t off, void *host) = \ -{ = \ - uint64_t *ptr =3D za + off; = \ - HOST(host, ptr[BE]); = \ - HOST(host + 8, ptr[!BE]); = \ -} = \ +#define DO_STQ(HNAME, VNAME) \ static inline void VNAME##_v_host(void *za, intptr_t off, void *host) = \ { = \ HNAME##_host(za, tile_vslice_offset(off), host); = \ } = \ -static inline void HNAME##_tlb(CPUARMState *env, void *za, intptr_t off, = \ - target_ulong addr, uintptr_t ra) = \ -{ = \ - uint64_t *ptr =3D za + off; = \ - TLB(env, useronly_clean_ptr(addr), ptr[BE], ra); = \ - TLB(env, useronly_clean_ptr(addr + 8), ptr[!BE], ra); = \ -} = \ static inline void VNAME##_v_tlb(CPUARMState *env, void *za, intptr_t off,= \ target_ulong addr, uintptr_t ra) = \ { = \ @@ -470,8 +438,8 @@ DO_LD(ld1s_le, uint32_t, ldl_le_p, cpu_ldl_le_data_ra) DO_LD(ld1d_be, uint64_t, ldq_be_p, cpu_ldq_be_data_ra) DO_LD(ld1d_le, uint64_t, ldq_le_p, cpu_ldq_le_data_ra) =20 -DO_LDQ(sve_ld1qq_be, sme_ld1q_be, 1, ldq_be_p, cpu_ldq_be_data_ra) -DO_LDQ(sve_ld1qq_le, sme_ld1q_le, 0, ldq_le_p, cpu_ldq_le_data_ra) +DO_LDQ(sve_ld1qq_be, sme_ld1q_be) +DO_LDQ(sve_ld1qq_le, sme_ld1q_le) =20 DO_ST(st1b, uint8_t, stb_p, cpu_stb_data_ra) DO_ST(st1h_be, uint16_t, stw_be_p, cpu_stw_be_data_ra) @@ -481,8 +449,8 @@ DO_ST(st1s_le, uint32_t, stl_le_p, cpu_stl_le_data_ra) DO_ST(st1d_be, uint64_t, stq_be_p, cpu_stq_be_data_ra) DO_ST(st1d_le, uint64_t, stq_le_p, cpu_stq_le_data_ra) =20 -DO_STQ(sve_st1qq_be, sme_st1q_be, 1, stq_be_p, cpu_stq_be_data_ra) -DO_STQ(sve_st1qq_le, sme_st1q_le, 0, stq_le_p, cpu_stq_le_data_ra) +DO_STQ(sve_st1qq_be, sme_st1q_be) +DO_STQ(sve_st1qq_le, sme_st1q_le) =20 #undef DO_LD #undef DO_ST --=20 2.43.0