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([187.210.107.185]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-2efd4ea5d9fsm3843451fac.10.2025.07.02.05.38.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Jul 2025 05:38:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751459915; x=1752064715; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6v/8hNQy8fFPp5bDwpch38EpRvO2SIx0CPU+DT6r9Io=; b=bXq0ZAa8oCZz3vbZtPDhbk8ektzu/8givoHpRpv/SFGMWK85CyhduOPF/4FLF7btwd hMvfgma65+30tx0yuDu4WpvNpkc5m1eJBhv+hEj9QR1NRj4y6pwRURtBIN9HYL3dMwo4 B/3aZ+anJhWZP2l1DZ/1nEEXGEMNGzTHrRiXdXGY05c3/a8pac9z5Nk38no+MCI6kgUX zuxtUffqPMHi0uLcqb1DqhCcIEWLD6+jz2Oe7QR44wadS00WyhutyJXO17O9SWZamt4M 3UFuO8/KKAG85H0oOj6Ibr5syZXziyhlyfsfEH+5tF4UKOkEXYTeUit7cpAxru2lm7p9 5Vow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751459915; x=1752064715; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6v/8hNQy8fFPp5bDwpch38EpRvO2SIx0CPU+DT6r9Io=; b=N5ERv7kK1Sx9iqF06omk4N78BfTaDfQc9Vd6PIENXyPH+2XrXi0XLTg4T7Gc86RcUA m1hKKyU73U5Z9eagJbQh5qc+bpFXTP5TLF7TkrA6R0hmxaIWxJ91kSprjgPoWS4G8WDO ozXlLfL4OgEQMmHHIH2LCai2hXJ3Uhthmlb3zMeRHCoiKjv9n3DW2pjQpppjwMyTqEUl ANw45j7y+lf2RY2feSiDygxafl6lTGcyyJUl0WLdlwyYdQ0tutW8Ec401mLdkwFORAau a5A6Nok8/8Bvr5gIlv9HH4+baT+eWqi070Yy3PpAlmsFoeYBiiNfgXixd1CgWqq60FLv xkoQ== X-Gm-Message-State: AOJu0YwJ0RbSzNQ+sc4TLErE/7weLzLBoDpkjLC0ZFNeVz+w1t/6/3zR 25KSp2fVqs0JyzB4sPWfuk5KLQtyg2GmvSQ3zR8W45+BzMM5RnDpbL/t7f41WdgDdqLCxYGeVX1 1RbNm2Vs= X-Gm-Gg: ASbGncsFsgAkjM1sKEDkJJpRfu7yPuLo0xpMaYpIQm2aJfuHrwfHOg7NiRCRrfzMk9V DKZLqhycbi85OzoNskysFQ3IvBj3d+FrFV5VVzqh2Iyl2J+tIGKyzy3yr4cWJMc6rTBHr+crN63 rq31wzGmYfSbj19A6onefrqM1GxvhHtrtoNbb4Jy1tneNwTxNzVQPLSm27/jZyVIGz/FfT82lj9 jnfQrwNm6ymgxF/IOhjhINkO8tnmmYhsh/+GfgZl10GGwUvw4rYjPlcaZup31yWIGg53HX28zVL 1hwna2fO5SbWZSkcM5xha8K4vVjI9URmdVb56zI6wPKedHZ2BAW9cgaNNsbZGWDx9Q/NUg== X-Google-Smtp-Source: AGHT+IGkl21D44Jth5E2OxdM4Kn0uoohFGfIglxI7ATXg08bjDeRoSHmFb4B1TNJ4wJ7rYMyD3hLFA== X-Received: by 2002:a05:6871:2881:b0:2ef:9aa7:becb with SMTP id 586e51a60fabf-2f5a8c97853mr2030240fac.18.1751459915006; Wed, 02 Jul 2025 05:38:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org Subject: [PATCH v3 64/97] target/arm: Move scale by esz into helper_sve_while* Date: Wed, 2 Jul 2025 06:33:37 -0600 Message-ID: <20250702123410.761208-65-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250702123410.761208-1-richard.henderson@linaro.org> References: <20250702123410.761208-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::34; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x34.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751463719170116600 Content-Type: text/plain; charset="utf-8" Change the API to pass element count rather than bit count. This will be helpful later for predicate as counter. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/tcg/sve_helper.c | 2 ++ target/arm/tcg/translate-sve.c | 13 +++++-------- 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index ba5ab6b513..dbade6ece0 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -4135,6 +4135,7 @@ uint32_t HELPER(sve_whilel)(void *vd, uint32_t count,= uint32_t pred_desc) uint32_t oprbits =3D oprsz * 8; uint64_t esz_mask =3D pred_esz_masks[esz]; =20 + count <<=3D esz; do_zero(vd, oprsz); do_whilel(vd, esz_mask, count, oprbits); =20 @@ -4166,6 +4167,7 @@ uint32_t HELPER(sve_whileg)(void *vd, uint32_t count,= uint32_t pred_desc) uint32_t oprbits =3D oprsz * 8; uint64_t esz_mask =3D pred_esz_masks[esz]; =20 + count <<=3D esz; do_zero(vd, oprsz); do_whileg(vd, esz_mask, count, oprbits); =20 diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 210a029ab8..f74f2bb1b3 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -3198,9 +3198,6 @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a) t2 =3D tcg_temp_new_i32(); tcg_gen_extrl_i64_i32(t2, t0); =20 - /* Scale elements to bits. */ - tcg_gen_shli_i32(t2, t2, a->esz); - desc =3D FIELD_DP32(desc, PREDDESC, OPRSZ, vsz / 8); desc =3D FIELD_DP32(desc, PREDDESC, ESZ, a->esz); =20 @@ -3234,7 +3231,7 @@ static bool trans_WHILE_ptr(DisasContext *s, arg_WHIL= E_ptr *a) op0 =3D read_cpu_reg(s, a->rn, 1); op1 =3D read_cpu_reg(s, a->rm, 1); =20 - tmax =3D tcg_constant_i64(vsz); + tmax =3D tcg_constant_i64(vsz >> a->esz); diff =3D tcg_temp_new_i64(); =20 if (a->rw) { @@ -3244,15 +3241,15 @@ static bool trans_WHILE_ptr(DisasContext *s, arg_WH= ILE_ptr *a) tcg_gen_sub_i64(diff, op0, op1); tcg_gen_sub_i64(t1, op1, op0); tcg_gen_movcond_i64(TCG_COND_GEU, diff, op0, op1, diff, t1); - /* Round down to a multiple of ESIZE. */ - tcg_gen_andi_i64(diff, diff, -1 << a->esz); + /* Divide, rounding down, by ESIZE. */ + tcg_gen_shri_i64(diff, diff, a->esz); /* If op1 =3D=3D op0, diff =3D=3D 0, and the condition is always t= rue. */ tcg_gen_movcond_i64(TCG_COND_EQ, diff, op0, op1, tmax, diff); } else { /* WHILEWR */ tcg_gen_sub_i64(diff, op1, op0); - /* Round down to a multiple of ESIZE. */ - tcg_gen_andi_i64(diff, diff, -1 << a->esz); + /* Divide, rounding down, by ESIZE. */ + tcg_gen_shri_i64(diff, diff, a->esz); /* If op0 >=3D op1, diff <=3D 0, the condition is always true. */ tcg_gen_movcond_i64(TCG_COND_GEU, diff, op0, op1, tmax, diff); } --=20 2.43.0