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([187.210.107.185]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-2efd50b1bd3sm3785013fac.28.2025.07.02.05.22.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Jul 2025 05:22:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751458945; x=1752063745; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wJq8Ct14ZkJ7UIbuFZO9txkdxmDUbAj15XGDsXarXQw=; b=UqHYRTSEfCmn/L4BqmtKW1WznntwfGQODf/6W0H58JdvrYI4pxYsnCHEqefcVaUneH pElzn6NaeJavEIRDasJ02FcggcTs4Yol45aDApEGuGeh2RVyPQo3BU2RBV2342k0L/8y 9TTOC6hbWjMgD52qCaC5aip1rlyuS5O+iaqrG7JFm3P4P4LX4g2/xxv6R7zQFKn77AVS FO7ck4S6jOyYTHOjoZA01gW9WpTVYOyYCAAZ3O+JI5kYyqbi7GLSjIJYlsvGT/aOf5Xw xuy6sd15f3pXcaKzuS0xYqL97rxVjsl5QgXwno+O+UYrGUg7TYOWLnTWypesBkoioRsz HruA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751458945; x=1752063745; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wJq8Ct14ZkJ7UIbuFZO9txkdxmDUbAj15XGDsXarXQw=; b=FPV8/x26B2ZEmLOIniXfYvV/sUoNX6IsoBRRvjxMgvDk52SsOWIvNlAmhXLpCTlYH0 buZMbtsdz/8hpzhQw+i62FqrzJiXI+rxfUJ8JREqFnGvYziKMDoQVymxS9LOzjXYSYpp 16HydEpMiaTE1vjjniWEB/ieR4IIXBBO/Ssqbv7hqL7O9qbJl5cY5YdE5dCFnNsbuae5 TmBfy1zLBvY8aBHg0Waz0FlX5fVam/sGU0UsTEUgzPAMxo3As8hZBtQbxLU0JxaTJDnf 5UAb9ZKaFDowPxmfqhEA70JIkTrNGbs/Qy6Rd3LmIv9ETXVydRnc57Q2dml/VCr+zVpZ 0akQ== X-Gm-Message-State: AOJu0YyUEnjDA6WPjatQzLfvs2EsclwlGTP3AFKZihdkLAebIiBAL9Mu S7UXtBte7gTB3Wp9QBHva7U/c32l1nFfhdJAQp4J5IkBEBkI8ph7dN7YfMNzMcoKMEgl6yPjVtz 1ZJi4wUw= X-Gm-Gg: ASbGncsTQWm0WMOM9EWeipKQITKtCZi/2B26Cp/3W36WVqsrQRBxaFsjorbp6pq8u+1 8qsqSt/fO/mPmna0oPyv3ztp/bH8oyucSCUtZIqDQgHsXQXS2jRsmpLMjJPUjRPRA0zgRMYxheQ j0h5u6ASirhVD7z0B4dKlddz7Uqzqg9kX2HIn7EITXKcFZ80DukGBId5vJY0E6Zp6FTMJFVvN5o Gkr1pbJmvdomRzQa+hcSl1nuobYz2xxx4NilmWZshm2L/ct5UOcP/foqUULFkZKPFL5nyS7sXi7 6Xp1HhOOn+xrnB7c99dNgXpts1e006wpYyevQ280dwJmip/5Qt0Kr5DHkpVXr8JrYZS2Yg== X-Google-Smtp-Source: AGHT+IEIRUPE3usqCxNJwLC4aKA79SIrXOgCq4MUPCYQyjfqvVHamPQvUVsplWIzLvq9zFG3zO4WiA== X-Received: by 2002:a05:6871:440f:b0:2c2:561c:47e3 with SMTP id 586e51a60fabf-2f5a8c977eamr1585633fac.21.1751458945558; Wed, 02 Jul 2025 05:22:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, qemu-stable@nongnu.org Subject: [PATCH v3 08/10] target/arm: Fix f16_dotadd vs nan selection Date: Wed, 2 Jul 2025 06:22:11 -0600 Message-ID: <20250702122213.758588-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250702122213.758588-1-richard.henderson@linaro.org> References: <20250702122213.758588-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::34; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x34.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751459025890116600 Content-Type: text/plain; charset="utf-8" Implement FPProcessNaNs4 within f16_dotadd, rather than simply letting NaNs propagate through the function. Cc: qemu-stable@nongnu.org Fixes: 3916841ac75 ("target/arm: Implement FMOPA, FMOPS (widening)") Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/tcg/sme_helper.c | 62 +++++++++++++++++++++++++++---------- 1 file changed, 46 insertions(+), 16 deletions(-) diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index de0c6e54d4..8f33387e4b 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -1005,25 +1005,55 @@ static float32 f16_dotadd(float32 sum, uint32_t e1,= uint32_t e2, * - we have pre-set-up copy of s_std which is set to round-to-odd, * for the multiply (see below) */ - float64 e1r =3D float16_to_float64(e1 & 0xffff, true, s_f16); - float64 e1c =3D float16_to_float64(e1 >> 16, true, s_f16); - float64 e2r =3D float16_to_float64(e2 & 0xffff, true, s_f16); - float64 e2c =3D float16_to_float64(e2 >> 16, true, s_f16); - float64 t64; + float16 h1r =3D e1 & 0xffff; + float16 h1c =3D e1 >> 16; + float16 h2r =3D e2 & 0xffff; + float16 h2c =3D e2 >> 16; float32 t32; =20 - /* - * The ARM pseudocode function FPDot performs both multiplies - * and the add with a single rounding operation. Emulate this - * by performing the first multiply in round-to-odd, then doing - * the second multiply as fused multiply-add, and rounding to - * float32 all in one step. - */ - t64 =3D float64_mul(e1r, e2r, s_odd); - t64 =3D float64r32_muladd(e1c, e2c, t64, 0, s_std); + /* C.f. FPProcessNaNs4 */ + if (float16_is_any_nan(h1r) || float16_is_any_nan(h1c) || + float16_is_any_nan(h2r) || float16_is_any_nan(h2c)) { + float16 t16; =20 - /* This conversion is exact, because we've already rounded. */ - t32 =3D float64_to_float32(t64, s_std); + if (float16_is_signaling_nan(h1r, s_f16)) { + t16 =3D h1r; + } else if (float16_is_signaling_nan(h1c, s_f16)) { + t16 =3D h1c; + } else if (float16_is_signaling_nan(h2r, s_f16)) { + t16 =3D h2r; + } else if (float16_is_signaling_nan(h2c, s_f16)) { + t16 =3D h2c; + } else if (float16_is_any_nan(h1r)) { + t16 =3D h1r; + } else if (float16_is_any_nan(h1c)) { + t16 =3D h1c; + } else if (float16_is_any_nan(h2r)) { + t16 =3D h2r; + } else { + t16 =3D h2c; + } + t32 =3D float16_to_float32(t16, true, s_f16); + } else { + float64 e1r =3D float16_to_float64(h1r, true, s_f16); + float64 e1c =3D float16_to_float64(h1c, true, s_f16); + float64 e2r =3D float16_to_float64(h2r, true, s_f16); + float64 e2c =3D float16_to_float64(h2c, true, s_f16); + float64 t64; + + /* + * The ARM pseudocode function FPDot performs both multiplies + * and the add with a single rounding operation. Emulate this + * by performing the first multiply in round-to-odd, then doing + * the second multiply as fused multiply-add, and rounding to + * float32 all in one step. + */ + t64 =3D float64_mul(e1r, e2r, s_odd); + t64 =3D float64r32_muladd(e1c, e2c, t64, 0, s_std); + + /* This conversion is exact, because we've already rounded. */ + t32 =3D float64_to_float32(t64, s_std); + } =20 /* The final accumulation step is not fused. */ return float32_add(sum, t32, s_std); --=20 2.43.0