From nobody Sat Nov 15 14:53:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1751391075; cv=none; d=zohomail.com; s=zohoarc; b=agoF6EedwpwolGLTgF7unPo0vWNcUQN0kOLjAhT/kOscviii1FtXedIrQHjghq00geExJUlKVYJXU+/IL+KpCQ1fdUpOrgNIXzWT8nLpGr4rZPV/OLl08q9wQ5ZAts0gBiMI+OxPpNCpm/Bn8ni+sbTkla1+jS/+JIy947/JzMg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751391075; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=c9G5jqgbSCxpruLnLGaQ/ULvofCIGPDnFonvhQCzbgE=; b=Bnpk5xZYa7QRqKiA3NRPqMWEFW8WEdLuqQfp/5G0LIOx+lLXQcq3DX465Wa1SZloEmZ/HDQ9S5lkrn2htIIZhcvB5jaBlm7Lvrj8PXpZp6d/UKX1yTBLFziAGnt4S/LCe3/+YqFzrEqRW2vlSl0mx63ACdyEvotD9/c6s9bas+A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1751391075966608.6754514264243; Tue, 1 Jul 2025 10:31:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uWeoP-0005Dd-IE; Tue, 01 Jul 2025 13:30:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uWeoM-00052g-71 for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:30:26 -0400 Received: from linux.microsoft.com ([13.77.154.182]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uWeoJ-0007DO-Nq for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:30:25 -0400 Received: from localhost.localdomain (unknown [167.220.208.67]) by linux.microsoft.com (Postfix) with ESMTPSA id 759112119388; Tue, 1 Jul 2025 10:30:07 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 759112119388 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1751391011; bh=c9G5jqgbSCxpruLnLGaQ/ULvofCIGPDnFonvhQCzbgE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bV9ScnJehozLtJrX3hLSJGPfkqjp5PgBdFZaUgZd/RUZ6PZaQf3ijESSESjY8/ThO e536Iq5O1TJ0xGvycwEwQrIPbii93BJvx8OxRU7sgZgG+b+YK4IcZ1hY8H2QfplFjj Xu08f0o3fA6sGylAJIHlH7O59yzw2oBQMKczEaMw= From: Magnus Kulke To: qemu-devel@nongnu.org Cc: Cameron Esfahani , Phil Dennis-Jordan , Roman Bolshakov , Thomas Huth , Zhao Liu , Wei Liu , Paolo Bonzini , Wei Liu , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Markus Armbruster , Cornelia Huck , Magnus Kulke , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , "Michael S. Tsirkin" , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v2 17/27] target/i386/mshv: Implement mshv_get_special_regs() Date: Tue, 1 Jul 2025 19:28:24 +0200 Message-Id: <20250701172834.44849-18-magnuskulke@linux.microsoft.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250701172834.44849-1-magnuskulke@linux.microsoft.com> References: <20250701172834.44849-1-magnuskulke@linux.microsoft.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=magnuskulke@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1751391078255116600 Content-Type: text/plain; charset="utf-8" Retrieve special registers (e.g. segment, control, and descriptor table registers) from MSHV vCPUs. Various helper functions to map register state representations between Qemu and MSHV are introduced. Signed-off-by: Magnus Kulke --- include/system/mshv.h | 1 + target/i386/mshv/mshv-cpu.c | 105 ++++++++++++++++++++++++++++++++++++ 2 files changed, 106 insertions(+) diff --git a/include/system/mshv.h b/include/system/mshv.h index 65f7fa15a0..7d0fed3c42 100644 --- a/include/system/mshv.h +++ b/include/system/mshv.h @@ -89,6 +89,7 @@ void mshv_init_cpu_logic(void); int mshv_create_vcpu(int vm_fd, uint8_t vp_index, int *cpu_fd); void mshv_remove_vcpu(int vm_fd, int cpu_fd); int mshv_get_standard_regs(CPUState *cpu); +int mshv_get_special_regs(CPUState *cpu); int mshv_run_vcpu(int vm_fd, CPUState *cpu, hv_message *msg, MshvVmExit *e= xit); int mshv_load_regs(CPUState *cpu); int mshv_store_regs(CPUState *cpu); diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c index cb59d74eb4..53b6722af4 100644 --- a/target/i386/mshv/mshv-cpu.c +++ b/target/i386/mshv/mshv-cpu.c @@ -51,6 +51,26 @@ static enum hv_register_name STANDARD_REGISTER_NAMES[18]= =3D { HV_X64_REGISTER_RFLAGS, }; =20 +static enum hv_register_name SPECIAL_REGISTER_NAMES[17] =3D { + HV_X64_REGISTER_CS, + HV_X64_REGISTER_DS, + HV_X64_REGISTER_ES, + HV_X64_REGISTER_FS, + HV_X64_REGISTER_GS, + HV_X64_REGISTER_SS, + HV_X64_REGISTER_TR, + HV_X64_REGISTER_LDTR, + HV_X64_REGISTER_GDTR, + HV_X64_REGISTER_IDTR, + HV_X64_REGISTER_CR0, + HV_X64_REGISTER_CR2, + HV_X64_REGISTER_CR3, + HV_X64_REGISTER_CR4, + HV_X64_REGISTER_CR8, + HV_X64_REGISTER_EFER, + HV_X64_REGISTER_APIC_BASE, +}; + int mshv_set_generic_regs(int cpu_fd, hv_register_assoc *assocs, size_t n_= regs) { struct mshv_vp_registers input =3D { @@ -174,6 +194,85 @@ int mshv_get_standard_regs(CPUState *cpu) return 0; } =20 +static inline void populate_segment_reg(const hv_x64_segment_register *hv_= seg, + SegmentCache *seg) +{ + memset(seg, 0, sizeof(SegmentCache)); + + seg->base =3D hv_seg->base; + seg->limit =3D hv_seg->limit; + seg->selector =3D hv_seg->selector; + + seg->flags =3D (hv_seg->segment_type << DESC_TYPE_SHIFT) + | (hv_seg->present * DESC_P_MASK) + | (hv_seg->descriptor_privilege_level << DESC_DPL_SHIFT) + | (hv_seg->_default << DESC_B_SHIFT) + | (hv_seg->non_system_segment * DESC_S_MASK) + | (hv_seg->_long << DESC_L_SHIFT) + | (hv_seg->granularity * DESC_G_MASK) + | (hv_seg->available * DESC_AVL_MASK); + +} + +static inline void populate_table_reg(const hv_x64_table_register *hv_seg, + SegmentCache *tbl) +{ + memset(tbl, 0, sizeof(SegmentCache)); + + tbl->base =3D hv_seg->base; + tbl->limit =3D hv_seg->limit; +} + +static void populate_special_regs(const hv_register_assoc *assocs, + X86CPU *x86cpu) +{ + CPUX86State *env =3D &x86cpu->env; + + populate_segment_reg(&assocs[0].value.segment, &env->segs[R_CS]); + populate_segment_reg(&assocs[1].value.segment, &env->segs[R_DS]); + populate_segment_reg(&assocs[2].value.segment, &env->segs[R_ES]); + populate_segment_reg(&assocs[3].value.segment, &env->segs[R_FS]); + populate_segment_reg(&assocs[4].value.segment, &env->segs[R_GS]); + populate_segment_reg(&assocs[5].value.segment, &env->segs[R_SS]); + + populate_segment_reg(&assocs[6].value.segment, &env->tr); + populate_segment_reg(&assocs[7].value.segment, &env->ldt); + + populate_table_reg(&assocs[8].value.table, &env->gdt); + populate_table_reg(&assocs[9].value.table, &env->idt); + + env->cr[0] =3D assocs[10].value.reg64; + env->cr[2] =3D assocs[11].value.reg64; + env->cr[3] =3D assocs[12].value.reg64; + env->cr[4] =3D assocs[13].value.reg64; + + cpu_set_apic_tpr(x86cpu->apic_state, assocs[14].value.reg64); + env->efer =3D assocs[15].value.reg64; + cpu_set_apic_base(x86cpu->apic_state, assocs[16].value.reg64); +} + + +int mshv_get_special_regs(CPUState *cpu) +{ + struct hv_register_assoc assocs[ARRAY_SIZE(SPECIAL_REGISTER_NAMES)]; + int ret; + X86CPU *x86cpu =3D X86_CPU(cpu); + int cpu_fd =3D mshv_vcpufd(cpu); + size_t n_regs =3D ARRAY_SIZE(SPECIAL_REGISTER_NAMES); + + for (size_t i =3D 0; i < n_regs; i++) { + assocs[i].name =3D SPECIAL_REGISTER_NAMES[i]; + } + ret =3D get_generic_regs(cpu_fd, assocs, n_regs); + if (ret < 0) { + error_report("failed to get special registers"); + return -errno; + } + + populate_special_regs(assocs, x86cpu); + return 0; +} + int mshv_load_regs(CPUState *cpu) { int ret; @@ -184,6 +283,12 @@ int mshv_load_regs(CPUState *cpu) return -1; } =20 + ret =3D mshv_get_special_regs(cpu); + if (ret < 0) { + error_report("Failed to load special registers"); + return -1; + } + return 0; } =20 --=20 2.34.1