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Tue, 01 Jul 2025 10:07:31 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/43] arm/cpu: Store aa64dfr0/1 into the idregs array Date: Tue, 1 Jul 2025 18:06:44 +0100 Message-ID: <20250701170720.4072660-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751389755343116600 Content-Type: text/plain; charset="utf-8" From: Eric Auger Reviewed-by: Richard Henderson Reviewed-by: Sebastian Ott Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck Message-id: 20250617153931.1330449-7-cohuck@redhat.com Signed-off-by: Peter Maydell --- target/arm/cpu-features.h | 16 ++++++++-------- target/arm/cpu.h | 2 -- target/arm/internals.h | 6 +++--- target/arm/cpu.c | 15 +++++---------- target/arm/cpu64.c | 4 ++-- target/arm/helper.c | 4 ++-- target/arm/hvf/hvf.c | 4 ++-- target/arm/kvm.c | 12 +++++------- target/arm/tcg/cpu64.c | 32 ++++++++++++++++---------------- 9 files changed, 43 insertions(+), 52 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 89c9278639b..9517e8a74c8 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -901,30 +901,30 @@ static inline bool isar_feature_aa64_nv2(const ARMISA= Registers *id) =20 static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >=3D 4 && - FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) !=3D 0xf; + return FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) >=3D 4 && + FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) !=3D 0xf; } =20 static inline bool isar_feature_aa64_pmuv3p4(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >=3D 5 && - FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) !=3D 0xf; + return FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) >=3D 5 && + FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) !=3D 0xf; } =20 static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >=3D 6 && - FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) !=3D 0xf; + return FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) >=3D 6 && + FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) !=3D 0xf; } =20 static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >=3D 8; + return FIELD_EX64_IDREG(id, ID_AA64DFR0, DEBUGVER) >=3D 8; } =20 static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id) { - return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >=3D 0; + return FIELD_SEX64_IDREG(id, ID_AA64DFR0, DOUBLELOCK) >=3D 0; } =20 static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index df9b7cc8c84..c7935377c6f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1074,8 +1074,6 @@ struct ArchCPU { uint32_t dbgdidr; uint32_t dbgdevid; uint32_t dbgdevid1; - uint64_t id_aa64dfr0; - uint64_t id_aa64dfr1; uint64_t id_aa64smfr0; uint64_t reset_pmcr_el0; uint64_t idregs[NUM_ID_IDX]; diff --git a/target/arm/internals.h b/target/arm/internals.h index 3360de9150f..6216f68c94f 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1175,7 +1175,7 @@ static inline bool regime_using_lpae_format(CPUARMSta= te *env, ARMMMUIdx mmu_idx) static inline int arm_num_brps(ARMCPU *cpu) { if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) + 1; + return FIELD_EX64_IDREG(&cpu->isar, ID_AA64DFR0, BRPS) + 1; } else { return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, BRPS) + 1; } @@ -1189,7 +1189,7 @@ static inline int arm_num_brps(ARMCPU *cpu) static inline int arm_num_wrps(ARMCPU *cpu) { if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) + 1; + return FIELD_EX64_IDREG(&cpu->isar, ID_AA64DFR0, WRPS) + 1; } else { return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, WRPS) + 1; } @@ -1203,7 +1203,7 @@ static inline int arm_num_wrps(ARMCPU *cpu) static inline int arm_num_ctx_cmps(ARMCPU *cpu) { if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) + = 1; + return FIELD_EX64_IDREG(&cpu->isar, ID_AA64DFR0, CTX_CMPS) + 1; } else { return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, CTX_CMPS) + 1; } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d39e8dc9560..400bee84943 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2347,8 +2347,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) cpu); #endif } else { - cpu->isar.id_aa64dfr0 =3D - FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); + FIELD_DP64_IDREG(isar, ID_AA64DFR0, PMUVER, 0); cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFM= ON, 0); cpu->pmceid0 =3D 0; cpu->pmceid1 =3D 0; @@ -2408,19 +2407,15 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) * try to access the non-existent system registers for them. */ /* FEAT_SPE (Statistical Profiling Extension) */ - cpu->isar.id_aa64dfr0 =3D - FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0); + FIELD_DP64_IDREG(isar, ID_AA64DFR0, PMSVER, 0); /* FEAT_TRBE (Trace Buffer Extension) */ - cpu->isar.id_aa64dfr0 =3D - FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0); + FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEBUFFER, 0); /* FEAT_TRF (Self-hosted Trace Extension) */ - cpu->isar.id_aa64dfr0 =3D - FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0); + FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEFILT, 0); cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, TRACEFILT, 0); /* Trace Macrocell system register access */ - cpu->isar.id_aa64dfr0 =3D - FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEVER, 0); + FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEVER, 0); cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPTRC, 0); /* Memory mapped trace */ diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 500f3646bfa..a215ba8b479 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -671,7 +671,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->isar.id_isar5 =3D 0x00011121; cpu->isar.id_isar6 =3D 0; SET_IDREG(isar, ID_AA64PFR0, 0x00002222); - cpu->isar.id_aa64dfr0 =3D 0x10305106; + SET_IDREG(isar, ID_AA64DFR0, 0x10305106); SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); SET_IDREG(isar, ID_AA64MMFR0, 0x00001124); cpu->isar.dbgdidr =3D 0x3516d000; @@ -733,7 +733,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->isar.id_isar5 =3D 0x00011121; cpu->isar.id_isar6 =3D 0; SET_IDREG(isar, ID_AA64PFR0, 0x00002222); - cpu->isar.id_aa64dfr0 =3D 0x10305106; + SET_IDREG(isar, ID_AA64DFR0, 0x10305106); SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); SET_IDREG(isar, ID_AA64MMFR0, 0x00001122); /* 40 bit physical addr */ cpu->isar.dbgdidr =3D 0x3516d000; diff --git a/target/arm/helper.c b/target/arm/helper.c index fe0bda749f4..2ac132c1db8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7963,12 +7963,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64dfr0 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64DFR0) }, { .name =3D "ID_AA64DFR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64dfr1 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64DFR1) }, { .name =3D "ID_AA64DFR2_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 37a6303ec2a..5c95ccc5b8d 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -868,8 +868,8 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) } regs[] =3D { { HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.idregs[ID_AA64PFR0_EL1_ID= X] }, { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.idregs[ID_AA64PFR1_EL1_ID= X] }, - { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.id_aa64dfr0 }, - { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 }, + { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.idregs[ID_AA64DFR0_EL1_ID= X] }, + { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.idregs[ID_AA64DFR1_EL1_ID= X] }, { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.idregs[ID_AA64ISAR0_EL1_= IDX] }, { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.idregs[ID_AA64ISAR1_EL1_= IDX] }, /* Add ID_AA64ISAR2_EL1 here when HVF supports it */ diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 1dde96fbbda..479e5860e02 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -316,10 +316,8 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFe= atures *ahcf) err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64PFR1_EL1_IDX); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0, ARM64_SYS_REG(3, 0, 0, 4, 5)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr0, - ARM64_SYS_REG(3, 0, 0, 5, 0)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1, - ARM64_SYS_REG(3, 0, 0, 5, 1)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64DFR0_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64DFR1_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64ISAR0_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64ISAR1_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64ISAR2_EL1_IDX); @@ -390,10 +388,10 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUF= eatures *ahcf) * We only do this if the CPU supports AArch32 at EL1. */ if (FIELD_EX32_IDREG(&ahcf->isar, ID_AA64PFR0, EL1) >=3D 2) { - int wrps =3D FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, W= RPS); - int brps =3D FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, B= RPS); + int wrps =3D FIELD_EX64_IDREG(&ahcf->isar, ID_AA64DFR0, WRPS); + int brps =3D FIELD_EX64_IDREG(&ahcf->isar, ID_AA64DFR0, BRPS); int ctx_cmps =3D - FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS); + FIELD_EX64_IDREG(&ahcf->isar, ID_AA64DFR0, CTX_CMPS); int version =3D 6; /* ARMv8 debug architecture */ bool has_el3 =3D !!FIELD_EX32_IDREG(&ahcf->isar, ID_AA64PFR0, EL3); diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 9efb7f0ce80..7e18d31a253 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -65,8 +65,8 @@ static void aarch64_a35_initfn(Object *obj) cpu->isar.id_isar5 =3D 0x00011121; SET_IDREG(isar, ID_AA64PFR0, 0x00002222); SET_IDREG(isar, ID_AA64PFR1, 0); - cpu->isar.id_aa64dfr0 =3D 0x10305106; - cpu->isar.id_aa64dfr1 =3D 0; + SET_IDREG(isar, ID_AA64DFR0, 0x10305106); + SET_IDREG(isar, ID_AA64DFR1, 0); SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); SET_IDREG(isar, ID_AA64ISAR1, 0); SET_IDREG(isar, ID_AA64MMFR0, 0x00101122); @@ -219,7 +219,7 @@ static void aarch64_a55_initfn(Object *obj) cpu->clidr =3D 0x82000023; cpu->ctr =3D 0x84448004; /* L1Ip =3D VIPT */ cpu->dcz_blocksize =3D 4; /* 64 bytes */ - cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; + SET_IDREG(isar, ID_AA64DFR0, 0x0000000010305408ull); SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull); SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101122ull); @@ -310,7 +310,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->isar.id_isar4 =3D 0x00011142; cpu->isar.id_isar5 =3D 0x00011121; SET_IDREG(isar, ID_AA64PFR0, 0x00002222); - cpu->isar.id_aa64dfr0 =3D 0x10305106; + SET_IDREG(isar, ID_AA64DFR0, 0x10305106); SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); SET_IDREG(isar, ID_AA64MMFR0, 0x00001124); cpu->isar.dbgdidr =3D 0x3516d000; @@ -352,7 +352,7 @@ static void aarch64_a76_initfn(Object *obj) cpu->clidr =3D 0x82000023; cpu->ctr =3D 0x8444C004; cpu->dcz_blocksize =3D 4; - cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; + SET_IDREG(isar, ID_AA64DFR0, 0x0000000010305408ull), SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull); SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101122ull); @@ -426,8 +426,8 @@ static void aarch64_a64fx_initfn(Object *obj) cpu->reset_sctlr =3D 0x30000180; SET_IDREG(isar, ID_AA64PFR0, 0x0000000101111111); /* No RAS Extensions= */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000000); - cpu->isar.id_aa64dfr0 =3D 0x0000000010305408; - cpu->isar.id_aa64dfr1 =3D 0x0000000000000000; + SET_IDREG(isar, ID_AA64DFR0, 0x0000000010305408), + SET_IDREG(isar, ID_AA64DFR1, 0x0000000000000000), cpu->id_aa64afr0 =3D 0x0000000000000000; cpu->id_aa64afr1 =3D 0x0000000000000000; SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000001122); @@ -600,7 +600,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj) cpu->clidr =3D 0x82000023; cpu->ctr =3D 0x8444c004; cpu->dcz_blocksize =3D 4; - cpu->isar.id_aa64dfr0 =3D 0x0000000110305408ull; + SET_IDREG(isar, ID_AA64DFR0, 0x0000000110305408ull); SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull); SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101125ull); @@ -678,8 +678,8 @@ static void aarch64_neoverse_v1_initfn(Object *obj) cpu->dcz_blocksize =3D 4; cpu->id_aa64afr0 =3D 0x00000000; cpu->id_aa64afr1 =3D 0x00000000; - cpu->isar.id_aa64dfr0 =3D 0x000001f210305519ull; - cpu->isar.id_aa64dfr1 =3D 0x00000000; + SET_IDREG(isar, ID_AA64DFR0, 0x000001f210305519ull), + SET_IDREG(isar, ID_AA64DFR1, 0x00000000), SET_IDREG(isar, ID_AA64ISAR0, 0x1011111110212120ull); /* with FEAT_RNG= */ SET_IDREG(isar, ID_AA64ISAR1, 0x0011000001211032ull); SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101125ull); @@ -925,8 +925,8 @@ static void aarch64_a710_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in = later */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000221ull); SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */ - cpu->isar.id_aa64dfr0 =3D 0x000011f010305619ull; - cpu->isar.id_aa64dfr1 =3D 0; + SET_IDREG(isar, ID_AA64DFR0, 0x000011f010305619ull); + SET_IDREG(isar, ID_AA64DFR1, 0); cpu->id_aa64afr0 =3D 0; cpu->id_aa64afr1 =3D 0; SET_IDREG(isar, ID_AA64ISAR0, 0x0221111110212120ull); /* with Crypto */ @@ -1027,8 +1027,8 @@ static void aarch64_neoverse_n2_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in = later */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000221ull); SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */ - cpu->isar.id_aa64dfr0 =3D 0x000011f210305619ull; - cpu->isar.id_aa64dfr1 =3D 0; + SET_IDREG(isar, ID_AA64DFR0, 0x000011f210305619ull); + SET_IDREG(isar, ID_AA64DFR1, 0); cpu->id_aa64afr0 =3D 0; cpu->id_aa64afr1 =3D 0; SET_IDREG(isar, ID_AA64ISAR0, 0x1221111110212120ull); /* with Crypto a= nd FEAT_RNG */ @@ -1261,11 +1261,11 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */ SET_IDREG(isar, ID_AA64ZFR0, t); =20 - t =3D cpu->isar.id_aa64dfr0; + t =3D GET_IDREG(isar, ID_AA64DFR0); t =3D FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 10); /* FEAT_Debugv8p8 */ t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */ t =3D FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* FEAT_HPMN0 */ - cpu->isar.id_aa64dfr0 =3D t; + SET_IDREG(isar, ID_AA64DFR0, t); =20 t =3D cpu->isar.id_aa64smfr0; t =3D FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */ --=20 2.43.0