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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a88c80bb28sm13475658f8f.43.2025.07.01.10.07.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 10:07:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751389647; x=1751994447; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=TZZRCIb9Wcs9eycneRt/wbJqeHZCRyd5Iwo548bi/gU=; b=ha9cinIqVMqItyESf/c+3UeeHHXKAsdKtlW5D5tKWLCCdijtcc3q0v2l9v5f6VbvkG tRMMYYwLKOedVOPRNTotHFT64RTSdC+WLXSIM+xaaXTWolgNfkAa/XzfULU9GBpi5BRV xJK4+ykwu8pxtOMPhwoAhJovOTxIU6Wb0dKaWXAKO9rkgnu3RwFflIJP69p0S3bMONMv Gc2SYYrdj9AtddQkH74ka2qKi3D1PU+QSizw9w4BBZvdAJABlbBRHSjT2bb27P+BSM5L kdPJQ7TTiCJIwWX2DtpZkin4qxJ6/V9G2EQwRQ2Ha0r1q2+V0NRJ3LOkMaP6DBk9SvGu Ui4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751389647; x=1751994447; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TZZRCIb9Wcs9eycneRt/wbJqeHZCRyd5Iwo548bi/gU=; b=fPyDuTy/NSyd1ZOQpe9paT5u5q2ggvBiF1mVjZrZ3YwiL/IwJx5je0UpEsIijOoZCz 9EY+gZpvUyk1BKEcFxnEv25pIhx40nT4DOnHFOeT1sEO1Bz8XCdDFk7ZUMSaCO3cLlIY Vdg/A1hLDziBal78D9P2rLhCJp5L6xS2auUagYKBn70ZlDSx3ZRnLmPIAS9Lpi4xCfSR 52+Ae1ndsh/aKRo0FTUQkExoTfX0mzslYQvxnwO7qV2Pu1N+Oeuxo91/9k1B30a2T1+4 VvulBVqBjPWM9diS6Tf0kQ5TQZFzT6euGD4GxM9hI6BbQuQ0v7MSJuzqVy/fyRDKLS6b BhOA== X-Gm-Message-State: AOJu0Yz07cVnPSGfC5CwpMPZXjL58bmw1qAXMmb+YC5DBT0SbnTC/m3c oQRoEHQy30ddakGo3LzI6dWLK7Ti0ypsPiY5mnfFg7krrWWPEqbwYYHGGpP8LKZ4lmize/IgRlb iemwS X-Gm-Gg: ASbGncvj+66Zp7oA2MQQrP+RXzcrBNAhNIh0cAV1vaObGeZVx8Lf8NlFE/uxXVFs3U5 5FRE/GITi5D/V8KaHDkdV+DuTEkbE50Wo5QHMnbYBrBhKkiItRrMJGaJZ++MYmC2k9lwodKiB91 UM6cWRh/MYlvrLIldByw3PGIrn65AT44/4N1y/ISsyFTQB6qftSbDEwYWuvakVr44aaEgW/jEW+ /wl11a1vjp2BqrmznDiEo5lS2m7p684oEEcD66ZEkw0WDPAvWmNe0R0dBWIt3LeLw1Q3IWwBHTn feILoSCuqAyREXMips1HHMnjkDpJh4gYE3aCjnZ8gjq43KjyzCPqa6q9ZOpobiSgY8cH8FeBsNj NHoA= X-Google-Smtp-Source: AGHT+IHph7LI9zvwUAIl7LyAQpWo1I8JYcNQVl7ixI8YW8l/u+aEGK4gizuiPolcnBp2FPAIHr+gdA== X-Received: by 2002:a05:600c:1547:b0:453:cd0:903c with SMTP id 5b1f17b1804b1-453a8fc441emr37413045e9.2.1751389646629; Tue, 01 Jul 2025 10:07:26 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/43] arm/cpu: Store aa64isar0/aa64zfr0 into the idregs arrays Date: Tue, 1 Jul 2025 18:06:40 +0100 Message-ID: <20250701170720.4072660-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751390059396116600 Content-Type: text/plain; charset="utf-8" From: Eric Auger Also add kvm accessors for storing host features into idregs. Reviewed-by: Richard Henderson Reviewed-by: Sebastian Ott Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck Message-id: 20250617153931.1330449-3-cohuck@redhat.com Signed-off-by: Peter Maydell --- target/arm/cpu-features.h | 57 ++++++++++++++++++++------------------- target/arm/cpu.h | 2 -- target/arm/cpu.c | 9 +++---- target/arm/cpu64.c | 8 +++--- target/arm/helper.c | 6 +++-- target/arm/hvf/hvf.c | 3 ++- target/arm/kvm.c | 30 ++++++++++++++++++--- target/arm/tcg/cpu64.c | 44 ++++++++++++++++++------------ 8 files changed, 97 insertions(+), 62 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 4452e7c21e3..6a47f1a6d22 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -23,6 +23,7 @@ #include "hw/registerfields.h" #include "qemu/host-utils.h" #include "cpu.h" +#include "cpu-sysregs.h" =20 /* * Naming convention for isar_feature functions: @@ -377,92 +378,92 @@ static inline bool isar_feature_aa32_doublelock(const= ARMISARegisters *id) */ static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, AES) !=3D 0; } =20 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, AES) > 1; } =20 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SHA1) !=3D 0; } =20 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SHA2) !=3D 0; } =20 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SHA2) > 1; } =20 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, CRC32) !=3D 0; } =20 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, ATOMIC) !=3D 0; } =20 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, RDM) !=3D 0; } =20 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SHA3) !=3D 0; } =20 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SM3) !=3D 0; } =20 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SM4) !=3D 0; } =20 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, DP) !=3D 0; } =20 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, FHM) !=3D 0; } =20 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, TS) !=3D 0; } =20 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, TS) >=3D 2; } =20 static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, RNDR) !=3D 0; } =20 static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) =3D=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, TLB) =3D=3D 2; } =20 static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, TLB) !=3D 0; } =20 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) @@ -928,52 +929,52 @@ static inline bool isar_feature_aa64_doublelock(const= ARMISARegisters *id) =20 static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SVEVER) !=3D 0; } =20 static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, AES) !=3D 0; } =20 static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *= id) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) >=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, AES) >=3D 2; } =20 static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *i= d) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, BITPERM) !=3D 0; } =20 static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BFLOAT16) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, BFLOAT16) !=3D 0; } =20 static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SHA3) !=3D 0; } =20 static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SM4) !=3D 0; } =20 static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, I8MM) !=3D 0; } =20 static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, F32MM) !=3D 0; } =20 static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, F64MM) !=3D 0; } =20 static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 45409f84ef0..7b5c7a4abc7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1074,7 +1074,6 @@ struct ArchCPU { uint32_t dbgdidr; uint32_t dbgdevid; uint32_t dbgdevid1; - uint64_t id_aa64isar0; uint64_t id_aa64isar1; uint64_t id_aa64isar2; uint64_t id_aa64pfr0; @@ -1085,7 +1084,6 @@ struct ArchCPU { uint64_t id_aa64mmfr3; uint64_t id_aa64dfr0; uint64_t id_aa64dfr1; - uint64_t id_aa64zfr0; uint64_t id_aa64smfr0; uint64_t reset_pmcr_el0; uint64_t idregs[NUM_ID_IDX]; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index e025e241eda..f033411b5da 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1962,6 +1962,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) { CPUState *cs =3D CPU(dev); ARMCPU *cpu =3D ARM_CPU(dev); + ARMISARegisters *isar =3D &cpu->isar; ARMCPUClass *acc =3D ARM_CPU_GET_CLASS(dev); CPUARMState *env =3D &cpu->env; Error *local_err =3D NULL; @@ -2167,7 +2168,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) =20 unset_feature(env, ARM_FEATURE_NEON); =20 - t =3D cpu->isar.id_aa64isar0; + t =3D GET_IDREG(isar, ID_AA64ISAR0); t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 0); t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0); t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0); @@ -2175,7 +2176,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) t =3D FIELD_DP64(t, ID_AA64ISAR0, SM3, 0); t =3D FIELD_DP64(t, ID_AA64ISAR0, SM4, 0); t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 0); - cpu->isar.id_aa64isar0 =3D t; + SET_IDREG(isar, ID_AA64ISAR0, t); =20 t =3D cpu->isar.id_aa64isar1; t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); @@ -2220,9 +2221,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) uint64_t t; uint32_t u; =20 - t =3D cpu->isar.id_aa64isar0; - t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); - cpu->isar.id_aa64isar0 =3D t; + FIELD_DP64_IDREG(isar, ID_AA64ISAR0, FHM, 0); =20 t =3D cpu->isar.id_aa64isar1; t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 77054e0ec38..c105fcc4ea5 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -136,7 +136,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) * SVE is disabled and so are all vector lengths. Good. * Disable all SVE extensions as well. */ - cpu->isar.id_aa64zfr0 =3D 0; + SET_IDREG(&cpu->isar, ID_AA64ZFR0, 0); return; } =20 @@ -639,6 +639,7 @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) static void aarch64_a57_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,cortex-a57"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -676,7 +677,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->isar.id_isar6 =3D 0; cpu->isar.id_aa64pfr0 =3D 0x00002222; cpu->isar.id_aa64dfr0 =3D 0x10305106; - cpu->isar.id_aa64isar0 =3D 0x00011120; + SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); cpu->isar.id_aa64mmfr0 =3D 0x00001124; cpu->isar.dbgdidr =3D 0x3516d000; cpu->isar.dbgdevid =3D 0x01110f13; @@ -700,6 +701,7 @@ static void aarch64_a57_initfn(Object *obj) static void aarch64_a53_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,cortex-a53"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -737,7 +739,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->isar.id_isar6 =3D 0; cpu->isar.id_aa64pfr0 =3D 0x00002222; cpu->isar.id_aa64dfr0 =3D 0x10305106; - cpu->isar.id_aa64isar0 =3D 0x00011120; + SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); cpu->isar.id_aa64mmfr0 =3D 0x00001122; /* 40 bit physical addr */ cpu->isar.dbgdidr =3D 0x3516d000; cpu->isar.dbgdevid =3D 0x00110f13; diff --git a/target/arm/helper.c b/target/arm/helper.c index 889d3088079..638550e45ac 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7750,6 +7750,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ CPUARMState *env =3D &cpu->env; + ARMISARegisters *isar =3D &cpu->isar; + if (arm_feature(env, ARM_FEATURE_M)) { /* M profile has no coprocessor registers */ return; @@ -7941,7 +7943,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64zfr0 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64ZFR0)}, { .name =3D "ID_AA64SMFR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, @@ -8001,7 +8003,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64isar0 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64ISAR0)}, { .name =3D "ID_AA64ISAR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 42258cc2d88..5d25260c5c3 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -19,6 +19,7 @@ #include "system/hw_accel.h" #include "hvf_arm.h" #include "cpregs.h" +#include "cpu-sysregs.h" =20 #include =20 @@ -866,7 +867,7 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.id_aa64pfr1 }, { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.id_aa64dfr0 }, { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 }, - { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.id_aa64isar0 }, + { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.idregs[ID_AA64ISAR0_EL1_= IDX] }, { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.id_aa64isar1 }, /* Add ID_AA64ISAR2_EL1 here when HVF supports it */ { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 }, diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 74fda8b8090..bd33b0f656e 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -26,6 +26,7 @@ #include "system/kvm_int.h" #include "kvm_arm.h" #include "cpu.h" +#include "cpu-sysregs.h" #include "trace.h" #include "internals.h" #include "hw/pci/pci.h" @@ -218,6 +219,28 @@ static bool kvm_arm_pauth_supported(void) kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_GENERIC)); } =20 + +static uint64_t idregs_sysreg_to_kvm_reg(ARMSysRegs sysreg) +{ + return ARM64_SYS_REG((sysreg & CP_REG_ARM64_SYSREG_OP0_MASK) >> CP_REG= _ARM64_SYSREG_OP0_SHIFT, + (sysreg & CP_REG_ARM64_SYSREG_OP1_MASK) >> CP_REG= _ARM64_SYSREG_OP1_SHIFT, + (sysreg & CP_REG_ARM64_SYSREG_CRN_MASK) >> CP_REG= _ARM64_SYSREG_CRN_SHIFT, + (sysreg & CP_REG_ARM64_SYSREG_CRM_MASK) >> CP_REG= _ARM64_SYSREG_CRM_SHIFT, + (sysreg & CP_REG_ARM64_SYSREG_OP2_MASK) >> CP_REG= _ARM64_SYSREG_OP2_SHIFT); +} + +/* read a sysreg value and store it in the idregs */ +static int get_host_cpu_reg(int fd, ARMHostCPUFeatures *ahcf, ARMIDRegiste= rIdx index) +{ + uint64_t *reg; + int ret; + + reg =3D &ahcf->isar.idregs[index]; + ret =3D read_sys_reg64(fd, reg, + idregs_sysreg_to_kvm_reg(id_register_sysreg[index= ])); + return ret; +} + static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) { /* Identify the feature bits corresponding to the host CPU, and @@ -267,6 +290,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) =20 ahcf->target =3D init.target; ahcf->dtb_compatible =3D "arm,arm-v8"; + int fd =3D fdarray[2]; =20 err =3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0, ARM64_SYS_REG(3, 0, 0, 4, 0)); @@ -298,8 +322,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) ARM64_SYS_REG(3, 0, 0, 5, 0)); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1, ARM64_SYS_REG(3, 0, 0, 5, 1)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0, - ARM64_SYS_REG(3, 0, 0, 6, 0)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64ISAR0_EL1_IDX); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1, ARM64_SYS_REG(3, 0, 0, 6, 1)); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar2, @@ -408,8 +431,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) * enabled SVE support, which resulted in an error rather than= RAZ. * So only read the register if we set KVM_ARM_VCPU_SVE above. */ - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, - ARM64_SYS_REG(3, 0, 0, 4, 4)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64ZFR0_EL1_IDX); } } =20 diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 5d8ed2794d3..ed681ee08b0 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -32,6 +32,7 @@ static void aarch64_a35_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,cortex-a35"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -66,7 +67,7 @@ static void aarch64_a35_initfn(Object *obj) cpu->isar.id_aa64pfr1 =3D 0; cpu->isar.id_aa64dfr0 =3D 0x10305106; cpu->isar.id_aa64dfr1 =3D 0; - cpu->isar.id_aa64isar0 =3D 0x00011120; + SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); cpu->isar.id_aa64isar1 =3D 0; cpu->isar.id_aa64mmfr0 =3D 0x00101122; cpu->isar.id_aa64mmfr1 =3D 0; @@ -204,6 +205,7 @@ static const Property arm_cpu_lpa2_property =3D static void aarch64_a55_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,cortex-a55"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -221,7 +223,7 @@ static void aarch64_a55_initfn(Object *obj) cpu->ctr =3D 0x84448004; /* L1Ip =3D VIPT */ cpu->dcz_blocksize =3D 4; /* 64 bytes */ cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; - cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; + SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; @@ -276,6 +278,7 @@ static void aarch64_a55_initfn(Object *obj) static void aarch64_a72_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,cortex-a72"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -311,7 +314,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->isar.id_isar5 =3D 0x00011121; cpu->isar.id_aa64pfr0 =3D 0x00002222; cpu->isar.id_aa64dfr0 =3D 0x10305106; - cpu->isar.id_aa64isar0 =3D 0x00011120; + SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); cpu->isar.id_aa64mmfr0 =3D 0x00001124; cpu->isar.dbgdidr =3D 0x3516d000; cpu->isar.dbgdevid =3D 0x01110f13; @@ -335,6 +338,7 @@ static void aarch64_a72_initfn(Object *obj) static void aarch64_a76_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,cortex-a76"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -352,7 +356,7 @@ static void aarch64_a76_initfn(Object *obj) cpu->ctr =3D 0x8444C004; cpu->dcz_blocksize =3D 4; cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; - cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; + SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; @@ -408,6 +412,7 @@ static void aarch64_a76_initfn(Object *obj) static void aarch64_a64fx_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,a64fx"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -431,9 +436,9 @@ static void aarch64_a64fx_initfn(Object *obj) cpu->isar.id_aa64mmfr0 =3D 0x0000000000001122; cpu->isar.id_aa64mmfr1 =3D 0x0000000011212100; cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011; - cpu->isar.id_aa64isar0 =3D 0x0000000010211120; + SET_IDREG(isar, ID_AA64ISAR0, 0x0000000010211120); cpu->isar.id_aa64isar1 =3D 0x0000000000010001; - cpu->isar.id_aa64zfr0 =3D 0x0000000000000000; + SET_IDREG(isar, ID_AA64ZFR0, 0x0000000000000000); cpu->clidr =3D 0x0000000080000023; /* 64KB L1 dcache */ cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 256, 64 * KiB,= 7); @@ -581,6 +586,7 @@ static void define_neoverse_v1_cp_reginfo(ARMCPU *cpu) static void aarch64_neoverse_n1_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,neoverse-n1"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -598,7 +604,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj) cpu->ctr =3D 0x8444c004; cpu->dcz_blocksize =3D 4; cpu->isar.id_aa64dfr0 =3D 0x0000000110305408ull; - cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; + SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; @@ -656,6 +662,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj) static void aarch64_neoverse_v1_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,neoverse-v1"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -676,7 +683,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj) cpu->id_aa64afr1 =3D 0x00000000; cpu->isar.id_aa64dfr0 =3D 0x000001f210305519ull; cpu->isar.id_aa64dfr1 =3D 0x00000000; - cpu->isar.id_aa64isar0 =3D 0x1011111110212120ull; /* with FEAT_RNG */ + SET_IDREG(isar, ID_AA64ISAR0, 0x1011111110212120ull); /* with FEAT_RNG= */ cpu->isar.id_aa64isar1 =3D 0x0011100001211032ull; cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; @@ -735,7 +742,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000043; =20 /* From 3.7.5 ID_AA64ZFR0_EL1 */ - cpu->isar.id_aa64zfr0 =3D 0x0000100000100000; + SET_IDREG(isar, ID_AA64ZFR0, 0x0000100000100000); cpu->sve_vq.supported =3D (1 << 0) /* 128bit */ | (1 << 1); /* 256bit */ =20 @@ -882,6 +889,7 @@ static const ARMCPRegInfo cortex_a710_cp_reginfo[] =3D { static void aarch64_a710_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,cortex-a710"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -919,12 +927,12 @@ static void aarch64_a710_initfn(Object *obj) cpu->isar.id_pfr2 =3D 0x00000011; cpu->isar.id_aa64pfr0 =3D 0x1201111120111112ull; /* GIC filled in lat= er */ cpu->isar.id_aa64pfr1 =3D 0x0000000000000221ull; - cpu->isar.id_aa64zfr0 =3D 0x0000110100110021ull; /* with Crypto */ + SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */ cpu->isar.id_aa64dfr0 =3D 0x000011f010305619ull; cpu->isar.id_aa64dfr1 =3D 0; cpu->id_aa64afr0 =3D 0; cpu->id_aa64afr1 =3D 0; - cpu->isar.id_aa64isar0 =3D 0x0221111110212120ull; /* with Crypto */ + SET_IDREG(isar, ID_AA64ISAR0, 0x0221111110212120ull); /* with Crypto */ cpu->isar.id_aa64isar1 =3D 0x0010111101211052ull; cpu->isar.id_aa64mmfr0 =3D 0x0000022200101122ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; @@ -983,6 +991,7 @@ static const ARMCPRegInfo neoverse_n2_cp_reginfo[] =3D { static void aarch64_neoverse_n2_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,neoverse-n2"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -1020,12 +1029,12 @@ static void aarch64_neoverse_n2_initfn(Object *obj) cpu->isar.id_pfr2 =3D 0x00000011; cpu->isar.id_aa64pfr0 =3D 0x1201111120111112ull; /* GIC filled in lat= er */ cpu->isar.id_aa64pfr1 =3D 0x0000000000000221ull; - cpu->isar.id_aa64zfr0 =3D 0x0000110100110021ull; /* with Crypto */ + SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */ cpu->isar.id_aa64dfr0 =3D 0x000011f210305619ull; cpu->isar.id_aa64dfr1 =3D 0; cpu->id_aa64afr0 =3D 0; cpu->id_aa64afr1 =3D 0; - cpu->isar.id_aa64isar0 =3D 0x1221111110212120ull; /* with Crypto and F= EAT_RNG */ + SET_IDREG(isar, ID_AA64ISAR0, 0x1221111110212120ull); /* with Crypto a= nd FEAT_RNG */ cpu->isar.id_aa64isar1 =3D 0x0011111101211052ull; cpu->isar.id_aa64mmfr0 =3D 0x0000022200101125ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; @@ -1083,6 +1092,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj) void aarch64_max_tcg_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; uint64_t t; uint32_t u; =20 @@ -1133,7 +1143,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, CTR_EL0, DIC, 1); cpu->ctr =3D t; =20 - t =3D cpu->isar.id_aa64isar0; + t =3D GET_IDREG(isar, ID_AA64ISAR0); t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */ @@ -1148,7 +1158,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */ t =3D FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ t =3D FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */ - cpu->isar.id_aa64isar0 =3D t; + SET_IDREG(isar, ID_AA64ISAR0, t); =20 t =3D cpu->isar.id_aa64isar1; t =3D FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */ @@ -1244,7 +1254,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */ cpu->isar.id_aa64mmfr3 =3D t; =20 - t =3D cpu->isar.id_aa64zfr0; + t =3D GET_IDREG(isar, ID_AA64ZFR0); t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */ t =3D FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */ @@ -1254,7 +1264,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */ t =3D FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */ t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */ - cpu->isar.id_aa64zfr0 =3D t; + SET_IDREG(isar, ID_AA64ZFR0, t); =20 t =3D cpu->isar.id_aa64dfr0; t =3D FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 10); /* FEAT_Debugv8p8 */ --=20 2.43.0