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Tue, 01 Jul 2025 10:07:33 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/43] arm/cpu: Store id_isar0-7 into the idregs array Date: Tue, 1 Jul 2025 18:06:46 +0100 Message-ID: <20250701170720.4072660-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751390087444116600 Content-Type: text/plain; charset="utf-8" From: Eric Auger Reviewed-by: Richard Henderson Reviewed-by: Sebastian Ott Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck Message-id: 20250617153931.1330449-9-cohuck@redhat.com Signed-off-by: Peter Maydell --- target/arm/cpu-features.h | 36 +++++----- target/arm/cpu.h | 7 -- hw/intc/armv7m_nvic.c | 12 ++-- target/arm/cpu.c | 24 +++---- target/arm/cpu64.c | 28 ++++---- target/arm/helper.c | 14 ++-- target/arm/kvm.c | 21 ++---- target/arm/tcg/cpu-v7m.c | 90 +++++++++++++----------- target/arm/tcg/cpu32.c | 144 +++++++++++++++++++++----------------- target/arm/tcg/cpu64.c | 108 ++++++++++++++-------------- 10 files changed, 243 insertions(+), 241 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 051ed7b8847..75a2cc40779 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -46,93 +46,93 @@ */ static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR0, DIVIDE) !=3D 0; } =20 static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; + return FIELD_EX32_IDREG(id, ID_ISAR0, DIVIDE) > 1; } =20 static inline bool isar_feature_aa32_lob(const ARMISARegisters *id) { /* (M-profile) low-overhead loops and branch future */ - return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >=3D 3; + return FIELD_EX32_IDREG(id, ID_ISAR0, CMPBRANCH) >=3D 3; } =20 static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR1, JAZELLE) !=3D 0; } =20 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR5, AES) !=3D 0; } =20 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; + return FIELD_EX32_IDREG(id, ID_ISAR5, AES) > 1; } =20 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR5, SHA1) !=3D 0; } =20 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR5, SHA2) !=3D 0; } =20 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR5, CRC32) !=3D 0; } =20 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR5, RDM) !=3D 0; } =20 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR5, VCMA) !=3D 0; } =20 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR6, JSCVT) !=3D 0; } =20 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR6, DP) !=3D 0; } =20 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR6, FHM) !=3D 0; } =20 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR6, SB) !=3D 0; } =20 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR6, SPECRES) !=3D 0; } =20 static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar6, ID_ISAR6, BF16) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR6, BF16) !=3D 0; } =20 static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR6, I8MM) !=3D 0; } =20 static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1083ae7623b..353c18e6799 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1050,13 +1050,6 @@ struct ArchCPU { * field by reading the value from the KVM vCPU. */ struct ARMISARegisters { - uint32_t id_isar0; - uint32_t id_isar1; - uint32_t id_isar2; - uint32_t id_isar3; - uint32_t id_isar4; - uint32_t id_isar5; - uint32_t id_isar6; uint32_t id_mmfr0; uint32_t id_mmfr1; uint32_t id_mmfr2; diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 83ff74f899f..fdb7f58e367 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1303,32 +1303,32 @@ static uint32_t nvic_readl(NVICState *s, uint32_t o= ffset, MemTxAttrs attrs) if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_isar0; + return GET_IDREG(&cpu->isar, ID_ISAR0); case 0xd64: /* ISAR1. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_isar1; + return GET_IDREG(&cpu->isar, ID_ISAR1); case 0xd68: /* ISAR2. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_isar2; + return GET_IDREG(&cpu->isar, ID_ISAR2); case 0xd6c: /* ISAR3. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_isar3; + return GET_IDREG(&cpu->isar, ID_ISAR3); case 0xd70: /* ISAR4. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_isar4; + return GET_IDREG(&cpu->isar, ID_ISAR4); case 0xd74: /* ISAR5. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_isar5; + return GET_IDREG(&cpu->isar, ID_ISAR5); case 0xd78: /* CLIDR */ return cpu->clidr; case 0xd7c: /* CTR */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 400bee84943..cf811e47d99 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2126,10 +2126,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) =20 FIELD_DP64_IDREG(isar, ID_AA64PFR0, FP, 0xf); =20 - u =3D cpu->isar.id_isar6; + u =3D GET_IDREG(isar, ID_ISAR6); u =3D FIELD_DP32(u, ID_ISAR6, JSCVT, 0); u =3D FIELD_DP32(u, ID_ISAR6, BF16, 0); - cpu->isar.id_isar6 =3D u; + SET_IDREG(isar, ID_ISAR6, u); =20 u =3D cpu->isar.mvfr0; u =3D FIELD_DP32(u, MVFR0, FPSP, 0); @@ -2181,20 +2181,20 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) =20 FIELD_DP64_IDREG(isar, ID_AA64PFR0, ADVSIMD, 0xf); =20 - u =3D cpu->isar.id_isar5; + u =3D GET_IDREG(isar, ID_ISAR5); u =3D FIELD_DP32(u, ID_ISAR5, AES, 0); u =3D FIELD_DP32(u, ID_ISAR5, SHA1, 0); u =3D FIELD_DP32(u, ID_ISAR5, SHA2, 0); u =3D FIELD_DP32(u, ID_ISAR5, RDM, 0); u =3D FIELD_DP32(u, ID_ISAR5, VCMA, 0); - cpu->isar.id_isar5 =3D u; + SET_IDREG(isar, ID_ISAR5, u); =20 - u =3D cpu->isar.id_isar6; + u =3D GET_IDREG(isar, ID_ISAR6); u =3D FIELD_DP32(u, ID_ISAR6, DP, 0); u =3D FIELD_DP32(u, ID_ISAR6, FHM, 0); u =3D FIELD_DP32(u, ID_ISAR6, BF16, 0); u =3D FIELD_DP32(u, ID_ISAR6, I8MM, 0); - cpu->isar.id_isar6 =3D u; + SET_IDREG(isar, ID_ISAR6, u); =20 if (!arm_feature(env, ARM_FEATURE_M)) { u =3D cpu->isar.mvfr1; @@ -2232,19 +2232,17 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) =20 unset_feature(env, ARM_FEATURE_THUMB_DSP); =20 - u =3D cpu->isar.id_isar1; - u =3D FIELD_DP32(u, ID_ISAR1, EXTEND, 1); - cpu->isar.id_isar1 =3D u; + FIELD_DP32_IDREG(isar, ID_ISAR1, EXTEND, 1); =20 - u =3D cpu->isar.id_isar2; + u =3D GET_IDREG(isar, ID_ISAR2); u =3D FIELD_DP32(u, ID_ISAR2, MULTU, 1); u =3D FIELD_DP32(u, ID_ISAR2, MULTS, 1); - cpu->isar.id_isar2 =3D u; + SET_IDREG(isar, ID_ISAR2, u); =20 - u =3D cpu->isar.id_isar3; + u =3D GET_IDREG(isar, ID_ISAR3); u =3D FIELD_DP32(u, ID_ISAR3, SIMD, 1); u =3D FIELD_DP32(u, ID_ISAR3, SATURATE, 0); - cpu->isar.id_isar3 =3D u; + SET_IDREG(isar, ID_ISAR3, u); } =20 =20 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 0f938155d28..6be62c0711b 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -660,13 +660,13 @@ static void aarch64_a57_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02102211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00011142; - cpu->isar.id_isar5 =3D 0x00011121; - cpu->isar.id_isar6 =3D 0; + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232042); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00011142); + SET_IDREG(isar, ID_ISAR5, 0x00011121); + SET_IDREG(isar, ID_ISAR6, 0); SET_IDREG(isar, ID_AA64PFR0, 0x00002222); SET_IDREG(isar, ID_AA64DFR0, 0x10305106); SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); @@ -722,13 +722,13 @@ static void aarch64_a53_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02102211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00011142; - cpu->isar.id_isar5 =3D 0x00011121; - cpu->isar.id_isar6 =3D 0; + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232042); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00011142); + SET_IDREG(isar, ID_ISAR5, 0x00011121); + SET_IDREG(isar, ID_ISAR6, 0); SET_IDREG(isar, ID_AA64PFR0, 0x00002222); SET_IDREG(isar, ID_AA64DFR0, 0x10305106); SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); diff --git a/target/arm/helper.c b/target/arm/helper.c index 39729d3a8d0..7e0b3f164e1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7830,32 +7830,32 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_isar0 }, + .resetvalue =3D GET_IDREG(isar, ID_ISAR0)}, { .name =3D "ID_ISAR1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_isar1 }, + .resetvalue =3D GET_IDREG(isar, ID_ISAR1)}, { .name =3D "ID_ISAR2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_isar2 }, + .resetvalue =3D GET_IDREG(isar, ID_ISAR2)}, { .name =3D "ID_ISAR3", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 3, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_isar3 }, + .resetvalue =3D GET_IDREG(isar, ID_ISAR3) }, { .name =3D "ID_ISAR4", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_isar4 }, + .resetvalue =3D GET_IDREG(isar, ID_ISAR4) }, { .name =3D "ID_ISAR5", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_isar5 }, + .resetvalue =3D GET_IDREG(isar, ID_ISAR5) }, { .name =3D "ID_MMFR4", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, @@ -7865,7 +7865,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_isar6 }, + .resetvalue =3D GET_IDREG(isar, ID_ISAR6) }, }; define_arm_cp_regs(cpu, v6_idregs); define_arm_cp_regs(cpu, v6_cp_reginfo); diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 87368558614..eef9481737b 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -346,22 +346,15 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUF= eatures *ahcf) ARM64_SYS_REG(3, 0, 0, 1, 6)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3, ARM64_SYS_REG(3, 0, 0, 1, 7)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, - ARM64_SYS_REG(3, 0, 0, 2, 0)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, - ARM64_SYS_REG(3, 0, 0, 2, 1)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2, - ARM64_SYS_REG(3, 0, 0, 2, 2)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3, - ARM64_SYS_REG(3, 0, 0, 2, 3)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4, - ARM64_SYS_REG(3, 0, 0, 2, 4)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5, - ARM64_SYS_REG(3, 0, 0, 2, 5)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_ISAR0_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_ISAR1_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_ISAR2_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_ISAR3_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_ISAR4_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_ISAR5_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_ISAR6_EL1_IDX); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4, ARM64_SYS_REG(3, 0, 0, 2, 6)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6, - ARM64_SYS_REG(3, 0, 0, 2, 7)); =20 err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, ARM64_SYS_REG(3, 0, 0, 3, 0)); diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 8e1a083b911..198c9f3e98c 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -45,6 +45,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int = interrupt_request) static void cortex_m0_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; set_feature(&cpu->env, ARM_FEATURE_V6); set_feature(&cpu->env, ARM_FEATURE_M); =20 @@ -66,18 +67,19 @@ static void cortex_m0_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x00000000; cpu->isar.id_mmfr2 =3D 0x00000000; cpu->isar.id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01141110; - cpu->isar.id_isar1 =3D 0x02111000; - cpu->isar.id_isar2 =3D 0x21112231; - cpu->isar.id_isar3 =3D 0x01111110; - cpu->isar.id_isar4 =3D 0x01310102; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; + SET_IDREG(isar, ID_ISAR0, 0x01141110); + SET_IDREG(isar, ID_ISAR1, 0x02111000); + SET_IDREG(isar, ID_ISAR2, 0x21112231); + SET_IDREG(isar, ID_ISAR3, 0x01111110); + SET_IDREG(isar, ID_ISAR4, 0x01310102); + SET_IDREG(isar, ID_ISAR5, 0x00000000); + SET_IDREG(isar, ID_ISAR6, 0x00000000); } =20 static void cortex_m3_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; set_feature(&cpu->env, ARM_FEATURE_V7); set_feature(&cpu->env, ARM_FEATURE_M); set_feature(&cpu->env, ARM_FEATURE_M_MAIN); @@ -91,18 +93,19 @@ static void cortex_m3_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x00000000; cpu->isar.id_mmfr2 =3D 0x00000000; cpu->isar.id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01141110; - cpu->isar.id_isar1 =3D 0x02111000; - cpu->isar.id_isar2 =3D 0x21112231; - cpu->isar.id_isar3 =3D 0x01111110; - cpu->isar.id_isar4 =3D 0x01310102; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; + SET_IDREG(isar, ID_ISAR0, 0x01141110); + SET_IDREG(isar, ID_ISAR1, 0x02111000); + SET_IDREG(isar, ID_ISAR2, 0x21112231); + SET_IDREG(isar, ID_ISAR3, 0x01111110); + SET_IDREG(isar, ID_ISAR4, 0x01310102); + SET_IDREG(isar, ID_ISAR5, 0x00000000); + SET_IDREG(isar, ID_ISAR6, 0x00000000); } =20 static void cortex_m4_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 set_feature(&cpu->env, ARM_FEATURE_V7); set_feature(&cpu->env, ARM_FEATURE_M); @@ -121,18 +124,19 @@ static void cortex_m4_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x00000000; cpu->isar.id_mmfr2 =3D 0x00000000; cpu->isar.id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01141110; - cpu->isar.id_isar1 =3D 0x02111000; - cpu->isar.id_isar2 =3D 0x21112231; - cpu->isar.id_isar3 =3D 0x01111110; - cpu->isar.id_isar4 =3D 0x01310102; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; + SET_IDREG(isar, ID_ISAR0, 0x01141110); + SET_IDREG(isar, ID_ISAR1, 0x02111000); + SET_IDREG(isar, ID_ISAR2, 0x21112231); + SET_IDREG(isar, ID_ISAR3, 0x01111110); + SET_IDREG(isar, ID_ISAR4, 0x01310102); + SET_IDREG(isar, ID_ISAR5, 0x00000000); + SET_IDREG(isar, ID_ISAR6, 0x00000000); } =20 static void cortex_m7_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 set_feature(&cpu->env, ARM_FEATURE_V7); set_feature(&cpu->env, ARM_FEATURE_M); @@ -151,18 +155,19 @@ static void cortex_m7_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x00000000; cpu->isar.id_mmfr2 =3D 0x01000000; cpu->isar.id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01101110; - cpu->isar.id_isar1 =3D 0x02112000; - cpu->isar.id_isar2 =3D 0x20232231; - cpu->isar.id_isar3 =3D 0x01111131; - cpu->isar.id_isar4 =3D 0x01310132; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; + SET_IDREG(isar, ID_ISAR0, 0x01101110); + SET_IDREG(isar, ID_ISAR1, 0x02112000); + SET_IDREG(isar, ID_ISAR2, 0x20232231); + SET_IDREG(isar, ID_ISAR3, 0x01111131); + SET_IDREG(isar, ID_ISAR4, 0x01310132); + SET_IDREG(isar, ID_ISAR5, 0x00000000); + SET_IDREG(isar, ID_ISAR6, 0x00000000); } =20 static void cortex_m33_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_M); @@ -183,13 +188,13 @@ static void cortex_m33_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x00000000; cpu->isar.id_mmfr2 =3D 0x01000000; cpu->isar.id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01101110; - cpu->isar.id_isar1 =3D 0x02212000; - cpu->isar.id_isar2 =3D 0x20232232; - cpu->isar.id_isar3 =3D 0x01111131; - cpu->isar.id_isar4 =3D 0x01310132; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; + SET_IDREG(isar, ID_ISAR0, 0x01101110); + SET_IDREG(isar, ID_ISAR1, 0x02212000); + SET_IDREG(isar, ID_ISAR2, 0x20232232); + SET_IDREG(isar, ID_ISAR3, 0x01111131); + SET_IDREG(isar, ID_ISAR4, 0x01310132); + SET_IDREG(isar, ID_ISAR5, 0x00000000); + SET_IDREG(isar, ID_ISAR6, 0x00000000); cpu->clidr =3D 0x00000000; cpu->ctr =3D 0x8000c000; } @@ -197,6 +202,7 @@ static void cortex_m33_initfn(Object *obj) static void cortex_m55_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_V8_1M); @@ -220,13 +226,13 @@ static void cortex_m55_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x00000000; cpu->isar.id_mmfr2 =3D 0x01000000; cpu->isar.id_mmfr3 =3D 0x00000011; - cpu->isar.id_isar0 =3D 0x01103110; - cpu->isar.id_isar1 =3D 0x02212000; - cpu->isar.id_isar2 =3D 0x20232232; - cpu->isar.id_isar3 =3D 0x01111131; - cpu->isar.id_isar4 =3D 0x01310132; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; + SET_IDREG(isar, ID_ISAR0, 0x01103110); + SET_IDREG(isar, ID_ISAR1, 0x02212000); + SET_IDREG(isar, ID_ISAR2, 0x20232232); + SET_IDREG(isar, ID_ISAR3, 0x01111131); + SET_IDREG(isar, ID_ISAR4, 0x01310132); + SET_IDREG(isar, ID_ISAR5, 0x00000000); + SET_IDREG(isar, ID_ISAR6, 0x00000000); cpu->clidr =3D 0x00000000; /* caches not implemented */ cpu->ctr =3D 0x8303c003; } diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 2c45b7eddda..937a72b12c9 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -23,18 +23,19 @@ void aa32_max_features(ARMCPU *cpu) { uint32_t t; + ARMISARegisters *isar =3D &cpu->isar; =20 /* Add additional features supported by QEMU */ - t =3D cpu->isar.id_isar5; + t =3D GET_IDREG(isar, ID_ISAR5); t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */ t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */ t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */ t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */ t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */ - cpu->isar.id_isar5 =3D t; + SET_IDREG(isar, ID_ISAR5, t); =20 - t =3D cpu->isar.id_isar6; + t =3D GET_IDREG(isar, ID_ISAR6); t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */ t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */ t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */ @@ -42,7 +43,7 @@ void aa32_max_features(ARMCPU *cpu) t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */ t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */ t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */ - cpu->isar.id_isar6 =3D t; + SET_IDREG(isar, ID_ISAR6, t); =20 t =3D cpu->isar.mvfr1; t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */ @@ -140,7 +141,7 @@ static void arm926_initfn(Object *obj) * ARMv5 does not have the ID_ISAR registers, but we can still * set the field to indicate Jazelle support within QEMU. */ - cpu->isar.id_isar1 =3D FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELL= E, 1); + FIELD_DP32_IDREG(&cpu->isar, ID_ISAR1, JAZELLE, 1); /* * Similarly, we need to set MVFR0 fields to enable vfp and short vect= or * support even though ARMv5 doesn't have this register. @@ -182,7 +183,7 @@ static void arm1026_initfn(Object *obj) * ARMv5 does not have the ID_ISAR registers, but we can still * set the field to indicate Jazelle support within QEMU. */ - cpu->isar.id_isar1 =3D FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELL= E, 1); + FIELD_DP32_IDREG(&cpu->isar, ID_ISAR1, JAZELLE, 1); /* * Similarly, we need to set MVFR0 fields to enable vfp and short vect= or * support even though ARMv5 doesn't have this register. @@ -206,6 +207,7 @@ static void arm1026_initfn(Object *obj) static void arm1136_r2_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; /* * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an * older core than plain "arm1136". In particular this does not @@ -233,17 +235,18 @@ static void arm1136_r2_initfn(Object *obj) cpu->isar.id_mmfr0 =3D 0x01130003; cpu->isar.id_mmfr1 =3D 0x10030302; cpu->isar.id_mmfr2 =3D 0x01222110; - cpu->isar.id_isar0 =3D 0x00140011; - cpu->isar.id_isar1 =3D 0x12002111; - cpu->isar.id_isar2 =3D 0x11231111; - cpu->isar.id_isar3 =3D 0x01102131; - cpu->isar.id_isar4 =3D 0x141; + SET_IDREG(isar, ID_ISAR0, 0x00140011); + SET_IDREG(isar, ID_ISAR1, 0x12002111); + SET_IDREG(isar, ID_ISAR2, 0x11231111); + SET_IDREG(isar, ID_ISAR3, 0x01102131); + SET_IDREG(isar, ID_ISAR4, 0x141); cpu->reset_auxcr =3D 7; } =20 static void arm1136_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,arm1136"; set_feature(&cpu->env, ARM_FEATURE_V6K); @@ -264,17 +267,18 @@ static void arm1136_initfn(Object *obj) cpu->isar.id_mmfr0 =3D 0x01130003; cpu->isar.id_mmfr1 =3D 0x10030302; cpu->isar.id_mmfr2 =3D 0x01222110; - cpu->isar.id_isar0 =3D 0x00140011; - cpu->isar.id_isar1 =3D 0x12002111; - cpu->isar.id_isar2 =3D 0x11231111; - cpu->isar.id_isar3 =3D 0x01102131; - cpu->isar.id_isar4 =3D 0x141; + SET_IDREG(isar, ID_ISAR0, 0x00140011); + SET_IDREG(isar, ID_ISAR1, 0x12002111); + SET_IDREG(isar, ID_ISAR2, 0x11231111); + SET_IDREG(isar, ID_ISAR3, 0x01102131); + SET_IDREG(isar, ID_ISAR4, 0x141); cpu->reset_auxcr =3D 7; } =20 static void arm1176_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,arm1176"; set_feature(&cpu->env, ARM_FEATURE_V6K); @@ -296,17 +300,18 @@ static void arm1176_initfn(Object *obj) cpu->isar.id_mmfr0 =3D 0x01130003; cpu->isar.id_mmfr1 =3D 0x10030302; cpu->isar.id_mmfr2 =3D 0x01222100; - cpu->isar.id_isar0 =3D 0x0140011; - cpu->isar.id_isar1 =3D 0x12002111; - cpu->isar.id_isar2 =3D 0x11231121; - cpu->isar.id_isar3 =3D 0x01102131; - cpu->isar.id_isar4 =3D 0x01141; + SET_IDREG(isar, ID_ISAR0, 0x0140011); + SET_IDREG(isar, ID_ISAR1, 0x12002111); + SET_IDREG(isar, ID_ISAR2, 0x11231121); + SET_IDREG(isar, ID_ISAR3, 0x01102131); + SET_IDREG(isar, ID_ISAR4, 0x01141); cpu->reset_auxcr =3D 7; } =20 static void arm11mpcore_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,arm11mpcore"; set_feature(&cpu->env, ARM_FEATURE_V6K); @@ -325,11 +330,11 @@ static void arm11mpcore_initfn(Object *obj) cpu->isar.id_mmfr0 =3D 0x01100103; cpu->isar.id_mmfr1 =3D 0x10020302; cpu->isar.id_mmfr2 =3D 0x01222000; - cpu->isar.id_isar0 =3D 0x00100011; - cpu->isar.id_isar1 =3D 0x12002111; - cpu->isar.id_isar2 =3D 0x11221011; - cpu->isar.id_isar3 =3D 0x01102131; - cpu->isar.id_isar4 =3D 0x141; + SET_IDREG(isar, ID_ISAR0, 0x00100011); + SET_IDREG(isar, ID_ISAR1, 0x12002111); + SET_IDREG(isar, ID_ISAR2, 0x11221011); + SET_IDREG(isar, ID_ISAR3, 0x01102131); + SET_IDREG(isar, ID_ISAR4, 0x141); cpu->reset_auxcr =3D 1; } =20 @@ -343,6 +348,7 @@ static const ARMCPRegInfo cortexa8_cp_reginfo[] =3D { static void cortex_a8_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,cortex-a8"; set_feature(&cpu->env, ARM_FEATURE_V7); @@ -365,11 +371,11 @@ static void cortex_a8_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x20000000; cpu->isar.id_mmfr2 =3D 0x01202000; cpu->isar.id_mmfr3 =3D 0x11; - cpu->isar.id_isar0 =3D 0x00101111; - cpu->isar.id_isar1 =3D 0x12112111; - cpu->isar.id_isar2 =3D 0x21232031; - cpu->isar.id_isar3 =3D 0x11112131; - cpu->isar.id_isar4 =3D 0x00111142; + SET_IDREG(isar, ID_ISAR0, 0x00101111); + SET_IDREG(isar, ID_ISAR1, 0x12112111); + SET_IDREG(isar, ID_ISAR2, 0x21232031); + SET_IDREG(isar, ID_ISAR3, 0x11112131); + SET_IDREG(isar, ID_ISAR4, 0x00111142); cpu->isar.dbgdidr =3D 0x15141000; cpu->clidr =3D (1 << 27) | (2 << 24) | 3; cpu->ccsidr[0] =3D 0xe007e01a; /* 16k L1 dcache. */ @@ -412,6 +418,7 @@ static const ARMCPRegInfo cortexa9_cp_reginfo[] =3D { static void cortex_a9_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,cortex-a9"; set_feature(&cpu->env, ARM_FEATURE_V7); @@ -440,11 +447,11 @@ static void cortex_a9_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x20000000; cpu->isar.id_mmfr2 =3D 0x01230000; cpu->isar.id_mmfr3 =3D 0x00002111; - cpu->isar.id_isar0 =3D 0x00101111; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232041; - cpu->isar.id_isar3 =3D 0x11112131; - cpu->isar.id_isar4 =3D 0x00111142; + SET_IDREG(isar, ID_ISAR0, 0x00101111); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232041); + SET_IDREG(isar, ID_ISAR3, 0x11112131); + SET_IDREG(isar, ID_ISAR4, 0x00111142); cpu->isar.dbgdidr =3D 0x35141000; cpu->clidr =3D (1 << 27) | (1 << 24) | 3; cpu->ccsidr[0] =3D 0xe00fe019; /* 16k L1 dcache. */ @@ -479,6 +486,7 @@ static const ARMCPRegInfo cortexa15_cp_reginfo[] =3D { static void cortex_a7_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,cortex-a7"; set_feature(&cpu->env, ARM_FEATURE_V7VE); @@ -509,11 +517,11 @@ static void cortex_a7_initfn(Object *obj) * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but * table 4-41 gives 0x02101110, which includes the arm div insns. */ - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232041; - cpu->isar.id_isar3 =3D 0x11112131; - cpu->isar.id_isar4 =3D 0x10011142; + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232041); + SET_IDREG(isar, ID_ISAR3, 0x11112131); + SET_IDREG(isar, ID_ISAR4, 0x10011142); cpu->isar.dbgdidr =3D 0x3515f005; cpu->isar.dbgdevid =3D 0x01110f13; cpu->isar.dbgdevid1 =3D 0x1; @@ -528,6 +536,7 @@ static void cortex_a7_initfn(Object *obj) static void cortex_a15_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,cortex-a15"; set_feature(&cpu->env, ARM_FEATURE_V7VE); @@ -556,11 +565,11 @@ static void cortex_a15_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x20000000; cpu->isar.id_mmfr2 =3D 0x01240000; cpu->isar.id_mmfr3 =3D 0x02102211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232041; - cpu->isar.id_isar3 =3D 0x11112131; - cpu->isar.id_isar4 =3D 0x10011142; + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232041); + SET_IDREG(isar, ID_ISAR3, 0x11112131); + SET_IDREG(isar, ID_ISAR4, 0x10011142); cpu->isar.dbgdidr =3D 0x3515f021; cpu->isar.dbgdevid =3D 0x01110f13; cpu->isar.dbgdevid1 =3D 0x0; @@ -585,6 +594,7 @@ static const ARMCPRegInfo cortexr5_cp_reginfo[] =3D { static void cortex_r5_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 set_feature(&cpu->env, ARM_FEATURE_V7); set_feature(&cpu->env, ARM_FEATURE_V7MP); @@ -599,13 +609,13 @@ static void cortex_r5_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x00000000; cpu->isar.id_mmfr2 =3D 0x01200000; cpu->isar.id_mmfr3 =3D 0x0211; - cpu->isar.id_isar0 =3D 0x02101111; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232141; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x0010142; - cpu->isar.id_isar5 =3D 0x0; - cpu->isar.id_isar6 =3D 0x0; + SET_IDREG(isar, ID_ISAR0, 0x02101111); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232141); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x0010142); + SET_IDREG(isar, ID_ISAR5, 0x0); + SET_IDREG(isar, ID_ISAR6, 0x0); cpu->mp_is_up =3D true; cpu->pmsav7_dregion =3D 16; cpu->isar.reset_pmcr_el0 =3D 0x41151800; @@ -720,6 +730,7 @@ static const ARMCPRegInfo cortex_r52_cp_reginfo[] =3D { static void cortex_r52_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_EL2); @@ -746,12 +757,12 @@ static void cortex_r52_initfn(Object *obj) cpu->isar.id_mmfr2 =3D 0x01200000; cpu->isar.id_mmfr3 =3D 0xf0102211; cpu->isar.id_mmfr4 =3D 0x00000010; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232142; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00010142; - cpu->isar.id_isar5 =3D 0x00010001; + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232142); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00010142); + SET_IDREG(isar, ID_ISAR5, 0x00010001); cpu->isar.dbgdidr =3D 0x77168000; cpu->clidr =3D (1 << 27) | (1 << 24) | 0x3; cpu->ccsidr[0] =3D 0x700fe01a; /* 32KB L1 dcache */ @@ -949,6 +960,7 @@ static void pxa270c5_initfn(Object *obj) static void arm_max_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 /* aarch64_a57_initfn, advertising none of the aarch64 features */ cpu->dtb_compatible =3D "arm,cortex-a57"; @@ -976,13 +988,13 @@ static void arm_max_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02102211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00011142; - cpu->isar.id_isar5 =3D 0x00011121; - cpu->isar.id_isar6 =3D 0; + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232042); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00011142); + SET_IDREG(isar, ID_ISAR5, 0x00011121); + SET_IDREG(isar, ID_ISAR6, 0); cpu->isar.reset_pmcr_el0 =3D 0x41013000; cpu->clidr =3D 0x0a200023; cpu->ccsidr[0] =3D 0x701fe00a; /* 32KB L1 dcache */ diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 80a99ab025d..dd4dc8ada56 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -57,12 +57,12 @@ static void aarch64_a35_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02102211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00011142; - cpu->isar.id_isar5 =3D 0x00011121; + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232042); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00011142); + SET_IDREG(isar, ID_ISAR5, 0x00011121); SET_IDREG(isar, ID_AA64PFR0, 0x00002222); SET_IDREG(isar, ID_AA64PFR1, 0); SET_IDREG(isar, ID_AA64DFR0, 0x10305106); @@ -229,13 +229,13 @@ static void aarch64_a55_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_dfr0 =3D 0x04010088; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00011142; - cpu->isar.id_isar5 =3D 0x01011121; - cpu->isar.id_isar6 =3D 0x00000010; + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232042); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00011142); + SET_IDREG(isar, ID_ISAR5, 0x01011121); + SET_IDREG(isar, ID_ISAR6, 0x00000010); cpu->isar.id_mmfr0 =3D 0x10201105; cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; @@ -303,12 +303,12 @@ static void aarch64_a72_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02102211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00011142; - cpu->isar.id_isar5 =3D 0x00011121; + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232042); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00011142); + SET_IDREG(isar, ID_ISAR5, 0x00011121); SET_IDREG(isar, ID_AA64PFR0, 0x00002222); SET_IDREG(isar, ID_AA64DFR0, 0x10305106); SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); @@ -362,13 +362,13 @@ static void aarch64_a76_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_dfr0 =3D 0x04010088; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00010142; - cpu->isar.id_isar5 =3D 0x01011121; - cpu->isar.id_isar6 =3D 0x00000010; + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232042); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00010142); + SET_IDREG(isar, ID_ISAR5, 0x01011121); + SET_IDREG(isar, ID_ISAR6, 0x00000010); cpu->isar.id_mmfr0 =3D 0x10201105; cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; @@ -610,13 +610,13 @@ static void aarch64_neoverse_n1_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_dfr0 =3D 0x04010088; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00010142; - cpu->isar.id_isar5 =3D 0x01011121; - cpu->isar.id_isar6 =3D 0x00000010; + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232042); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00010142); + SET_IDREG(isar, ID_ISAR5, 0x01011121); + SET_IDREG(isar, ID_ISAR6, 0x00000010); cpu->isar.id_mmfr0 =3D 0x10201105; cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; @@ -689,13 +689,13 @@ static void aarch64_neoverse_v1_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_dfr0 =3D 0x15011099; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00010142; - cpu->isar.id_isar5 =3D 0x11011121; - cpu->isar.id_isar6 =3D 0x01100111; + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232042); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00010142); + SET_IDREG(isar, ID_ISAR5, 0x11011121); + SET_IDREG(isar, ID_ISAR6, 0x01100111); cpu->isar.id_mmfr0 =3D 0x10201105; cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; @@ -910,14 +910,14 @@ static void aarch64_a710_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02122211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00010142; - cpu->isar.id_isar5 =3D 0x11011121; /* with Crypto */ + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232042); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00010142); + SET_IDREG(isar, ID_ISAR5, 0x11011121); /* with Crypto */ cpu->isar.id_mmfr4 =3D 0x21021110; - cpu->isar.id_isar6 =3D 0x01111111; + SET_IDREG(isar, ID_ISAR6, 0x01111111); cpu->isar.mvfr0 =3D 0x10110222; cpu->isar.mvfr1 =3D 0x13211111; cpu->isar.mvfr2 =3D 0x00000043; @@ -1012,14 +1012,14 @@ static void aarch64_neoverse_n2_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02122211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00010142; - cpu->isar.id_isar5 =3D 0x11011121; /* with Crypto */ + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232042); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00010142); + SET_IDREG(isar, ID_ISAR5, 0x11011121); /* with Crypto */ cpu->isar.id_mmfr4 =3D 0x01021110; - cpu->isar.id_isar6 =3D 0x01111111; + SET_IDREG(isar, ID_ISAR6, 0x01111111); cpu->isar.mvfr0 =3D 0x10110222; cpu->isar.mvfr1 =3D 0x13211111; cpu->isar.mvfr2 =3D 0x00000043; --=20 2.43.0