From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1751390098; cv=none; d=zohomail.com; s=zohoarc; b=LF//FLqAcvyFxOMSKmRCDebPOUPyoUEPD4evl6TcGsr//JqdaI8BkMcXD3sShrAfoTAdZB037xJ0VhiPUP+d127I9HSreLxQyiPqyYaxTnD/ARfYMyr1twKmO9Uvqi3fStaSUarfoFSqJDIi1KJa5HjBmSuJ8MA1VkYgY3OkGfc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751390098; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=bO/eRE0oLZeR5GcJzymVIXIdadc1wAcqQphyP71Niqg=; b=DzAxJo722u4malia4n9FGko6a/2pMtWTrop7o+lLiA27nKU65bli/gCbeRZoR4z5s7NmfbFaXQ/PFzcM7r7KkpCrobch3r3BCzc3MFVV7y+9+N4Y/hYNUziBvy4c8WOXz6MrUMM98HiLLQPO7HZbgN5l9okC1HkecKNkfMviSPo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1751390098877139.09300767202137; Tue, 1 Jul 2025 10:14:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uWeSd-0005iP-4n; Tue, 01 Jul 2025 13:07:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uWeSG-0005RL-IE for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:07:39 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uWeSB-0003KU-0b for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:07:34 -0400 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-3a50956e5d3so5017143f8f.1 for ; Tue, 01 Jul 2025 10:07:25 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a88c80bb28sm13475658f8f.43.2025.07.01.10.07.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 10:07:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751389643; x=1751994443; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=bO/eRE0oLZeR5GcJzymVIXIdadc1wAcqQphyP71Niqg=; b=T3w7VavbYkhgsK00Yvi4EW08c2Lj0qJryjuhM16A5YFDWdZr3GPlFl0Sa+1O+0sxwW JEMZvsI23PiNmgwAmPkJ4jG+3FOgOu2xEPHZaz7q6ZOkfEriCc6ZHjpB0KUTJB3hif5U 7S/mrOmvUbFyXa56YLeojiJ+SUrzKg7408ytfL/Y0DK5mlIV2wVa2niemGQrdr06adCq ApR6pfeEe8PU42EpZhP2hq7HlCUTgoMrayGkFJcJr1bP3c+VPL4wEJgrNkvdYZx4boYK 3VW2WRJwrd+LiDx0hzzj+12UOQGJspbWWb8GRKcCXDhD6rtBgv2P9XgkBJ/BW/dG5z1A UujA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751389643; x=1751994443; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bO/eRE0oLZeR5GcJzymVIXIdadc1wAcqQphyP71Niqg=; b=mv+Sg0/MJFzgZB2d8qK+fo90sW8GybDOsAQ4eQv2g0lIB7Wpa1UqdzLpH2XYtNEQ2D tqCI53Nrhq4mqm3M7wDUjI0Wgjp8e3r8Fx59GLQ7Tb+pK/QOhoeV8O6QmTStWIOkwVzj lTJtv4prZPZzrmbpx3x7YS5rp8ds46/GrrgkijsZLjYk8DRh3KrbHN8QS3lJOagfwxk0 1Nwin2k+98pxi9n74ZDynniJR7DrqCdORSH/S+O/4m41W3XOGpcKy+0fma1SIjx5aXQg AsoYzMZiBRGjoMjE9FdUe2L/RjR5g/3x9CakglLGRC3Jg8qZbNilMjmkA4rvULIZa76i h9zA== X-Gm-Message-State: AOJu0YyYd6DGZ+qfhKSnpr15ZY3IqNuW/EtBRQdJ+Yxz/WaclEtsGe44 wjelhLxFSJDqlDaN0QXlGboOMsVvbGvIr3s2e9WFwhi361oqlqxR1Haovr6eJPzzINja19cNTpU Q8agf X-Gm-Gg: ASbGncv17jePxWMRhq3oJem+yI9/P3sV1LyF97MeEwG4DpLLur/GrIXiZ0EBZkQiL7L mnIBhGieG+kYB1BVVKeEUW9wvIiJDOCUOwnz7oqVlIgsyVQTVzup7fMZuNCzkHAfUT0iC/SAWJk R0QJ57w+Ig5sp+BBbubQC/biY1JtpmyBt/HHO9fOxUvYwwSbR1DFDsQkYAAyKjAILSQLiJALKvb YmczQ6IA1CDe0zuDI+lH4WIL7lUx4pnYfmlfIsZgrPHQ9QOcUZCv0fJltdJmw7WjN/pUPDtLkFr ObrNCVL8zEzr4UApqzkp7ESrC3R7yCCZ3r0oytJgDGSCJo2iffa5RyzYj0YliW1d0oGO X-Google-Smtp-Source: AGHT+IEYWLZxdobjA8crRmR+FwWhkomues9TZK+twHaLr9sCQp8g9mNHsqLY7Zr3JfWhZIWThh4CQA== X-Received: by 2002:adf:ea50:0:b0:3a5:52b3:103b with SMTP id ffacd0b85a97d-3a90d0d6d11mr13527678f8f.4.1751389643455; Tue, 01 Jul 2025 10:07:23 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/43] MAINTAINERS: add myself as reviewer for Apple Silicon HVF Date: Tue, 1 Jul 2025 18:06:37 +0100 Message-ID: <20250701170720.4072660-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751390099587116600 Content-Type: text/plain; charset="utf-8" From: Mads Ynddal I've both publicly and private been digging around the Apple Silicon HVF co= de, and use it daily as part of my job. I feel I have a solid understanding of = it, so I thought I'd step up and assist. I've added myself as reviewer to the common "HVF" as well, to be informed of changes that might affect the Apple Silicon HVF code, which will be my prim= ary focus. Signed-off-by: Mads Ynddal Message-id: 20250617093001.70080-1-mads@ynddal.dk Signed-off-by: Peter Maydell --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index d1672fda8dd..b3b2a112073 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -511,6 +511,7 @@ F: system/cpus.c =20 Apple Silicon HVF CPUs M: Alexander Graf +R: Mads Ynddal S: Maintained F: target/arm/hvf/ F: target/arm/hvf-stub.c @@ -527,6 +528,7 @@ HVF M: Cameron Esfahani M: Roman Bolshakov R: Phil Dennis-Jordan +R: Mads Ynddal W: https://wiki.qemu.org/Features/HVF S: Maintained F: accel/hvf/ --=20 2.43.0 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1751389960; cv=none; d=zohomail.com; s=zohoarc; b=MZiHUcvxju00axDYmGKDcsPuX04a03pU6hQFVoPOXSxMkVE64TyUsboLiC6lqZJ/gpRT0MQBVmwFjl+xclg4TrVZ3G4S7Og/sNgZIda9D45QVVXL3jhSXfi1Bg/k5IkrJyWz964bhc/QzbYrM2qH7Ug6nPb2zstUXGly2zCNbE4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751389960; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=qVAzEalqJxujtmncmmPvxYDDmAvLtGutu9NBUWptPQA=; b=Wwh6P7mx/hxikJlsdTZUaLk2z5cH4F+GqvNugMwYicy7EjJctBYikj0tnkxDdJXmQjm3cRbVNObbvDiejTfM7EP/VYSdloT9D/cuo2PbqJ00i7FzFk+HQ5P0Ae5vPwsksJ1kNmLXeAcKk0N88JfTLAuPTI0rppob454xy2ICImA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1751389959997216.99536605059916; Tue, 1 Jul 2025 10:12:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uWeSQ-0005V9-7S; Tue, 01 Jul 2025 13:07:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uWeSG-0005RI-Gx for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:07:39 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uWeSA-0003Ks-Aa for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:07:34 -0400 Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-3a6cdc27438so3016749f8f.2 for ; Tue, 01 Jul 2025 10:07:26 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a88c80bb28sm13475658f8f.43.2025.07.01.10.07.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 10:07:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751389644; x=1751994444; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=qVAzEalqJxujtmncmmPvxYDDmAvLtGutu9NBUWptPQA=; b=QA08r9Aisdh1F1vaib+3ukBHhOAxztldWecm8I8bI42XOmy9HCbT1DE/tIW51+g/kY 7Tby5GxTh5N+fcXtNBa/fq7OzWyBgWMbFORkbLteyYrbJ0czy9fftZ8VSMBS5bYUAyVA IQlH5MnNsNAFGeJcm5d9B+JnihEe9T2oZfCsnf1yIvoItINb3hq884kOP9SH6AJIE9UF KqFqAN2AlO3cG4aPjEpIT+LBkXEsqEwhQTipLOZpxPSXlMTUMesKRRVOL2ZO4byOjjBF HZKpu+G4M3i/+Zsot18jVuOhcc53JL1AY9AayWlxDYrTRwMHnnSdtd8r9vfZZlBhjOVo czpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751389644; x=1751994444; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qVAzEalqJxujtmncmmPvxYDDmAvLtGutu9NBUWptPQA=; b=qWpPsd64GeEvThAwGYu/jlt0xN2E8r0sfnMMufZJ7mqwwV19WV9EpMB2C9xMmbysEk TXw8rjqJA+ceJ2K/VZ4Ki9F3eNsuDaQGswsj1CoEjiKe+RADlO6vOV0HqMT7o0U05JJl IuJe6gTxd/zXmlgXV16OAqR04yHPx4SlrDg++9WeRML8bR5S2tH5ary0qJOBCLYSOndR OW50U/IwZ0Qew/iIqPH3j8hsXKvs+lSVw+G+z6Q+NS7aD/1OcC7z3Ch0MJkyY0OJ3UeX D/AtOLWZ6XyEBkf1K1KG6QU4zN8Rev+q6NNsnGxKcIm+OFueyS+dc98PV6UZ5icIdZIH V25Q== X-Gm-Message-State: AOJu0YxaBNfEdb0Dh2J+QPmFVZUEKQQBdPUd8o6dtOFi49i6Nbx1VCFS fheeQsf0U1Pj3pfaT3dvkDGnmg0s7P900ZMyIkrh1Vrzinbik/CZ7v6pU9dexmrpivwKBLbtQ1P sZQ9J X-Gm-Gg: ASbGncsxt4qapF2dc91r1xVV2EVEfTBFdLq3w4oxoUBrImdL4YEblxT+4B2UUsmwVYo 8QcHDZ0LhfUCysYZPTzIGUgSqpddDyUwzXWxtVgxKD+csEAtcx6ugjWdG6zzucvtFWELpSa+IMv 9Inha3ZeOSeq1LJKPE87tFR/TybFdIjCcNK7EbgSfUCPxX7QW5N90bMMoCaxKunCfkhflBpLL+d NZQgrJvOxHntD47UcBsnLSNC1yGm9GMT9OGNaSOsKXMddSFL2Pp+iLB1Ch9jjOMsn4VJmNFwzKV NOkiWqlTbscaC7XH4AS0jP1FIxpd2rGOcGTRf4mt/5eO9NQw/WsCgWhOitOXCUm6s95f X-Google-Smtp-Source: AGHT+IEg8T5mGcjdQ9YcXXleR92TI4j2iB9+NXY/sKR52wvGJCY+hXjOCMVpor/r4o64LcgyNFqyDw== X-Received: by 2002:a05:6000:2188:b0:3a4:d79a:35a6 with SMTP id ffacd0b85a97d-3a8f482c094mr12665995f8f.14.1751389644508; Tue, 01 Jul 2025 10:07:24 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/43] target/arm: Make RETA[AB] UNDEF when pauth is not implemented Date: Tue, 1 Jul 2025 18:06:38 +0100 Message-ID: <20250701170720.4072660-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751389963770116600 From: Solomon Tan According to the Arm A-profile A64 Instruction Set Architecture, RETA[AB] should be decoded as UNDEF if the pauth feature is not implemented. We got this right in the initial implementation, but accidentally dropped the feature-check when we converted these insns to decodetree. Cc: qemu-stable@nongnu.org Fixes: 0ebbe9021254f ("target/arm: Convert BRA[AB]Z, BLR[AB]Z, RETA[AB] to = decodetree") Signed-off-by: Solomon Tan Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Message-id: 20250616171549.59190-1-root@wjsota.com Signed-off-by: Peter Maydell --- target/arm/tcg/translate-a64.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index ac80f572a2d..d0719b5665f 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1816,6 +1816,10 @@ static bool trans_RETA(DisasContext *s, arg_reta *a) { TCGv_i64 dst; =20 + if (!dc_isar_feature(aa64_pauth, s)) { + return false; + } + dst =3D auth_branch_target(s, cpu_reg(s, 30), cpu_X[31], !a->m); gen_a64_set_pc(s, dst); s->base.is_jmp =3D DISAS_JUMP; --=20 2.43.0 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1751389716; cv=none; d=zohomail.com; s=zohoarc; b=INiDMtUQefsCwkQkSGPfvv04DL0DLHya38b/g9jxieaFOKSwVtkWI6mytJrGNQzBl2ghwZKwSkqMtDoPlKC73Ykgt6hMYsu7olY1OWqv1dVrz9/Iv7Vs84nLSksiDmYewEQrINqTsSqQw4GqP+u31qICsxCpRrQrlKOFbcM5Dg4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751389716; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=d8RIzQ3n1BHH0dQFwFKHTX86k4EkDTNAuy4IxtboWro=; b=fx+JLL3xsN+0Lfh6K4BLexTeLzWv80LNPzg0Hdk4ZYtTzuf5uICxDF0dm613fnrPKNtVVmfsSrlMnFr5LO7FsHmClRGQOKtYz/ak7mpksIDL7SL2P20LaICSLcUdoJSHI1aW+A2ecpl7Uop+0uC8ljed4gECOXuZtxVFZZy73sY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1751389716106944.8185912426167; Tue, 1 Jul 2025 10:08:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uWeSS-0005Yh-6Z; Tue, 01 Jul 2025 13:07:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uWeSG-0005RT-Ke for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:07:39 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uWeSA-0003LF-Ks for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:07:32 -0400 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-3ab112dea41so1965688f8f.1 for ; Tue, 01 Jul 2025 10:07:27 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a88c80bb28sm13475658f8f.43.2025.07.01.10.07.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 10:07:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751389646; x=1751994446; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=d8RIzQ3n1BHH0dQFwFKHTX86k4EkDTNAuy4IxtboWro=; b=oyOEs8JnYSRJfgqWK0Z9Y7MAKvUjbJysLFUVURKPnA5+j+nIIp1S73NsDVSuskmJnK /cUlmIh8yUBDm84U7e922VBQbJA3+fOHx5kBTBN7N0zWjLCDtov8XTycdfd2VSsd3DNF n/U+k2ZehGvQP/n22vbsZBsAHOccxXEo7xCf/zKCt4QfLq4OhtrICa+qbSC57L8nGM+D FkGlP3gaMnj3Qdzu+TBqo5EVzppO3DSifbxvHhnMi29LBctpu/CpNxVXw6l2SsIGmvL4 ZGGXZtV4imMJkLw351DQfgbdfihyeBMiEhctxCIfNuDkRry0pVAU+g6HJ2qexQC3RFxh If8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751389646; x=1751994446; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d8RIzQ3n1BHH0dQFwFKHTX86k4EkDTNAuy4IxtboWro=; b=eTEiuWyKYNAoVgMaqzNp31ChbeiGmxOT/7av67chjHhAWe1sdyZv/aTnHTYoWOIWQ7 zW1iqn/EH4EEVqXOgbvrlcQZJhaPQncubEAdrIMOR0g6J8IWRR++TM+S8a0m8wWI33RM hdW7n9wQmmYHRQHEkkTlvkZZ3jE56N1sWezubfVR20geVO8hmZdEZdtFAtkVayTcioXA wJUgwHIvJeF7S1VkHrSEsKyK0oNmaWHG9hXS5guYexxM3mrGHBbqkjRGrPV8VfxUTiNy dLxPGpjxgv1U3c2wa8n8XoaJDG6Yu30oqx/BP7MQwybHpUtZgv6vRN72LGAb0YR2qXg4 /PSA== X-Gm-Message-State: AOJu0Yyei+laDHpDqyCcEaTyGDiU/KD51ML8bgz7h32wvmFYcyIgjDKN PD0g8qiz7g/UM+yPKdoO8W+Dj/V7E8S3ZwK1ueq1EWVYztsXYFQNlopv+frwfKpD+zd6BXWJXqi TDUM4 X-Gm-Gg: ASbGncubPUAbqVc0+t7jpsVQea87DNBcfO/k4ljpP3vI3WAUnqvZu7fC2Vaz4UMYmLD mkGTSeYSGvBfz2kHmMza8CLvYKUXn59oclMjaDGdMQWreHLa/Mxdg5vO4gQWVUUhhAJYssGdGoV yXDObkIZjQEmsMavggy2depXN4NC3POHWCFkvI+wxd3+kQzgB8wwSg4dxGPwvGdHJ+zvx6jjtXM WO1AWPSr8ZZ5Ry/uaxWOXQb+wbE3YIBEwaJVv7gPXOrzj7sjs8AbrzNfyvyc/Ms2FnqPctEKFC4 yUJhr3wRgAlJ0huenBUlVc20FDXL23PuHSFPw30Lqnsaepw+S+DW95XxWBji6BROoSRG X-Google-Smtp-Source: AGHT+IEJfjDjH0c5vm+RyFH7ct0ZZe7nSbnXUlExopnnxsOptjv7TfqSt/NfB5FFVHl7dT34ooA1LQ== X-Received: by 2002:a05:6000:4107:b0:3a5:2653:7322 with SMTP id ffacd0b85a97d-3a8fda35aa8mr14931752f8f.3.1751389645685; Tue, 01 Jul 2025 10:07:25 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/43] arm/cpu: Add sysreg definitions in cpu-sysregs.h Date: Tue, 1 Jul 2025 18:06:39 +0100 Message-ID: <20250701170720.4072660-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751389719056116600 Content-Type: text/plain; charset="utf-8" From: Eric Auger This new header contains macros that define aarch64 registers. In a subsequent patch, this will be replaced by a more exhaustive version that will be generated from linux arch/arm64/tools/sysreg file. Those macros are sufficient to migrate the storage of those ID regs from named fields in isar struct to an array cell. [CH: reworked to use different structures] [CH: moved accessors from the patches first using them to here, dropped interaction with writable registers, which will happen later] [CH: use DEF magic suggested by rth] Reviewed-by: Richard Henderson Reviewed-by: Sebastian Ott Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck Message-id: 20250617153931.1330449-2-cohuck@redhat.com Signed-off-by: Peter Maydell --- target/arm/cpu-sysregs.h | 42 +++++++++++++++++++++++++++++++ target/arm/cpu.h | 49 ++++++++++++++++++++++++++++++++++++ target/arm/cpu-sysregs.h.inc | 36 ++++++++++++++++++++++++++ target/arm/cpu64.c | 22 ++++++++++++++++ 4 files changed, 149 insertions(+) create mode 100644 target/arm/cpu-sysregs.h create mode 100644 target/arm/cpu-sysregs.h.inc diff --git a/target/arm/cpu-sysregs.h b/target/arm/cpu-sysregs.h new file mode 100644 index 00000000000..7877a3b06a8 --- /dev/null +++ b/target/arm/cpu-sysregs.h @@ -0,0 +1,42 @@ +/* + * Definitions for Arm ID system registers + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef ARM_CPU_SYSREGS_H +#define ARM_CPU_SYSREGS_H + +/* + * Following is similar to the coprocessor regs encodings, but with an arg= ument + * ordering that matches the ARM ARM. We also reuse the various CP_REG_ de= fines + * that actually are the same as the equivalent KVM_REG_ values. + */ +#define ENCODE_ID_REG(op0, op1, crn, crm, op2) \ + (((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ + ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ + ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ + ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ + ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) + +#define DEF(NAME, OP0, OP1, CRN, CRM, OP2) NAME##_IDX, + +typedef enum ARMIDRegisterIdx { +#include "cpu-sysregs.h.inc" + NUM_ID_IDX, +} ARMIDRegisterIdx; + +#undef DEF +#define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \ + SYS_##NAME =3D ENCODE_ID_REG(OP0, OP1, CRN, CRM, OP2), + +typedef enum ARMSysRegs { +#include "cpu-sysregs.h.inc" +} ARMSysRegs; + +#undef DEF + +extern const uint32_t id_register_sysreg[NUM_ID_IDX]; + +int get_sysreg_idx(ARMSysRegs sysreg); + +#endif /* ARM_CPU_SYSREGS_H */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 302c24e2324..45409f84ef0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -32,6 +32,7 @@ #include "qapi/qapi-types-common.h" #include "target/arm/multiprocessing.h" #include "target/arm/gtimer.h" +#include "target/arm/cpu-sysregs.h" =20 #define EXCP_UDEF 1 /* undefined instruction */ #define EXCP_SWI 2 /* software interrupt */ @@ -834,6 +835,53 @@ typedef struct { uint32_t map, init, supported; } ARMVQMap; =20 +/* REG is ID_XXX */ +#define FIELD_DP64_IDREG(ISAR, REG, FIELD, VALUE) \ + ({ \ + ARMISARegisters *i_ =3D (ISAR); \ + uint64_t regval =3D i_->idregs[REG ## _EL1_IDX]; \ + regval =3D FIELD_DP64(regval, REG, FIELD, VALUE); \ + i_->idregs[REG ## _EL1_IDX] =3D regval; \ + }) + +#define FIELD_DP32_IDREG(ISAR, REG, FIELD, VALUE) \ + ({ \ + ARMISARegisters *i_ =3D (ISAR); \ + uint64_t regval =3D i_->idregs[REG ## _EL1_IDX]; \ + regval =3D FIELD_DP32(regval, REG, FIELD, VALUE); \ + i_->idregs[REG ## _EL1_IDX] =3D regval; \ + }) + +#define FIELD_EX64_IDREG(ISAR, REG, FIELD) \ + ({ \ + const ARMISARegisters *i_ =3D (ISAR); \ + FIELD_EX64(i_->idregs[REG ## _EL1_IDX], REG, FIELD); \ + }) + +#define FIELD_EX32_IDREG(ISAR, REG, FIELD) \ + ({ \ + const ARMISARegisters *i_ =3D (ISAR); \ + FIELD_EX32(i_->idregs[REG ## _EL1_IDX], REG, FIELD); \ + }) + +#define FIELD_SEX64_IDREG(ISAR, REG, FIELD) \ + ({ \ + const ARMISARegisters *i_ =3D (ISAR); \ + FIELD_SEX64(i_->idregs[REG ## _EL1_IDX], REG, FIELD); \ + }) + +#define SET_IDREG(ISAR, REG, VALUE) \ + ({ \ + ARMISARegisters *i_ =3D (ISAR); \ + i_->idregs[REG ## _EL1_IDX] =3D VALUE; \ + }) + +#define GET_IDREG(ISAR, REG) \ + ({ \ + const ARMISARegisters *i_ =3D (ISAR); \ + i_->idregs[REG ## _EL1_IDX]; \ + }) + /** * ARMCPU: * @env: #CPUARMState @@ -1040,6 +1088,7 @@ struct ArchCPU { uint64_t id_aa64zfr0; uint64_t id_aa64smfr0; uint64_t reset_pmcr_el0; + uint64_t idregs[NUM_ID_IDX]; } isar; uint64_t midr; uint32_t revidr; diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc new file mode 100644 index 00000000000..cb99286f704 --- /dev/null +++ b/target/arm/cpu-sysregs.h.inc @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +DEF(ID_AA64PFR0_EL1, 3, 0, 0, 4, 0) +DEF(ID_AA64PFR1_EL1, 3, 0, 0, 4, 1) +DEF(ID_AA64SMFR0_EL1, 3, 0, 0, 4, 5) +DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0) +DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1) +DEF(ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0) +DEF(ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1) +DEF(ID_AA64ISAR2_EL1, 3, 0, 0, 6, 2) +DEF(ID_AA64MMFR0_EL1, 3, 0, 0, 7, 0) +DEF(ID_AA64MMFR1_EL1, 3, 0, 0, 7, 1) +DEF(ID_AA64MMFR2_EL1, 3, 0, 0, 7, 2) +DEF(ID_AA64MMFR3_EL1, 3, 0, 0, 7, 3) +DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0) +DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1) +DEF(ID_DFR0_EL1, 3, 0, 0, 1, 2) +DEF(ID_MMFR0_EL1, 3, 0, 0, 1, 4) +DEF(ID_MMFR1_EL1, 3, 0, 0, 1, 5) +DEF(ID_MMFR2_EL1, 3, 0, 0, 1, 6) +DEF(ID_MMFR3_EL1, 3, 0, 0, 1, 7) +DEF(ID_ISAR0_EL1, 3, 0, 0, 2, 0) +DEF(ID_ISAR1_EL1, 3, 0, 0, 2, 1) +DEF(ID_ISAR2_EL1, 3, 0, 0, 2, 2) +DEF(ID_ISAR3_EL1, 3, 0, 0, 2, 3) +DEF(ID_ISAR4_EL1, 3, 0, 0, 2, 4) +DEF(ID_ISAR5_EL1, 3, 0, 0, 2, 5) +DEF(ID_MMFR4_EL1, 3, 0, 0, 2, 6) +DEF(ID_ISAR6_EL1, 3, 0, 0, 2, 7) +DEF(MVFR0_EL1, 3, 0, 0, 3, 0) +DEF(MVFR1_EL1, 3, 0, 0, 3, 1) +DEF(MVFR2_EL1, 3, 0, 0, 3, 2) +DEF(ID_PFR2_EL1, 3, 0, 0, 3, 4) +DEF(ID_DFR1_EL1, 3, 0, 0, 3, 5) +DEF(ID_MMFR5_EL1, 3, 0, 0, 3, 6) +DEF(ID_AA64ZFR0_EL1, 3, 0, 0, 4, 4) +DEF(CTR_EL0, 3, 3, 0, 0, 1) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 200da1c489b..77054e0ec38 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -36,6 +36,28 @@ #include "cpu-features.h" #include "cpregs.h" =20 +/* convert between _IDX and SYS_ */ +#define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \ + [NAME##_IDX] =3D SYS_##NAME, + +const uint32_t id_register_sysreg[NUM_ID_IDX] =3D { +#include "cpu-sysregs.h.inc" +}; + +#undef DEF +#define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \ + case SYS_##NAME: return NAME##_IDX; + +int get_sysreg_idx(ARMSysRegs sysreg) +{ + switch (sysreg) { +#include "cpu-sysregs.h.inc" + } + g_assert_not_reached(); +} + +#undef DEF + void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { /* --=20 2.43.0 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1751390057; cv=none; d=zohomail.com; s=zohoarc; b=bMLp3Yr13hPGsLkdi8ugSYjLv592OAXs5XEB2y0Jb9XdAILA8+Tv3uOMdUdZwyFaeYOyBgGsZJui/MUeNQhys70ffTIyh9rn8HPjsVcSr1Z3CXiisEpsbtyKacUIO4v6Y0jzBqX0kH6wsffiLEXPpyOZoyhOm3beG6/v8hGUQiI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751390057; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; 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Reviewed-by: Richard Henderson Reviewed-by: Sebastian Ott Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck Message-id: 20250617153931.1330449-3-cohuck@redhat.com Signed-off-by: Peter Maydell --- target/arm/cpu-features.h | 57 ++++++++++++++++++++------------------- target/arm/cpu.h | 2 -- target/arm/cpu.c | 9 +++---- target/arm/cpu64.c | 8 +++--- target/arm/helper.c | 6 +++-- target/arm/hvf/hvf.c | 3 ++- target/arm/kvm.c | 30 ++++++++++++++++++--- target/arm/tcg/cpu64.c | 44 ++++++++++++++++++------------ 8 files changed, 97 insertions(+), 62 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 4452e7c21e3..6a47f1a6d22 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -23,6 +23,7 @@ #include "hw/registerfields.h" #include "qemu/host-utils.h" #include "cpu.h" +#include "cpu-sysregs.h" =20 /* * Naming convention for isar_feature functions: @@ -377,92 +378,92 @@ static inline bool isar_feature_aa32_doublelock(const= ARMISARegisters *id) */ static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, AES) !=3D 0; } =20 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, AES) > 1; } =20 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SHA1) !=3D 0; } =20 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SHA2) !=3D 0; } =20 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SHA2) > 1; } =20 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, CRC32) !=3D 0; } =20 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, ATOMIC) !=3D 0; } =20 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, RDM) !=3D 0; } =20 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SHA3) !=3D 0; } =20 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SM3) !=3D 0; } =20 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SM4) !=3D 0; } =20 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, DP) !=3D 0; } =20 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, FHM) !=3D 0; } =20 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, TS) !=3D 0; } =20 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, TS) >=3D 2; } =20 static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, RNDR) !=3D 0; } =20 static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) =3D=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, TLB) =3D=3D 2; } =20 static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, TLB) !=3D 0; } =20 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) @@ -928,52 +929,52 @@ static inline bool isar_feature_aa64_doublelock(const= ARMISARegisters *id) =20 static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SVEVER) !=3D 0; } =20 static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, AES) !=3D 0; } =20 static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *= id) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) >=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, AES) >=3D 2; } =20 static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *i= d) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, BITPERM) !=3D 0; } =20 static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BFLOAT16) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, BFLOAT16) !=3D 0; } =20 static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SHA3) !=3D 0; } =20 static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SM4) !=3D 0; } =20 static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, I8MM) !=3D 0; } =20 static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, F32MM) !=3D 0; } =20 static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, F64MM) !=3D 0; } =20 static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 45409f84ef0..7b5c7a4abc7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1074,7 +1074,6 @@ struct ArchCPU { uint32_t dbgdidr; uint32_t dbgdevid; uint32_t dbgdevid1; - uint64_t id_aa64isar0; uint64_t id_aa64isar1; uint64_t id_aa64isar2; uint64_t id_aa64pfr0; @@ -1085,7 +1084,6 @@ struct ArchCPU { uint64_t id_aa64mmfr3; uint64_t id_aa64dfr0; uint64_t id_aa64dfr1; - uint64_t id_aa64zfr0; uint64_t id_aa64smfr0; uint64_t reset_pmcr_el0; uint64_t idregs[NUM_ID_IDX]; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index e025e241eda..f033411b5da 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1962,6 +1962,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) { CPUState *cs =3D CPU(dev); ARMCPU *cpu =3D ARM_CPU(dev); + ARMISARegisters *isar =3D &cpu->isar; ARMCPUClass *acc =3D ARM_CPU_GET_CLASS(dev); CPUARMState *env =3D &cpu->env; Error *local_err =3D NULL; @@ -2167,7 +2168,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) =20 unset_feature(env, ARM_FEATURE_NEON); =20 - t =3D cpu->isar.id_aa64isar0; + t =3D GET_IDREG(isar, ID_AA64ISAR0); t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 0); t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0); t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0); @@ -2175,7 +2176,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) t =3D FIELD_DP64(t, ID_AA64ISAR0, SM3, 0); t =3D FIELD_DP64(t, ID_AA64ISAR0, SM4, 0); t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 0); - cpu->isar.id_aa64isar0 =3D t; + SET_IDREG(isar, ID_AA64ISAR0, t); =20 t =3D cpu->isar.id_aa64isar1; t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); @@ -2220,9 +2221,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) uint64_t t; uint32_t u; =20 - t =3D cpu->isar.id_aa64isar0; - t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); - cpu->isar.id_aa64isar0 =3D t; + FIELD_DP64_IDREG(isar, ID_AA64ISAR0, FHM, 0); =20 t =3D cpu->isar.id_aa64isar1; t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 77054e0ec38..c105fcc4ea5 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -136,7 +136,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) * SVE is disabled and so are all vector lengths. Good. * Disable all SVE extensions as well. */ - cpu->isar.id_aa64zfr0 =3D 0; + SET_IDREG(&cpu->isar, ID_AA64ZFR0, 0); return; } =20 @@ -639,6 +639,7 @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) static void aarch64_a57_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,cortex-a57"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -676,7 +677,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->isar.id_isar6 =3D 0; cpu->isar.id_aa64pfr0 =3D 0x00002222; cpu->isar.id_aa64dfr0 =3D 0x10305106; - cpu->isar.id_aa64isar0 =3D 0x00011120; + SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); cpu->isar.id_aa64mmfr0 =3D 0x00001124; cpu->isar.dbgdidr =3D 0x3516d000; cpu->isar.dbgdevid =3D 0x01110f13; @@ -700,6 +701,7 @@ static void aarch64_a57_initfn(Object *obj) static void aarch64_a53_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,cortex-a53"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -737,7 +739,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->isar.id_isar6 =3D 0; cpu->isar.id_aa64pfr0 =3D 0x00002222; cpu->isar.id_aa64dfr0 =3D 0x10305106; - cpu->isar.id_aa64isar0 =3D 0x00011120; + SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); cpu->isar.id_aa64mmfr0 =3D 0x00001122; /* 40 bit physical addr */ cpu->isar.dbgdidr =3D 0x3516d000; cpu->isar.dbgdevid =3D 0x00110f13; diff --git a/target/arm/helper.c b/target/arm/helper.c index 889d3088079..638550e45ac 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7750,6 +7750,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ CPUARMState *env =3D &cpu->env; + ARMISARegisters *isar =3D &cpu->isar; + if (arm_feature(env, ARM_FEATURE_M)) { /* M profile has no coprocessor registers */ return; @@ -7941,7 +7943,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64zfr0 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64ZFR0)}, { .name =3D "ID_AA64SMFR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, @@ -8001,7 +8003,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64isar0 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64ISAR0)}, { .name =3D "ID_AA64ISAR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 42258cc2d88..5d25260c5c3 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -19,6 +19,7 @@ #include "system/hw_accel.h" #include "hvf_arm.h" #include "cpregs.h" +#include "cpu-sysregs.h" =20 #include =20 @@ -866,7 +867,7 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.id_aa64pfr1 }, { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.id_aa64dfr0 }, { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 }, - { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.id_aa64isar0 }, + { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.idregs[ID_AA64ISAR0_EL1_= IDX] }, { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.id_aa64isar1 }, /* Add ID_AA64ISAR2_EL1 here when HVF supports it */ { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 }, diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 74fda8b8090..bd33b0f656e 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -26,6 +26,7 @@ #include "system/kvm_int.h" #include "kvm_arm.h" #include "cpu.h" +#include "cpu-sysregs.h" #include "trace.h" #include "internals.h" #include "hw/pci/pci.h" @@ -218,6 +219,28 @@ static bool kvm_arm_pauth_supported(void) kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_GENERIC)); } =20 + +static uint64_t idregs_sysreg_to_kvm_reg(ARMSysRegs sysreg) +{ + return ARM64_SYS_REG((sysreg & CP_REG_ARM64_SYSREG_OP0_MASK) >> CP_REG= _ARM64_SYSREG_OP0_SHIFT, + (sysreg & CP_REG_ARM64_SYSREG_OP1_MASK) >> CP_REG= _ARM64_SYSREG_OP1_SHIFT, + (sysreg & CP_REG_ARM64_SYSREG_CRN_MASK) >> CP_REG= _ARM64_SYSREG_CRN_SHIFT, + (sysreg & CP_REG_ARM64_SYSREG_CRM_MASK) >> CP_REG= _ARM64_SYSREG_CRM_SHIFT, + (sysreg & CP_REG_ARM64_SYSREG_OP2_MASK) >> CP_REG= _ARM64_SYSREG_OP2_SHIFT); +} + +/* read a sysreg value and store it in the idregs */ +static int get_host_cpu_reg(int fd, ARMHostCPUFeatures *ahcf, ARMIDRegiste= rIdx index) +{ + uint64_t *reg; + int ret; + + reg =3D &ahcf->isar.idregs[index]; + ret =3D read_sys_reg64(fd, reg, + idregs_sysreg_to_kvm_reg(id_register_sysreg[index= ])); + return ret; +} + static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) { /* Identify the feature bits corresponding to the host CPU, and @@ -267,6 +290,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) =20 ahcf->target =3D init.target; ahcf->dtb_compatible =3D "arm,arm-v8"; + int fd =3D fdarray[2]; =20 err =3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0, ARM64_SYS_REG(3, 0, 0, 4, 0)); @@ -298,8 +322,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) ARM64_SYS_REG(3, 0, 0, 5, 0)); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1, ARM64_SYS_REG(3, 0, 0, 5, 1)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0, - ARM64_SYS_REG(3, 0, 0, 6, 0)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64ISAR0_EL1_IDX); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1, ARM64_SYS_REG(3, 0, 0, 6, 1)); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar2, @@ -408,8 +431,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) * enabled SVE support, which resulted in an error rather than= RAZ. * So only read the register if we set KVM_ARM_VCPU_SVE above. */ - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, - ARM64_SYS_REG(3, 0, 0, 4, 4)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64ZFR0_EL1_IDX); } } =20 diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 5d8ed2794d3..ed681ee08b0 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -32,6 +32,7 @@ static void aarch64_a35_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,cortex-a35"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -66,7 +67,7 @@ static void aarch64_a35_initfn(Object *obj) cpu->isar.id_aa64pfr1 =3D 0; cpu->isar.id_aa64dfr0 =3D 0x10305106; cpu->isar.id_aa64dfr1 =3D 0; - cpu->isar.id_aa64isar0 =3D 0x00011120; + SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); cpu->isar.id_aa64isar1 =3D 0; cpu->isar.id_aa64mmfr0 =3D 0x00101122; cpu->isar.id_aa64mmfr1 =3D 0; @@ -204,6 +205,7 @@ static const Property arm_cpu_lpa2_property =3D static void aarch64_a55_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,cortex-a55"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -221,7 +223,7 @@ static void aarch64_a55_initfn(Object *obj) cpu->ctr =3D 0x84448004; /* L1Ip =3D VIPT */ cpu->dcz_blocksize =3D 4; /* 64 bytes */ cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; - cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; + SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; @@ -276,6 +278,7 @@ static void aarch64_a55_initfn(Object *obj) static void aarch64_a72_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,cortex-a72"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -311,7 +314,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->isar.id_isar5 =3D 0x00011121; cpu->isar.id_aa64pfr0 =3D 0x00002222; cpu->isar.id_aa64dfr0 =3D 0x10305106; - cpu->isar.id_aa64isar0 =3D 0x00011120; + SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); cpu->isar.id_aa64mmfr0 =3D 0x00001124; cpu->isar.dbgdidr =3D 0x3516d000; cpu->isar.dbgdevid =3D 0x01110f13; @@ -335,6 +338,7 @@ static void aarch64_a72_initfn(Object *obj) static void aarch64_a76_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,cortex-a76"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -352,7 +356,7 @@ static void aarch64_a76_initfn(Object *obj) cpu->ctr =3D 0x8444C004; cpu->dcz_blocksize =3D 4; cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; - cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; + SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; @@ -408,6 +412,7 @@ static void aarch64_a76_initfn(Object *obj) static void aarch64_a64fx_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,a64fx"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -431,9 +436,9 @@ static void aarch64_a64fx_initfn(Object *obj) cpu->isar.id_aa64mmfr0 =3D 0x0000000000001122; cpu->isar.id_aa64mmfr1 =3D 0x0000000011212100; cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011; - cpu->isar.id_aa64isar0 =3D 0x0000000010211120; + SET_IDREG(isar, ID_AA64ISAR0, 0x0000000010211120); cpu->isar.id_aa64isar1 =3D 0x0000000000010001; - cpu->isar.id_aa64zfr0 =3D 0x0000000000000000; + SET_IDREG(isar, ID_AA64ZFR0, 0x0000000000000000); cpu->clidr =3D 0x0000000080000023; /* 64KB L1 dcache */ cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 256, 64 * KiB,= 7); @@ -581,6 +586,7 @@ static void define_neoverse_v1_cp_reginfo(ARMCPU *cpu) static void aarch64_neoverse_n1_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,neoverse-n1"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -598,7 +604,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj) cpu->ctr =3D 0x8444c004; cpu->dcz_blocksize =3D 4; cpu->isar.id_aa64dfr0 =3D 0x0000000110305408ull; - cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; + SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; @@ -656,6 +662,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj) static void aarch64_neoverse_v1_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,neoverse-v1"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -676,7 +683,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj) cpu->id_aa64afr1 =3D 0x00000000; cpu->isar.id_aa64dfr0 =3D 0x000001f210305519ull; cpu->isar.id_aa64dfr1 =3D 0x00000000; - cpu->isar.id_aa64isar0 =3D 0x1011111110212120ull; /* with FEAT_RNG */ + SET_IDREG(isar, ID_AA64ISAR0, 0x1011111110212120ull); /* with FEAT_RNG= */ cpu->isar.id_aa64isar1 =3D 0x0011100001211032ull; cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; @@ -735,7 +742,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000043; =20 /* From 3.7.5 ID_AA64ZFR0_EL1 */ - cpu->isar.id_aa64zfr0 =3D 0x0000100000100000; + SET_IDREG(isar, ID_AA64ZFR0, 0x0000100000100000); cpu->sve_vq.supported =3D (1 << 0) /* 128bit */ | (1 << 1); /* 256bit */ =20 @@ -882,6 +889,7 @@ static const ARMCPRegInfo cortex_a710_cp_reginfo[] =3D { static void aarch64_a710_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,cortex-a710"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -919,12 +927,12 @@ static void aarch64_a710_initfn(Object *obj) cpu->isar.id_pfr2 =3D 0x00000011; cpu->isar.id_aa64pfr0 =3D 0x1201111120111112ull; /* GIC filled in lat= er */ cpu->isar.id_aa64pfr1 =3D 0x0000000000000221ull; - cpu->isar.id_aa64zfr0 =3D 0x0000110100110021ull; /* with Crypto */ + SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */ cpu->isar.id_aa64dfr0 =3D 0x000011f010305619ull; cpu->isar.id_aa64dfr1 =3D 0; cpu->id_aa64afr0 =3D 0; cpu->id_aa64afr1 =3D 0; - cpu->isar.id_aa64isar0 =3D 0x0221111110212120ull; /* with Crypto */ + SET_IDREG(isar, ID_AA64ISAR0, 0x0221111110212120ull); /* with Crypto */ cpu->isar.id_aa64isar1 =3D 0x0010111101211052ull; cpu->isar.id_aa64mmfr0 =3D 0x0000022200101122ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; @@ -983,6 +991,7 @@ static const ARMCPRegInfo neoverse_n2_cp_reginfo[] =3D { static void aarch64_neoverse_n2_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,neoverse-n2"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -1020,12 +1029,12 @@ static void aarch64_neoverse_n2_initfn(Object *obj) cpu->isar.id_pfr2 =3D 0x00000011; cpu->isar.id_aa64pfr0 =3D 0x1201111120111112ull; /* GIC filled in lat= er */ cpu->isar.id_aa64pfr1 =3D 0x0000000000000221ull; - cpu->isar.id_aa64zfr0 =3D 0x0000110100110021ull; /* with Crypto */ + SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */ cpu->isar.id_aa64dfr0 =3D 0x000011f210305619ull; cpu->isar.id_aa64dfr1 =3D 0; cpu->id_aa64afr0 =3D 0; cpu->id_aa64afr1 =3D 0; - cpu->isar.id_aa64isar0 =3D 0x1221111110212120ull; /* with Crypto and F= EAT_RNG */ + SET_IDREG(isar, ID_AA64ISAR0, 0x1221111110212120ull); /* with Crypto a= nd FEAT_RNG */ cpu->isar.id_aa64isar1 =3D 0x0011111101211052ull; cpu->isar.id_aa64mmfr0 =3D 0x0000022200101125ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; @@ -1083,6 +1092,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj) void aarch64_max_tcg_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; uint64_t t; uint32_t u; =20 @@ -1133,7 +1143,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, CTR_EL0, DIC, 1); cpu->ctr =3D t; =20 - t =3D cpu->isar.id_aa64isar0; + t =3D GET_IDREG(isar, ID_AA64ISAR0); t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */ @@ -1148,7 +1158,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */ t =3D FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ t =3D FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */ - cpu->isar.id_aa64isar0 =3D t; + SET_IDREG(isar, ID_AA64ISAR0, t); =20 t =3D cpu->isar.id_aa64isar1; t =3D FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */ @@ -1244,7 +1254,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */ cpu->isar.id_aa64mmfr3 =3D t; =20 - t =3D cpu->isar.id_aa64zfr0; + t =3D GET_IDREG(isar, ID_AA64ZFR0); t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */ t =3D FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */ @@ -1254,7 +1264,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); 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Tue, 01 Jul 2025 10:07:27 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/43] arm/cpu: Store aa64isar1/2 into the idregs array Date: Tue, 1 Jul 2025 18:06:41 +0100 Message-ID: <20250701170720.4072660-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751390157259116600 Content-Type: text/plain; charset="utf-8" From: Eric Auger Reviewed-by: Richard Henderson Reviewed-by: Sebastian Ott Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck Message-id: 20250617153931.1330449-4-cohuck@redhat.com Signed-off-by: Peter Maydell --- target/arm/cpu-features.h | 44 +++++++++++++++++++-------------------- target/arm/cpu.h | 2 -- target/arm/cpu.c | 13 ++++-------- target/arm/cpu64.c | 9 ++++---- target/arm/helper.c | 4 ++-- target/arm/hvf/hvf.c | 2 +- target/arm/kvm.c | 6 ++---- target/arm/tcg/cpu64.c | 24 ++++++++++----------- 8 files changed, 48 insertions(+), 56 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 6a47f1a6d22..43c9695be0d 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -468,17 +468,17 @@ static inline bool isar_feature_aa64_tlbios(const ARM= ISARegisters *id) =20 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, JSCVT) !=3D 0; } =20 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, FCMA) !=3D 0; } =20 static inline bool isar_feature_aa64_xs(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, XS) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, XS) !=3D 0; } =20 /* @@ -502,9 +502,9 @@ isar_feature_pauth_feature(const ARMISARegisters *id) * Architecturally, only one of {APA,API,APA3} may be active (non-zero) * and the other two must be zero. Thus we may avoid conditionals. */ - return (FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) | - FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, API) | - FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3)); + return (FIELD_EX64_IDREG(id, ID_AA64ISAR1, APA) | + FIELD_EX64_IDREG(id, ID_AA64ISAR1, API) | + FIELD_EX64_IDREG(id, ID_AA64ISAR2, APA3)); } =20 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) @@ -522,7 +522,7 @@ static inline bool isar_feature_aa64_pauth_qarma5(const= ARMISARegisters *id) * Return true if pauth is enabled with the architected QARMA5 algorit= hm. * QEMU will always enable or disable both APA and GPA. */ - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, APA) !=3D 0; } =20 static inline bool isar_feature_aa64_pauth_qarma3(const ARMISARegisters *i= d) @@ -531,77 +531,77 @@ static inline bool isar_feature_aa64_pauth_qarma3(con= st ARMISARegisters *id) * Return true if pauth is enabled with the architected QARMA3 algorit= hm. * QEMU will always enable or disable both APA3 and GPA3. */ - return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR2, APA3) !=3D 0; } =20 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, SB) !=3D 0; } =20 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, SPECRES) !=3D 0; } =20 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, FRINTTS) !=3D 0; } =20 static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, DPB) !=3D 0; } =20 static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, DPB) >=3D 2; } =20 static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, BF16) !=3D 0; } =20 static inline bool isar_feature_aa64_ebf16(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) > 1; + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, BF16) > 1; } =20 static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, LRCPC) !=3D 0; } =20 static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, LRCPC) >=3D 2; } =20 static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, I8MM) !=3D 0; } =20 static inline bool isar_feature_aa64_wfxt(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, WFXT) >=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64ISAR2, WFXT) >=3D 2; } =20 static inline bool isar_feature_aa64_hbc(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, BC) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR2, BC) !=3D 0; } =20 static inline bool isar_feature_aa64_mops(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, MOPS); + return FIELD_EX64_IDREG(id, ID_AA64ISAR2, MOPS); } =20 static inline bool isar_feature_aa64_rpres(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, RPRES); + return FIELD_EX64_IDREG(id, ID_AA64ISAR2, RPRES); } =20 static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7b5c7a4abc7..b81bc46966f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1074,8 +1074,6 @@ struct ArchCPU { uint32_t dbgdidr; uint32_t dbgdevid; uint32_t dbgdevid1; - uint64_t id_aa64isar1; - uint64_t id_aa64isar2; uint64_t id_aa64pfr0; uint64_t id_aa64pfr1; uint64_t id_aa64mmfr0; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f033411b5da..2777de72944 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2123,9 +2123,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) uint64_t t; uint32_t u; =20 - t =3D cpu->isar.id_aa64isar1; - t =3D FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); - cpu->isar.id_aa64isar1 =3D t; + FIELD_DP64_IDREG(isar, ID_AA64ISAR1, JSCVT, 0); =20 t =3D cpu->isar.id_aa64pfr0; t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); @@ -2178,11 +2176,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 0); SET_IDREG(isar, ID_AA64ISAR0, t); =20 - t =3D cpu->isar.id_aa64isar1; + t =3D GET_IDREG(isar, ID_AA64ISAR1); t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); t =3D FIELD_DP64(t, ID_AA64ISAR1, BF16, 0); t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); - cpu->isar.id_aa64isar1 =3D t; + SET_IDREG(isar, ID_AA64ISAR1, t); =20 t =3D cpu->isar.id_aa64pfr0; t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); @@ -2218,14 +2216,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) } =20 if (!cpu->has_neon && !cpu->has_vfp) { - uint64_t t; uint32_t u; =20 FIELD_DP64_IDREG(isar, ID_AA64ISAR0, FHM, 0); =20 - t =3D cpu->isar.id_aa64isar1; - t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); - cpu->isar.id_aa64isar1 =3D t; + FIELD_DP64_IDREG(isar, ID_AA64ISAR1, FRINTTS, 0); =20 u =3D cpu->isar.mvfr0; u =3D FIELD_DP32(u, MVFR0, SIMDREG, 0); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index c105fcc4ea5..e2b25b00431 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -502,6 +502,7 @@ void aarch64_add_sme_properties(Object *obj) void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { ARMPauthFeature features =3D cpu_isar_feature(pauth_feature, cpu); + ARMISARegisters *isar =3D &cpu->isar; uint64_t isar1, isar2; =20 /* @@ -512,13 +513,13 @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) * * Begin by disabling all fields. */ - isar1 =3D cpu->isar.id_aa64isar1; + isar1 =3D GET_IDREG(isar, ID_AA64ISAR1); isar1 =3D FIELD_DP64(isar1, ID_AA64ISAR1, APA, 0); isar1 =3D FIELD_DP64(isar1, ID_AA64ISAR1, GPA, 0); isar1 =3D FIELD_DP64(isar1, ID_AA64ISAR1, API, 0); isar1 =3D FIELD_DP64(isar1, ID_AA64ISAR1, GPI, 0); =20 - isar2 =3D cpu->isar.id_aa64isar2; + isar2 =3D GET_IDREG(isar, ID_AA64ISAR2); isar2 =3D FIELD_DP64(isar2, ID_AA64ISAR2, APA3, 0); isar2 =3D FIELD_DP64(isar2, ID_AA64ISAR2, GPA3, 0); =20 @@ -580,8 +581,8 @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) } } =20 - cpu->isar.id_aa64isar1 =3D isar1; - cpu->isar.id_aa64isar2 =3D isar2; + SET_IDREG(isar, ID_AA64ISAR1, isar1); + SET_IDREG(isar, ID_AA64ISAR2, isar2); } =20 static const Property arm_cpu_pauth_property =3D diff --git a/target/arm/helper.c b/target/arm/helper.c index 638550e45ac..fd2a86b6b0e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8008,12 +8008,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64isar1 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64ISAR1)}, { .name =3D "ID_AA64ISAR2_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64isar2 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64ISAR2)}, { .name =3D "ID_AA64ISAR3_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 3, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 5d25260c5c3..7554282410f 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -868,7 +868,7 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.id_aa64dfr0 }, { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 }, { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.idregs[ID_AA64ISAR0_EL1_= IDX] }, - { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.id_aa64isar1 }, + { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.idregs[ID_AA64ISAR1_EL1_= IDX] }, /* Add ID_AA64ISAR2_EL1 here when HVF supports it */ { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 }, { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 }, diff --git a/target/arm/kvm.c b/target/arm/kvm.c index bd33b0f656e..6fa5bdff42a 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -323,10 +323,8 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFe= atures *ahcf) err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1, ARM64_SYS_REG(3, 0, 0, 5, 1)); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64ISAR0_EL1_IDX); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1, - ARM64_SYS_REG(3, 0, 0, 6, 1)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar2, - ARM64_SYS_REG(3, 0, 0, 6, 2)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64ISAR1_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64ISAR2_EL1_IDX); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr0, ARM64_SYS_REG(3, 0, 0, 7, 0)); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1, diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index ed681ee08b0..91750264724 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -68,7 +68,7 @@ static void aarch64_a35_initfn(Object *obj) cpu->isar.id_aa64dfr0 =3D 0x10305106; cpu->isar.id_aa64dfr1 =3D 0; SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); - cpu->isar.id_aa64isar1 =3D 0; + SET_IDREG(isar, ID_AA64ISAR1, 0); cpu->isar.id_aa64mmfr0 =3D 0x00101122; cpu->isar.id_aa64mmfr1 =3D 0; cpu->clidr =3D 0x0a200023; @@ -224,7 +224,7 @@ static void aarch64_a55_initfn(Object *obj) cpu->dcz_blocksize =3D 4; /* 64 bytes */ cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); - cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; + SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull); cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; @@ -357,7 +357,7 @@ static void aarch64_a76_initfn(Object *obj) cpu->dcz_blocksize =3D 4; cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); - cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; + SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull); cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; @@ -437,7 +437,7 @@ static void aarch64_a64fx_initfn(Object *obj) cpu->isar.id_aa64mmfr1 =3D 0x0000000011212100; cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011; SET_IDREG(isar, ID_AA64ISAR0, 0x0000000010211120); - cpu->isar.id_aa64isar1 =3D 0x0000000000010001; + SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000010001); SET_IDREG(isar, ID_AA64ZFR0, 0x0000000000000000); cpu->clidr =3D 0x0000000080000023; /* 64KB L1 dcache */ @@ -605,7 +605,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj) cpu->dcz_blocksize =3D 4; cpu->isar.id_aa64dfr0 =3D 0x0000000110305408ull; SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); - cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; + SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull); cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; @@ -684,7 +684,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj) cpu->isar.id_aa64dfr0 =3D 0x000001f210305519ull; cpu->isar.id_aa64dfr1 =3D 0x00000000; SET_IDREG(isar, ID_AA64ISAR0, 0x1011111110212120ull); /* with FEAT_RNG= */ - cpu->isar.id_aa64isar1 =3D 0x0011100001211032ull; + SET_IDREG(isar, ID_AA64ISAR1, 0x0011000001211032ull); cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; cpu->isar.id_aa64mmfr2 =3D 0x0220011102101011ull; @@ -933,7 +933,7 @@ static void aarch64_a710_initfn(Object *obj) cpu->id_aa64afr0 =3D 0; cpu->id_aa64afr1 =3D 0; SET_IDREG(isar, ID_AA64ISAR0, 0x0221111110212120ull); /* with Crypto */ - cpu->isar.id_aa64isar1 =3D 0x0010111101211052ull; + SET_IDREG(isar, ID_AA64ISAR1, 0x0010111101211052ull); cpu->isar.id_aa64mmfr0 =3D 0x0000022200101122ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; cpu->isar.id_aa64mmfr2 =3D 0x1221011110101011ull; @@ -1035,7 +1035,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj) cpu->id_aa64afr0 =3D 0; cpu->id_aa64afr1 =3D 0; SET_IDREG(isar, ID_AA64ISAR0, 0x1221111110212120ull); /* with Crypto a= nd FEAT_RNG */ - cpu->isar.id_aa64isar1 =3D 0x0011111101211052ull; + SET_IDREG(isar, ID_AA64ISAR1, 0x0011111101211052ull); cpu->isar.id_aa64mmfr0 =3D 0x0000022200101125ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; cpu->isar.id_aa64mmfr2 =3D 0x1221011112101011ull; @@ -1160,7 +1160,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */ SET_IDREG(isar, ID_AA64ISAR0, t); =20 - t =3D cpu->isar.id_aa64isar1; + t =3D GET_IDREG(isar, ID_AA64ISAR1); t =3D FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */ t =3D FIELD_DP64(t, ID_AA64ISAR1, APA, PauthFeat_FPACCOMBINED); t =3D FIELD_DP64(t, ID_AA64ISAR1, API, 1); @@ -1174,14 +1174,14 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */ t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ t =3D FIELD_DP64(t, ID_AA64ISAR1, XS, 1); /* FEAT_XS */ - cpu->isar.id_aa64isar1 =3D t; + SET_IDREG(isar, ID_AA64ISAR1, t); =20 - t =3D cpu->isar.id_aa64isar2; + t =3D GET_IDREG(isar, ID_AA64ISAR2); t =3D FIELD_DP64(t, ID_AA64ISAR2, RPRES, 1); /* FEAT_RPRES */ t =3D FIELD_DP64(t, ID_AA64ISAR2, MOPS, 1); /* FEAT_MOPS */ t =3D FIELD_DP64(t, ID_AA64ISAR2, BC, 1); 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Tue, 01 Jul 2025 10:07:28 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/43] arm/cpu: Store aa64pfr0/1 into the idregs array Date: Tue, 1 Jul 2025 18:06:42 +0100 Message-ID: <20250701170720.4072660-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751390235611116600 Content-Type: text/plain; charset="utf-8" From: Eric Auger Reviewed-by: Richard Henderson Reviewed-by: Sebastian Ott Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck Message-id: 20250617153931.1330449-5-cohuck@redhat.com Signed-off-by: Peter Maydell --- target/arm/cpu-features.h | 40 ++++++++++++++++----------------- target/arm/cpu.h | 2 -- target/arm/cpu.c | 29 ++++++++---------------- target/arm/cpu64.c | 14 ++++-------- target/arm/helper.c | 6 ++--- target/arm/hvf/hvf.c | 9 ++++---- target/arm/kvm.c | 12 +++++----- target/arm/tcg/cpu64.c | 47 ++++++++++++++++++--------------------- 8 files changed, 68 insertions(+), 91 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 43c9695be0d..3adea85b79b 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -607,68 +607,68 @@ static inline bool isar_feature_aa64_rpres(const ARMI= SARegisters *id) static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) { /* We always set the AdvSIMD and FP fields identically. */ - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) !=3D 0xf; + return FIELD_EX64_IDREG(id, ID_AA64PFR0, FP) !=3D 0xf; } =20 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) { /* We always set the AdvSIMD and FP fields identically wrt FP16. */ - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) =3D=3D 1; + return FIELD_EX64_IDREG(id, ID_AA64PFR0, FP) =3D=3D 1; } =20 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64PFR0, EL0) >=3D 2; } =20 static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64PFR0, EL1) >=3D 2; } =20 static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL2) >=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64PFR0, EL2) >=3D 2; } =20 static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64PFR0, RAS) !=3D 0; } =20 static inline bool isar_feature_aa64_doublefault(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) >=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64PFR0, RAS) >=3D 2; } =20 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64PFR0, SVE) !=3D 0; } =20 static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64PFR0, SEL2) !=3D 0; } =20 static inline bool isar_feature_aa64_rme(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RME) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64PFR0, RME) !=3D 0; } =20 static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64PFR0, DIT) !=3D 0; } =20 static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id) { - int key =3D FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2); + int key =3D FIELD_EX64_IDREG(id, ID_AA64PFR0, CSV2); if (key >=3D 2) { return true; /* FEAT_CSV2_2 */ } if (key =3D=3D 1) { - key =3D FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC); + key =3D FIELD_EX64_IDREG(id, ID_AA64PFR1, CSV2_FRAC); return key >=3D 2; /* FEAT_CSV2_1p2 */ } return false; @@ -676,37 +676,37 @@ static inline bool isar_feature_aa64_scxtnum(const AR= MISARegisters *id) =20 static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64PFR1, SSBS) !=3D 0; } =20 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64PFR1, BT) !=3D 0; } =20 static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *i= d) { - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64PFR1, MTE) !=3D 0; } =20 static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64PFR1, MTE) >=3D 2; } =20 static inline bool isar_feature_aa64_mte3(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >=3D 3; + return FIELD_EX64_IDREG(id, ID_AA64PFR1, MTE) >=3D 3; } =20 static inline bool isar_feature_aa64_sme(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64PFR1, SME) !=3D 0; } =20 static inline bool isar_feature_aa64_nmi(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, NMI) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64PFR1, NMI) !=3D 0; } =20 static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b81bc46966f..05157a49d75 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1074,8 +1074,6 @@ struct ArchCPU { uint32_t dbgdidr; uint32_t dbgdevid; uint32_t dbgdevid1; - uint64_t id_aa64pfr0; - uint64_t id_aa64pfr1; uint64_t id_aa64mmfr0; uint64_t id_aa64mmfr1; uint64_t id_aa64mmfr2; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2777de72944..d39e8dc9560 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2120,14 +2120,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) } =20 if (!cpu->has_vfp) { - uint64_t t; uint32_t u; =20 FIELD_DP64_IDREG(isar, ID_AA64ISAR1, JSCVT, 0); =20 - t =3D cpu->isar.id_aa64pfr0; - t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); - cpu->isar.id_aa64pfr0 =3D t; + FIELD_DP64_IDREG(isar, ID_AA64PFR0, FP, 0xf); =20 u =3D cpu->isar.id_isar6; u =3D FIELD_DP32(u, ID_ISAR6, JSCVT, 0); @@ -2182,9 +2179,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); SET_IDREG(isar, ID_AA64ISAR1, t); =20 - t =3D cpu->isar.id_aa64pfr0; - t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); - cpu->isar.id_aa64pfr0 =3D t; + FIELD_DP64_IDREG(isar, ID_AA64PFR0, ADVSIMD, 0xf); =20 u =3D cpu->isar.id_isar5; u =3D FIELD_DP32(u, ID_ISAR5, AES, 0); @@ -2326,12 +2321,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) */ cpu->isar.id_pfr1 =3D FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECUR= ITY, 0); cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSD= BG, 0); - cpu->isar.id_aa64pfr0 =3D FIELD_DP64(cpu->isar.id_aa64pfr0, - ID_AA64PFR0, EL3, 0); + FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL3, 0); =20 /* Disable the realm management extension, which requires EL3. */ - cpu->isar.id_aa64pfr0 =3D FIELD_DP64(cpu->isar.id_aa64pfr0, - ID_AA64PFR0, RME, 0); + FIELD_DP64_IDREG(isar, ID_AA64PFR0, RME, 0); } =20 if (!cpu->has_el2) { @@ -2366,8 +2359,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * Disable the hypervisor feature bits in the processor feature * registers if we don't have EL2. */ - cpu->isar.id_aa64pfr0 =3D FIELD_DP64(cpu->isar.id_aa64pfr0, - ID_AA64PFR0, EL2, 0); + FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL2, 0); cpu->isar.id_pfr1 =3D FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, VIRTUALIZATION, 0); } @@ -2388,8 +2380,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * This matches Cortex-A710 BROADCASTMTE input being LOW. */ if (tcg_enabled() && cpu->tag_memory =3D=3D NULL) { - cpu->isar.id_aa64pfr1 =3D - FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1); + FIELD_DP64_IDREG(isar, ID_AA64PFR1, MTE, 1); } =20 /* @@ -2397,7 +2388,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * enabled on the guest (i.e mte=3Doff), clear guest's MTE bits." */ if (kvm_enabled() && !cpu->kvm_mte) { - FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); + FIELD_DP64_IDREG(isar, ID_AA64PFR1, MTE, 0); } #endif } @@ -2436,13 +2427,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0); /* FEAT_AMU (Activity Monitors Extension) */ - cpu->isar.id_aa64pfr0 =3D - FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, AMU, 0); + FIELD_DP64_IDREG(isar, ID_AA64PFR0, AMU, 0); cpu->isar.id_pfr0 =3D FIELD_DP32(cpu->isar.id_pfr0, ID_PFR0, AMU, 0); /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */ - cpu->isar.id_aa64pfr0 =3D - FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, MPAM, 0); + FIELD_DP64_IDREG(isar, ID_AA64PFR0, MPAM, 0); } =20 /* MPU can be configured out of a PMSA CPU either by setting has-mpu diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index e2b25b00431..502aac91730 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -310,16 +310,13 @@ static bool cpu_arm_get_sve(Object *obj, Error **errp) static void cpu_arm_set_sve(Object *obj, bool value, Error **errp) { ARMCPU *cpu =3D ARM_CPU(obj); - uint64_t t; =20 if (value && kvm_enabled() && !kvm_arm_sve_supported()) { error_setg(errp, "'sve' feature not supported by KVM on this host"= ); return; } =20 - t =3D cpu->isar.id_aa64pfr0; - t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, value); - cpu->isar.id_aa64pfr0 =3D t; + FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR0, SVE, value); } =20 void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp) @@ -370,11 +367,8 @@ static bool cpu_arm_get_sme(Object *obj, Error **errp) static void cpu_arm_set_sme(Object *obj, bool value, Error **errp) { ARMCPU *cpu =3D ARM_CPU(obj); - uint64_t t; =20 - t =3D cpu->isar.id_aa64pfr1; - t =3D FIELD_DP64(t, ID_AA64PFR1, SME, value); - cpu->isar.id_aa64pfr1 =3D t; + FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR1, SME, value); } =20 static bool cpu_arm_get_sme_fa64(Object *obj, Error **errp) @@ -676,7 +670,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->isar.id_isar4 =3D 0x00011142; cpu->isar.id_isar5 =3D 0x00011121; cpu->isar.id_isar6 =3D 0; - cpu->isar.id_aa64pfr0 =3D 0x00002222; + SET_IDREG(isar, ID_AA64PFR0, 0x00002222); cpu->isar.id_aa64dfr0 =3D 0x10305106; SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); cpu->isar.id_aa64mmfr0 =3D 0x00001124; @@ -738,7 +732,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->isar.id_isar4 =3D 0x00011142; cpu->isar.id_isar5 =3D 0x00011121; cpu->isar.id_isar6 =3D 0; - cpu->isar.id_aa64pfr0 =3D 0x00002222; + SET_IDREG(isar, ID_AA64PFR0, 0x00002222); cpu->isar.id_aa64dfr0 =3D 0x10305106; SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); cpu->isar.id_aa64mmfr0 =3D 0x00001122; /* 40 bit physical addr */ diff --git a/target/arm/helper.c b/target/arm/helper.c index fd2a86b6b0e..b221e8df6c0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6943,7 +6943,7 @@ static uint64_t id_pfr1_read(CPUARMState *env, const = ARMCPRegInfo *ri) static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) { ARMCPU *cpu =3D env_archcpu(env); - uint64_t pfr0 =3D cpu->isar.id_aa64pfr0; + uint64_t pfr0 =3D GET_IDREG(&cpu->isar, ID_AA64PFR0); =20 if (env->gicv3state) { pfr0 |=3D 1 << 24; @@ -7916,7 +7916,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, #ifdef CONFIG_USER_ONLY .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->isar.id_aa64pfr0 + .resetvalue =3D GET_IDREG(isar, ID_AA64PFR0) #else .type =3D ARM_CP_NO_RAW, .accessfn =3D access_aa64_tid3, @@ -7928,7 +7928,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64pfr1}, + .resetvalue =3D GET_IDREG(isar, ID_AA64PFR1)}, { .name =3D "ID_AA64PFR2_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 7554282410f..e1bfca5947c 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -863,8 +863,8 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) int reg; uint64_t *val; } regs[] =3D { - { HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.id_aa64pfr0 }, - { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.id_aa64pfr1 }, + { HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.idregs[ID_AA64PFR0_EL1_ID= X] }, + { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.idregs[ID_AA64PFR1_EL1_ID= X] }, { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.id_aa64dfr0 }, { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 }, { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.idregs[ID_AA64ISAR0_EL1_= IDX] }, @@ -911,7 +911,8 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) * - fix any assumptions we made that SME implies SVE (since * on the M4 there is SME but not SVE) */ - host_isar.id_aa64pfr1 &=3D ~R_ID_AA64PFR1_SME_MASK; + SET_IDREG(&host_isar, ID_AA64PFR1, + GET_IDREG(&host_isar, ID_AA64PFR1) & ~R_ID_AA64PFR1_SME_MASK= ); =20 ahcf->isar =3D host_isar; =20 @@ -928,7 +929,7 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) ahcf->reset_sctlr |=3D 0x00800000; =20 /* Make sure we don't advertise AArch32 support for EL0/EL1 */ - if ((host_isar.id_aa64pfr0 & 0xff) !=3D 0x11) { + if ((GET_IDREG(&host_isar, ID_AA64PFR0) & 0xff) !=3D 0x11) { return false; } =20 diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 6fa5bdff42a..1e19dba4cb0 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -292,8 +292,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) ahcf->dtb_compatible =3D "arm,arm-v8"; int fd =3D fdarray[2]; =20 - err =3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0, - ARM64_SYS_REG(3, 0, 0, 4, 0)); + err =3D get_host_cpu_reg(fd, ahcf, ID_AA64PFR0_EL1_IDX); if (unlikely(err < 0)) { /* * Before v4.15, the kernel only exposed a limited number of system @@ -311,11 +310,10 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUF= eatures *ahcf) * ??? Either of these sounds like too much effort just * to work around running a modern host kernel. */ - ahcf->isar.id_aa64pfr0 =3D 0x00000011; /* EL1&0, AArch64 only */ + SET_IDREG(&ahcf->isar, ID_AA64PFR0, 0x00000011); /* EL1&0, AArch64= only */ err =3D 0; } else { - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1, - ARM64_SYS_REG(3, 0, 0, 4, 1)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64PFR1_EL1_IDX); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0, ARM64_SYS_REG(3, 0, 0, 4, 5)); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr0, @@ -395,14 +393,14 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUF= eatures *ahcf) * arch/arm64/kvm/sys_regs.c:trap_dbgidr() does. * We only do this if the CPU supports AArch32 at EL1. */ - if (FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL1) >=3D 2) { + if (FIELD_EX32_IDREG(&ahcf->isar, ID_AA64PFR0, EL1) >=3D 2) { int wrps =3D FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, W= RPS); int brps =3D FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, B= RPS); int ctx_cmps =3D FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS); int version =3D 6; /* ARMv8 debug architecture */ bool has_el3 =3D - !!FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL3); + !!FIELD_EX32_IDREG(&ahcf->isar, ID_AA64PFR0, EL3); uint32_t dbgdidr =3D 0; =20 dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, WRPS, wrps); diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 91750264724..7a730c7974f 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -63,8 +63,8 @@ static void aarch64_a35_initfn(Object *obj) cpu->isar.id_isar3 =3D 0x01112131; cpu->isar.id_isar4 =3D 0x00011142; cpu->isar.id_isar5 =3D 0x00011121; - cpu->isar.id_aa64pfr0 =3D 0x00002222; - cpu->isar.id_aa64pfr1 =3D 0; + SET_IDREG(isar, ID_AA64PFR0, 0x00002222); + SET_IDREG(isar, ID_AA64PFR1, 0); cpu->isar.id_aa64dfr0 =3D 0x10305106; cpu->isar.id_aa64dfr1 =3D 0; SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); @@ -158,11 +158,8 @@ static bool cpu_arm_get_rme(Object *obj, Error **errp) static void cpu_arm_set_rme(Object *obj, bool value, Error **errp) { ARMCPU *cpu =3D ARM_CPU(obj); - uint64_t t; =20 - t =3D cpu->isar.id_aa64pfr0; - t =3D FIELD_DP64(t, ID_AA64PFR0, RME, value); - cpu->isar.id_aa64pfr0 =3D t; + FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR0, RME, value); } =20 static void cpu_max_set_l0gptsz(Object *obj, Visitor *v, const char *name, @@ -228,8 +225,8 @@ static void aarch64_a55_initfn(Object *obj) cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; - cpu->isar.id_aa64pfr0 =3D 0x0000000010112222ull; - cpu->isar.id_aa64pfr1 =3D 0x0000000000000010ull; + SET_IDREG(isar, ID_AA64PFR0, 0x0000000010112222ull); + SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_dfr0 =3D 0x04010088; cpu->isar.id_isar0 =3D 0x02101110; @@ -312,7 +309,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->isar.id_isar3 =3D 0x01112131; cpu->isar.id_isar4 =3D 0x00011142; cpu->isar.id_isar5 =3D 0x00011121; - cpu->isar.id_aa64pfr0 =3D 0x00002222; + SET_IDREG(isar, ID_AA64PFR0, 0x00002222); cpu->isar.id_aa64dfr0 =3D 0x10305106; SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); cpu->isar.id_aa64mmfr0 =3D 0x00001124; @@ -361,8 +358,8 @@ static void aarch64_a76_initfn(Object *obj) cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; - cpu->isar.id_aa64pfr0 =3D 0x1100000010111112ull; /* GIC filled in lat= er */ - cpu->isar.id_aa64pfr1 =3D 0x0000000000000010ull; + SET_IDREG(isar, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in = later */ + SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_dfr0 =3D 0x04010088; cpu->isar.id_isar0 =3D 0x02101110; @@ -427,8 +424,8 @@ static void aarch64_a64fx_initfn(Object *obj) cpu->revidr =3D 0x00000000; cpu->ctr =3D 0x86668006; cpu->reset_sctlr =3D 0x30000180; - cpu->isar.id_aa64pfr0 =3D 0x0000000101111111; /* No RAS Extensions */ - cpu->isar.id_aa64pfr1 =3D 0x0000000000000000; + SET_IDREG(isar, ID_AA64PFR0, 0x0000000101111111); /* No RAS Extensions= */ + SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000000); cpu->isar.id_aa64dfr0 =3D 0x0000000010305408; cpu->isar.id_aa64dfr1 =3D 0x0000000000000000; cpu->id_aa64afr0 =3D 0x0000000000000000; @@ -609,8 +606,8 @@ static void aarch64_neoverse_n1_initfn(Object *obj) cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; - cpu->isar.id_aa64pfr0 =3D 0x1100000010111112ull; /* GIC filled in lat= er */ - cpu->isar.id_aa64pfr1 =3D 0x0000000000000020ull; + SET_IDREG(isar, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in = later */ + SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_dfr0 =3D 0x04010088; cpu->isar.id_isar0 =3D 0x02101110; @@ -688,8 +685,8 @@ static void aarch64_neoverse_v1_initfn(Object *obj) cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; cpu->isar.id_aa64mmfr2 =3D 0x0220011102101011ull; - cpu->isar.id_aa64pfr0 =3D 0x1101110120111112ull; /* GIC filled in lat= er */ - cpu->isar.id_aa64pfr1 =3D 0x0000000000000020ull; + SET_IDREG(isar, ID_AA64PFR0, 0x1101110120111112ull); /* GIC filled in = later */ + SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_dfr0 =3D 0x15011099; cpu->isar.id_isar0 =3D 0x02101110; @@ -925,8 +922,8 @@ static void aarch64_a710_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x13211111; cpu->isar.mvfr2 =3D 0x00000043; cpu->isar.id_pfr2 =3D 0x00000011; - cpu->isar.id_aa64pfr0 =3D 0x1201111120111112ull; /* GIC filled in lat= er */ - cpu->isar.id_aa64pfr1 =3D 0x0000000000000221ull; + SET_IDREG(isar, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in = later */ + SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000221ull); SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */ cpu->isar.id_aa64dfr0 =3D 0x000011f010305619ull; cpu->isar.id_aa64dfr1 =3D 0; @@ -1027,8 +1024,8 @@ static void aarch64_neoverse_n2_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x13211111; cpu->isar.mvfr2 =3D 0x00000043; cpu->isar.id_pfr2 =3D 0x00000011; - cpu->isar.id_aa64pfr0 =3D 0x1201111120111112ull; /* GIC filled in lat= er */ - cpu->isar.id_aa64pfr1 =3D 0x0000000000000221ull; + SET_IDREG(isar, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in = later */ + SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000221ull); SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */ cpu->isar.id_aa64dfr0 =3D 0x000011f210305619ull; cpu->isar.id_aa64dfr1 =3D 0; @@ -1183,7 +1180,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR2, WFXT, 2); /* FEAT_WFxT */ SET_IDREG(isar, ID_AA64ISAR2, t); =20 - t =3D cpu->isar.id_aa64pfr0; + t =3D GET_IDREG(isar, ID_AA64PFR0); t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ t =3D FIELD_DP64(t, ID_AA64PFR0, RAS, 2); /* FEAT_RASv1p1 + FEAT= _DoubleFault */ @@ -1192,9 +1189,9 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ t =3D FIELD_DP64(t, ID_AA64PFR0, CSV2, 3); /* FEAT_CSV2_3 */ t =3D FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */ - cpu->isar.id_aa64pfr0 =3D t; + SET_IDREG(isar, ID_AA64PFR0, t); =20 - t =3D cpu->isar.id_aa64pfr1; + t =3D GET_IDREG(isar, ID_AA64PFR1); t =3D FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */ t =3D FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */ /* @@ -1207,7 +1204,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */ t =3D FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_3 */ t =3D FIELD_DP64(t, ID_AA64PFR1, NMI, 1); /* FEAT_NMI */ - cpu->isar.id_aa64pfr1 =3D t; + SET_IDREG(isar, ID_AA64PFR1, t); =20 t =3D cpu->isar.id_aa64mmfr0; t =3D FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */ --=20 2.43.0 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tue, 01 Jul 2025 10:07:29 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/43] arm/cpu: Store aa64mmfr0-3 into the idregs array Date: Tue, 1 Jul 2025 18:06:43 +0100 Message-ID: <20250701170720.4072660-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751389850318116600 Content-Type: text/plain; charset="utf-8" From: Eric Auger Reviewed-by: Richard Henderson Reviewed-by: Sebastian Ott Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck Message-id: 20250617153931.1330449-6-cohuck@redhat.com Signed-off-by: Peter Maydell --- target/arm/cpu-features.h | 74 +++++++++++++++++++-------------------- target/arm/cpu.h | 4 --- target/arm/cpu64.c | 8 ++--- target/arm/helper.c | 8 ++--- target/arm/hvf/hvf.c | 21 ++++++----- target/arm/kvm.c | 12 +++---- target/arm/ptw.c | 6 ++-- target/arm/tcg/cpu64.c | 64 ++++++++++++++++----------------- 8 files changed, 95 insertions(+), 102 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 3adea85b79b..89c9278639b 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -711,192 +711,192 @@ static inline bool isar_feature_aa64_nmi(const ARMI= SARegisters *id) =20 static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) { - return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >=3D 1; + return FIELD_SEX64_IDREG(id, ID_AA64MMFR0, TGRAN4) >=3D 1; } =20 static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *= id) { - unsigned t =3D FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); + unsigned t =3D FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN4_2); return t >=3D 3 || (t =3D=3D 0 && isar_feature_aa64_tgran4_lpa2(id)); } =20 static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *i= d) { - return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN16) >=3D 2; } =20 static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters = *id) { - unsigned t =3D FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); + unsigned t =3D FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN16_2); return t >=3D 3 || (t =3D=3D 0 && isar_feature_aa64_tgran16_lpa2(id)); } =20 static inline bool isar_feature_aa64_tgran4(const ARMISARegisters *id) { - return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >=3D 0; + return FIELD_SEX64_IDREG(id, ID_AA64MMFR0, TGRAN4) >=3D 0; } =20 static inline bool isar_feature_aa64_tgran16(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >=3D 1; + return FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN16) >=3D 1; } =20 static inline bool isar_feature_aa64_tgran64(const ARMISARegisters *id) { - return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64) >=3D 0; + return FIELD_SEX64_IDREG(id, ID_AA64MMFR0, TGRAN64) >=3D 0; } =20 static inline bool isar_feature_aa64_tgran4_2(const ARMISARegisters *id) { - unsigned t =3D FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); + unsigned t =3D FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN4_2); return t >=3D 2 || (t =3D=3D 0 && isar_feature_aa64_tgran4(id)); } =20 static inline bool isar_feature_aa64_tgran16_2(const ARMISARegisters *id) { - unsigned t =3D FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); + unsigned t =3D FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN16_2); return t >=3D 2 || (t =3D=3D 0 && isar_feature_aa64_tgran16(id)); } =20 static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id) { - unsigned t =3D FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64_2); + unsigned t =3D FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN64_2); return t >=3D 2 || (t =3D=3D 0 && isar_feature_aa64_tgran64(id)); } =20 static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR0, FGT) !=3D 0; } =20 static inline bool isar_feature_aa64_ecv_traps(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR0, ECV) > 0; } =20 static inline bool isar_feature_aa64_ecv(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 1; + return FIELD_EX64_IDREG(id, ID_AA64MMFR0, ECV) > 1; } =20 static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR1, VH) !=3D 0; } =20 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR1, LO) !=3D 0; } =20 static inline bool isar_feature_aa64_pan(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR1, PAN) !=3D 0; } =20 static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64MMFR1, PAN) >=3D 2; } =20 static inline bool isar_feature_aa64_pan3(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >=3D 3; + return FIELD_EX64_IDREG(id, ID_AA64MMFR1, PAN) >=3D 3; } =20 static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR1, HCX) !=3D 0; } =20 static inline bool isar_feature_aa64_afp(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, AFP) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR1, AFP) !=3D 0; } =20 static inline bool isar_feature_aa64_tidcp1(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, TIDCP1) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR1, TIDCP1) !=3D 0; } =20 static inline bool isar_feature_aa64_cmow(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, CMOW) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR1, CMOW) !=3D 0; } =20 static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR1, HAFDBS) !=3D 0; } =20 static inline bool isar_feature_aa64_hdbs(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) >=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64MMFR1, HAFDBS) >=3D 2; } =20 static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR1, XNX) !=3D 0; } =20 static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR2, UAO) !=3D 0; } =20 static inline bool isar_feature_aa64_st(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR2, ST) !=3D 0; } =20 static inline bool isar_feature_aa64_lse2(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, AT) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR2, AT) !=3D 0; } =20 static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, FWB) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR2, FWB) !=3D 0; } =20 static inline bool isar_feature_aa64_ids(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR2, IDS) !=3D 0; } =20 static inline bool isar_feature_aa64_half_evt(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >=3D 1; + return FIELD_EX64_IDREG(id, ID_AA64MMFR2, EVT) >=3D 1; } =20 static inline bool isar_feature_aa64_evt(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64MMFR2, EVT) >=3D 2; } =20 static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR2, CCIDX) !=3D 0; } =20 static inline bool isar_feature_aa64_lva(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR2, VARANGE) !=3D 0; } =20 static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, E0PD) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR2, E0PD) !=3D 0; } =20 static inline bool isar_feature_aa64_nv(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, NV) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR2, NV) !=3D 0; } =20 static inline bool isar_feature_aa64_nv2(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, NV) >=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64MMFR2, NV) >=3D 2; } =20 static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 05157a49d75..df9b7cc8c84 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1074,10 +1074,6 @@ struct ArchCPU { uint32_t dbgdidr; uint32_t dbgdevid; uint32_t dbgdevid1; - uint64_t id_aa64mmfr0; - uint64_t id_aa64mmfr1; - uint64_t id_aa64mmfr2; - uint64_t id_aa64mmfr3; uint64_t id_aa64dfr0; uint64_t id_aa64dfr1; uint64_t id_aa64smfr0; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 502aac91730..500f3646bfa 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -623,12 +623,12 @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) return; } =20 - t =3D cpu->isar.id_aa64mmfr0; + t =3D GET_IDREG(&cpu->isar, ID_AA64MMFR0); t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 2); /* 16k pages w/ LPA2 = */ t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN4, 1); /* 4k pages w/ LPA2 = */ t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 3); /* 16k stage2 w/ LPA2= */ t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 3); /* 4k stage2 w/ LPA2= */ - cpu->isar.id_aa64mmfr0 =3D t; + SET_IDREG(&cpu->isar, ID_AA64MMFR0, t); } =20 static void aarch64_a57_initfn(Object *obj) @@ -673,7 +673,7 @@ static void aarch64_a57_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR0, 0x00002222); cpu->isar.id_aa64dfr0 =3D 0x10305106; SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); - cpu->isar.id_aa64mmfr0 =3D 0x00001124; + SET_IDREG(isar, ID_AA64MMFR0, 0x00001124); cpu->isar.dbgdidr =3D 0x3516d000; cpu->isar.dbgdevid =3D 0x01110f13; cpu->isar.dbgdevid1 =3D 0x2; @@ -735,7 +735,7 @@ static void aarch64_a53_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR0, 0x00002222); cpu->isar.id_aa64dfr0 =3D 0x10305106; SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); - cpu->isar.id_aa64mmfr0 =3D 0x00001122; /* 40 bit physical addr */ + SET_IDREG(isar, ID_AA64MMFR0, 0x00001122); /* 40 bit physical addr */ cpu->isar.dbgdidr =3D 0x3516d000; cpu->isar.dbgdevid =3D 0x00110f13; cpu->isar.dbgdevid1 =3D 0x1; diff --git a/target/arm/helper.c b/target/arm/helper.c index b221e8df6c0..fe0bda749f4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8043,22 +8043,22 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64mmfr0 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64MMFR0)}, { .name =3D "ID_AA64MMFR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64mmfr1 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64MMFR1) }, { .name =3D "ID_AA64MMFR2_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64mmfr2 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64MMFR2) }, { .name =3D "ID_AA64MMFR3_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 3, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64mmfr3 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64MMFR3) }, { .name =3D "ID_AA64MMFR4_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index e1bfca5947c..37a6303ec2a 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -846,14 +846,17 @@ static uint64_t hvf_get_reg(CPUState *cpu, int rt) return val; } =20 -static void clamp_id_aa64mmfr0_parange_to_ipa_size(uint64_t *id_aa64mmfr0) +static void clamp_id_aa64mmfr0_parange_to_ipa_size(ARMISARegisters *isar) { uint32_t ipa_size =3D chosen_ipa_bit_size ? chosen_ipa_bit_size : hvf_arm_get_max_ipa_bit_size(); + uint64_t id_aa64mmfr0; =20 /* Clamp down the PARange to the IPA size the kernel supports. */ uint8_t index =3D round_down_to_parange_index(ipa_size); - *id_aa64mmfr0 =3D (*id_aa64mmfr0 & ~R_ID_AA64MMFR0_PARANGE_MASK) | ind= ex; + id_aa64mmfr0 =3D GET_IDREG(isar, ID_AA64MMFR0); + id_aa64mmfr0 =3D (id_aa64mmfr0 & ~R_ID_AA64MMFR0_PARANGE_MASK) | index; + SET_IDREG(isar, ID_AA64MMFR0, id_aa64mmfr0); } =20 static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) @@ -870,9 +873,9 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.idregs[ID_AA64ISAR0_EL1_= IDX] }, { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.idregs[ID_AA64ISAR1_EL1_= IDX] }, /* Add ID_AA64ISAR2_EL1 here when HVF supports it */ - { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 }, - { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 }, - { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.id_aa64mmfr2 }, + { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.idregs[ID_AA64MMFR0_EL1_= IDX] }, + { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.idregs[ID_AA64MMFR1_EL1_= IDX] }, + { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.idregs[ID_AA64MMFR2_EL1_= IDX] }, /* Add ID_AA64MMFR3_EL1 here when HVF supports it */ }; hv_vcpu_t fd; @@ -899,7 +902,7 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) r |=3D hv_vcpu_get_sys_reg(fd, HV_SYS_REG_MIDR_EL1, &ahcf->midr); r |=3D hv_vcpu_destroy(fd); =20 - clamp_id_aa64mmfr0_parange_to_ipa_size(&host_isar.id_aa64mmfr0); + clamp_id_aa64mmfr0_parange_to_ipa_size(&host_isar); =20 /* * Disable SME, which is not properly handled by QEMU hvf yet. @@ -1067,12 +1070,12 @@ int hvf_arch_init_vcpu(CPUState *cpu) =20 /* We're limited to underlying hardware caps, override internal versio= ns */ ret =3D hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64MMFR0_EL= 1, - &arm_cpu->isar.id_aa64mmfr0); + &arm_cpu->isar.idregs[ID_AA64MMFR0_EL1_IDX]); assert_hvf_ok(ret); =20 - clamp_id_aa64mmfr0_parange_to_ipa_size(&arm_cpu->isar.id_aa64mmfr0); + clamp_id_aa64mmfr0_parange_to_ipa_size(&arm_cpu->isar); ret =3D hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64MMFR0_EL= 1, - arm_cpu->isar.id_aa64mmfr0); + arm_cpu->isar.idregs[ID_AA64MMFR0_EL1_IDX]); assert_hvf_ok(ret); =20 return 0; diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 1e19dba4cb0..1dde96fbbda 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -323,14 +323,10 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUF= eatures *ahcf) err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64ISAR0_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64ISAR1_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64ISAR2_EL1_IDX); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr0, - ARM64_SYS_REG(3, 0, 0, 7, 0)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1, - ARM64_SYS_REG(3, 0, 0, 7, 1)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2, - ARM64_SYS_REG(3, 0, 0, 7, 2)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr3, - ARM64_SYS_REG(3, 0, 0, 7, 3)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64MMFR0_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64MMFR1_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64MMFR2_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64MMFR3_EL1_IDX); =20 /* * Note that if AArch32 support is not present in the host, diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 44170d831cc..561bf2678e5 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -122,7 +122,7 @@ unsigned int arm_pamax(ARMCPU *cpu) { if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { unsigned int parange =3D - FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); + FIELD_EX64_IDREG(&cpu->isar, ID_AA64MMFR0, PARANGE); =20 /* * id_aa64mmfr0 is a read-only register so values outside of the @@ -332,7 +332,7 @@ static bool granule_protection_check(CPUARMState *env, = uint64_t paddress, * physical address size is invalid. */ pps =3D FIELD_EX64(gpccr, GPCCR, PPS); - if (pps > FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE)) { + if (pps > FIELD_EX64_IDREG(&cpu->isar, ID_AA64MMFR0, PARANGE)) { goto fault_walk; } pps =3D pamax_map[pps]; @@ -1703,7 +1703,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, * ID_AA64MMFR0 is a read-only register so values outside of the * supported mappings can be considered an implementation error. */ - ps =3D FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); + ps =3D FIELD_EX64_IDREG(&cpu->isar, ID_AA64MMFR0, PARANGE); ps =3D MIN(ps, param.ps); assert(ps < ARRAY_SIZE(pamax_map)); outputsize =3D pamax_map[ps]; diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 7a730c7974f..9efb7f0ce80 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -69,8 +69,8 @@ static void aarch64_a35_initfn(Object *obj) cpu->isar.id_aa64dfr1 =3D 0; SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); SET_IDREG(isar, ID_AA64ISAR1, 0); - cpu->isar.id_aa64mmfr0 =3D 0x00101122; - cpu->isar.id_aa64mmfr1 =3D 0; + SET_IDREG(isar, ID_AA64MMFR0, 0x00101122); + SET_IDREG(isar, ID_AA64MMFR1, 0); cpu->clidr =3D 0x0a200023; cpu->dcz_blocksize =3D 4; =20 @@ -222,9 +222,9 @@ static void aarch64_a55_initfn(Object *obj) cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull); - cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; - cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; - cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; + SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101122ull); + SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull); + SET_IDREG(isar, ID_AA64MMFR2, 0x0000000000001011ull); SET_IDREG(isar, ID_AA64PFR0, 0x0000000010112222ull); SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull); cpu->id_afr0 =3D 0x00000000; @@ -312,7 +312,7 @@ static void aarch64_a72_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR0, 0x00002222); cpu->isar.id_aa64dfr0 =3D 0x10305106; SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); - cpu->isar.id_aa64mmfr0 =3D 0x00001124; + SET_IDREG(isar, ID_AA64MMFR0, 0x00001124); cpu->isar.dbgdidr =3D 0x3516d000; cpu->isar.dbgdevid =3D 0x01110f13; cpu->isar.dbgdevid1 =3D 0x2; @@ -355,9 +355,9 @@ static void aarch64_a76_initfn(Object *obj) cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull); - cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; - cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; - cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; + SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101122ull); + SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull); + SET_IDREG(isar, ID_AA64MMFR2, 0x0000000000001011ull); SET_IDREG(isar, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in = later */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull); cpu->id_afr0 =3D 0x00000000; @@ -430,9 +430,9 @@ static void aarch64_a64fx_initfn(Object *obj) cpu->isar.id_aa64dfr1 =3D 0x0000000000000000; cpu->id_aa64afr0 =3D 0x0000000000000000; cpu->id_aa64afr1 =3D 0x0000000000000000; - cpu->isar.id_aa64mmfr0 =3D 0x0000000000001122; - cpu->isar.id_aa64mmfr1 =3D 0x0000000011212100; - cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011; + SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000001122); + SET_IDREG(isar, ID_AA64MMFR1, 0x0000000011212100); + SET_IDREG(isar, ID_AA64MMFR2, 0x0000000000001011); SET_IDREG(isar, ID_AA64ISAR0, 0x0000000010211120); SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000010001); SET_IDREG(isar, ID_AA64ZFR0, 0x0000000000000000); @@ -603,9 +603,9 @@ static void aarch64_neoverse_n1_initfn(Object *obj) cpu->isar.id_aa64dfr0 =3D 0x0000000110305408ull; SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull); - cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; - cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; - cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; + SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101125ull); + SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull); + SET_IDREG(isar, ID_AA64MMFR2, 0x0000000000001011ull); SET_IDREG(isar, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in = later */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull); cpu->id_afr0 =3D 0x00000000; @@ -682,9 +682,9 @@ static void aarch64_neoverse_v1_initfn(Object *obj) cpu->isar.id_aa64dfr1 =3D 0x00000000; SET_IDREG(isar, ID_AA64ISAR0, 0x1011111110212120ull); /* with FEAT_RNG= */ SET_IDREG(isar, ID_AA64ISAR1, 0x0011000001211032ull); - cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; - cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; - cpu->isar.id_aa64mmfr2 =3D 0x0220011102101011ull; + SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101125ull); + SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull), + SET_IDREG(isar, ID_AA64MMFR2, 0x0220011102101011ull), SET_IDREG(isar, ID_AA64PFR0, 0x1101110120111112ull); /* GIC filled in = later */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull); cpu->id_afr0 =3D 0x00000000; @@ -931,9 +931,9 @@ static void aarch64_a710_initfn(Object *obj) cpu->id_aa64afr1 =3D 0; SET_IDREG(isar, ID_AA64ISAR0, 0x0221111110212120ull); /* with Crypto */ SET_IDREG(isar, ID_AA64ISAR1, 0x0010111101211052ull); - cpu->isar.id_aa64mmfr0 =3D 0x0000022200101122ull; - cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; - cpu->isar.id_aa64mmfr2 =3D 0x1221011110101011ull; + SET_IDREG(isar, ID_AA64MMFR0, 0x0000022200101122ull); + SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull); + SET_IDREG(isar, ID_AA64MMFR2, 0x1221011110101011ull); cpu->clidr =3D 0x0000001482000023ull; cpu->gm_blocksize =3D 4; cpu->ctr =3D 0x000000049444c004ull; @@ -1033,9 +1033,9 @@ static void aarch64_neoverse_n2_initfn(Object *obj) cpu->id_aa64afr1 =3D 0; SET_IDREG(isar, ID_AA64ISAR0, 0x1221111110212120ull); /* with Crypto a= nd FEAT_RNG */ SET_IDREG(isar, ID_AA64ISAR1, 0x0011111101211052ull); - cpu->isar.id_aa64mmfr0 =3D 0x0000022200101125ull; - cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; - cpu->isar.id_aa64mmfr2 =3D 0x1221011112101011ull; + SET_IDREG(isar, ID_AA64MMFR0, 0x0000022200101125ull); + SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull); + SET_IDREG(isar, ID_AA64MMFR2, 0x1221011112101011ull); cpu->clidr =3D 0x0000001482000023ull; cpu->gm_blocksize =3D 4; cpu->ctr =3D 0x00000004b444c004ull; @@ -1206,7 +1206,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR1, NMI, 1); /* FEAT_NMI */ SET_IDREG(isar, ID_AA64PFR1, t); =20 - t =3D cpu->isar.id_aa64mmfr0; + t =3D GET_IDREG(isar, ID_AA64MMFR0); t =3D FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */ t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supporte= d */ t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 support= ed */ @@ -1214,9 +1214,9 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 support= ed */ t =3D FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* FEAT_FGT */ t =3D FIELD_DP64(t, ID_AA64MMFR0, ECV, 2); /* FEAT_ECV */ - cpu->isar.id_aa64mmfr0 =3D t; + SET_IDREG(isar, ID_AA64MMFR0, t); =20 - t =3D cpu->isar.id_aa64mmfr1; + t =3D GET_IDREG(isar, ID_AA64MMFR1); t =3D FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */ t =3D FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ @@ -1229,9 +1229,9 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR1, AFP, 1); /* FEAT_AFP */ t =3D FIELD_DP64(t, ID_AA64MMFR1, TIDCP1, 1); /* FEAT_TIDCP1 */ t =3D FIELD_DP64(t, ID_AA64MMFR1, CMOW, 1); /* FEAT_CMOW */ - cpu->isar.id_aa64mmfr1 =3D t; + SET_IDREG(isar, ID_AA64MMFR1, t); =20 - t =3D cpu->isar.id_aa64mmfr2; + t =3D GET_IDREG(isar, ID_AA64MMFR2); t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ t =3D FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */ @@ -1245,11 +1245,9 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2= */ t =3D FIELD_DP64(t, ID_AA64MMFR2, EVT, 2); /* FEAT_EVT */ t =3D FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */ - cpu->isar.id_aa64mmfr2 =3D t; + SET_IDREG(isar, ID_AA64MMFR2, t); =20 - t =3D cpu->isar.id_aa64mmfr3; - t =3D FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */ - cpu->isar.id_aa64mmfr3 =3D t; + FIELD_DP64_IDREG(isar, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPE= C */ =20 t =3D GET_IDREG(isar, ID_AA64ZFR0); t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); --=20 2.43.0 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 01 Jul 2025 10:07:31 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/43] arm/cpu: Store aa64dfr0/1 into the idregs array Date: Tue, 1 Jul 2025 18:06:44 +0100 Message-ID: <20250701170720.4072660-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751389755343116600 Content-Type: text/plain; charset="utf-8" From: Eric Auger Reviewed-by: Richard Henderson Reviewed-by: Sebastian Ott Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck Message-id: 20250617153931.1330449-7-cohuck@redhat.com Signed-off-by: Peter Maydell --- target/arm/cpu-features.h | 16 ++++++++-------- target/arm/cpu.h | 2 -- target/arm/internals.h | 6 +++--- target/arm/cpu.c | 15 +++++---------- target/arm/cpu64.c | 4 ++-- target/arm/helper.c | 4 ++-- target/arm/hvf/hvf.c | 4 ++-- target/arm/kvm.c | 12 +++++------- target/arm/tcg/cpu64.c | 32 ++++++++++++++++---------------- 9 files changed, 43 insertions(+), 52 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 89c9278639b..9517e8a74c8 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -901,30 +901,30 @@ static inline bool isar_feature_aa64_nv2(const ARMISA= Registers *id) =20 static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >=3D 4 && - FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) !=3D 0xf; + return FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) >=3D 4 && + FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) !=3D 0xf; } =20 static inline bool isar_feature_aa64_pmuv3p4(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >=3D 5 && - FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) !=3D 0xf; + return FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) >=3D 5 && + FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) !=3D 0xf; } =20 static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >=3D 6 && - FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) !=3D 0xf; + return FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) >=3D 6 && + FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) !=3D 0xf; } =20 static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >=3D 8; + return FIELD_EX64_IDREG(id, ID_AA64DFR0, DEBUGVER) >=3D 8; } =20 static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id) { - return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >=3D 0; + return FIELD_SEX64_IDREG(id, ID_AA64DFR0, DOUBLELOCK) >=3D 0; } =20 static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index df9b7cc8c84..c7935377c6f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1074,8 +1074,6 @@ struct ArchCPU { uint32_t dbgdidr; uint32_t dbgdevid; uint32_t dbgdevid1; - uint64_t id_aa64dfr0; - uint64_t id_aa64dfr1; uint64_t id_aa64smfr0; uint64_t reset_pmcr_el0; uint64_t idregs[NUM_ID_IDX]; diff --git a/target/arm/internals.h b/target/arm/internals.h index 3360de9150f..6216f68c94f 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1175,7 +1175,7 @@ static inline bool regime_using_lpae_format(CPUARMSta= te *env, ARMMMUIdx mmu_idx) static inline int arm_num_brps(ARMCPU *cpu) { if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) + 1; + return FIELD_EX64_IDREG(&cpu->isar, ID_AA64DFR0, BRPS) + 1; } else { return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, BRPS) + 1; } @@ -1189,7 +1189,7 @@ static inline int arm_num_brps(ARMCPU *cpu) static inline int arm_num_wrps(ARMCPU *cpu) { if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) + 1; + return FIELD_EX64_IDREG(&cpu->isar, ID_AA64DFR0, WRPS) + 1; } else { return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, WRPS) + 1; } @@ -1203,7 +1203,7 @@ static inline int arm_num_wrps(ARMCPU *cpu) static inline int arm_num_ctx_cmps(ARMCPU *cpu) { if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) + = 1; + return FIELD_EX64_IDREG(&cpu->isar, ID_AA64DFR0, CTX_CMPS) + 1; } else { return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, CTX_CMPS) + 1; } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d39e8dc9560..400bee84943 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2347,8 +2347,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) cpu); #endif } else { - cpu->isar.id_aa64dfr0 =3D - FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); + FIELD_DP64_IDREG(isar, ID_AA64DFR0, PMUVER, 0); cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFM= ON, 0); cpu->pmceid0 =3D 0; cpu->pmceid1 =3D 0; @@ -2408,19 +2407,15 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) * try to access the non-existent system registers for them. */ /* FEAT_SPE (Statistical Profiling Extension) */ - cpu->isar.id_aa64dfr0 =3D - FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0); + FIELD_DP64_IDREG(isar, ID_AA64DFR0, PMSVER, 0); /* FEAT_TRBE (Trace Buffer Extension) */ - cpu->isar.id_aa64dfr0 =3D - FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0); + FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEBUFFER, 0); /* FEAT_TRF (Self-hosted Trace Extension) */ - cpu->isar.id_aa64dfr0 =3D - FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0); + FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEFILT, 0); cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, TRACEFILT, 0); /* Trace Macrocell system register access */ - cpu->isar.id_aa64dfr0 =3D - FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEVER, 0); + FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEVER, 0); cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPTRC, 0); /* Memory mapped trace */ diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 500f3646bfa..a215ba8b479 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -671,7 +671,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->isar.id_isar5 =3D 0x00011121; cpu->isar.id_isar6 =3D 0; SET_IDREG(isar, ID_AA64PFR0, 0x00002222); - cpu->isar.id_aa64dfr0 =3D 0x10305106; + SET_IDREG(isar, ID_AA64DFR0, 0x10305106); SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); SET_IDREG(isar, ID_AA64MMFR0, 0x00001124); cpu->isar.dbgdidr =3D 0x3516d000; @@ -733,7 +733,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->isar.id_isar5 =3D 0x00011121; cpu->isar.id_isar6 =3D 0; SET_IDREG(isar, ID_AA64PFR0, 0x00002222); - cpu->isar.id_aa64dfr0 =3D 0x10305106; + SET_IDREG(isar, ID_AA64DFR0, 0x10305106); SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); SET_IDREG(isar, ID_AA64MMFR0, 0x00001122); /* 40 bit physical addr */ cpu->isar.dbgdidr =3D 0x3516d000; diff --git a/target/arm/helper.c b/target/arm/helper.c index fe0bda749f4..2ac132c1db8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7963,12 +7963,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64dfr0 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64DFR0) }, { .name =3D "ID_AA64DFR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64dfr1 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64DFR1) }, { .name =3D "ID_AA64DFR2_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 37a6303ec2a..5c95ccc5b8d 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -868,8 +868,8 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) } regs[] =3D { { HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.idregs[ID_AA64PFR0_EL1_ID= X] }, { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.idregs[ID_AA64PFR1_EL1_ID= X] }, - { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.id_aa64dfr0 }, - { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 }, + { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.idregs[ID_AA64DFR0_EL1_ID= X] }, + { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.idregs[ID_AA64DFR1_EL1_ID= X] }, { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.idregs[ID_AA64ISAR0_EL1_= IDX] }, { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.idregs[ID_AA64ISAR1_EL1_= IDX] }, /* Add ID_AA64ISAR2_EL1 here when HVF supports it */ diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 1dde96fbbda..479e5860e02 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -316,10 +316,8 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFe= atures *ahcf) err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64PFR1_EL1_IDX); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0, ARM64_SYS_REG(3, 0, 0, 4, 5)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr0, - ARM64_SYS_REG(3, 0, 0, 5, 0)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1, - ARM64_SYS_REG(3, 0, 0, 5, 1)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64DFR0_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64DFR1_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64ISAR0_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64ISAR1_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64ISAR2_EL1_IDX); @@ -390,10 +388,10 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUF= eatures *ahcf) * We only do this if the CPU supports AArch32 at EL1. */ if (FIELD_EX32_IDREG(&ahcf->isar, ID_AA64PFR0, EL1) >=3D 2) { - int wrps =3D FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, W= RPS); - int brps =3D FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, B= RPS); + int wrps =3D FIELD_EX64_IDREG(&ahcf->isar, ID_AA64DFR0, WRPS); + int brps =3D FIELD_EX64_IDREG(&ahcf->isar, ID_AA64DFR0, BRPS); int ctx_cmps =3D - FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS); + FIELD_EX64_IDREG(&ahcf->isar, ID_AA64DFR0, CTX_CMPS); int version =3D 6; /* ARMv8 debug architecture */ bool has_el3 =3D !!FIELD_EX32_IDREG(&ahcf->isar, ID_AA64PFR0, EL3); diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 9efb7f0ce80..7e18d31a253 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -65,8 +65,8 @@ static void aarch64_a35_initfn(Object *obj) cpu->isar.id_isar5 =3D 0x00011121; SET_IDREG(isar, ID_AA64PFR0, 0x00002222); SET_IDREG(isar, ID_AA64PFR1, 0); - cpu->isar.id_aa64dfr0 =3D 0x10305106; - cpu->isar.id_aa64dfr1 =3D 0; + SET_IDREG(isar, ID_AA64DFR0, 0x10305106); + SET_IDREG(isar, ID_AA64DFR1, 0); SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); SET_IDREG(isar, ID_AA64ISAR1, 0); SET_IDREG(isar, ID_AA64MMFR0, 0x00101122); @@ -219,7 +219,7 @@ static void aarch64_a55_initfn(Object *obj) cpu->clidr =3D 0x82000023; cpu->ctr =3D 0x84448004; /* L1Ip =3D VIPT */ cpu->dcz_blocksize =3D 4; /* 64 bytes */ - cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; + SET_IDREG(isar, ID_AA64DFR0, 0x0000000010305408ull); SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull); SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101122ull); @@ -310,7 +310,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->isar.id_isar4 =3D 0x00011142; cpu->isar.id_isar5 =3D 0x00011121; SET_IDREG(isar, ID_AA64PFR0, 0x00002222); - cpu->isar.id_aa64dfr0 =3D 0x10305106; + SET_IDREG(isar, ID_AA64DFR0, 0x10305106); SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); SET_IDREG(isar, ID_AA64MMFR0, 0x00001124); cpu->isar.dbgdidr =3D 0x3516d000; @@ -352,7 +352,7 @@ static void aarch64_a76_initfn(Object *obj) cpu->clidr =3D 0x82000023; cpu->ctr =3D 0x8444C004; cpu->dcz_blocksize =3D 4; - cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; + SET_IDREG(isar, ID_AA64DFR0, 0x0000000010305408ull), SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull); SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101122ull); @@ -426,8 +426,8 @@ static void aarch64_a64fx_initfn(Object *obj) cpu->reset_sctlr =3D 0x30000180; SET_IDREG(isar, ID_AA64PFR0, 0x0000000101111111); /* No RAS Extensions= */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000000); - cpu->isar.id_aa64dfr0 =3D 0x0000000010305408; - cpu->isar.id_aa64dfr1 =3D 0x0000000000000000; + SET_IDREG(isar, ID_AA64DFR0, 0x0000000010305408), + SET_IDREG(isar, ID_AA64DFR1, 0x0000000000000000), cpu->id_aa64afr0 =3D 0x0000000000000000; cpu->id_aa64afr1 =3D 0x0000000000000000; SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000001122); @@ -600,7 +600,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj) cpu->clidr =3D 0x82000023; cpu->ctr =3D 0x8444c004; cpu->dcz_blocksize =3D 4; - cpu->isar.id_aa64dfr0 =3D 0x0000000110305408ull; + SET_IDREG(isar, ID_AA64DFR0, 0x0000000110305408ull); SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull); SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101125ull); @@ -678,8 +678,8 @@ static void aarch64_neoverse_v1_initfn(Object *obj) cpu->dcz_blocksize =3D 4; cpu->id_aa64afr0 =3D 0x00000000; cpu->id_aa64afr1 =3D 0x00000000; - cpu->isar.id_aa64dfr0 =3D 0x000001f210305519ull; - cpu->isar.id_aa64dfr1 =3D 0x00000000; + SET_IDREG(isar, ID_AA64DFR0, 0x000001f210305519ull), + SET_IDREG(isar, ID_AA64DFR1, 0x00000000), SET_IDREG(isar, ID_AA64ISAR0, 0x1011111110212120ull); /* with FEAT_RNG= */ SET_IDREG(isar, ID_AA64ISAR1, 0x0011000001211032ull); SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101125ull); @@ -925,8 +925,8 @@ static void aarch64_a710_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in = later */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000221ull); SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */ - cpu->isar.id_aa64dfr0 =3D 0x000011f010305619ull; - cpu->isar.id_aa64dfr1 =3D 0; + SET_IDREG(isar, ID_AA64DFR0, 0x000011f010305619ull); + SET_IDREG(isar, ID_AA64DFR1, 0); cpu->id_aa64afr0 =3D 0; cpu->id_aa64afr1 =3D 0; SET_IDREG(isar, ID_AA64ISAR0, 0x0221111110212120ull); /* with Crypto */ @@ -1027,8 +1027,8 @@ static void aarch64_neoverse_n2_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in = later */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000221ull); SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */ - cpu->isar.id_aa64dfr0 =3D 0x000011f210305619ull; - cpu->isar.id_aa64dfr1 =3D 0; + SET_IDREG(isar, ID_AA64DFR0, 0x000011f210305619ull); + SET_IDREG(isar, ID_AA64DFR1, 0); cpu->id_aa64afr0 =3D 0; cpu->id_aa64afr1 =3D 0; SET_IDREG(isar, ID_AA64ISAR0, 0x1221111110212120ull); /* with Crypto a= nd FEAT_RNG */ @@ -1261,11 +1261,11 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */ SET_IDREG(isar, ID_AA64ZFR0, t); =20 - t =3D cpu->isar.id_aa64dfr0; + t =3D GET_IDREG(isar, ID_AA64DFR0); t =3D FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 10); /* FEAT_Debugv8p8 */ t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); 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Tue, 01 Jul 2025 10:07:32 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/43] arm/cpu: Store aa64smfr0 into the idregs array Date: Tue, 1 Jul 2025 18:06:45 +0100 Message-ID: <20250701170720.4072660-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751390065331116600 Content-Type: text/plain; charset="utf-8" From: Eric Auger Reviewed-by: Richard Henderson Reviewed-by: Sebastian Ott Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck Message-id: 20250617153931.1330449-8-cohuck@redhat.com Signed-off-by: Peter Maydell --- target/arm/cpu-features.h | 6 +++--- target/arm/cpu.h | 1 - target/arm/cpu64.c | 7 ++----- target/arm/helper.c | 2 +- target/arm/kvm.c | 3 +-- target/arm/tcg/cpu64.c | 4 ++-- 6 files changed, 9 insertions(+), 14 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 9517e8a74c8..051ed7b8847 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -979,17 +979,17 @@ static inline bool isar_feature_aa64_sve_f64mm(const = ARMISARegisters *id) =20 static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, F64F64); + return FIELD_EX64_IDREG(id, ID_AA64SMFR0, F64F64); } =20 static inline bool isar_feature_aa64_sme_i16i64(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, I16I64) =3D=3D 0xf; + return FIELD_EX64_IDREG(id, ID_AA64SMFR0, I16I64) =3D=3D 0xf; } =20 static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, FA64); + return FIELD_EX64_IDREG(id, ID_AA64SMFR0, FA64); } =20 /* diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c7935377c6f..1083ae7623b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1074,7 +1074,6 @@ struct ArchCPU { uint32_t dbgdidr; uint32_t dbgdevid; uint32_t dbgdevid1; - uint64_t id_aa64smfr0; uint64_t reset_pmcr_el0; uint64_t idregs[NUM_ID_IDX]; } isar; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index a215ba8b479..0f938155d28 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -328,7 +328,7 @@ void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp) =20 if (vq_map =3D=3D 0) { if (!cpu_isar_feature(aa64_sme, cpu)) { - cpu->isar.id_aa64smfr0 =3D 0; + SET_IDREG(&cpu->isar, ID_AA64SMFR0, 0); return; } =20 @@ -381,11 +381,8 @@ static bool cpu_arm_get_sme_fa64(Object *obj, Error **= errp) static void cpu_arm_set_sme_fa64(Object *obj, bool value, Error **errp) { ARMCPU *cpu =3D ARM_CPU(obj); - uint64_t t; =20 - t =3D cpu->isar.id_aa64smfr0; - t =3D FIELD_DP64(t, ID_AA64SMFR0, FA64, value); - cpu->isar.id_aa64smfr0 =3D t; + FIELD_DP64_IDREG(&cpu->isar, ID_AA64SMFR0, FA64, value); } =20 #ifdef CONFIG_USER_ONLY diff --git a/target/arm/helper.c b/target/arm/helper.c index 2ac132c1db8..39729d3a8d0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7948,7 +7948,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64smfr0 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64SMFR0)}, { .name =3D "ID_AA64PFR6_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 479e5860e02..87368558614 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -314,8 +314,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) err =3D 0; } else { err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64PFR1_EL1_IDX); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0, - ARM64_SYS_REG(3, 0, 0, 4, 5)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64SMFR0_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64DFR0_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64DFR1_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64ISAR0_EL1_IDX); diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 7e18d31a253..80a99ab025d 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1267,7 +1267,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* FEAT_HPMN0 */ SET_IDREG(isar, ID_AA64DFR0, t); =20 - t =3D cpu->isar.id_aa64smfr0; + t =3D GET_IDREG(isar, ID_AA64SMFR0); t =3D FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */ t =3D FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* FEAT_SME */ t =3D FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* FEAT_SME */ @@ -1275,7 +1275,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); 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Tue, 01 Jul 2025 10:07:33 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/43] arm/cpu: Store id_isar0-7 into the idregs array Date: Tue, 1 Jul 2025 18:06:46 +0100 Message-ID: <20250701170720.4072660-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751390087444116600 Content-Type: text/plain; charset="utf-8" From: Eric Auger Reviewed-by: Richard Henderson Reviewed-by: Sebastian Ott Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck Message-id: 20250617153931.1330449-9-cohuck@redhat.com Signed-off-by: Peter Maydell --- target/arm/cpu-features.h | 36 +++++----- target/arm/cpu.h | 7 -- hw/intc/armv7m_nvic.c | 12 ++-- target/arm/cpu.c | 24 +++---- target/arm/cpu64.c | 28 ++++---- target/arm/helper.c | 14 ++-- target/arm/kvm.c | 21 ++---- target/arm/tcg/cpu-v7m.c | 90 +++++++++++++----------- target/arm/tcg/cpu32.c | 144 +++++++++++++++++++++----------------- target/arm/tcg/cpu64.c | 108 ++++++++++++++-------------- 10 files changed, 243 insertions(+), 241 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 051ed7b8847..75a2cc40779 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -46,93 +46,93 @@ */ static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR0, DIVIDE) !=3D 0; } =20 static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; + return FIELD_EX32_IDREG(id, ID_ISAR0, DIVIDE) > 1; } =20 static inline bool isar_feature_aa32_lob(const ARMISARegisters *id) { /* (M-profile) low-overhead loops and branch future */ - return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >=3D 3; + return FIELD_EX32_IDREG(id, ID_ISAR0, CMPBRANCH) >=3D 3; } =20 static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR1, JAZELLE) !=3D 0; } =20 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR5, AES) !=3D 0; } =20 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; + return FIELD_EX32_IDREG(id, ID_ISAR5, AES) > 1; } =20 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR5, SHA1) !=3D 0; } =20 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR5, SHA2) !=3D 0; } =20 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR5, CRC32) !=3D 0; } =20 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR5, RDM) !=3D 0; } =20 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR5, VCMA) !=3D 0; } =20 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR6, JSCVT) !=3D 0; } =20 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR6, DP) !=3D 0; } =20 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR6, FHM) !=3D 0; } =20 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR6, SB) !=3D 0; } =20 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR6, SPECRES) !=3D 0; } =20 static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar6, ID_ISAR6, BF16) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR6, BF16) !=3D 0; } =20 static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR6, I8MM) !=3D 0; } =20 static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1083ae7623b..353c18e6799 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1050,13 +1050,6 @@ struct ArchCPU { * field by reading the value from the KVM vCPU. */ struct ARMISARegisters { - uint32_t id_isar0; - uint32_t id_isar1; - uint32_t id_isar2; - uint32_t id_isar3; - uint32_t id_isar4; - uint32_t id_isar5; - uint32_t id_isar6; uint32_t id_mmfr0; uint32_t id_mmfr1; uint32_t id_mmfr2; diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 83ff74f899f..fdb7f58e367 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1303,32 +1303,32 @@ static uint32_t nvic_readl(NVICState *s, uint32_t o= ffset, MemTxAttrs attrs) if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_isar0; + return GET_IDREG(&cpu->isar, ID_ISAR0); case 0xd64: /* ISAR1. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_isar1; + return GET_IDREG(&cpu->isar, ID_ISAR1); case 0xd68: /* ISAR2. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_isar2; + return GET_IDREG(&cpu->isar, ID_ISAR2); case 0xd6c: /* ISAR3. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_isar3; + return GET_IDREG(&cpu->isar, ID_ISAR3); case 0xd70: /* ISAR4. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_isar4; + return GET_IDREG(&cpu->isar, ID_ISAR4); case 0xd74: /* ISAR5. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_isar5; + return GET_IDREG(&cpu->isar, ID_ISAR5); case 0xd78: /* CLIDR */ return cpu->clidr; case 0xd7c: /* CTR */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 400bee84943..cf811e47d99 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2126,10 +2126,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) =20 FIELD_DP64_IDREG(isar, ID_AA64PFR0, FP, 0xf); =20 - u =3D cpu->isar.id_isar6; + u =3D GET_IDREG(isar, ID_ISAR6); u =3D FIELD_DP32(u, ID_ISAR6, JSCVT, 0); u =3D FIELD_DP32(u, ID_ISAR6, BF16, 0); - cpu->isar.id_isar6 =3D u; + SET_IDREG(isar, ID_ISAR6, u); =20 u =3D cpu->isar.mvfr0; u =3D FIELD_DP32(u, MVFR0, FPSP, 0); @@ -2181,20 +2181,20 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) =20 FIELD_DP64_IDREG(isar, ID_AA64PFR0, ADVSIMD, 0xf); =20 - u =3D cpu->isar.id_isar5; + u =3D GET_IDREG(isar, ID_ISAR5); u =3D FIELD_DP32(u, ID_ISAR5, AES, 0); u =3D FIELD_DP32(u, ID_ISAR5, SHA1, 0); u =3D FIELD_DP32(u, ID_ISAR5, SHA2, 0); u =3D FIELD_DP32(u, ID_ISAR5, RDM, 0); u =3D FIELD_DP32(u, ID_ISAR5, VCMA, 0); - cpu->isar.id_isar5 =3D u; + SET_IDREG(isar, ID_ISAR5, u); =20 - u =3D cpu->isar.id_isar6; + u =3D GET_IDREG(isar, ID_ISAR6); u =3D FIELD_DP32(u, ID_ISAR6, DP, 0); u =3D FIELD_DP32(u, ID_ISAR6, FHM, 0); u =3D FIELD_DP32(u, ID_ISAR6, BF16, 0); u =3D FIELD_DP32(u, ID_ISAR6, I8MM, 0); - cpu->isar.id_isar6 =3D u; + SET_IDREG(isar, ID_ISAR6, u); =20 if (!arm_feature(env, ARM_FEATURE_M)) { u =3D cpu->isar.mvfr1; @@ -2232,19 +2232,17 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) =20 unset_feature(env, ARM_FEATURE_THUMB_DSP); =20 - u =3D cpu->isar.id_isar1; - u =3D FIELD_DP32(u, ID_ISAR1, EXTEND, 1); - cpu->isar.id_isar1 =3D u; + FIELD_DP32_IDREG(isar, ID_ISAR1, EXTEND, 1); =20 - u =3D cpu->isar.id_isar2; + u =3D GET_IDREG(isar, ID_ISAR2); u =3D FIELD_DP32(u, ID_ISAR2, MULTU, 1); u =3D FIELD_DP32(u, ID_ISAR2, MULTS, 1); - cpu->isar.id_isar2 =3D u; + SET_IDREG(isar, ID_ISAR2, u); =20 - u =3D cpu->isar.id_isar3; + u =3D GET_IDREG(isar, ID_ISAR3); u =3D FIELD_DP32(u, ID_ISAR3, SIMD, 1); u =3D FIELD_DP32(u, ID_ISAR3, SATURATE, 0); - cpu->isar.id_isar3 =3D u; + SET_IDREG(isar, ID_ISAR3, u); } =20 =20 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 0f938155d28..6be62c0711b 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -660,13 +660,13 @@ static void aarch64_a57_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02102211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00011142; - cpu->isar.id_isar5 =3D 0x00011121; - cpu->isar.id_isar6 =3D 0; + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232042); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00011142); + SET_IDREG(isar, ID_ISAR5, 0x00011121); + SET_IDREG(isar, ID_ISAR6, 0); SET_IDREG(isar, ID_AA64PFR0, 0x00002222); SET_IDREG(isar, ID_AA64DFR0, 0x10305106); SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); @@ -722,13 +722,13 @@ static void aarch64_a53_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02102211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00011142; - cpu->isar.id_isar5 =3D 0x00011121; - cpu->isar.id_isar6 =3D 0; + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232042); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00011142); + SET_IDREG(isar, ID_ISAR5, 0x00011121); + SET_IDREG(isar, ID_ISAR6, 0); SET_IDREG(isar, ID_AA64PFR0, 0x00002222); SET_IDREG(isar, ID_AA64DFR0, 0x10305106); SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); diff --git a/target/arm/helper.c b/target/arm/helper.c index 39729d3a8d0..7e0b3f164e1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7830,32 +7830,32 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_isar0 }, + .resetvalue =3D GET_IDREG(isar, ID_ISAR0)}, { .name =3D "ID_ISAR1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_isar1 }, + .resetvalue =3D GET_IDREG(isar, ID_ISAR1)}, { .name =3D "ID_ISAR2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_isar2 }, + .resetvalue =3D GET_IDREG(isar, ID_ISAR2)}, { .name =3D "ID_ISAR3", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 3, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_isar3 }, + .resetvalue =3D GET_IDREG(isar, ID_ISAR3) }, { .name =3D "ID_ISAR4", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_isar4 }, + .resetvalue =3D GET_IDREG(isar, ID_ISAR4) }, { .name =3D "ID_ISAR5", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_isar5 }, + .resetvalue =3D GET_IDREG(isar, ID_ISAR5) }, { .name =3D "ID_MMFR4", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, @@ -7865,7 +7865,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_isar6 }, + .resetvalue =3D GET_IDREG(isar, ID_ISAR6) }, }; define_arm_cp_regs(cpu, v6_idregs); define_arm_cp_regs(cpu, v6_cp_reginfo); diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 87368558614..eef9481737b 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -346,22 +346,15 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUF= eatures *ahcf) ARM64_SYS_REG(3, 0, 0, 1, 6)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3, ARM64_SYS_REG(3, 0, 0, 1, 7)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, - ARM64_SYS_REG(3, 0, 0, 2, 0)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, - ARM64_SYS_REG(3, 0, 0, 2, 1)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2, - ARM64_SYS_REG(3, 0, 0, 2, 2)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3, - ARM64_SYS_REG(3, 0, 0, 2, 3)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4, - ARM64_SYS_REG(3, 0, 0, 2, 4)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5, - ARM64_SYS_REG(3, 0, 0, 2, 5)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_ISAR0_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_ISAR1_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_ISAR2_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_ISAR3_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_ISAR4_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_ISAR5_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_ISAR6_EL1_IDX); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4, ARM64_SYS_REG(3, 0, 0, 2, 6)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6, - ARM64_SYS_REG(3, 0, 0, 2, 7)); =20 err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, ARM64_SYS_REG(3, 0, 0, 3, 0)); diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 8e1a083b911..198c9f3e98c 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -45,6 +45,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int = interrupt_request) static void cortex_m0_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; set_feature(&cpu->env, ARM_FEATURE_V6); set_feature(&cpu->env, ARM_FEATURE_M); =20 @@ -66,18 +67,19 @@ static void cortex_m0_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x00000000; cpu->isar.id_mmfr2 =3D 0x00000000; cpu->isar.id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01141110; - cpu->isar.id_isar1 =3D 0x02111000; - cpu->isar.id_isar2 =3D 0x21112231; - cpu->isar.id_isar3 =3D 0x01111110; - cpu->isar.id_isar4 =3D 0x01310102; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; + SET_IDREG(isar, ID_ISAR0, 0x01141110); + SET_IDREG(isar, ID_ISAR1, 0x02111000); + SET_IDREG(isar, ID_ISAR2, 0x21112231); + SET_IDREG(isar, ID_ISAR3, 0x01111110); + SET_IDREG(isar, ID_ISAR4, 0x01310102); + SET_IDREG(isar, ID_ISAR5, 0x00000000); + SET_IDREG(isar, ID_ISAR6, 0x00000000); } =20 static void cortex_m3_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; set_feature(&cpu->env, ARM_FEATURE_V7); set_feature(&cpu->env, ARM_FEATURE_M); set_feature(&cpu->env, ARM_FEATURE_M_MAIN); @@ -91,18 +93,19 @@ static void cortex_m3_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x00000000; cpu->isar.id_mmfr2 =3D 0x00000000; cpu->isar.id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01141110; - cpu->isar.id_isar1 =3D 0x02111000; - cpu->isar.id_isar2 =3D 0x21112231; - cpu->isar.id_isar3 =3D 0x01111110; - cpu->isar.id_isar4 =3D 0x01310102; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; + SET_IDREG(isar, ID_ISAR0, 0x01141110); + SET_IDREG(isar, ID_ISAR1, 0x02111000); + SET_IDREG(isar, ID_ISAR2, 0x21112231); + SET_IDREG(isar, ID_ISAR3, 0x01111110); + SET_IDREG(isar, ID_ISAR4, 0x01310102); + SET_IDREG(isar, ID_ISAR5, 0x00000000); + SET_IDREG(isar, ID_ISAR6, 0x00000000); } =20 static void cortex_m4_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 set_feature(&cpu->env, ARM_FEATURE_V7); set_feature(&cpu->env, ARM_FEATURE_M); @@ -121,18 +124,19 @@ static void cortex_m4_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x00000000; cpu->isar.id_mmfr2 =3D 0x00000000; cpu->isar.id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01141110; - cpu->isar.id_isar1 =3D 0x02111000; - cpu->isar.id_isar2 =3D 0x21112231; - cpu->isar.id_isar3 =3D 0x01111110; - cpu->isar.id_isar4 =3D 0x01310102; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; + SET_IDREG(isar, ID_ISAR0, 0x01141110); + SET_IDREG(isar, ID_ISAR1, 0x02111000); + SET_IDREG(isar, ID_ISAR2, 0x21112231); + SET_IDREG(isar, ID_ISAR3, 0x01111110); + SET_IDREG(isar, ID_ISAR4, 0x01310102); + SET_IDREG(isar, ID_ISAR5, 0x00000000); + SET_IDREG(isar, ID_ISAR6, 0x00000000); } =20 static void cortex_m7_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 set_feature(&cpu->env, ARM_FEATURE_V7); set_feature(&cpu->env, ARM_FEATURE_M); @@ -151,18 +155,19 @@ static void cortex_m7_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x00000000; cpu->isar.id_mmfr2 =3D 0x01000000; cpu->isar.id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01101110; - cpu->isar.id_isar1 =3D 0x02112000; - cpu->isar.id_isar2 =3D 0x20232231; - cpu->isar.id_isar3 =3D 0x01111131; - cpu->isar.id_isar4 =3D 0x01310132; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; + SET_IDREG(isar, ID_ISAR0, 0x01101110); + SET_IDREG(isar, ID_ISAR1, 0x02112000); + SET_IDREG(isar, ID_ISAR2, 0x20232231); + SET_IDREG(isar, ID_ISAR3, 0x01111131); + SET_IDREG(isar, ID_ISAR4, 0x01310132); + SET_IDREG(isar, ID_ISAR5, 0x00000000); + SET_IDREG(isar, ID_ISAR6, 0x00000000); } =20 static void cortex_m33_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_M); @@ -183,13 +188,13 @@ static void cortex_m33_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x00000000; cpu->isar.id_mmfr2 =3D 0x01000000; cpu->isar.id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01101110; - cpu->isar.id_isar1 =3D 0x02212000; - cpu->isar.id_isar2 =3D 0x20232232; - cpu->isar.id_isar3 =3D 0x01111131; - cpu->isar.id_isar4 =3D 0x01310132; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; + SET_IDREG(isar, ID_ISAR0, 0x01101110); + SET_IDREG(isar, ID_ISAR1, 0x02212000); + SET_IDREG(isar, ID_ISAR2, 0x20232232); + SET_IDREG(isar, ID_ISAR3, 0x01111131); + SET_IDREG(isar, ID_ISAR4, 0x01310132); + SET_IDREG(isar, ID_ISAR5, 0x00000000); + SET_IDREG(isar, ID_ISAR6, 0x00000000); cpu->clidr =3D 0x00000000; cpu->ctr =3D 0x8000c000; } @@ -197,6 +202,7 @@ static void cortex_m33_initfn(Object *obj) static void cortex_m55_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_V8_1M); @@ -220,13 +226,13 @@ static void cortex_m55_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x00000000; cpu->isar.id_mmfr2 =3D 0x01000000; cpu->isar.id_mmfr3 =3D 0x00000011; - cpu->isar.id_isar0 =3D 0x01103110; - cpu->isar.id_isar1 =3D 0x02212000; - cpu->isar.id_isar2 =3D 0x20232232; - cpu->isar.id_isar3 =3D 0x01111131; - cpu->isar.id_isar4 =3D 0x01310132; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; + SET_IDREG(isar, ID_ISAR0, 0x01103110); + SET_IDREG(isar, ID_ISAR1, 0x02212000); + SET_IDREG(isar, ID_ISAR2, 0x20232232); + SET_IDREG(isar, ID_ISAR3, 0x01111131); + SET_IDREG(isar, ID_ISAR4, 0x01310132); + SET_IDREG(isar, ID_ISAR5, 0x00000000); + SET_IDREG(isar, ID_ISAR6, 0x00000000); cpu->clidr =3D 0x00000000; /* caches not implemented */ cpu->ctr =3D 0x8303c003; } diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 2c45b7eddda..937a72b12c9 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -23,18 +23,19 @@ void aa32_max_features(ARMCPU *cpu) { uint32_t t; + ARMISARegisters *isar =3D &cpu->isar; =20 /* Add additional features supported by QEMU */ - t =3D cpu->isar.id_isar5; + t =3D GET_IDREG(isar, ID_ISAR5); t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */ t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */ t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */ t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */ t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */ - cpu->isar.id_isar5 =3D t; + SET_IDREG(isar, ID_ISAR5, t); =20 - t =3D cpu->isar.id_isar6; + t =3D GET_IDREG(isar, ID_ISAR6); t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */ t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */ t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */ @@ -42,7 +43,7 @@ void aa32_max_features(ARMCPU *cpu) t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */ t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */ t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */ - cpu->isar.id_isar6 =3D t; + SET_IDREG(isar, ID_ISAR6, t); =20 t =3D cpu->isar.mvfr1; t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */ @@ -140,7 +141,7 @@ static void arm926_initfn(Object *obj) * ARMv5 does not have the ID_ISAR registers, but we can still * set the field to indicate Jazelle support within QEMU. */ - cpu->isar.id_isar1 =3D FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELL= E, 1); + FIELD_DP32_IDREG(&cpu->isar, ID_ISAR1, JAZELLE, 1); /* * Similarly, we need to set MVFR0 fields to enable vfp and short vect= or * support even though ARMv5 doesn't have this register. @@ -182,7 +183,7 @@ static void arm1026_initfn(Object *obj) * ARMv5 does not have the ID_ISAR registers, but we can still * set the field to indicate Jazelle support within QEMU. */ - cpu->isar.id_isar1 =3D FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELL= E, 1); + FIELD_DP32_IDREG(&cpu->isar, ID_ISAR1, JAZELLE, 1); /* * Similarly, we need to set MVFR0 fields to enable vfp and short vect= or * support even though ARMv5 doesn't have this register. @@ -206,6 +207,7 @@ static void arm1026_initfn(Object *obj) static void arm1136_r2_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; /* * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an * older core than plain "arm1136". In particular this does not @@ -233,17 +235,18 @@ static void arm1136_r2_initfn(Object *obj) cpu->isar.id_mmfr0 =3D 0x01130003; cpu->isar.id_mmfr1 =3D 0x10030302; cpu->isar.id_mmfr2 =3D 0x01222110; - cpu->isar.id_isar0 =3D 0x00140011; - cpu->isar.id_isar1 =3D 0x12002111; - cpu->isar.id_isar2 =3D 0x11231111; - cpu->isar.id_isar3 =3D 0x01102131; - cpu->isar.id_isar4 =3D 0x141; + SET_IDREG(isar, ID_ISAR0, 0x00140011); + SET_IDREG(isar, ID_ISAR1, 0x12002111); + SET_IDREG(isar, ID_ISAR2, 0x11231111); + SET_IDREG(isar, ID_ISAR3, 0x01102131); + SET_IDREG(isar, ID_ISAR4, 0x141); cpu->reset_auxcr =3D 7; } =20 static void arm1136_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,arm1136"; set_feature(&cpu->env, ARM_FEATURE_V6K); @@ -264,17 +267,18 @@ static void arm1136_initfn(Object *obj) cpu->isar.id_mmfr0 =3D 0x01130003; cpu->isar.id_mmfr1 =3D 0x10030302; cpu->isar.id_mmfr2 =3D 0x01222110; - cpu->isar.id_isar0 =3D 0x00140011; - cpu->isar.id_isar1 =3D 0x12002111; - cpu->isar.id_isar2 =3D 0x11231111; - cpu->isar.id_isar3 =3D 0x01102131; - cpu->isar.id_isar4 =3D 0x141; + SET_IDREG(isar, ID_ISAR0, 0x00140011); + SET_IDREG(isar, ID_ISAR1, 0x12002111); + SET_IDREG(isar, ID_ISAR2, 0x11231111); + SET_IDREG(isar, ID_ISAR3, 0x01102131); + SET_IDREG(isar, ID_ISAR4, 0x141); cpu->reset_auxcr =3D 7; } =20 static void arm1176_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,arm1176"; set_feature(&cpu->env, ARM_FEATURE_V6K); @@ -296,17 +300,18 @@ static void arm1176_initfn(Object *obj) cpu->isar.id_mmfr0 =3D 0x01130003; cpu->isar.id_mmfr1 =3D 0x10030302; cpu->isar.id_mmfr2 =3D 0x01222100; - cpu->isar.id_isar0 =3D 0x0140011; - cpu->isar.id_isar1 =3D 0x12002111; - cpu->isar.id_isar2 =3D 0x11231121; - cpu->isar.id_isar3 =3D 0x01102131; - cpu->isar.id_isar4 =3D 0x01141; + SET_IDREG(isar, ID_ISAR0, 0x0140011); + SET_IDREG(isar, ID_ISAR1, 0x12002111); + SET_IDREG(isar, ID_ISAR2, 0x11231121); + SET_IDREG(isar, ID_ISAR3, 0x01102131); + SET_IDREG(isar, ID_ISAR4, 0x01141); cpu->reset_auxcr =3D 7; } =20 static void arm11mpcore_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,arm11mpcore"; set_feature(&cpu->env, ARM_FEATURE_V6K); @@ -325,11 +330,11 @@ static void arm11mpcore_initfn(Object *obj) cpu->isar.id_mmfr0 =3D 0x01100103; cpu->isar.id_mmfr1 =3D 0x10020302; cpu->isar.id_mmfr2 =3D 0x01222000; - cpu->isar.id_isar0 =3D 0x00100011; - cpu->isar.id_isar1 =3D 0x12002111; - cpu->isar.id_isar2 =3D 0x11221011; - cpu->isar.id_isar3 =3D 0x01102131; - cpu->isar.id_isar4 =3D 0x141; + SET_IDREG(isar, ID_ISAR0, 0x00100011); + SET_IDREG(isar, ID_ISAR1, 0x12002111); + SET_IDREG(isar, ID_ISAR2, 0x11221011); + SET_IDREG(isar, ID_ISAR3, 0x01102131); + SET_IDREG(isar, ID_ISAR4, 0x141); cpu->reset_auxcr =3D 1; } =20 @@ -343,6 +348,7 @@ static const ARMCPRegInfo cortexa8_cp_reginfo[] =3D { static void cortex_a8_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,cortex-a8"; set_feature(&cpu->env, ARM_FEATURE_V7); @@ -365,11 +371,11 @@ static void cortex_a8_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x20000000; cpu->isar.id_mmfr2 =3D 0x01202000; cpu->isar.id_mmfr3 =3D 0x11; - cpu->isar.id_isar0 =3D 0x00101111; - cpu->isar.id_isar1 =3D 0x12112111; - cpu->isar.id_isar2 =3D 0x21232031; - cpu->isar.id_isar3 =3D 0x11112131; - cpu->isar.id_isar4 =3D 0x00111142; + SET_IDREG(isar, ID_ISAR0, 0x00101111); + SET_IDREG(isar, ID_ISAR1, 0x12112111); + SET_IDREG(isar, ID_ISAR2, 0x21232031); + SET_IDREG(isar, ID_ISAR3, 0x11112131); + SET_IDREG(isar, ID_ISAR4, 0x00111142); cpu->isar.dbgdidr =3D 0x15141000; cpu->clidr =3D (1 << 27) | (2 << 24) | 3; cpu->ccsidr[0] =3D 0xe007e01a; /* 16k L1 dcache. */ @@ -412,6 +418,7 @@ static const ARMCPRegInfo cortexa9_cp_reginfo[] =3D { static void cortex_a9_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,cortex-a9"; set_feature(&cpu->env, ARM_FEATURE_V7); @@ -440,11 +447,11 @@ static void cortex_a9_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x20000000; cpu->isar.id_mmfr2 =3D 0x01230000; cpu->isar.id_mmfr3 =3D 0x00002111; - cpu->isar.id_isar0 =3D 0x00101111; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232041; - cpu->isar.id_isar3 =3D 0x11112131; - cpu->isar.id_isar4 =3D 0x00111142; + SET_IDREG(isar, ID_ISAR0, 0x00101111); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232041); + SET_IDREG(isar, ID_ISAR3, 0x11112131); + SET_IDREG(isar, ID_ISAR4, 0x00111142); cpu->isar.dbgdidr =3D 0x35141000; cpu->clidr =3D (1 << 27) | (1 << 24) | 3; cpu->ccsidr[0] =3D 0xe00fe019; /* 16k L1 dcache. */ @@ -479,6 +486,7 @@ static const ARMCPRegInfo cortexa15_cp_reginfo[] =3D { static void cortex_a7_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,cortex-a7"; set_feature(&cpu->env, ARM_FEATURE_V7VE); @@ -509,11 +517,11 @@ static void cortex_a7_initfn(Object *obj) * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but * table 4-41 gives 0x02101110, which includes the arm div insns. */ - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232041; - cpu->isar.id_isar3 =3D 0x11112131; - cpu->isar.id_isar4 =3D 0x10011142; + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232041); + SET_IDREG(isar, ID_ISAR3, 0x11112131); + SET_IDREG(isar, ID_ISAR4, 0x10011142); cpu->isar.dbgdidr =3D 0x3515f005; cpu->isar.dbgdevid =3D 0x01110f13; cpu->isar.dbgdevid1 =3D 0x1; @@ -528,6 +536,7 @@ static void cortex_a7_initfn(Object *obj) static void cortex_a15_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,cortex-a15"; set_feature(&cpu->env, ARM_FEATURE_V7VE); @@ -556,11 +565,11 @@ static void cortex_a15_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x20000000; cpu->isar.id_mmfr2 =3D 0x01240000; cpu->isar.id_mmfr3 =3D 0x02102211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232041; - cpu->isar.id_isar3 =3D 0x11112131; - cpu->isar.id_isar4 =3D 0x10011142; + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232041); + SET_IDREG(isar, ID_ISAR3, 0x11112131); + SET_IDREG(isar, ID_ISAR4, 0x10011142); cpu->isar.dbgdidr =3D 0x3515f021; cpu->isar.dbgdevid =3D 0x01110f13; cpu->isar.dbgdevid1 =3D 0x0; @@ -585,6 +594,7 @@ static const ARMCPRegInfo cortexr5_cp_reginfo[] =3D { static void cortex_r5_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 set_feature(&cpu->env, ARM_FEATURE_V7); set_feature(&cpu->env, ARM_FEATURE_V7MP); @@ -599,13 +609,13 @@ static void cortex_r5_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x00000000; cpu->isar.id_mmfr2 =3D 0x01200000; cpu->isar.id_mmfr3 =3D 0x0211; - cpu->isar.id_isar0 =3D 0x02101111; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232141; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x0010142; - cpu->isar.id_isar5 =3D 0x0; - cpu->isar.id_isar6 =3D 0x0; + SET_IDREG(isar, ID_ISAR0, 0x02101111); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232141); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x0010142); + SET_IDREG(isar, ID_ISAR5, 0x0); + SET_IDREG(isar, ID_ISAR6, 0x0); cpu->mp_is_up =3D true; cpu->pmsav7_dregion =3D 16; cpu->isar.reset_pmcr_el0 =3D 0x41151800; @@ -720,6 +730,7 @@ static const ARMCPRegInfo cortex_r52_cp_reginfo[] =3D { static void cortex_r52_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_EL2); @@ -746,12 +757,12 @@ static void cortex_r52_initfn(Object *obj) cpu->isar.id_mmfr2 =3D 0x01200000; cpu->isar.id_mmfr3 =3D 0xf0102211; cpu->isar.id_mmfr4 =3D 0x00000010; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232142; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00010142; - cpu->isar.id_isar5 =3D 0x00010001; + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232142); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00010142); + SET_IDREG(isar, ID_ISAR5, 0x00010001); cpu->isar.dbgdidr =3D 0x77168000; cpu->clidr =3D (1 << 27) | (1 << 24) | 0x3; cpu->ccsidr[0] =3D 0x700fe01a; /* 32KB L1 dcache */ @@ -949,6 +960,7 @@ static void pxa270c5_initfn(Object *obj) static void arm_max_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 /* aarch64_a57_initfn, advertising none of the aarch64 features */ cpu->dtb_compatible =3D "arm,cortex-a57"; @@ -976,13 +988,13 @@ static void arm_max_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02102211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00011142; - cpu->isar.id_isar5 =3D 0x00011121; - cpu->isar.id_isar6 =3D 0; + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232042); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00011142); + SET_IDREG(isar, ID_ISAR5, 0x00011121); + SET_IDREG(isar, ID_ISAR6, 0); cpu->isar.reset_pmcr_el0 =3D 0x41013000; cpu->clidr =3D 0x0a200023; cpu->ccsidr[0] =3D 0x701fe00a; /* 32KB L1 dcache */ diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 80a99ab025d..dd4dc8ada56 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -57,12 +57,12 @@ static void aarch64_a35_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02102211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00011142; - cpu->isar.id_isar5 =3D 0x00011121; + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232042); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00011142); + SET_IDREG(isar, ID_ISAR5, 0x00011121); SET_IDREG(isar, ID_AA64PFR0, 0x00002222); SET_IDREG(isar, ID_AA64PFR1, 0); SET_IDREG(isar, ID_AA64DFR0, 0x10305106); @@ -229,13 +229,13 @@ static void aarch64_a55_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_dfr0 =3D 0x04010088; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00011142; - cpu->isar.id_isar5 =3D 0x01011121; - cpu->isar.id_isar6 =3D 0x00000010; + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232042); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00011142); + SET_IDREG(isar, ID_ISAR5, 0x01011121); + SET_IDREG(isar, ID_ISAR6, 0x00000010); cpu->isar.id_mmfr0 =3D 0x10201105; cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; @@ -303,12 +303,12 @@ static void aarch64_a72_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02102211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00011142; - cpu->isar.id_isar5 =3D 0x00011121; + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232042); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00011142); + SET_IDREG(isar, ID_ISAR5, 0x00011121); SET_IDREG(isar, ID_AA64PFR0, 0x00002222); SET_IDREG(isar, ID_AA64DFR0, 0x10305106); SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); @@ -362,13 +362,13 @@ static void aarch64_a76_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_dfr0 =3D 0x04010088; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00010142; - cpu->isar.id_isar5 =3D 0x01011121; - cpu->isar.id_isar6 =3D 0x00000010; + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232042); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00010142); + SET_IDREG(isar, ID_ISAR5, 0x01011121); + SET_IDREG(isar, ID_ISAR6, 0x00000010); cpu->isar.id_mmfr0 =3D 0x10201105; cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; @@ -610,13 +610,13 @@ static void aarch64_neoverse_n1_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_dfr0 =3D 0x04010088; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00010142; - cpu->isar.id_isar5 =3D 0x01011121; - cpu->isar.id_isar6 =3D 0x00000010; + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232042); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00010142); + SET_IDREG(isar, ID_ISAR5, 0x01011121); + SET_IDREG(isar, ID_ISAR6, 0x00000010); cpu->isar.id_mmfr0 =3D 0x10201105; cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; @@ -689,13 +689,13 @@ static void aarch64_neoverse_v1_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_dfr0 =3D 0x15011099; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00010142; - cpu->isar.id_isar5 =3D 0x11011121; - cpu->isar.id_isar6 =3D 0x01100111; + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232042); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00010142); + SET_IDREG(isar, ID_ISAR5, 0x11011121); + SET_IDREG(isar, ID_ISAR6, 0x01100111); cpu->isar.id_mmfr0 =3D 0x10201105; cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; @@ -910,14 +910,14 @@ static void aarch64_a710_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02122211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00010142; - cpu->isar.id_isar5 =3D 0x11011121; /* with Crypto */ + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232042); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00010142); + SET_IDREG(isar, ID_ISAR5, 0x11011121); /* with Crypto */ cpu->isar.id_mmfr4 =3D 0x21021110; - cpu->isar.id_isar6 =3D 0x01111111; + SET_IDREG(isar, ID_ISAR6, 0x01111111); cpu->isar.mvfr0 =3D 0x10110222; cpu->isar.mvfr1 =3D 0x13211111; cpu->isar.mvfr2 =3D 0x00000043; @@ -1012,14 +1012,14 @@ static void aarch64_neoverse_n2_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02122211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00010142; - cpu->isar.id_isar5 =3D 0x11011121; /* with Crypto */ + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232042); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00010142); + SET_IDREG(isar, ID_ISAR5, 0x11011121); /* with Crypto */ cpu->isar.id_mmfr4 =3D 0x01021110; - cpu->isar.id_isar6 =3D 0x01111111; + SET_IDREG(isar, ID_ISAR6, 0x01111111); cpu->isar.mvfr0 =3D 0x10110222; cpu->isar.mvfr1 =3D 0x13211111; cpu->isar.mvfr2 =3D 0x00000043; --=20 2.43.0 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1751389835; cv=none; d=zohomail.com; s=zohoarc; b=BaaIeHPuOK803nc1YV5W2qUEoKTJ/guFhiQsJud258x+gO7XOVhFc5WAP/d6NPFfmbVQI64yCIetmCr8W0IZBQs75yeBfbbR0NaubmAIa0Q8E6hR3n3MLVkuPU0vdkGWUobySFfgOTLrtW+haw3GPgOy4tZEwthg9n9vrtQBZTE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751389835; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; 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Tue, 01 Jul 2025 10:07:34 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/43] arm/cpu: Store id_pfr0/1/2 into the idregs array Date: Tue, 1 Jul 2025 18:06:47 +0100 Message-ID: <20250701170720.4072660-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751389838258116600 Content-Type: text/plain; charset="utf-8" From: Eric Auger Reviewed-by: Richard Henderson Reviewed-by: Sebastian Ott Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck Message-id: 20250617153931.1330449-10-cohuck@redhat.com Signed-off-by: Peter Maydell --- target/arm/cpu-features.h | 10 ++++---- target/arm/cpu.h | 3 --- hw/intc/armv7m_nvic.c | 5 ++-- target/arm/cpu.c | 8 +++--- target/arm/cpu64.c | 8 +++--- target/arm/helper.c | 8 +++--- target/arm/kvm.c | 9 +++---- target/arm/tcg/cpu-v7m.c | 24 +++++++++--------- target/arm/tcg/cpu32.c | 52 +++++++++++++++++++-------------------- target/arm/tcg/cpu64.c | 44 ++++++++++++++++----------------- 10 files changed, 82 insertions(+), 89 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 75a2cc40779..a34378577f0 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -137,12 +137,12 @@ static inline bool isar_feature_aa32_i8mm(const ARMIS= ARegisters *id) =20 static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) { - return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) !=3D 0; + return FIELD_EX32_IDREG(id, ID_PFR0, RAS) !=3D 0; } =20 static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id) { - return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) !=3D 0; + return FIELD_EX32_IDREG(id, ID_PFR1, MPROGMOD) !=3D 0; } =20 static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id) @@ -151,7 +151,7 @@ static inline bool isar_feature_aa32_m_sec_state(const = ARMISARegisters *id) * Return true if M-profile state handling insns * (VSCCLRM, CLRM, FPCTX access insns) are implemented */ - return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >=3D 3; + return FIELD_EX32_IDREG(id, ID_PFR1, SECURITY) >=3D 3; } =20 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) @@ -350,12 +350,12 @@ static inline bool isar_feature_aa32_evt(const ARMISA= Registers *id) =20 static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) { - return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) !=3D 0; + return FIELD_EX32_IDREG(id, ID_PFR0, DIT) !=3D 0; } =20 static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id) { - return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) !=3D 0; + return FIELD_EX32_IDREG(id, ID_PFR2, SSBS) !=3D 0; } =20 static inline bool isar_feature_aa32_debugv7p1(const ARMISARegisters *id) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 353c18e6799..30401926e11 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1056,9 +1056,6 @@ struct ArchCPU { uint32_t id_mmfr3; uint32_t id_mmfr4; uint32_t id_mmfr5; - uint32_t id_pfr0; - uint32_t id_pfr1; - uint32_t id_pfr2; uint32_t mvfr0; uint32_t mvfr1; uint32_t mvfr2; diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index fdb7f58e367..330205fa342 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -988,6 +988,7 @@ static void nvic_nmi_trigger(void *opaque, int n, int l= evel) static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) { ARMCPU *cpu =3D s->cpu; + ARMISARegisters *isar =3D &cpu->isar; uint32_t val; =20 switch (offset) { @@ -1263,12 +1264,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t o= ffset, MemTxAttrs attrs) if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_pfr0; + return GET_IDREG(isar, ID_PFR0); case 0xd44: /* PFR1. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_pfr1; + return GET_IDREG(isar, ID_PFR1); case 0xd48: /* DFR0. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index cf811e47d99..62c06c7269c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2317,7 +2317,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * Disable the security extension feature bits in the processor * feature registers as well. */ - cpu->isar.id_pfr1 =3D FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECUR= ITY, 0); + FIELD_DP32_IDREG(isar, ID_PFR1, SECURITY, 0); cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSD= BG, 0); FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL3, 0); =20 @@ -2357,8 +2357,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * registers if we don't have EL2. */ FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL2, 0); - cpu->isar.id_pfr1 =3D FIELD_DP32(cpu->isar.id_pfr1, - ID_PFR1, VIRTUALIZATION, 0); + FIELD_DP32_IDREG(isar, ID_PFR1, VIRTUALIZATION, 0); } =20 if (cpu_isar_feature(aa64_mte, cpu)) { @@ -2421,8 +2420,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0); /* FEAT_AMU (Activity Monitors Extension) */ FIELD_DP64_IDREG(isar, ID_AA64PFR0, AMU, 0); - cpu->isar.id_pfr0 =3D - FIELD_DP32(cpu->isar.id_pfr0, ID_PFR0, AMU, 0); + FIELD_DP32_IDREG(isar, ID_PFR0, AMU, 0); /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */ FIELD_DP64_IDREG(isar, ID_AA64PFR0, MPAM, 0); } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 6be62c0711b..5b628aa7ebf 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -652,8 +652,8 @@ static void aarch64_a57_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000043; cpu->ctr =3D 0x8444c004; cpu->reset_sctlr =3D 0x00c50838; - cpu->isar.id_pfr0 =3D 0x00000131; - cpu->isar.id_pfr1 =3D 0x00011011; + SET_IDREG(isar, ID_PFR0, 0x00000131); + SET_IDREG(isar, ID_PFR1, 0x00011011); cpu->isar.id_dfr0 =3D 0x03010066; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10101105; @@ -714,8 +714,8 @@ static void aarch64_a53_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000043; cpu->ctr =3D 0x84448004; /* L1Ip =3D VIPT */ cpu->reset_sctlr =3D 0x00c50838; - cpu->isar.id_pfr0 =3D 0x00000131; - cpu->isar.id_pfr1 =3D 0x00011011; + SET_IDREG(isar, ID_PFR0, 0x00000131); + SET_IDREG(isar, ID_PFR1, 0x00011011); cpu->isar.id_dfr0 =3D 0x03010066; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10101105; diff --git a/target/arm/helper.c b/target/arm/helper.c index 7e0b3f164e1..03299238224 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6932,7 +6932,7 @@ static void define_pmu_regs(ARMCPU *cpu) static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) { ARMCPU *cpu =3D env_archcpu(env); - uint64_t pfr1 =3D cpu->isar.id_pfr1; + uint64_t pfr1 =3D GET_IDREG(&cpu->isar, ID_PFR1); =20 if (env->gicv3state) { pfr1 |=3D 1 << 28; @@ -7777,7 +7777,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_pfr0 }, + .resetvalue =3D GET_IDREG(isar, ID_PFR0)}, /* * ID_PFR1 is not a plain ARM_CP_CONST because we don't know * the value of the GIC field until after we define these regs. @@ -7788,7 +7788,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .accessfn =3D access_aa32_tid3, #ifdef CONFIG_USER_ONLY .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->isar.id_pfr1, + .resetvalue =3D GET_IDREG(isar, ID_PFR1), #else .type =3D ARM_CP_NO_RAW, .accessfn =3D access_aa32_tid3, @@ -8130,7 +8130,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_pfr2 }, + .resetvalue =3D GET_IDREG(isar, ID_PFR2)}, { .name =3D "ID_DFR1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/kvm.c b/target/arm/kvm.c index eef9481737b..d945e652b3e 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -332,10 +332,8 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFe= atures *ahcf) * than skipping the reads and leaving 0, as we must avoid * considering the values in every case. */ - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr0, - ARM64_SYS_REG(3, 0, 0, 1, 0)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr1, - ARM64_SYS_REG(3, 0, 0, 1, 1)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_PFR0_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_PFR1_EL1_IDX); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0, ARM64_SYS_REG(3, 0, 0, 1, 2)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0, @@ -362,8 +360,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) ARM64_SYS_REG(3, 0, 0, 3, 1)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2, ARM64_SYS_REG(3, 0, 0, 3, 2)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr2, - ARM64_SYS_REG(3, 0, 0, 3, 4)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_PFR2_EL1_IDX); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr1, ARM64_SYS_REG(3, 0, 0, 3, 5)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr5, diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 198c9f3e98c..4a2c3bd01a3 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -59,8 +59,8 @@ static void cortex_m0_initfn(Object *obj) * by looking at ID register fields. We use the same values as * for the M3. */ - cpu->isar.id_pfr0 =3D 0x00000030; - cpu->isar.id_pfr1 =3D 0x00000200; + SET_IDREG(isar, ID_PFR0, 0x00000030); + SET_IDREG(isar, ID_PFR1, 0x00000200); cpu->isar.id_dfr0 =3D 0x00100000; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00000030; @@ -85,8 +85,8 @@ static void cortex_m3_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_M_MAIN); cpu->midr =3D 0x410fc231; cpu->pmsav7_dregion =3D 8; - cpu->isar.id_pfr0 =3D 0x00000030; - cpu->isar.id_pfr1 =3D 0x00000200; + SET_IDREG(isar, ID_PFR0, 0x00000030); + SET_IDREG(isar, ID_PFR1, 0x00000200); cpu->isar.id_dfr0 =3D 0x00100000; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00000030; @@ -116,8 +116,8 @@ static void cortex_m4_initfn(Object *obj) cpu->isar.mvfr0 =3D 0x10110021; cpu->isar.mvfr1 =3D 0x11000011; cpu->isar.mvfr2 =3D 0x00000000; - cpu->isar.id_pfr0 =3D 0x00000030; - cpu->isar.id_pfr1 =3D 0x00000200; + SET_IDREG(isar, ID_PFR0, 0x00000030); + SET_IDREG(isar, ID_PFR1, 0x00000200); cpu->isar.id_dfr0 =3D 0x00100000; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00000030; @@ -147,8 +147,8 @@ static void cortex_m7_initfn(Object *obj) cpu->isar.mvfr0 =3D 0x10110221; cpu->isar.mvfr1 =3D 0x12000011; cpu->isar.mvfr2 =3D 0x00000040; - cpu->isar.id_pfr0 =3D 0x00000030; - cpu->isar.id_pfr1 =3D 0x00000200; + SET_IDREG(isar, ID_PFR0, 0x00000030); + SET_IDREG(isar, ID_PFR1, 0x00000200); cpu->isar.id_dfr0 =3D 0x00100000; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00100030; @@ -180,8 +180,8 @@ static void cortex_m33_initfn(Object *obj) cpu->isar.mvfr0 =3D 0x10110021; cpu->isar.mvfr1 =3D 0x11000011; cpu->isar.mvfr2 =3D 0x00000040; - cpu->isar.id_pfr0 =3D 0x00000030; - cpu->isar.id_pfr1 =3D 0x00000210; + SET_IDREG(isar, ID_PFR0, 0x00000030); + SET_IDREG(isar, ID_PFR1, 0x00000210); cpu->isar.id_dfr0 =3D 0x00200000; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00101F40; @@ -218,8 +218,8 @@ static void cortex_m55_initfn(Object *obj) cpu->isar.mvfr0 =3D 0x10110221; cpu->isar.mvfr1 =3D 0x12100211; cpu->isar.mvfr2 =3D 0x00000040; - cpu->isar.id_pfr0 =3D 0x20000030; - cpu->isar.id_pfr1 =3D 0x00000230; + SET_IDREG(isar, ID_PFR0, 0x20000030); + SET_IDREG(isar, ID_PFR1, 0x00000230); cpu->isar.id_dfr0 =3D 0x10200000; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00111040; diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 937a72b12c9..56374db2692 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -71,16 +71,16 @@ void aa32_max_features(ARMCPU *cpu) t =3D FIELD_DP32(t, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */ cpu->isar.id_mmfr5 =3D t; =20 - t =3D cpu->isar.id_pfr0; + t =3D GET_IDREG(isar, ID_PFR0); t =3D FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */ t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ t =3D FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ - cpu->isar.id_pfr0 =3D t; + SET_IDREG(isar, ID_PFR0, t); =20 - t =3D cpu->isar.id_pfr2; + t =3D GET_IDREG(isar, ID_PFR2); t =3D FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */ t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ - cpu->isar.id_pfr2 =3D t; + SET_IDREG(isar, ID_PFR2, t); =20 t =3D cpu->isar.id_dfr0; t =3D FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */ @@ -228,8 +228,8 @@ static void arm1136_r2_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x00000000; cpu->ctr =3D 0x1dd20d2; cpu->reset_sctlr =3D 0x00050078; - cpu->isar.id_pfr0 =3D 0x111; - cpu->isar.id_pfr1 =3D 0x1; + SET_IDREG(isar, ID_PFR0, 0x111); + SET_IDREG(isar, ID_PFR1, 0x1); cpu->isar.id_dfr0 =3D 0x2; cpu->id_afr0 =3D 0x3; cpu->isar.id_mmfr0 =3D 0x01130003; @@ -260,8 +260,8 @@ static void arm1136_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x00000000; cpu->ctr =3D 0x1dd20d2; cpu->reset_sctlr =3D 0x00050078; - cpu->isar.id_pfr0 =3D 0x111; - cpu->isar.id_pfr1 =3D 0x1; + SET_IDREG(isar, ID_PFR0, 0x111); + SET_IDREG(isar, ID_PFR1, 0x1); cpu->isar.id_dfr0 =3D 0x2; cpu->id_afr0 =3D 0x3; cpu->isar.id_mmfr0 =3D 0x01130003; @@ -293,8 +293,8 @@ static void arm1176_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x00000000; cpu->ctr =3D 0x1dd20d2; cpu->reset_sctlr =3D 0x00050078; - cpu->isar.id_pfr0 =3D 0x111; - cpu->isar.id_pfr1 =3D 0x11; + SET_IDREG(isar, ID_PFR0, 0x111); + SET_IDREG(isar, ID_PFR1, 0x11); cpu->isar.id_dfr0 =3D 0x33; cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x01130003; @@ -323,8 +323,8 @@ static void arm11mpcore_initfn(Object *obj) cpu->isar.mvfr0 =3D 0x11111111; cpu->isar.mvfr1 =3D 0x00000000; cpu->ctr =3D 0x1d192992; /* 32K icache 32K dcache */ - cpu->isar.id_pfr0 =3D 0x111; - cpu->isar.id_pfr1 =3D 0x1; + SET_IDREG(isar, ID_PFR0, 0x111); + SET_IDREG(isar, ID_PFR1, 0x1); cpu->isar.id_dfr0 =3D 0; cpu->id_afr0 =3D 0x2; cpu->isar.id_mmfr0 =3D 0x01100103; @@ -363,8 +363,8 @@ static void cortex_a8_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x00011111; cpu->ctr =3D 0x82048004; cpu->reset_sctlr =3D 0x00c50078; - cpu->isar.id_pfr0 =3D 0x1031; - cpu->isar.id_pfr1 =3D 0x11; + SET_IDREG(isar, ID_PFR0, 0x1031); + SET_IDREG(isar, ID_PFR1, 0x11); cpu->isar.id_dfr0 =3D 0x400; cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x31100003; @@ -439,8 +439,8 @@ static void cortex_a9_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x01111111; cpu->ctr =3D 0x80038003; cpu->reset_sctlr =3D 0x00c50078; - cpu->isar.id_pfr0 =3D 0x1031; - cpu->isar.id_pfr1 =3D 0x11; + SET_IDREG(isar, ID_PFR0, 0x1031); + SET_IDREG(isar, ID_PFR1, 0x11); cpu->isar.id_dfr0 =3D 0x000; cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x00100103; @@ -505,8 +505,8 @@ static void cortex_a7_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x11111111; cpu->ctr =3D 0x84448003; cpu->reset_sctlr =3D 0x00c50078; - cpu->isar.id_pfr0 =3D 0x00001131; - cpu->isar.id_pfr1 =3D 0x00011011; + SET_IDREG(isar, ID_PFR0, 0x00001131); + SET_IDREG(isar, ID_PFR1, 0x00011011); cpu->isar.id_dfr0 =3D 0x02010555; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10101105; @@ -557,8 +557,8 @@ static void cortex_a15_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x11111111; cpu->ctr =3D 0x8444c004; cpu->reset_sctlr =3D 0x00c50078; - cpu->isar.id_pfr0 =3D 0x00001131; - cpu->isar.id_pfr1 =3D 0x00011011; + SET_IDREG(isar, ID_PFR0, 0x00001131); + SET_IDREG(isar, ID_PFR1, 0x00011011); cpu->isar.id_dfr0 =3D 0x02010555; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10201105; @@ -601,8 +601,8 @@ static void cortex_r5_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_PMSA); set_feature(&cpu->env, ARM_FEATURE_PMU); cpu->midr =3D 0x411fc153; /* r1p3 */ - cpu->isar.id_pfr0 =3D 0x0131; - cpu->isar.id_pfr1 =3D 0x001; + SET_IDREG(isar, ID_PFR0, 0x0131); + SET_IDREG(isar, ID_PFR1, 0x001); cpu->isar.id_dfr0 =3D 0x010400; cpu->id_afr0 =3D 0x0; cpu->isar.id_mmfr0 =3D 0x0210030; @@ -748,8 +748,8 @@ static void cortex_r52_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000043; cpu->ctr =3D 0x8144c004; cpu->reset_sctlr =3D 0x30c50838; - cpu->isar.id_pfr0 =3D 0x00000131; - cpu->isar.id_pfr1 =3D 0x10111001; + SET_IDREG(isar, ID_PFR0, 0x00000131); + SET_IDREG(isar, ID_PFR1, 0x10111001); cpu->isar.id_dfr0 =3D 0x03010006; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00211040; @@ -980,8 +980,8 @@ static void arm_max_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000043; cpu->ctr =3D 0x8444c004; cpu->reset_sctlr =3D 0x00c50838; - cpu->isar.id_pfr0 =3D 0x00000131; - cpu->isar.id_pfr1 =3D 0x00011011; + SET_IDREG(isar, ID_PFR0, 0x00000131); + SET_IDREG(isar, ID_PFR1, 0x00011011); cpu->isar.id_dfr0 =3D 0x03010066; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10101105; diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index dd4dc8ada56..c3f90e9d135 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -49,8 +49,8 @@ static void aarch64_a35_initfn(Object *obj) cpu->midr =3D 0x411fd040; cpu->revidr =3D 0; cpu->ctr =3D 0x84448004; - cpu->isar.id_pfr0 =3D 0x00000131; - cpu->isar.id_pfr1 =3D 0x00011011; + SET_IDREG(isar, ID_PFR0, 0x00000131); + SET_IDREG(isar, ID_PFR1, 0x00011011); cpu->isar.id_dfr0 =3D 0x03010066; cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x10201105; @@ -241,9 +241,9 @@ static void aarch64_a55_initfn(Object *obj) cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02122211; cpu->isar.id_mmfr4 =3D 0x00021110; - cpu->isar.id_pfr0 =3D 0x10010131; - cpu->isar.id_pfr1 =3D 0x00011011; - cpu->isar.id_pfr2 =3D 0x00000011; + SET_IDREG(isar, ID_PFR0, 0x10010131); + SET_IDREG(isar, ID_PFR1, 0x00011011); + SET_IDREG(isar, ID_PFR2, 0x00000011); cpu->midr =3D 0x412FD050; /* r2p0 */ cpu->revidr =3D 0; =20 @@ -295,8 +295,8 @@ static void aarch64_a72_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000043; cpu->ctr =3D 0x8444c004; cpu->reset_sctlr =3D 0x00c50838; - cpu->isar.id_pfr0 =3D 0x00000131; - cpu->isar.id_pfr1 =3D 0x00011011; + SET_IDREG(isar, ID_PFR0, 0x00000131); + SET_IDREG(isar, ID_PFR1, 0x00011011); cpu->isar.id_dfr0 =3D 0x03010066; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10201105; @@ -374,9 +374,9 @@ static void aarch64_a76_initfn(Object *obj) cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02122211; cpu->isar.id_mmfr4 =3D 0x00021110; - cpu->isar.id_pfr0 =3D 0x10010131; - cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ - cpu->isar.id_pfr2 =3D 0x00000011; + SET_IDREG(isar, ID_PFR0, 0x10010131); + SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ + SET_IDREG(isar, ID_PFR2, 0x00000011); cpu->midr =3D 0x414fd0b1; /* r4p1 */ cpu->revidr =3D 0; =20 @@ -622,9 +622,9 @@ static void aarch64_neoverse_n1_initfn(Object *obj) cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02122211; cpu->isar.id_mmfr4 =3D 0x00021110; - cpu->isar.id_pfr0 =3D 0x10010131; - cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ - cpu->isar.id_pfr2 =3D 0x00000011; + SET_IDREG(isar, ID_PFR0, 0x10010131); + SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ + SET_IDREG(isar, ID_PFR2, 0x00000011); cpu->midr =3D 0x414fd0c1; /* r4p1 */ cpu->revidr =3D 0; =20 @@ -701,9 +701,9 @@ static void aarch64_neoverse_v1_initfn(Object *obj) cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02122211; cpu->isar.id_mmfr4 =3D 0x01021110; - cpu->isar.id_pfr0 =3D 0x21110131; - cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ - cpu->isar.id_pfr2 =3D 0x00000011; + SET_IDREG(isar, ID_PFR0, 0x21110131); + SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ + SET_IDREG(isar, ID_PFR2, 0x00000011); cpu->midr =3D 0x411FD402; /* r1p2 */ cpu->revidr =3D 0; =20 @@ -902,8 +902,8 @@ static void aarch64_a710_initfn(Object *obj) /* Ordered by Section B.4: AArch64 registers */ cpu->midr =3D 0x412FD471; /* r2p1 */ cpu->revidr =3D 0; - cpu->isar.id_pfr0 =3D 0x21110131; - cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ + SET_IDREG(isar, ID_PFR0, 0x21110131); + SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ cpu->isar.id_dfr0 =3D 0x16011099; cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x10201105; @@ -921,7 +921,7 @@ static void aarch64_a710_initfn(Object *obj) cpu->isar.mvfr0 =3D 0x10110222; cpu->isar.mvfr1 =3D 0x13211111; cpu->isar.mvfr2 =3D 0x00000043; - cpu->isar.id_pfr2 =3D 0x00000011; + SET_IDREG(isar, ID_PFR2, 0x00000011); SET_IDREG(isar, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in = later */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000221ull); SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */ @@ -1004,8 +1004,8 @@ static void aarch64_neoverse_n2_initfn(Object *obj) /* Ordered by Section B.5: AArch64 ID registers */ cpu->midr =3D 0x410FD493; /* r0p3 */ cpu->revidr =3D 0; - cpu->isar.id_pfr0 =3D 0x21110131; - cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ + SET_IDREG(isar, ID_PFR0, 0x21110131); + SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ cpu->isar.id_dfr0 =3D 0x16011099; cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x10201105; @@ -1023,7 +1023,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj) cpu->isar.mvfr0 =3D 0x10110222; cpu->isar.mvfr1 =3D 0x13211111; cpu->isar.mvfr2 =3D 0x00000043; - cpu->isar.id_pfr2 =3D 0x00000011; + SET_IDREG(isar, ID_PFR2, 0x00000011); SET_IDREG(isar, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in = later */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000221ull); SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */ --=20 2.43.0 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 01 Jul 2025 10:07:35 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/43] arm/cpu: Store id_dfr0/1 into the idregs array Date: Tue, 1 Jul 2025 18:06:48 +0100 Message-ID: <20250701170720.4072660-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751389918921116600 Content-Type: text/plain; charset="utf-8" From: Eric Auger Reviewed-by: Richard Henderson Reviewed-by: Sebastian Ott Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck Message-id: 20250617153931.1330449-11-cohuck@redhat.com Signed-off-by: Peter Maydell --- target/arm/cpu-features.h | 16 ++++++++-------- target/arm/cpu.h | 2 -- hw/intc/armv7m_nvic.c | 2 +- target/arm/cpu.c | 13 +++++-------- target/arm/cpu64.c | 4 ++-- target/arm/helper.c | 4 ++-- target/arm/kvm.c | 6 ++---- target/arm/tcg/cpu-v7m.c | 12 ++++++------ target/arm/tcg/cpu32.c | 30 ++++++++++++++---------------- target/arm/tcg/cpu64.c | 16 ++++++++-------- 10 files changed, 48 insertions(+), 57 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index a34378577f0..0292a7cd6ec 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -300,22 +300,22 @@ static inline bool isar_feature_aa32_ats1e1(const ARM= ISARegisters *id) static inline bool isar_feature_aa32_pmuv3p1(const ARMISARegisters *id) { /* 0xf means "non-standard IMPDEF PMU" */ - return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >=3D 4 && - FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) !=3D 0xf; + return FIELD_EX32_IDREG(id, ID_DFR0, PERFMON) >=3D 4 && + FIELD_EX32_IDREG(id, ID_DFR0, PERFMON) !=3D 0xf; } =20 static inline bool isar_feature_aa32_pmuv3p4(const ARMISARegisters *id) { /* 0xf means "non-standard IMPDEF PMU" */ - return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >=3D 5 && - FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) !=3D 0xf; + return FIELD_EX32_IDREG(id, ID_DFR0, PERFMON) >=3D 5 && + FIELD_EX32_IDREG(id, ID_DFR0, PERFMON) !=3D 0xf; } =20 static inline bool isar_feature_aa32_pmuv3p5(const ARMISARegisters *id) { /* 0xf means "non-standard IMPDEF PMU" */ - return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >=3D 6 && - FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) !=3D 0xf; + return FIELD_EX32_IDREG(id, ID_DFR0, PERFMON) >=3D 6 && + FIELD_EX32_IDREG(id, ID_DFR0, PERFMON) !=3D 0xf; } =20 static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) @@ -360,12 +360,12 @@ static inline bool isar_feature_aa32_ssbs(const ARMIS= ARegisters *id) =20 static inline bool isar_feature_aa32_debugv7p1(const ARMISARegisters *id) { - return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >=3D 5; + return FIELD_EX32_IDREG(id, ID_DFR0, COPDBG) >=3D 5; } =20 static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id) { - return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >=3D 8; + return FIELD_EX32_IDREG(id, ID_DFR0, COPDBG) >=3D 8; } =20 static inline bool isar_feature_aa32_doublelock(const ARMISARegisters *id) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 30401926e11..c799105eeb2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1059,8 +1059,6 @@ struct ArchCPU { uint32_t mvfr0; uint32_t mvfr1; uint32_t mvfr2; - uint32_t id_dfr0; - uint32_t id_dfr1; uint32_t dbgdidr; uint32_t dbgdevid; uint32_t dbgdevid1; diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 330205fa342..2566dd63431 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1274,7 +1274,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t off= set, MemTxAttrs attrs) if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_dfr0; + return GET_IDREG(isar, ID_DFR0); case 0xd4c: /* AFR0. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 62c06c7269c..8e77414c2b9 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2318,7 +2318,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * feature registers as well. */ FIELD_DP32_IDREG(isar, ID_PFR1, SECURITY, 0); - cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSD= BG, 0); + FIELD_DP32_IDREG(isar, ID_DFR0, COPSDBG, 0); FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL3, 0); =20 /* Disable the realm management extension, which requires EL3. */ @@ -2346,7 +2346,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) #endif } else { FIELD_DP64_IDREG(isar, ID_AA64DFR0, PMUVER, 0); - cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFM= ON, 0); + FIELD_DP32_IDREG(isar, ID_DFR0, PERFMON, 0); cpu->pmceid0 =3D 0; cpu->pmceid1 =3D 0; } @@ -2409,15 +2409,12 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEBUFFER, 0); /* FEAT_TRF (Self-hosted Trace Extension) */ FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEFILT, 0); - cpu->isar.id_dfr0 =3D - FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, TRACEFILT, 0); + FIELD_DP32_IDREG(isar, ID_DFR0, TRACEFILT, 0); /* Trace Macrocell system register access */ FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEVER, 0); - cpu->isar.id_dfr0 =3D - FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPTRC, 0); + FIELD_DP32_IDREG(isar, ID_DFR0, COPTRC, 0); /* Memory mapped trace */ - cpu->isar.id_dfr0 =3D - FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0); + FIELD_DP32_IDREG(isar, ID_DFR0, MMAPTRC, 0); /* FEAT_AMU (Activity Monitors Extension) */ FIELD_DP64_IDREG(isar, ID_AA64PFR0, AMU, 0); FIELD_DP32_IDREG(isar, ID_PFR0, AMU, 0); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 5b628aa7ebf..47c2eed3c99 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -654,7 +654,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50838; SET_IDREG(isar, ID_PFR0, 0x00000131); SET_IDREG(isar, ID_PFR1, 0x00011011); - cpu->isar.id_dfr0 =3D 0x03010066; + SET_IDREG(isar, ID_DFR0, 0x03010066); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10101105; cpu->isar.id_mmfr1 =3D 0x40000000; @@ -716,7 +716,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50838; SET_IDREG(isar, ID_PFR0, 0x00000131); SET_IDREG(isar, ID_PFR1, 0x00011011); - cpu->isar.id_dfr0 =3D 0x03010066; + SET_IDREG(isar, ID_DFR0, 0x03010066); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10101105; cpu->isar.id_mmfr1 =3D 0x40000000; diff --git a/target/arm/helper.c b/target/arm/helper.c index 03299238224..4d90ff7fd51 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7800,7 +7800,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_dfr0 }, + .resetvalue =3D GET_IDREG(isar, ID_DFR0)}, { .name =3D "ID_AFR0", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 3, .access =3D PL1_R, .type =3D ARM_CP_CONST, @@ -8135,7 +8135,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_dfr1 }, + .resetvalue =3D GET_IDREG(isar, ID_DFR1)}, { .name =3D "ID_MMFR5", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/kvm.c b/target/arm/kvm.c index d945e652b3e..2a6a5329b43 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -334,8 +334,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) */ err |=3D get_host_cpu_reg(fd, ahcf, ID_PFR0_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_PFR1_EL1_IDX); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0, - ARM64_SYS_REG(3, 0, 0, 1, 2)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_DFR0_EL1_IDX); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0, ARM64_SYS_REG(3, 0, 0, 1, 4)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1, @@ -361,8 +360,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2, ARM64_SYS_REG(3, 0, 0, 3, 2)); err |=3D get_host_cpu_reg(fd, ahcf, ID_PFR2_EL1_IDX); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr1, - ARM64_SYS_REG(3, 0, 0, 3, 5)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_DFR1_EL1_IDX); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr5, ARM64_SYS_REG(3, 0, 0, 3, 6)); =20 diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 4a2c3bd01a3..9697c362c19 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -61,7 +61,7 @@ static void cortex_m0_initfn(Object *obj) */ SET_IDREG(isar, ID_PFR0, 0x00000030); SET_IDREG(isar, ID_PFR1, 0x00000200); - cpu->isar.id_dfr0 =3D 0x00100000; + SET_IDREG(isar, ID_DFR0, 0x00100000); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00000030; cpu->isar.id_mmfr1 =3D 0x00000000; @@ -87,7 +87,7 @@ static void cortex_m3_initfn(Object *obj) cpu->pmsav7_dregion =3D 8; SET_IDREG(isar, ID_PFR0, 0x00000030); SET_IDREG(isar, ID_PFR1, 0x00000200); - cpu->isar.id_dfr0 =3D 0x00100000; + SET_IDREG(isar, ID_DFR0, 0x00100000); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00000030; cpu->isar.id_mmfr1 =3D 0x00000000; @@ -118,7 +118,7 @@ static void cortex_m4_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000000; SET_IDREG(isar, ID_PFR0, 0x00000030); SET_IDREG(isar, ID_PFR1, 0x00000200); - cpu->isar.id_dfr0 =3D 0x00100000; + SET_IDREG(isar, ID_DFR0, 0x00100000); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00000030; cpu->isar.id_mmfr1 =3D 0x00000000; @@ -149,7 +149,7 @@ static void cortex_m7_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000040; SET_IDREG(isar, ID_PFR0, 0x00000030); SET_IDREG(isar, ID_PFR1, 0x00000200); - cpu->isar.id_dfr0 =3D 0x00100000; + SET_IDREG(isar, ID_DFR0, 0x00100000); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00100030; cpu->isar.id_mmfr1 =3D 0x00000000; @@ -182,7 +182,7 @@ static void cortex_m33_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000040; SET_IDREG(isar, ID_PFR0, 0x00000030); SET_IDREG(isar, ID_PFR1, 0x00000210); - cpu->isar.id_dfr0 =3D 0x00200000; + SET_IDREG(isar, ID_DFR0, 0x00200000); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00101F40; cpu->isar.id_mmfr1 =3D 0x00000000; @@ -220,7 +220,7 @@ static void cortex_m55_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000040; SET_IDREG(isar, ID_PFR0, 0x20000030); SET_IDREG(isar, ID_PFR1, 0x00000230); - cpu->isar.id_dfr0 =3D 0x10200000; + SET_IDREG(isar, ID_DFR0, 0x10200000); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00111040; cpu->isar.id_mmfr1 =3D 0x00000000; diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 56374db2692..bec69fe52e4 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -82,11 +82,11 @@ void aa32_max_features(ARMCPU *cpu) t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ SET_IDREG(isar, ID_PFR2, t); =20 - t =3D cpu->isar.id_dfr0; + t =3D GET_IDREG(isar, ID_DFR0); t =3D FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */ t =3D FIELD_DP32(t, ID_DFR0, COPSDBG, 10); /* FEAT_Debugv8p8 */ t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */ - cpu->isar.id_dfr0 =3D t; + SET_IDREG(isar, ID_DFR0, t); =20 /* Debug ID registers. */ =20 @@ -116,9 +116,7 @@ void aa32_max_features(ARMCPU *cpu) t =3D FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2); cpu->isar.dbgdevid1 =3D t; =20 - t =3D cpu->isar.id_dfr1; - t =3D FIELD_DP32(t, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */ - cpu->isar.id_dfr1 =3D t; + FIELD_DP32_IDREG(isar, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */ } =20 /* CPU models. These are not needed for the AArch64 linux-user build. */ @@ -230,7 +228,7 @@ static void arm1136_r2_initfn(Object *obj) cpu->reset_sctlr =3D 0x00050078; SET_IDREG(isar, ID_PFR0, 0x111); SET_IDREG(isar, ID_PFR1, 0x1); - cpu->isar.id_dfr0 =3D 0x2; + SET_IDREG(isar, ID_DFR0, 0x2); cpu->id_afr0 =3D 0x3; cpu->isar.id_mmfr0 =3D 0x01130003; cpu->isar.id_mmfr1 =3D 0x10030302; @@ -262,7 +260,7 @@ static void arm1136_initfn(Object *obj) cpu->reset_sctlr =3D 0x00050078; SET_IDREG(isar, ID_PFR0, 0x111); SET_IDREG(isar, ID_PFR1, 0x1); - cpu->isar.id_dfr0 =3D 0x2; + SET_IDREG(isar, ID_DFR0, 0x2); cpu->id_afr0 =3D 0x3; cpu->isar.id_mmfr0 =3D 0x01130003; cpu->isar.id_mmfr1 =3D 0x10030302; @@ -295,7 +293,7 @@ static void arm1176_initfn(Object *obj) cpu->reset_sctlr =3D 0x00050078; SET_IDREG(isar, ID_PFR0, 0x111); SET_IDREG(isar, ID_PFR1, 0x11); - cpu->isar.id_dfr0 =3D 0x33; + SET_IDREG(isar, ID_DFR0, 0x33); cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x01130003; cpu->isar.id_mmfr1 =3D 0x10030302; @@ -325,7 +323,7 @@ static void arm11mpcore_initfn(Object *obj) cpu->ctr =3D 0x1d192992; /* 32K icache 32K dcache */ SET_IDREG(isar, ID_PFR0, 0x111); SET_IDREG(isar, ID_PFR1, 0x1); - cpu->isar.id_dfr0 =3D 0; + SET_IDREG(isar, ID_DFR0, 0); cpu->id_afr0 =3D 0x2; cpu->isar.id_mmfr0 =3D 0x01100103; cpu->isar.id_mmfr1 =3D 0x10020302; @@ -365,7 +363,7 @@ static void cortex_a8_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50078; SET_IDREG(isar, ID_PFR0, 0x1031); SET_IDREG(isar, ID_PFR1, 0x11); - cpu->isar.id_dfr0 =3D 0x400; + SET_IDREG(isar, ID_DFR0, 0x400); cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x31100003; cpu->isar.id_mmfr1 =3D 0x20000000; @@ -441,7 +439,7 @@ static void cortex_a9_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50078; SET_IDREG(isar, ID_PFR0, 0x1031); SET_IDREG(isar, ID_PFR1, 0x11); - cpu->isar.id_dfr0 =3D 0x000; + SET_IDREG(isar, ID_DFR0, 0x000); cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x00100103; cpu->isar.id_mmfr1 =3D 0x20000000; @@ -507,7 +505,7 @@ static void cortex_a7_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50078; SET_IDREG(isar, ID_PFR0, 0x00001131); SET_IDREG(isar, ID_PFR1, 0x00011011); - cpu->isar.id_dfr0 =3D 0x02010555; + SET_IDREG(isar, ID_DFR0, 0x02010555); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10101105; cpu->isar.id_mmfr1 =3D 0x40000000; @@ -559,7 +557,7 @@ static void cortex_a15_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50078; SET_IDREG(isar, ID_PFR0, 0x00001131); SET_IDREG(isar, ID_PFR1, 0x00011011); - cpu->isar.id_dfr0 =3D 0x02010555; + SET_IDREG(isar, ID_DFR0, 0x02010555); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10201105; cpu->isar.id_mmfr1 =3D 0x20000000; @@ -603,7 +601,7 @@ static void cortex_r5_initfn(Object *obj) cpu->midr =3D 0x411fc153; /* r1p3 */ SET_IDREG(isar, ID_PFR0, 0x0131); SET_IDREG(isar, ID_PFR1, 0x001); - cpu->isar.id_dfr0 =3D 0x010400; + SET_IDREG(isar, ID_DFR0, 0x010400); cpu->id_afr0 =3D 0x0; cpu->isar.id_mmfr0 =3D 0x0210030; cpu->isar.id_mmfr1 =3D 0x00000000; @@ -750,7 +748,7 @@ static void cortex_r52_initfn(Object *obj) cpu->reset_sctlr =3D 0x30c50838; SET_IDREG(isar, ID_PFR0, 0x00000131); SET_IDREG(isar, ID_PFR1, 0x10111001); - cpu->isar.id_dfr0 =3D 0x03010006; + SET_IDREG(isar, ID_DFR0, 0x03010006); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00211040; cpu->isar.id_mmfr1 =3D 0x40000000; @@ -982,7 +980,7 @@ static void arm_max_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50838; SET_IDREG(isar, ID_PFR0, 0x00000131); SET_IDREG(isar, ID_PFR1, 0x00011011); - cpu->isar.id_dfr0 =3D 0x03010066; + SET_IDREG(isar, ID_DFR0, 0x03010066); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10101105; cpu->isar.id_mmfr1 =3D 0x40000000; diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index c3f90e9d135..aeaade488fe 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -51,7 +51,7 @@ static void aarch64_a35_initfn(Object *obj) cpu->ctr =3D 0x84448004; SET_IDREG(isar, ID_PFR0, 0x00000131); SET_IDREG(isar, ID_PFR1, 0x00011011); - cpu->isar.id_dfr0 =3D 0x03010066; + SET_IDREG(isar, ID_DFR0, 0x03010066); cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x10201105; cpu->isar.id_mmfr1 =3D 0x40000000; @@ -228,7 +228,7 @@ static void aarch64_a55_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR0, 0x0000000010112222ull); SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_dfr0 =3D 0x04010088; + SET_IDREG(isar, ID_DFR0, 0x04010088); SET_IDREG(isar, ID_ISAR0, 0x02101110); SET_IDREG(isar, ID_ISAR1, 0x13112111); SET_IDREG(isar, ID_ISAR2, 0x21232042); @@ -297,7 +297,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50838; SET_IDREG(isar, ID_PFR0, 0x00000131); SET_IDREG(isar, ID_PFR1, 0x00011011); - cpu->isar.id_dfr0 =3D 0x03010066; + SET_IDREG(isar, ID_DFR0, 0x03010066); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10201105; cpu->isar.id_mmfr1 =3D 0x40000000; @@ -361,7 +361,7 @@ static void aarch64_a76_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in = later */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_dfr0 =3D 0x04010088; + SET_IDREG(isar, ID_DFR0, 0x04010088); SET_IDREG(isar, ID_ISAR0, 0x02101110); SET_IDREG(isar, ID_ISAR1, 0x13112111); SET_IDREG(isar, ID_ISAR2, 0x21232042); @@ -609,7 +609,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in = later */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_dfr0 =3D 0x04010088; + SET_IDREG(isar, ID_DFR0, 0x04010088); SET_IDREG(isar, ID_ISAR0, 0x02101110); SET_IDREG(isar, ID_ISAR1, 0x13112111); SET_IDREG(isar, ID_ISAR2, 0x21232042); @@ -688,7 +688,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR0, 0x1101110120111112ull); /* GIC filled in = later */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_dfr0 =3D 0x15011099; + SET_IDREG(isar, ID_DFR0, 0x15011099); SET_IDREG(isar, ID_ISAR0, 0x02101110); SET_IDREG(isar, ID_ISAR1, 0x13112111); SET_IDREG(isar, ID_ISAR2, 0x21232042); @@ -904,7 +904,7 @@ static void aarch64_a710_initfn(Object *obj) cpu->revidr =3D 0; SET_IDREG(isar, ID_PFR0, 0x21110131); SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ - cpu->isar.id_dfr0 =3D 0x16011099; + SET_IDREG(isar, ID_DFR0, 0x16011099); cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x10201105; cpu->isar.id_mmfr1 =3D 0x40000000; @@ -1006,7 +1006,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj) cpu->revidr =3D 0; SET_IDREG(isar, ID_PFR0, 0x21110131); SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ - cpu->isar.id_dfr0 =3D 0x16011099; + SET_IDREG(isar, ID_DFR0, 0x16011099); cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x10201105; cpu->isar.id_mmfr1 =3D 0x40000000; --=20 2.43.0 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tue, 01 Jul 2025 10:07:36 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/43] arm/cpu: Store id_mmfr0-5 into the idregs array Date: Tue, 1 Jul 2025 18:06:49 +0100 Message-ID: <20250701170720.4072660-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751390162972116600 Content-Type: text/plain; charset="utf-8" From: Eric Auger Reviewed-by: Richard Henderson Reviewed-by: Sebastian Ott Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck Message-id: 20250617153931.1330449-12-cohuck@redhat.com Signed-off-by: Peter Maydell --- target/arm/cpu-features.h | 18 ++++---- target/arm/cpu.h | 6 --- hw/intc/armv7m_nvic.c | 8 ++-- target/arm/cpu64.c | 16 +++---- target/arm/helper.c | 12 ++--- target/arm/kvm.c | 18 +++----- target/arm/tcg/cpu-v7m.c | 48 ++++++++++---------- target/arm/tcg/cpu32.c | 94 +++++++++++++++++++-------------------- target/arm/tcg/cpu64.c | 76 +++++++++++++++---------------- 9 files changed, 140 insertions(+), 156 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 0292a7cd6ec..5d8adfb73b6 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -284,17 +284,17 @@ static inline bool isar_feature_aa32_vminmaxnm(const = ARMISARegisters *id) =20 static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id) { - return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >=3D 4; + return FIELD_EX32_IDREG(id, ID_MMFR0, VMSA) >=3D 4; } =20 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) { - return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) !=3D 0; + return FIELD_EX32_IDREG(id, ID_MMFR3, PAN) !=3D 0; } =20 static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) { - return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >=3D 2; + return FIELD_EX32_IDREG(id, ID_MMFR3, PAN) >=3D 2; } =20 static inline bool isar_feature_aa32_pmuv3p1(const ARMISARegisters *id) @@ -320,32 +320,32 @@ static inline bool isar_feature_aa32_pmuv3p5(const AR= MISARegisters *id) =20 static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) { - return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) !=3D 0; + return FIELD_EX32_IDREG(id, ID_MMFR4, HPDS) !=3D 0; } =20 static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id) { - return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) !=3D 0; + return FIELD_EX32_IDREG(id, ID_MMFR4, AC2) !=3D 0; } =20 static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id) { - return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) !=3D 0; + return FIELD_EX32_IDREG(id, ID_MMFR4, CCIDX) !=3D 0; } =20 static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id) { - return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) !=3D 0; + return FIELD_EX32_IDREG(id, ID_MMFR4, XNX) !=3D 0; } =20 static inline bool isar_feature_aa32_half_evt(const ARMISARegisters *id) { - return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >=3D 1; + return FIELD_EX32_IDREG(id, ID_MMFR4, EVT) >=3D 1; } =20 static inline bool isar_feature_aa32_evt(const ARMISARegisters *id) { - return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >=3D 2; + return FIELD_EX32_IDREG(id, ID_MMFR4, EVT) >=3D 2; } =20 static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c799105eeb2..8744922330d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1050,12 +1050,6 @@ struct ArchCPU { * field by reading the value from the KVM vCPU. */ struct ARMISARegisters { - uint32_t id_mmfr0; - uint32_t id_mmfr1; - uint32_t id_mmfr2; - uint32_t id_mmfr3; - uint32_t id_mmfr4; - uint32_t id_mmfr5; uint32_t mvfr0; uint32_t mvfr1; uint32_t mvfr2; diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 2566dd63431..6d85720f1b4 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1284,22 +1284,22 @@ static uint32_t nvic_readl(NVICState *s, uint32_t o= ffset, MemTxAttrs attrs) if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_mmfr0; + return GET_IDREG(isar, ID_MMFR0); case 0xd54: /* MMFR1. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_mmfr1; + return GET_IDREG(isar, ID_MMFR1); case 0xd58: /* MMFR2. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_mmfr2; + return GET_IDREG(isar, ID_MMFR2); case 0xd5c: /* MMFR3. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_mmfr3; + return GET_IDREG(isar, ID_MMFR3); case 0xd60: /* ISAR0. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 47c2eed3c99..1f3406708bd 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -656,10 +656,10 @@ static void aarch64_a57_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x00011011); SET_IDREG(isar, ID_DFR0, 0x03010066); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x10101105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02102211; + SET_IDREG(isar, ID_MMFR0, 0x10101105); + SET_IDREG(isar, ID_MMFR1, 0x40000000); + SET_IDREG(isar, ID_MMFR2, 0x01260000); + SET_IDREG(isar, ID_MMFR3, 0x02102211); SET_IDREG(isar, ID_ISAR0, 0x02101110); SET_IDREG(isar, ID_ISAR1, 0x13112111); SET_IDREG(isar, ID_ISAR2, 0x21232042); @@ -718,10 +718,10 @@ static void aarch64_a53_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x00011011); SET_IDREG(isar, ID_DFR0, 0x03010066); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x10101105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02102211; + SET_IDREG(isar, ID_MMFR0, 0x10101105); + SET_IDREG(isar, ID_MMFR1, 0x40000000); + SET_IDREG(isar, ID_MMFR2, 0x01260000); + SET_IDREG(isar, ID_MMFR3, 0x02102211); SET_IDREG(isar, ID_ISAR0, 0x02101110); SET_IDREG(isar, ID_ISAR1, 0x13112111); SET_IDREG(isar, ID_ISAR2, 0x21232042); diff --git a/target/arm/helper.c b/target/arm/helper.c index 4d90ff7fd51..c311d2df217 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7810,22 +7810,22 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_mmfr0 }, + .resetvalue =3D GET_IDREG(isar, ID_MMFR0)}, { .name =3D "ID_MMFR1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_mmfr1 }, + .resetvalue =3D GET_IDREG(isar, ID_MMFR1)}, { .name =3D "ID_MMFR2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_mmfr2 }, + .resetvalue =3D GET_IDREG(isar, ID_MMFR2)}, { .name =3D "ID_MMFR3", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_mmfr3 }, + .resetvalue =3D GET_IDREG(isar, ID_MMFR3)}, { .name =3D "ID_ISAR0", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, @@ -7860,7 +7860,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_mmfr4 }, + .resetvalue =3D GET_IDREG(isar, ID_MMFR4)}, { .name =3D "ID_ISAR6", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, @@ -8140,7 +8140,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_mmfr5 }, + .resetvalue =3D GET_IDREG(isar, ID_MMFR5)}, { .name =3D "RES_0_C0_C3_7", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 2a6a5329b43..3df046b2b91 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -335,14 +335,10 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUF= eatures *ahcf) err |=3D get_host_cpu_reg(fd, ahcf, ID_PFR0_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_PFR1_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_DFR0_EL1_IDX); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0, - ARM64_SYS_REG(3, 0, 0, 1, 4)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1, - ARM64_SYS_REG(3, 0, 0, 1, 5)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr2, - ARM64_SYS_REG(3, 0, 0, 1, 6)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3, - ARM64_SYS_REG(3, 0, 0, 1, 7)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_MMFR0_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_MMFR1_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_MMFR2_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_MMFR3_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_ISAR0_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_ISAR1_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_ISAR2_EL1_IDX); @@ -350,8 +346,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) err |=3D get_host_cpu_reg(fd, ahcf, ID_ISAR4_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_ISAR5_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_ISAR6_EL1_IDX); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4, - ARM64_SYS_REG(3, 0, 0, 2, 6)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_MMFR4_EL1_IDX); =20 err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, ARM64_SYS_REG(3, 0, 0, 3, 0)); @@ -361,8 +356,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) ARM64_SYS_REG(3, 0, 0, 3, 2)); err |=3D get_host_cpu_reg(fd, ahcf, ID_PFR2_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_DFR1_EL1_IDX); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr5, - ARM64_SYS_REG(3, 0, 0, 3, 6)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_MMFR5_EL1_IDX); =20 /* * DBGDIDR is a bit complicated because the kernel doesn't diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 9697c362c19..eddd7117d5b 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -63,10 +63,10 @@ static void cortex_m0_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x00000200); SET_IDREG(isar, ID_DFR0, 0x00100000); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x00000030; - cpu->isar.id_mmfr1 =3D 0x00000000; - cpu->isar.id_mmfr2 =3D 0x00000000; - cpu->isar.id_mmfr3 =3D 0x00000000; + SET_IDREG(isar, ID_MMFR0, 0x00000030); + SET_IDREG(isar, ID_MMFR1, 0x00000000); + SET_IDREG(isar, ID_MMFR2, 0x00000000); + SET_IDREG(isar, ID_MMFR3, 0x00000000); SET_IDREG(isar, ID_ISAR0, 0x01141110); SET_IDREG(isar, ID_ISAR1, 0x02111000); SET_IDREG(isar, ID_ISAR2, 0x21112231); @@ -89,10 +89,10 @@ static void cortex_m3_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x00000200); SET_IDREG(isar, ID_DFR0, 0x00100000); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x00000030; - cpu->isar.id_mmfr1 =3D 0x00000000; - cpu->isar.id_mmfr2 =3D 0x00000000; - cpu->isar.id_mmfr3 =3D 0x00000000; + SET_IDREG(isar, ID_MMFR0, 0x00000030); + SET_IDREG(isar, ID_MMFR1, 0x00000000); + SET_IDREG(isar, ID_MMFR2, 0x00000000); + SET_IDREG(isar, ID_MMFR3, 0x00000000); SET_IDREG(isar, ID_ISAR0, 0x01141110); SET_IDREG(isar, ID_ISAR1, 0x02111000); SET_IDREG(isar, ID_ISAR2, 0x21112231); @@ -120,10 +120,10 @@ static void cortex_m4_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x00000200); SET_IDREG(isar, ID_DFR0, 0x00100000); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x00000030; - cpu->isar.id_mmfr1 =3D 0x00000000; - cpu->isar.id_mmfr2 =3D 0x00000000; - cpu->isar.id_mmfr3 =3D 0x00000000; + SET_IDREG(isar, ID_MMFR0, 0x00000030); + SET_IDREG(isar, ID_MMFR1, 0x00000000); + SET_IDREG(isar, ID_MMFR2, 0x00000000); + SET_IDREG(isar, ID_MMFR3, 0x00000000); SET_IDREG(isar, ID_ISAR0, 0x01141110); SET_IDREG(isar, ID_ISAR1, 0x02111000); SET_IDREG(isar, ID_ISAR2, 0x21112231); @@ -151,10 +151,10 @@ static void cortex_m7_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x00000200); SET_IDREG(isar, ID_DFR0, 0x00100000); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x00100030; - cpu->isar.id_mmfr1 =3D 0x00000000; - cpu->isar.id_mmfr2 =3D 0x01000000; - cpu->isar.id_mmfr3 =3D 0x00000000; + SET_IDREG(isar, ID_MMFR0, 0x00100030); + SET_IDREG(isar, ID_MMFR1, 0x00000000); + SET_IDREG(isar, ID_MMFR2, 0x01000000); + SET_IDREG(isar, ID_MMFR3, 0x00000000); SET_IDREG(isar, ID_ISAR0, 0x01101110); SET_IDREG(isar, ID_ISAR1, 0x02112000); SET_IDREG(isar, ID_ISAR2, 0x20232231); @@ -184,10 +184,10 @@ static void cortex_m33_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x00000210); SET_IDREG(isar, ID_DFR0, 0x00200000); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x00101F40; - cpu->isar.id_mmfr1 =3D 0x00000000; - cpu->isar.id_mmfr2 =3D 0x01000000; - cpu->isar.id_mmfr3 =3D 0x00000000; + SET_IDREG(isar, ID_MMFR0, 0x00101F40); + SET_IDREG(isar, ID_MMFR1, 0x00000000); + SET_IDREG(isar, ID_MMFR2, 0x01000000); + SET_IDREG(isar, ID_MMFR3, 0x00000000); SET_IDREG(isar, ID_ISAR0, 0x01101110); SET_IDREG(isar, ID_ISAR1, 0x02212000); SET_IDREG(isar, ID_ISAR2, 0x20232232); @@ -222,10 +222,10 @@ static void cortex_m55_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x00000230); SET_IDREG(isar, ID_DFR0, 0x10200000); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x00111040; - cpu->isar.id_mmfr1 =3D 0x00000000; - cpu->isar.id_mmfr2 =3D 0x01000000; - cpu->isar.id_mmfr3 =3D 0x00000011; + SET_IDREG(isar, ID_MMFR0, 0x00111040); + SET_IDREG(isar, ID_MMFR1, 0x00000000); + SET_IDREG(isar, ID_MMFR2, 0x01000000); + SET_IDREG(isar, ID_MMFR3, 0x00000011); SET_IDREG(isar, ID_ISAR0, 0x01103110); SET_IDREG(isar, ID_ISAR1, 0x02212000); SET_IDREG(isar, ID_ISAR2, 0x20232232); diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index bec69fe52e4..942b636aa5b 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -55,21 +55,17 @@ void aa32_max_features(ARMCPU *cpu) t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ cpu->isar.mvfr2 =3D t; =20 - t =3D cpu->isar.id_mmfr3; - t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */ - cpu->isar.id_mmfr3 =3D t; + FIELD_DP32_IDREG(isar, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */ =20 - t =3D cpu->isar.id_mmfr4; + t =3D GET_IDREG(isar, ID_MMFR4); t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 2); /* FEAT_HPDS2 */ t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */ t =3D FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT */ - cpu->isar.id_mmfr4 =3D t; + SET_IDREG(isar, ID_MMFR4, t); =20 - t =3D cpu->isar.id_mmfr5; - t =3D FIELD_DP32(t, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */ - cpu->isar.id_mmfr5 =3D t; + FIELD_DP32_IDREG(isar, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */ =20 t =3D GET_IDREG(isar, ID_PFR0); t =3D FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */ @@ -230,9 +226,9 @@ static void arm1136_r2_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x1); SET_IDREG(isar, ID_DFR0, 0x2); cpu->id_afr0 =3D 0x3; - cpu->isar.id_mmfr0 =3D 0x01130003; - cpu->isar.id_mmfr1 =3D 0x10030302; - cpu->isar.id_mmfr2 =3D 0x01222110; + SET_IDREG(isar, ID_MMFR0, 0x01130003); + SET_IDREG(isar, ID_MMFR1, 0x10030302); + SET_IDREG(isar, ID_MMFR2, 0x01222110); SET_IDREG(isar, ID_ISAR0, 0x00140011); SET_IDREG(isar, ID_ISAR1, 0x12002111); SET_IDREG(isar, ID_ISAR2, 0x11231111); @@ -262,9 +258,9 @@ static void arm1136_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x1); SET_IDREG(isar, ID_DFR0, 0x2); cpu->id_afr0 =3D 0x3; - cpu->isar.id_mmfr0 =3D 0x01130003; - cpu->isar.id_mmfr1 =3D 0x10030302; - cpu->isar.id_mmfr2 =3D 0x01222110; + SET_IDREG(isar, ID_MMFR0, 0x01130003); + SET_IDREG(isar, ID_MMFR1, 0x10030302); + SET_IDREG(isar, ID_MMFR2, 0x01222110); SET_IDREG(isar, ID_ISAR0, 0x00140011); SET_IDREG(isar, ID_ISAR1, 0x12002111); SET_IDREG(isar, ID_ISAR2, 0x11231111); @@ -295,9 +291,9 @@ static void arm1176_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x11); SET_IDREG(isar, ID_DFR0, 0x33); cpu->id_afr0 =3D 0; - cpu->isar.id_mmfr0 =3D 0x01130003; - cpu->isar.id_mmfr1 =3D 0x10030302; - cpu->isar.id_mmfr2 =3D 0x01222100; + SET_IDREG(isar, ID_MMFR0, 0x01130003); + SET_IDREG(isar, ID_MMFR1, 0x10030302); + SET_IDREG(isar, ID_MMFR2, 0x01222100); SET_IDREG(isar, ID_ISAR0, 0x0140011); SET_IDREG(isar, ID_ISAR1, 0x12002111); SET_IDREG(isar, ID_ISAR2, 0x11231121); @@ -325,9 +321,9 @@ static void arm11mpcore_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x1); SET_IDREG(isar, ID_DFR0, 0); cpu->id_afr0 =3D 0x2; - cpu->isar.id_mmfr0 =3D 0x01100103; - cpu->isar.id_mmfr1 =3D 0x10020302; - cpu->isar.id_mmfr2 =3D 0x01222000; + SET_IDREG(isar, ID_MMFR0, 0x01100103); + SET_IDREG(isar, ID_MMFR1, 0x10020302); + SET_IDREG(isar, ID_MMFR2, 0x01222000); SET_IDREG(isar, ID_ISAR0, 0x00100011); SET_IDREG(isar, ID_ISAR1, 0x12002111); SET_IDREG(isar, ID_ISAR2, 0x11221011); @@ -365,10 +361,10 @@ static void cortex_a8_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x11); SET_IDREG(isar, ID_DFR0, 0x400); cpu->id_afr0 =3D 0; - cpu->isar.id_mmfr0 =3D 0x31100003; - cpu->isar.id_mmfr1 =3D 0x20000000; - cpu->isar.id_mmfr2 =3D 0x01202000; - cpu->isar.id_mmfr3 =3D 0x11; + SET_IDREG(isar, ID_MMFR0, 0x31100003); + SET_IDREG(isar, ID_MMFR1, 0x20000000); + SET_IDREG(isar, ID_MMFR2, 0x01202000); + SET_IDREG(isar, ID_MMFR3, 0x11); SET_IDREG(isar, ID_ISAR0, 0x00101111); SET_IDREG(isar, ID_ISAR1, 0x12112111); SET_IDREG(isar, ID_ISAR2, 0x21232031); @@ -441,10 +437,10 @@ static void cortex_a9_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x11); SET_IDREG(isar, ID_DFR0, 0x000); cpu->id_afr0 =3D 0; - cpu->isar.id_mmfr0 =3D 0x00100103; - cpu->isar.id_mmfr1 =3D 0x20000000; - cpu->isar.id_mmfr2 =3D 0x01230000; - cpu->isar.id_mmfr3 =3D 0x00002111; + SET_IDREG(isar, ID_MMFR0, 0x00100103); + SET_IDREG(isar, ID_MMFR1, 0x20000000); + SET_IDREG(isar, ID_MMFR2, 0x01230000); + SET_IDREG(isar, ID_MMFR3, 0x00002111); SET_IDREG(isar, ID_ISAR0, 0x00101111); SET_IDREG(isar, ID_ISAR1, 0x13112111); SET_IDREG(isar, ID_ISAR2, 0x21232041); @@ -507,10 +503,10 @@ static void cortex_a7_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x00011011); SET_IDREG(isar, ID_DFR0, 0x02010555); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x10101105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01240000; - cpu->isar.id_mmfr3 =3D 0x02102211; + SET_IDREG(isar, ID_MMFR0, 0x10101105); + SET_IDREG(isar, ID_MMFR1, 0x40000000); + SET_IDREG(isar, ID_MMFR2, 0x01240000); + SET_IDREG(isar, ID_MMFR3, 0x02102211); /* * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but * table 4-41 gives 0x02101110, which includes the arm div insns. @@ -559,10 +555,10 @@ static void cortex_a15_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x00011011); SET_IDREG(isar, ID_DFR0, 0x02010555); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x20000000; - cpu->isar.id_mmfr2 =3D 0x01240000; - cpu->isar.id_mmfr3 =3D 0x02102211; + SET_IDREG(isar, ID_MMFR0, 0x10201105); + SET_IDREG(isar, ID_MMFR1, 0x20000000); + SET_IDREG(isar, ID_MMFR2, 0x01240000); + SET_IDREG(isar, ID_MMFR3, 0x02102211); SET_IDREG(isar, ID_ISAR0, 0x02101110); SET_IDREG(isar, ID_ISAR1, 0x13112111); SET_IDREG(isar, ID_ISAR2, 0x21232041); @@ -603,10 +599,10 @@ static void cortex_r5_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x001); SET_IDREG(isar, ID_DFR0, 0x010400); cpu->id_afr0 =3D 0x0; - cpu->isar.id_mmfr0 =3D 0x0210030; - cpu->isar.id_mmfr1 =3D 0x00000000; - cpu->isar.id_mmfr2 =3D 0x01200000; - cpu->isar.id_mmfr3 =3D 0x0211; + SET_IDREG(isar, ID_MMFR0, 0x0210030); + SET_IDREG(isar, ID_MMFR1, 0x00000000); + SET_IDREG(isar, ID_MMFR2, 0x01200000); + SET_IDREG(isar, ID_MMFR3, 0x0211); SET_IDREG(isar, ID_ISAR0, 0x02101111); SET_IDREG(isar, ID_ISAR1, 0x13112111); SET_IDREG(isar, ID_ISAR2, 0x21232141); @@ -750,11 +746,11 @@ static void cortex_r52_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x10111001); SET_IDREG(isar, ID_DFR0, 0x03010006); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x00211040; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01200000; - cpu->isar.id_mmfr3 =3D 0xf0102211; - cpu->isar.id_mmfr4 =3D 0x00000010; + SET_IDREG(isar, ID_MMFR0, 0x00211040); + SET_IDREG(isar, ID_MMFR1, 0x40000000); + SET_IDREG(isar, ID_MMFR2, 0x01200000); + SET_IDREG(isar, ID_MMFR3, 0xf0102211); + SET_IDREG(isar, ID_MMFR4, 0x00000010); SET_IDREG(isar, ID_ISAR0, 0x02101110); SET_IDREG(isar, ID_ISAR1, 0x13112111); SET_IDREG(isar, ID_ISAR2, 0x21232142); @@ -982,10 +978,10 @@ static void arm_max_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x00011011); SET_IDREG(isar, ID_DFR0, 0x03010066); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x10101105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02102211; + SET_IDREG(isar, ID_MMFR0, 0x10101105); + SET_IDREG(isar, ID_MMFR1, 0x40000000); + SET_IDREG(isar, ID_MMFR2, 0x01260000); + SET_IDREG(isar, ID_MMFR3, 0x02102211); SET_IDREG(isar, ID_ISAR0, 0x02101110); SET_IDREG(isar, ID_ISAR1, 0x13112111); SET_IDREG(isar, ID_ISAR2, 0x21232042); diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index aeaade488fe..937f29e253d 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -53,10 +53,10 @@ static void aarch64_a35_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x00011011); SET_IDREG(isar, ID_DFR0, 0x03010066); cpu->id_afr0 =3D 0; - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02102211; + SET_IDREG(isar, ID_MMFR0, 0x10201105); + SET_IDREG(isar, ID_MMFR1, 0x40000000); + SET_IDREG(isar, ID_MMFR2, 0x01260000); + SET_IDREG(isar, ID_MMFR3, 0x02102211); SET_IDREG(isar, ID_ISAR0, 0x02101110); SET_IDREG(isar, ID_ISAR1, 0x13112111); SET_IDREG(isar, ID_ISAR2, 0x21232042); @@ -236,11 +236,11 @@ static void aarch64_a55_initfn(Object *obj) SET_IDREG(isar, ID_ISAR4, 0x00011142); SET_IDREG(isar, ID_ISAR5, 0x01011121); SET_IDREG(isar, ID_ISAR6, 0x00000010); - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02122211; - cpu->isar.id_mmfr4 =3D 0x00021110; + SET_IDREG(isar, ID_MMFR0, 0x10201105); + SET_IDREG(isar, ID_MMFR1, 0x40000000); + SET_IDREG(isar, ID_MMFR2, 0x01260000); + SET_IDREG(isar, ID_MMFR3, 0x02122211); + SET_IDREG(isar, ID_MMFR4, 0x00021110); SET_IDREG(isar, ID_PFR0, 0x10010131); SET_IDREG(isar, ID_PFR1, 0x00011011); SET_IDREG(isar, ID_PFR2, 0x00000011); @@ -299,10 +299,10 @@ static void aarch64_a72_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x00011011); SET_IDREG(isar, ID_DFR0, 0x03010066); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02102211; + SET_IDREG(isar, ID_MMFR0, 0x10201105); + SET_IDREG(isar, ID_MMFR1, 0x40000000); + SET_IDREG(isar, ID_MMFR2, 0x01260000); + SET_IDREG(isar, ID_MMFR3, 0x02102211); SET_IDREG(isar, ID_ISAR0, 0x02101110); SET_IDREG(isar, ID_ISAR1, 0x13112111); SET_IDREG(isar, ID_ISAR2, 0x21232042); @@ -369,11 +369,11 @@ static void aarch64_a76_initfn(Object *obj) SET_IDREG(isar, ID_ISAR4, 0x00010142); SET_IDREG(isar, ID_ISAR5, 0x01011121); SET_IDREG(isar, ID_ISAR6, 0x00000010); - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02122211; - cpu->isar.id_mmfr4 =3D 0x00021110; + SET_IDREG(isar, ID_MMFR0, 0x10201105); + SET_IDREG(isar, ID_MMFR1, 0x40000000); + SET_IDREG(isar, ID_MMFR2, 0x01260000); + SET_IDREG(isar, ID_MMFR3, 0x02122211); + SET_IDREG(isar, ID_MMFR4, 0x00021110); SET_IDREG(isar, ID_PFR0, 0x10010131); SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ SET_IDREG(isar, ID_PFR2, 0x00000011); @@ -617,11 +617,11 @@ static void aarch64_neoverse_n1_initfn(Object *obj) SET_IDREG(isar, ID_ISAR4, 0x00010142); SET_IDREG(isar, ID_ISAR5, 0x01011121); SET_IDREG(isar, ID_ISAR6, 0x00000010); - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02122211; - cpu->isar.id_mmfr4 =3D 0x00021110; + SET_IDREG(isar, ID_MMFR0, 0x10201105); + SET_IDREG(isar, ID_MMFR1, 0x40000000); + SET_IDREG(isar, ID_MMFR2, 0x01260000); + SET_IDREG(isar, ID_MMFR3, 0x02122211); + SET_IDREG(isar, ID_MMFR4, 0x00021110); SET_IDREG(isar, ID_PFR0, 0x10010131); SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ SET_IDREG(isar, ID_PFR2, 0x00000011); @@ -696,11 +696,11 @@ static void aarch64_neoverse_v1_initfn(Object *obj) SET_IDREG(isar, ID_ISAR4, 0x00010142); SET_IDREG(isar, ID_ISAR5, 0x11011121); SET_IDREG(isar, ID_ISAR6, 0x01100111); - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02122211; - cpu->isar.id_mmfr4 =3D 0x01021110; + SET_IDREG(isar, ID_MMFR0, 0x10201105); + SET_IDREG(isar, ID_MMFR1, 0x40000000); + SET_IDREG(isar, ID_MMFR2, 0x01260000); + SET_IDREG(isar, ID_MMFR3, 0x02122211); + SET_IDREG(isar, ID_MMFR4, 0x01021110); SET_IDREG(isar, ID_PFR0, 0x21110131); SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ SET_IDREG(isar, ID_PFR2, 0x00000011); @@ -906,17 +906,17 @@ static void aarch64_a710_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ SET_IDREG(isar, ID_DFR0, 0x16011099); cpu->id_afr0 =3D 0; - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02122211; + SET_IDREG(isar, ID_MMFR0, 0x10201105); + SET_IDREG(isar, ID_MMFR1, 0x40000000); + SET_IDREG(isar, ID_MMFR2, 0x01260000); + SET_IDREG(isar, ID_MMFR3, 0x02122211); SET_IDREG(isar, ID_ISAR0, 0x02101110); SET_IDREG(isar, ID_ISAR1, 0x13112111); SET_IDREG(isar, ID_ISAR2, 0x21232042); SET_IDREG(isar, ID_ISAR3, 0x01112131); SET_IDREG(isar, ID_ISAR4, 0x00010142); SET_IDREG(isar, ID_ISAR5, 0x11011121); /* with Crypto */ - cpu->isar.id_mmfr4 =3D 0x21021110; + SET_IDREG(isar, ID_MMFR4, 0x21021110); SET_IDREG(isar, ID_ISAR6, 0x01111111); cpu->isar.mvfr0 =3D 0x10110222; cpu->isar.mvfr1 =3D 0x13211111; @@ -1008,17 +1008,17 @@ static void aarch64_neoverse_n2_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ SET_IDREG(isar, ID_DFR0, 0x16011099); cpu->id_afr0 =3D 0; - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02122211; + SET_IDREG(isar, ID_MMFR0, 0x10201105); + SET_IDREG(isar, ID_MMFR1, 0x40000000); + SET_IDREG(isar, ID_MMFR2, 0x01260000); + SET_IDREG(isar, ID_MMFR3, 0x02122211); SET_IDREG(isar, ID_ISAR0, 0x02101110); SET_IDREG(isar, ID_ISAR1, 0x13112111); SET_IDREG(isar, ID_ISAR2, 0x21232042); SET_IDREG(isar, ID_ISAR3, 0x01112131); SET_IDREG(isar, ID_ISAR4, 0x00010142); SET_IDREG(isar, ID_ISAR5, 0x11011121); /* with Crypto */ - cpu->isar.id_mmfr4 =3D 0x01021110; + SET_IDREG(isar, ID_MMFR4, 0x01021110); SET_IDREG(isar, ID_ISAR6, 0x01111111); cpu->isar.mvfr0 =3D 0x10110222; cpu->isar.mvfr1 =3D 0x13211111; --=20 2.43.0 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1751389721; cv=none; d=zohomail.com; s=zohoarc; b=WfrnCdEML0AHrAsuKkYj1mt2uyXrOczNbo1h2Xze7dONMD7pPTqZnaS2c3YK6bYsZ1C1qDTDRzb7ziqnbAaJc/w/1Yr2HXGOK41APQ3H87tOlJweWZZy55QLzoXMrGzPRbTVcgYECn1CZHgqR0G4Di0/N0a+LsUwuvAHQ5ZpvW0= ARC-Message-Signature: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a88c80bb28sm13475658f8f.43.2025.07.01.10.07.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 10:07:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751389657; x=1751994457; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=f4e7g+zAPhyn2jXoPUb8Dn9jnEqXYry2op4lCwZB1eQ=; b=FvVg4Zwh792cN6s6XS5ADBsx8Wq1a0nJcmi8cL1NO2VOr0oNWSCtRkpb2AzFQLIBFt UELFsWXPDSJ9Q+mn2fd6zDqtUtigwLtDBJo7hGbfzk80OnQR40G/9lh9q52fCMcLQpGG 4YczN3W9+8T/D4YOUkbluRyJxg3hoOTCGXKXl+kC1FDFPFQ6tkFFpgp7QP6d44J7Jw60 W/uYYXc27ygWkrg52Nlu2KQ2h4lmC+veAy+1te6pirZHd5DBL4g0jY+zQN29F7SITYGs YQafOZX9jweadwfLBPrurwIpgIRya0x7S+PH2mdzi3DTgvhTX6LhuGzFFxo/KGeA80Hy PiEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751389657; x=1751994457; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f4e7g+zAPhyn2jXoPUb8Dn9jnEqXYry2op4lCwZB1eQ=; b=RR6pGEtecdMCreon04MrELwGjnMOQGImYuJ8jKj3TJVM7uWejl4gzM+kyPXaqhV6FM oGeF3mrvrHk3PSuhJAHRbOrlxe2dATIXh6NdGiDReMww5GBvvCJKedkuo1B3Fc5YsO2c B7YKm0LONM1L2hndHNwA8V0aGVL+PCWcI6GCRf3Iegk1cntsnItAp9sEv/HVN9WqjHlj uN8Wo73AK6ma9e7mjjIlf1cXALhB9cgYQwLHHzMjvWGrxdJoM+7eZkqxSnpvkkO68k+B 2unOLd1CVdUgyckqdqYtQDiTe5rVrvfWwIRPSu2QTof/3/mGeaM2Gk5se2Ase41A38G8 9pNw== X-Gm-Message-State: AOJu0Yxv1mtWKpPYOPxJDwne2XHv6cAsEH6r1Mv3eaz/bfGNwQfoPMuZ QIeX+G7SY/qbG6bToXmnGj9TcPbPISnEqcRkhlWR+NeJeAfF3rbkaesq1Nc4kOnSewuqZd7K7A3 2ovGr X-Gm-Gg: ASbGncvNnXlGae4Md3NdIG54n4nJpjaXU6dicQWw4qAcnvYfzCBolSWfadmW8fUTNv3 UhJgUBrhwEeQwSuA+nJEutkodgiX2N0zyJuaPaKwENiAUyOQU1Ns4q5RjIQ8prAkERLH2QQWSCw vOYSbkCdg8JbBZcEZDkJKcGQknYBfF4WCs/wGnGJ9vTGBnuAo/Lu08t5b2R46mixpOdao3EMWh2 CyRVpMt4gh9cfRQvwvnjUyROSqXxeoUbR4rZSSKf+MNK1bGoFz5Ijdy8PpoQdmU0Sgn9vIVQ/7u XIM2WZDBfhNL4rN+Rmz7LaRvw6QG1s41R7l3kZpQUpW4M5JPkNTrJqQ6OhNDC7hdsD78 X-Google-Smtp-Source: AGHT+IHrCpzrPWhUMtSBEgV/mw60dVjx8EbN6UG34749A0+1UbALx2+9VdR64kRoonW+8dNkXOHyQA== X-Received: by 2002:a05:6000:2d09:b0:3a5:52b2:fa65 with SMTP id ffacd0b85a97d-3a8fdb2a75dmr12916075f8f.5.1751389657157; Tue, 01 Jul 2025 10:07:37 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/43] arm/kvm: use fd instead of fdarray[2] Date: Tue, 1 Jul 2025 18:06:50 +0100 Message-ID: <20250701170720.4072660-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751389722563116600 Content-Type: text/plain; charset="utf-8" From: Cornelia Huck We have fd, so might as well neaten things up. Suggested-by: Eric Auger Reviewed-by: Eric Auger Signed-off-by: Cornelia Huck Message-id: 20250617153931.1330449-15-cohuck@redhat.com Signed-off-by: Peter Maydell --- target/arm/kvm.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 3df046b2b91..70919aedd0a 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -348,11 +348,11 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUF= eatures *ahcf) err |=3D get_host_cpu_reg(fd, ahcf, ID_ISAR6_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_MMFR4_EL1_IDX); =20 - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, + err |=3D read_sys_reg32(fd, &ahcf->isar.mvfr0, ARM64_SYS_REG(3, 0, 0, 3, 0)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1, + err |=3D read_sys_reg32(fd, &ahcf->isar.mvfr1, ARM64_SYS_REG(3, 0, 0, 3, 1)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2, + err |=3D read_sys_reg32(fd, &ahcf->isar.mvfr2, ARM64_SYS_REG(3, 0, 0, 3, 2)); err |=3D get_host_cpu_reg(fd, ahcf, ID_PFR2_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_DFR1_EL1_IDX); @@ -390,7 +390,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) =20 if (pmu_supported) { /* PMCR_EL0 is only accessible if the vCPU has feature PMU_V3 = */ - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, + err |=3D read_sys_reg64(fd, &ahcf->isar.reset_pmcr_el0, ARM64_SYS_REG(3, 3, 9, 12, 0)); } =20 --=20 2.43.0 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1751389735; cv=none; d=zohomail.com; s=zohoarc; b=jw8vGPb8HnymzXwI9Ms2zx1Tq74ge69PwYZh+GLFH5JverWbdVU9E4VilwT+2ICBPXTNFSCyy1lb+MmjFFxlxNZ+X7g8WrFrK4OWAvjYTK7lWsSzDLVKdtM3QkMCLJVCiCr7S00TGXHghI1tTnEN7MIyNVLoa+2sFFEQniNGkAQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751389735; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=yGrl9aNeRGVvk2bktaVqb3xXDuq3A1i3mnww3L1qfrQ=; b=FGCw8iDFHVO7qAf7IF7D54tPG/rvu190s+Pm0wKybDn8KciyMb/mlN7V0R8u/DJ2KvME0/wxU3sKoi9pE/m0aJCGyruPFezN6n31+lJOU/plrh0NnpnkOhZ8PXFXOEXllU3I6xBy86/AJzZx99I5yAAzxZEzJXwwOB+Fo0zNWuA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1751389735744261.4760945422171; Tue, 1 Jul 2025 10:08:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uWeST-0005Zg-Ri; Tue, 01 Jul 2025 13:07:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uWeSQ-0005W4-Eg for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:07:46 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uWeSK-0003Sj-5q for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:07:45 -0400 Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-3a531fcaa05so2172505f8f.3 for ; Tue, 01 Jul 2025 10:07:39 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a88c80bb28sm13475658f8f.43.2025.07.01.10.07.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 10:07:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751389658; x=1751994458; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=yGrl9aNeRGVvk2bktaVqb3xXDuq3A1i3mnww3L1qfrQ=; b=KaKJLXZt1hJfwbR46PAhB3N3zv4Hze6BdU7bo5QECbd6iPWurg/HqicBsGhhnbSCHi GTdips4aBeAJY0PaQ9g1WpHmxh2TPvw48mI+d14kiqP5tSwImR/msRUa093WMt0EXuIM KLtZXXRTlnD9pUmsuXOPcmAwS7vVOGN8igNGQcAkKe449CKSpE1ydlAY2wLnpKsBKiul RSuD1SHMF9FKoNrcD2ZRBDlMzKvJHWI4ar2E2yEEIMP9en60VFCdKinQi5Sz390VkCkM 6x8tle77iDMcmqjbFV4TvgQeWgln4+CFm/Dbre5kJeYsS2LKgHHS2+zK+8qpQuTLUrpR q0vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751389658; x=1751994458; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yGrl9aNeRGVvk2bktaVqb3xXDuq3A1i3mnww3L1qfrQ=; b=lrcyZKBJPFyyO9P8ZHvHOfqdSe53j8W5O8j+IBgK+4ssyCMwCI3OxibUv/ZOyhFpS3 TergjPAerXKS+JbXUDBY//3ImOuJ/fu5rzT/cDNO1mD3RIDK9MwG86ZwnoNmUnIRQWOz 5sNiCifwH90z7TOHjOW3iIRw1JlP0sqLGq/ZoxUuAz7LAyuLGImUgW1srfdAxJe47XVE KhSWJ3L5fhDnAXOt20IyKZ13E0gwJUbnJvGYMlnUO1ecu4Gn+kUpkeQwKXtDi4udQnh6 sFVz8pk93KX7yEeFq0SsiSFR2nP/Vad0Jo8J3zVLwCk/Wrimu2J24eYMK3uAoZC3/Kdr W4UQ== X-Gm-Message-State: AOJu0YyqnrRNqMte3EaYJLBg+pawqwvX6r6geiOQdvQuHtG3mRtSp8vd asVCJAuxGcxo+0FuH0Kenx5Jxu9bgtm/rxlh3AHFSB3tn4a/yuMfFczrnFwCA8BJwo5KcwbXlpZ wbyFB X-Gm-Gg: ASbGncsjiT8vUcLsEfkmhcdI1IopUrbY2Ukr64FKPuUZ/irg8HTcxLNgxgyPC6p05d+ cT9O4OylFXlOPABgbi4HerOd+7jwqVMx26NutohPVtyd/POWwc8imwAxPjASvmAtZjE1DFLAqQC jj1vY1qxxtceYpRTuxy1mAn2PMYPxKKVofKN0CXJuh7FlG2VCBDeCwjlwM0D7adQiOhkCKy5LLk bGChEmUGjY3KerlGH7dp6wSIhCVO0cJ9u/MQ6VD7dCpjBXKEvMTqIemoEBgyduJHzf9tacsAbHn sWfYnvwa+iSc2zWoGo9eu0j84qDDxbC6G9Zm+93R4YEdhmsIYUfFmvHpzaQtu8J6uWOp X-Google-Smtp-Source: AGHT+IGbBFTZCFjbo4ph4l2nyZz9Qwlay26rDeNFJWCsrjae8kgKRU7fB9cJb5bwIxjoBC6xyIld/g== X-Received: by 2002:a05:6000:250f:b0:3a4:f936:7882 with SMTP id ffacd0b85a97d-3a8ffcca8b2mr18209555f8f.55.1751389658079; Tue, 01 Jul 2025 10:07:38 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/43] hw/intc/gicv3_its: Do not check its_class_name() Date: Tue, 1 Jul 2025 18:06:51 +0100 Message-ID: <20250701170720.4072660-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751389736853116600 From: Philippe Mathieu-Daud=C3=A9 Since commit cc5e719e2c8 ("kvm: require KVM_CAP_SIGNAL_MSI"), the single implementation of its_class_name() no longer returns NULL (it now always returns a valid char pointer). Hence, update the prototype docstring and remove the tautological checks that use the its_class_name() returned value. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Gustavo Romero Reviewed-by: Richard Henderson Reviewed-by: Eric Auger Message-id: 20250628195722.977078-2-gustavo.romero@linaro.org Signed-off-by: Peter Maydell --- include/hw/intc/arm_gicv3_its_common.h | 2 +- hw/arm/virt-acpi-build.c | 32 +++++++++++--------------- 2 files changed, 15 insertions(+), 19 deletions(-) diff --git a/include/hw/intc/arm_gicv3_its_common.h b/include/hw/intc/arm_g= icv3_its_common.h index 7dc712b38d2..3c7b543b018 100644 --- a/include/hw/intc/arm_gicv3_its_common.h +++ b/include/hw/intc/arm_gicv3_its_common.h @@ -128,7 +128,7 @@ struct GICv3ITSCommonClass { * Return the ITS class name to use depending on whether KVM acceleration * and KVM CAP_SIGNAL_MSI are supported * - * Returns: class name to use or NULL + * Returns: class name to use */ const char *its_class_name(void); =20 diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 7e8e0f0298d..9eee284c809 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -737,20 +737,18 @@ build_madt(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) memmap[VIRT_HIGH_GIC_REDIST2].si= ze); } =20 - if (its_class_name()) { - /* - * ACPI spec, Revision 6.0 Errata A - * (original 6.0 definition has invalid Length) - * 5.2.12.18 GIC ITS Structure - */ - build_append_int_noprefix(table_data, 0xF, 1); /* Type */ - build_append_int_noprefix(table_data, 20, 1); /* Length */ - build_append_int_noprefix(table_data, 0, 2); /* Reserved */ - build_append_int_noprefix(table_data, 0, 4); /* GIC ITS ID = */ - /* Physical Base Address */ - build_append_int_noprefix(table_data, memmap[VIRT_GIC_ITS].bas= e, 8); - build_append_int_noprefix(table_data, 0, 4); /* Reserved */ - } + /* + * ACPI spec, Revision 6.0 Errata A + * (original 6.0 definition has invalid Length) + * 5.2.12.18 GIC ITS Structure + */ + build_append_int_noprefix(table_data, 0xF, 1); /* Type */ + build_append_int_noprefix(table_data, 20, 1); /* Length */ + build_append_int_noprefix(table_data, 0, 2); /* Reserved */ + build_append_int_noprefix(table_data, 0, 4); /* GIC ITS ID */ + /* Physical Base Address */ + build_append_int_noprefix(table_data, memmap[VIRT_GIC_ITS].base, 8= ); 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a88c80bb28sm13475658f8f.43.2025.07.01.10.07.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 10:07:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751389659; x=1751994459; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=z3FS3pa/hJFQ3XazBFwVcLs+0F58UEBEFoq6YVldz6U=; b=TzohPTUJMTJvoiIqux5j4dC3P6SONAniudz7JGUTaOwtqerxgiTCcaMA86PiLUhX1l PS5q+kA4SPce89GeQKUZfMRvrwGyhVVu6KrVZ038ApDRefRHzpe+fE5yFt/B3PMj0SHq Dv5J/yF0Ys8s1urF+OKWIY2IoDur6j+odBjb7HpF3xBt79shEhcdFNPkek2RUgYDlRRO 8b+gIGdjkLzszS3/WohZIRGAdhaVBO/jP3vsi8/248cE/nJo2sQwmxwOyoLnmJQ5tw5G QNhgYsafHAhAPaT88kiSmw4pYdMZB+bCi1NVMGoZOVH48L6ni3vNWiOkGGzOstBZx9NF UxNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751389659; x=1751994459; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=z3FS3pa/hJFQ3XazBFwVcLs+0F58UEBEFoq6YVldz6U=; b=N6LSs0mf0sNRIwtUgfbaCf2LqTp7DWSReHJuVGqwFfmwcMGhfZmE3IRuuSa+fwatr7 jaETVlPnhSIWj4Bpyh5bJufI+Brgi9QesvfKbB39jURA6Nb1/n8QKd2B+GRJA0iyxo3y kYjKDRzNshlBtSCMwmofojof0hMfJWmuoIYw7OUYBRG6dM4sCIzSv1NBnNhiL4zD4lj2 rbSpMylCuY4uYh13DfIz94le+GhoyLKk2k+VnYKPfOBVtsKPT+NKp6enaCCdZ666sxz0 olTJTWeocI3hZZ8yUxpbPeVU6DsDjOWDGCysJlGGMxJO3gxSz7NRMUN8UvNAD9kInbJ/ wNFQ== X-Gm-Message-State: AOJu0YwJ121OFqSlWbG/7rH0a+FaEhjOvm9x06gULV7p4vIQiYiplc3I cSvJHl2yfGr+yqHSt1BeUf1YVGyBvscQGhIZS+1OICBiGtaZ+bPrHTqICjONwuL2u3Tmbuexldp f4+IB X-Gm-Gg: ASbGncslhJ8/+7vSN76Tb/ZeWMYrGxLgWMM03MmBiArjdLbaicgB7yYHOpwk9u0mV/E PLM8eLKlj9xWU3wL6/WSNixuxZaPypk28nSrJJMS9boqbC/0Hw9gXzYmeV/v6YRXiqAKm8QLTb0 9KOV6Mz++7B03RhUJcH2cADklXK9Ygk/dy8oX48JLj3BHQVkqzRTI8GXHMwaaNiM7kRVvEJJmox PKyLYQe/Dfim9oy5U3dV9U7CGHHXLioz9bd3cj6ao3Xwge7ucqgVf+y7eYZjQtNK7FzZdPYaBeg 2IeW3mN+1fSDDinjjmpINYP23AwPbt7nY7QvxpXgVmBLfzhCpXvBjhCsT9XfDYLrllRj X-Google-Smtp-Source: AGHT+IGhBDCQYHsFrr/puJelHd/xRVxXX7WYwqJiMBBfDNblxcIQnGFURb9On6widWE1YW9ojTGwZQ== X-Received: by 2002:a05:6000:4407:b0:3a5:52cc:346e with SMTP id ffacd0b85a97d-3a8fdb2accemr9792969f8f.6.1751389658928; Tue, 01 Jul 2025 10:07:38 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/43] hw/arm/virt: Simplify logic for setting instance's 'tcg_its' variable Date: Tue, 1 Jul 2025 18:06:52 +0100 Message-ID: <20250701170720.4072660-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751390380865116600 From: Gustavo Romero Because 'tcg_its' in the machine instance is set based on the machine class=E2=80=99s negated variable 'no_tcg_its', 'tcg_its' is the opposite of 'no_tcg_its' and hence the code in question can be simplified as: tcg_its =3D !no_tcg_its. Signed-off-by: Gustavo Romero Reviewed-by: Eric Auger Message-id: 20250628195722.977078-3-gustavo.romero@linaro.org Signed-off-by: Peter Maydell --- hw/arm/virt.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 99fde5836c9..6d9256a5255 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3342,12 +3342,8 @@ static void virt_instance_init(Object *obj) =20 /* Default allows ITS instantiation */ vms->its =3D true; - - if (vmc->no_tcg_its) { - vms->tcg_its =3D false; - } else { - vms->tcg_its =3D true; - } + /* Allow ITS emulation if the machine version supports it */ + vms->tcg_its =3D !vmc->no_tcg_its; =20 /* Default disallows iommu instantiation */ vms->iommu =3D VIRT_IOMMU_NONE; --=20 2.43.0 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1751390052; cv=none; d=zohomail.com; s=zohoarc; b=Vpbz3TNp4aeZG7Hywlzmr1DnnnV/t8z2mW6Kk0px35tp/pgya6vefb3dhA4l205B3Vj5FYTgikkbeEl/1NaolV7QngWEJ6oxpjMBMdveGl5lXzQsZeWZg2tuEMsVwA8G+EoakgFG8MCKenxZm7AXvDBy7EJjw2MBH7vhfchoOLs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751390052; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=QyDVgIZp4bZ0eZINB2aTxASGcxAgm9fpfWg3etKd2ss=; b=ihnwXcdyVg0eOJ7PgSOQDSA5sKx2qFdQD5A/5mOy2+voY5tZlanCChR06IcsDBhd08iZVmdPact95iVLLqBaDS2bmkuD9Dx5HZu3dcVT9dLHFdKPV8XmkmBw3qa9wKDpXKK1vef4xQO+gFA4R1pLnmcUbSzoHcw72c40J8irTdo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1751390052119489.2321484766801; Tue, 1 Jul 2025 10:14:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uWeSU-0005aC-NH; Tue, 01 Jul 2025 13:07:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uWeSQ-0005W3-EM for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:07:46 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uWeSL-0003Tz-Po for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:07:45 -0400 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-3a503d9ef59so2768939f8f.3 for ; Tue, 01 Jul 2025 10:07:41 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a88c80bb28sm13475658f8f.43.2025.07.01.10.07.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 10:07:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751389660; x=1751994460; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=QyDVgIZp4bZ0eZINB2aTxASGcxAgm9fpfWg3etKd2ss=; b=ino87tb3NOSjHiuWFxIZq885FKrRBFE0Op6Fv8jWujVyua//EUw0Vr4wZv9BxlWhCq izuQsiefZz3z3kDC2ULieg/HobvMUfypc89ZHOlBTyR9R79J3eSei4L77CJSBg9FTrNj ZYmk/o0wpImfzyTzLXt9qneFsVomhnadN/9ZxOdg7sIgbvMX7qYpneyFN+QS1H1t5y+N 8sj68hQgR/Dnk8dk8Xdcbb9Ssp7xaHSdy8WUKBD69lcNRl6BpcYrDm8MeZy1/v+XSov0 s9+R9z/tELVdbwR2COhyhWpTqujpNcWw6zqH/rpWdFtTo/+UL/gnBRLwdoDeenJlD6oW Z3Sg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751389660; x=1751994460; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QyDVgIZp4bZ0eZINB2aTxASGcxAgm9fpfWg3etKd2ss=; b=uhulFG7/ly2hsoUuGLMzVzUvg1P29UziZiNgKU+xgQsXISznwJYGEFpnLrx015ASLY PAOedpXV26o/X9hJ3P4dVPuLvyUNS6oGGvOB1hKrrWFGs4YuK+eUci3mHidbQHYQfFbn EcrGUmmU4XvxVbjQrF1UuEQSOOELx8zXEasuDjYQmd/TmsSL9stLSapzovSguo1y+P3P jI0i2nTPm2Yd3IbaM0J7eymarrAVDLs4bD4HLEhXw8OAW9fdKggx/V1olPzyncp7BrWx NztSIVIL0Hbq//WsCAmeDNWiOrh8GN/2LaSDqAYejIo6rvq+KlAur025SwCoPKxenlgg E1gQ== X-Gm-Message-State: AOJu0YyeduiLTN27FoahomE+82vUiLIMezezes6Ps1Ea1+mIWDIpjWmM fD21zvkbfk3N8QvDK4RwengY/O2JDDwnZUdFQPDWUdYi9g9UQV/1GDu4ItHlo3nT6m6rhU8lSuV GScW8 X-Gm-Gg: ASbGncvVdj1UXadnGOZR7QY7L9TIbnlV9hgAGV1ha9/hTLonSiTTKyNm9r/EIry/MJ3 knaByu7i7kh0yywklVKEaSsvYzJk4jZVJQH5QaGU7nRimVP6uOrQ1kjKboDIy5wKYhMPSvn/wy7 5SNzliPYFT38AeiXmY5GKtKECmZaMAhBu7AByGJEFUROPpykGDMV+17YZhs3ek7xNraVk1xvbGL qdQgVYnJ4vyWtMWuoMDbvmQRyKxjyYPOmjzqu0wfLHZcZAsKcuW1q/2KsuVXqNlbMOXzyyDCy5z LrVLb0kbRAAb/89I0TtW8tCaKfLUoG4DCB0jifHz4Ly35/L3CC/HuUZzCD295lwyP+WH X-Google-Smtp-Source: AGHT+IHJT2e69YKelHc25ATo1Q757ULd6PG/yYY2HdgCSY7hMY98iMS2tJJeLgxt0opClMW+N9HvQA== X-Received: by 2002:adf:b60e:0:b0:3a5:25e4:264f with SMTP id ffacd0b85a97d-3a8fdeff980mr12714619f8f.31.1751389659984; Tue, 01 Jul 2025 10:07:39 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/43] hw/arm/virt: Simplify create_its() Date: Tue, 1 Jul 2025 18:06:53 +0100 Message-ID: <20250701170720.4072660-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751390053392116600 From: Philippe Mathieu-Daud=C3=A9 No need to strstr() check the class name when we can use kvm_irqchip_in_kernel() to check if the ITS from the host can be used. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Eric Auger Reviewed-by: Gustavo Romero Message-id: 20250628195722.977078-4-gustavo.romero@linaro.org Signed-off-by: Peter Maydell --- hw/arm/virt.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 6d9256a5255..ae419e86712 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -705,21 +705,18 @@ static inline DeviceState *create_acpi_ged(VirtMachin= eState *vms) =20 static void create_its(VirtMachineState *vms) { - const char *itsclass =3D its_class_name(); DeviceState *dev; =20 - if (!strcmp(itsclass, "arm-gicv3-its")) { - if (!vms->tcg_its) { - itsclass =3D NULL; - } - } - - if (!itsclass) { - /* Do nothing if not supported */ + assert(vms->its); + if (!kvm_irqchip_in_kernel() && !vms->tcg_its) { + /* + * Do nothing if ITS is neither supported by the host nor emulated= by + * the machine. + */ return; } =20 - dev =3D qdev_new(itsclass); + dev =3D qdev_new(its_class_name()); =20 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic), &error_abort); --=20 2.43.0 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1751389759; cv=none; d=zohomail.com; s=zohoarc; b=TUBmXaV4lMpoC9OXdM0E9KI2q2QtoJAUJmcUORgCOLFY0e78/nM1hMM2lVADIKEGm9lXZ/wOm0CnIRISH8VAl7mtcgP7iwUR5EhxAeZBdag5Gn2DrRLuVF4MrSbmkBYBhGK3j+kdoV0vcMWQbkKjrA2XWIvTXQTHG1QsSo7ASKI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751389759; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=NhS7RJ8mQtVOq405DbFlZn2gFT3L5NLST1w6BzSpeM4=; b=WLbcJy3Nk70rU5UA8JhHOwa5+lVR+MOU2TeDYE2sfbFU1GaH+xf0vandEb1pcDq2likHWa0StrlVzsnYMJ72QhKu58g3MaaJ1OpESKDiSbmyRTFfyeyLDRemfUL0Z6J7t3PMwXJYYu7KP5Tub4cPG6Ip0FNYb+u1jLWe/VHUnzY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17513897598061021.5058371214192; Tue, 1 Jul 2025 10:09:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uWeSX-0005dY-LL; Tue, 01 Jul 2025 13:07:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uWeSR-0005Yd-S2 for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:07:48 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uWeSM-0003Ug-Q3 for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:07:47 -0400 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-3a536ecbf6fso3462789f8f.2 for ; Tue, 01 Jul 2025 10:07:42 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a88c80bb28sm13475658f8f.43.2025.07.01.10.07.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 10:07:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751389661; x=1751994461; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=NhS7RJ8mQtVOq405DbFlZn2gFT3L5NLST1w6BzSpeM4=; b=QtSNi3Fd7ethMioIIRsW2LU55TFPaSYJ662TjnUK52/4yh6Aoh4c2gFIpwbGi5HNDx 4rNHl4Y85/f5EW6BodxTKhmoI7DAMtl+FheVpERoQCKvdPgz4Agqgo6j9hbN3D8AlZz7 bKgZxSMb5R7RFowbbTe3+lS/9K02vGFER6eFROsoqyw41XhzW8n5cWHRM9L+o5a6ZtBj tpyP812a35hsaiR6oWYpm1J/pNnpGIAmZ5MssySe0sUOPyNTp8iGMFJ3KFLFwn8Y0HG0 jsHKG3JDLHSqIJ422CLx/rP46W0imOdvxGLL0yIN/rB8Jc5gNQWf1EXXgydOSfWnGthz Ym1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751389661; x=1751994461; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NhS7RJ8mQtVOq405DbFlZn2gFT3L5NLST1w6BzSpeM4=; b=c/7FSqH89mdMGIYFIqdeVlUAwQcL+/oyyryruhIw5dS59tWhpAQkRo3smruleF+41t y1mrH/0BRNqkHppZi/qS2uyT8YjpP6SQ+i6jWdE+H1l5FtZUKVszpfvaSnLBTKPVyCTZ 6wH+LP/KkDqVX2hvxpxEwKYAi95MkzeSezGLYwRNHk3d2iWzZTxaEU1sRdDHZnisYYSn FcHvU4LuCdFK1d+r4f1CdlDUzwYWjd8pYSsoKJUs/phpp5WyKLtk/CgtUGmk6MN+tSsS xrKENVZQskRGGriMVvik7MbMXoJv3cmTCDer9lQDfOufEkynqt8OOCR5zDlTL/Upzvab 9LBw== X-Gm-Message-State: AOJu0YwhstSHjbw3lwVwR80aqY7PndmW9a7J2vnnFty5gp2oJfSf71zp IMNxeJXru5D9KTE52EvOT1FoNERezMWqSRA6INjWf+K56JtjdX+j9aLGLQ+bwcjxiTXon447FNb sgy50 X-Gm-Gg: ASbGncvR7c2jypBzMcvMxemOtj254BXx1nKLtEp2R0s2B/OPZSPTU1xHtfp6s7FMav4 G9kgJPM5Ylisof1rtBR0m9j/ECshfA1h3o9gK+YqoRrMaOaIds2jB946N0M7JOp4isfyJSmfWge jX4bG7DLrv30rMD8moCV82vsbx2QXXQUcQmzc/eG93to4MgpKb+7LBbC6Vw0anszo8UNkjUZ5iF lls2EAyhux3jeHrbeVASxqeYnVFgy6/aWBMQiYD9FtzK7NYqJ9aNmNiqWpLCB88RAvmdXV+mVH1 jBLbZvBzhkATvgqfeImTZlvJ/cOgWzilvqB+vWE1TsgXADCPo4ntk4meunXNlUvxdp0c X-Google-Smtp-Source: AGHT+IHw9QqMbYXfKGge+25GwBrikk/VWM/v8O5cp7bW7JnDgXMIaxdFcxVpLpua942u/17G12JkHw== X-Received: by 2002:a05:6000:4011:b0:3a4:dd8e:e16b with SMTP id ffacd0b85a97d-3a8fe2d3c47mr15073529f8f.20.1751389660859; Tue, 01 Jul 2025 10:07:40 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/43] hw/arm/virt-acpi-build: Improve comment in build_iort Date: Tue, 1 Jul 2025 18:06:54 +0100 Message-ID: <20250701170720.4072660-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751389761092116600 Content-Type: text/plain; charset="utf-8" From: Gustavo Romero When building the Root Complex table, the comment about the code that maps the RC node to SMMU node is misleading because it reads "RC -> SMMUv3 -> ITS", but the code is only mapping the RCs IDs to the SMMUv3 node. The step of mapping from the SMMUv3 IDs to the ITS Group node is actually defined in another table (in the SMMUv3 node). So change the comment to read "RC -> SMMUv3" instead. Signed-off-by Gustavo Romero Reviewed-by: Eric Auger Message-id: 20250628195722.977078-5-gustavo.romero@linaro.org Signed-off-by: Peter Maydell --- hw/arm/virt-acpi-build.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 9eee284c809..e9cd3fb3511 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -370,7 +370,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) /* DeviceID mapping index (ignored since interrupts are GSIV based= ) */ build_append_int_noprefix(table_data, 0, 4); =20 - /* output IORT node is the ITS group node (the first node) */ + /* Output IORT node is the ITS Group node (the first node) */ build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET); } =20 @@ -407,23 +407,36 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3) { AcpiIortIdMapping *range; =20 - /* translated RIDs connect to SMMUv3 node: RC -> SMMUv3 -> ITS */ + /* + * Map RIDs (input) from RC to SMMUv3 nodes: RC -> SMMUv3. + * + * N.B.: The mapping from SMMUv3 to ITS Group node (SMMUv3 -> ITS)= is + * defined in the SMMUv3 table, where all SMMUv3 IDs are mapped to= the + * ITS Group node. + */ for (i =3D 0; i < smmu_idmaps->len; i++) { range =3D &g_array_index(smmu_idmaps, AcpiIortIdMapping, i); - /* output IORT node is the smmuv3 node */ + /* Output IORT node is the SMMUv3 node. */ build_iort_id_mapping(table_data, range->input_base, range->id_count, smmu_offset); } =20 - /* bypassed RIDs connect to ITS group node directly: RC -> ITS */ + /* + * Map bypassed (don't go throught the SMMU) RIDs (input) to ITS G= roup + * node directly: RC -> ITS. + */ for (i =3D 0; i < its_idmaps->len; i++) { range =3D &g_array_index(its_idmaps, AcpiIortIdMapping, i); - /* output IORT node is the ITS group node (the first node) */ + /* Output IORT node is the ITS Group node (the first node). */ build_iort_id_mapping(table_data, range->input_base, range->id_count, IORT_NODE_OFFSET); } } else { - /* output IORT node is the ITS group node (the first node) */ + /* + * Map all RIDs (input) to ITS Group node directly, since there is= no + * SMMU: RC -> ITS. + * Output IORT node is the ITS Group node (the first node). + */ build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET); } =20 --=20 2.43.0 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1751390456; cv=none; d=zohomail.com; s=zohoarc; b=GGWploXPNfSo1BrWRIY6CPHkwIsvjx5u6BcipmiUvDVIkmqvQUgiQDEvWco/0YyxDtQs+MfywVGf0KWY9JNL0IiBv8HgYVcaPQ73CWbHQ+guW4A9+gQ4bgJhdEKaaOeNk4SpkL4xd/1uu+k8fnZWwVUqvO2J7mY/LCKRZc2mDrE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751390456; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=2pAEd0wAmhj6AVBc7K+tCwpRXx/59qh0ouwfhyi5hL0=; b=QB1+ohB2LT4xiTmBUdoCADS3MWXMyGg24sEx7k5byTT6uUCOxkaAMaUI9eeIn5M1tUb2s3yawFHKo9YiqPPJnbR8xv5PxHzyFeJ4Mlgtt07CjWKRNfEwae2P8qmF8DH4z+7O2t7EiFhdjRNCnjuxYkTAtT/mO2BeuK0icLxRNfo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1751390456786190.30970929063562; Tue, 1 Jul 2025 10:20:56 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uWeSW-0005bd-6j; Tue, 01 Jul 2025 13:07:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uWeSR-0005Ye-Si for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:07:48 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uWeSN-0003VU-R4 for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:07:47 -0400 Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-3a507e88b0aso2773235f8f.1 for ; Tue, 01 Jul 2025 10:07:43 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a88c80bb28sm13475658f8f.43.2025.07.01.10.07.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 10:07:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751389662; x=1751994462; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=2pAEd0wAmhj6AVBc7K+tCwpRXx/59qh0ouwfhyi5hL0=; b=K6Lnjmjcz4nQ2+dosBGG0XjfrkG1Gw4e3mXFKjTXZ537N+P2BCPholIkosTGuoLHsI oDVx/Y6Qnt97LQRRkOuVzGTuVBSKtkeeH6UV7QFjiA32lxIbCapnhO9BWoE8VW1Xqw12 0GO19TcvGilTbBKxQ+/E3cSeSHSM08B6jmex61cLLxgpGqgOPuAdRqwfImL3lNQTrYuy o5Ej+6rv1tMt2x9WqAITIcyKfSsUHfRZagzhRXZFH/wYPX/JEoTZqWGC7nWy87GS1BJG rioNAucPa62aySBbMdM/D+UrYdamFAt31ThKxpya08JNizuDC2BQgnCSGmV6+3ztq8jO q2hQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751389662; x=1751994462; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2pAEd0wAmhj6AVBc7K+tCwpRXx/59qh0ouwfhyi5hL0=; b=Lnm5qBXAKtqrlkqy0ujAcMEa0nX31PPUseq3z6TlNcz8eXvG74XzXPMCy9Z/BszZ5l TxtmhW7OKSzX15xRB6/mv+WwHr/8EL4tlKtUgvLZgIM1NfWDlp8xV6Sf5Rg6bIBv/r1i orKh698UowkmD2jsIkzuQn3w/KysTF077qtmBs3tSvqKG6yP6GklLSJ5ukehGx7fp3RI FAoyZgwbXgLXiccfxbqfopQuay5Qd4z3/drYo4XBLMKqQvFtdfd1MhtOw9Bu0TaTRQc1 QeJfPsi8F7hpRSnZqKJHiUpG2806MKhYdDDxlT9T5ysgJy2/l+dXQgKARDPTOZsXRRi+ ZjmA== X-Gm-Message-State: AOJu0Ywu+6vh3t4o/a/+iuWvKTNFO5fxwxWy9yWYSCryw4OooZLPFWLz D++LAJ7wEaopzpAKp9NHnG2qqPR7N9BRZoc+0BWw5DEW6nI2Dybp1b6c/z3I9OUta8K5CYBvPWs BC7n6 X-Gm-Gg: ASbGncskpji+QqpkvIeb1q0K+y0yc42PQTmbPBnQqDg9tJYPl7IGHWOGZotwF/Apwkm deKJQXRwW3mUZVIROlcJB23lsU1heumyOVwXl8VKxVOu2HPWubyPeEitmYZuWecUqQJDJ8TGxDz cyDI3+eBb0EW4CqHm1ivK2nrek+IWMwAEn46ovVuIoqH6hPU+j9ZT5961wy8RmQ1CqArjj3GYXq 5u4eNDVAx+BM0M1gLgAmzRROnpKrKOmmRTFAy8Ldgp3wJyld5DmLnlIgnXzrTDbltn1Ar9xp9/f Bic2J1Np/UkiSRpWBsXPYov0z1ewTW2SKvF/pU/Hgfi1WuMsepTUb7cunGVp26wmcZqa X-Google-Smtp-Source: AGHT+IFxQG/EMmlROKRvb8QC6DoGBQ/+bikAu7HPaIH0ha84szBcdWzu+TIVo3JMD5yZf+RwSXon7Q== X-Received: by 2002:a05:6000:400b:b0:3b1:3466:6734 with SMTP id ffacd0b85a97d-3b134666914mr2336991f8f.44.1751389661713; Tue, 01 Jul 2025 10:07:41 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/43] hw/arm/virt-acpi-build: Factor out create_its_idmaps Date: Tue, 1 Jul 2025 18:06:55 +0100 Message-ID: <20250701170720.4072660-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751390458106116600 From: Gustavo Romero Factor out a new function, create_its_idmaps(), from the current build_iort code. Add proper comments to it clarifying how the ID ranges that go directly to the ITS Group node are computed based on the ones that are directed to the SMMU node. Suggested-by: Eric Auger Signed-off-by: Gustavo Romero Message-id: 20250628195722.977078-6-gustavo.romero@linaro.org [PMM: drop hardcoded tabs] Signed-off-by: Peter Maydell --- hw/arm/virt-acpi-build.c | 61 ++++++++++++++++++++++++++-------------- 1 file changed, 40 insertions(+), 21 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index e9cd3fb3511..5886192fe3f 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -266,6 +266,43 @@ static int iort_idmap_compare(gconstpointer a, gconstp= ointer b) return idmap_a->input_base - idmap_b->input_base; } =20 +/* Compute ID ranges (RIDs) from RC that are directed to the ITS Group nod= e */ +static void create_its_idmaps(GArray *its_idmaps, GArray *smmu_idmaps) +{ + AcpiIortIdMapping *idmap; + AcpiIortIdMapping next_range =3D {0}; + + /* + * Based on the RID ranges that are directed to the SMMU, determine the + * bypassed RID ranges, i.e., the ones that are directed to the ITS Gr= oup + * node and do not pass through the SMMU, by subtracting the SMMU-bound + * ranges from the full RID range (0x0000=E2=80=930xFFFF). + */ + for (int i =3D 0; i < smmu_idmaps->len; i++) { + idmap =3D &g_array_index(smmu_idmaps, AcpiIortIdMapping, i); + + if (next_range.input_base < idmap->input_base) { + next_range.id_count =3D idmap->input_base - next_range.input_b= ase; + g_array_append_val(its_idmaps, next_range); + } + + next_range.input_base =3D idmap->input_base + idmap->id_count; + } + + /* + * Append the last RC -> ITS ID mapping. + * + * RIDs are 16-bit, according to the PCI Express 2.0 Base Specificatio= n, rev + * 0.9, section 2.2.6.2, "Transaction Descriptor - Transaction ID Fiel= d", + * hence the end of the range is 0x10000. + */ + if (next_range.input_base < 0x10000) { + next_range.id_count =3D 0x10000 - next_range.input_base; + g_array_append_val(its_idmaps, next_range); + } +} + + /* * Input Output Remapping Table (IORT) * Conforms to "IO Remapping Table System Software on ARM Platforms", @@ -276,7 +313,6 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) { int i, nb_nodes, rc_mapping_count; size_t node_size, smmu_offset =3D 0; - AcpiIortIdMapping *idmap; uint32_t id =3D 0; GArray *smmu_idmaps =3D g_array_new(false, true, sizeof(AcpiIortIdMapp= ing)); GArray *its_idmaps =3D g_array_new(false, true, sizeof(AcpiIortIdMappi= ng)); @@ -287,8 +323,6 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) acpi_table_begin(&table, table_data); =20 if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3) { - AcpiIortIdMapping next_range =3D {0}; - object_child_foreach_recursive(object_get_root(), iort_host_bridges, smmu_idmaps); =20 @@ -296,25 +330,10 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) g_array_sort(smmu_idmaps, iort_idmap_compare); =20 /* - * Split the whole RIDs by mapping from RC to SMMU, - * build the ID mapping from RC to ITS directly. + * Knowing the ID ranges from the RC to the SMMU, it's possible to + * determine the ID ranges from RC that are directed to the ITS. */ - for (i =3D 0; i < smmu_idmaps->len; i++) { - idmap =3D &g_array_index(smmu_idmaps, AcpiIortIdMapping, i); - - if (next_range.input_base < idmap->input_base) { - next_range.id_count =3D idmap->input_base - next_range.inp= ut_base; - g_array_append_val(its_idmaps, next_range); - } - - next_range.input_base =3D idmap->input_base + idmap->id_count; - } - - /* Append the last RC -> ITS ID mapping */ - if (next_range.input_base < 0x10000) { - next_range.id_count =3D 0x10000 - next_range.input_base; - g_array_append_val(its_idmaps, next_range); - } + create_its_idmaps(its_idmaps, smmu_idmaps); =20 nb_nodes =3D 3; /* RC, ITS, SMMUv3 */ rc_mapping_count =3D smmu_idmaps->len + its_idmaps->len; --=20 2.43.0 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1751390238; cv=none; d=zohomail.com; s=zohoarc; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a88c80bb28sm13475658f8f.43.2025.07.01.10.07.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 10:07:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751389663; x=1751994463; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=VBvxJ1cilsn9V1RB9o7d6hcyA6rSrn3aogssV0H3S/w=; b=cmoi+F1Y7p08f9ic11Z74om+I+vTK521iIgBHzmnPVyOz9TAd6OgJRRQgNF89uzSkQ JKkGRHM8aSgJkvNnD3sMiCgQMy+/NA+Zvl5foxy2AawR/a6gDzoqmsIdtb4TzdNzrhcN 8CeTQsaZ/Daull0K556YShg7GU2kLo5XJyopsMF52iQxzs19jhLZUDPMyA9jdqh8MxS+ 3V8u7Jt1pcbBs8VJ6divfhKeJbnMv1bXGHVqmFVRQgv7IE2eARXm+BaNfAcZDKdt9txN 2oTHH5aB2NSXCZxgDkAMNd6g/z/xBemEwUT882kLiIW2WrqzK/tVecnQfkkWKd6FQXgn WNFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751389663; x=1751994463; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VBvxJ1cilsn9V1RB9o7d6hcyA6rSrn3aogssV0H3S/w=; b=XMINd11AB+khGP15Ey8BabDSjVctFfMyx0e3A8CRF22tJI/REmSpzRporxY8Ws7YnN Cs1Vykt2EhO1PgaWFr/d0qfXS84of9YC8uQr6sLtTnfsjFl3iqcEtOAtofitgwvHD3ve PS2YR3UbI6FbqfPSpwCx05RRHhDkpVMw8WvUfVZDReXn5HvNhJ8ug5agaMNOmAy5WQKr ObMIERqZRzJg8GhxNGY+ozp55SD2Ro1w14nl5U2rusB07HScPvmX6bGmmvej/QUNY0X0 5OhFx35AnDYs4Gre1qdnxgHP4VF1QdYlyirakrLkuSSVTZAbqZK7AadHG8OR/0NVBxVl Z2SQ== X-Gm-Message-State: AOJu0Yw6+iyH1h4GJk95xT9UbQgAxHSnr+ZpsrStTNPVaFYOxljhze0d wNw8uRLqvVBXfFsUNkmR5ROJfl6cdKHYb6kASIhA/NVHc6fnx8pWFiMeOWhhc7I8ERVMh0Cj/wp 3XiHS X-Gm-Gg: ASbGncueHKZjVRYEpUPboHsgODf/rYMhdPu1BzwdNwwYuBk4ZvjQOvhx7SHjMItj0Zj MgL+4Id5OmsDAGS9Gq4YEytKw0PSghkKXTsyfxPdCsA5bldi4GmzkDFy2Ms6p9c9vk0ax7i9ho9 0J5tIMcC1SiMUTxyUwb0whrgAMmOOVv4qNuPTsMMgSVJp2OdkoyfGWImHhAt8MLTOXxN0vxrNrg EPKLxyfy/KgpHfHX0I5gFO5vSgbBPyvXFNb+XUbJsEDUAyj+waOSoijh0/X+jAOIqKC+NY0hZfP 6/uAAAHsthfbY7n1tXrgdeeVeusTyEHzUQnjaV/FKVkpq2KbhPWkWAZPu8rAXkDqi8LU X-Google-Smtp-Source: AGHT+IHESZ7+ZFMbLry/oN0ZLhhp2B3Vyc+k3H1jCX8eOsjHe48I6G6p10zDdR3wp0p1I/UiP+vkRA== X-Received: by 2002:a05:600c:138a:b0:451:edc8:7806 with SMTP id 5b1f17b1804b1-453a629bc0emr51099325e9.32.1751389662607; Tue, 01 Jul 2025 10:07:42 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/43] qtest/bios-tables-test: Add test for when ITS is off on aarch64 Date: Tue, 1 Jul 2025 18:06:56 +0100 Message-ID: <20250701170720.4072660-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751390240026116600 From: Philippe Mathieu-Daud=C3=A9 Arm64 GIC ITS (Interrupt Translation Service) is an optional piece of hardware introduced in GICv3 and, being optional, it can be disabled in QEMU aarch64 VMs that support it using machine option "its=3Doff", like, for instance: "-M virt,its=3Doff". In ACPI, the ITS is advertised, if present, in the MADT (aka APIC) table, while the ID mappings from the Root Complex (RC) and from the SMMU nodes to the ITS Group nodes are described in the IORT table. This new test verifies that when the "its=3Doff" option is passed to the machine the ITS-related data is correctly pruned from the ACPI tables. The new blobs for this test will be added in a following commit. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Gustavo Romero Reviewed-by: Eric Auger Message-id: 20250628195722.977078-7-gustavo.romero@linaro.org Signed-off-by: Peter Maydell --- tests/qtest/bios-tables-test-allowed-diff.h | 2 ++ tests/qtest/bios-tables-test.c | 21 +++++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index dfb8523c8bf..a88198d5c2a 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,3 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/aarch64/virt/APIC.its_off", +"tests/data/acpi/aarch64/virt/IORT.its_off", diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index 0b2bdf9d0d4..4dbc07ec5ea 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -2146,6 +2146,25 @@ static void test_acpi_aarch64_virt_tcg_topology(void) free_test_data(&data); } =20 +static void test_acpi_aarch64_virt_tcg_its_off(void) +{ + test_data data =3D { + .machine =3D "virt", + .arch =3D "aarch64", + .variant =3D ".its_off", + .tcg_only =3D true, + .uefi_fl1 =3D "pc-bios/edk2-aarch64-code.fd", + .uefi_fl2 =3D "pc-bios/edk2-arm-vars.fd", + .cd =3D "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.= qcow2", + .ram_start =3D 0x40000000ULL, + .scan_len =3D 128ULL * 1024 * 1024, + }; + + test_acpi_one("-cpu cortex-a57 " + "-M gic-version=3D3,iommu=3Dsmmuv3,its=3Doff", &data); + free_test_data(&data); +} + static void test_acpi_q35_viot(void) { test_data data =3D { @@ -2577,6 +2596,8 @@ int main(int argc, char *argv[]) test_acpi_aarch64_virt_tcg_acpi_hmat); qtest_add_func("acpi/virt/topology", test_acpi_aarch64_virt_tcg_topology); + qtest_add_func("acpi/virt/its_off", + test_acpi_aarch64_virt_tcg_its_off); qtest_add_func("acpi/virt/numamem", test_acpi_aarch64_virt_tcg_numamem); qtest_add_func("acpi/virt/memhp", test_acpi_aarch64_virt_tcg_m= emhp); --=20 2.43.0 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1751389759; cv=none; d=zohomail.com; s=zohoarc; b=hoiQGsEoLXtu2gHyVW96wpQH8k0L0kb/ZHjiiQEKNt5qtG411Hmhvtv/OJWnh7xnhq/pBkFwoAm0V+x223AiDrH2LGmwBsbAkqIF5ypPTOngjanNFIDWXdYkwmqoQgaJb2H3gmbxN8FTo4mpZPemhpxBa88YM4A829966dxL/Ig= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751389759; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=ZYrrLyr/saAOViaU/sbCgDnzy/SOE3ZpjXc7CElUC4s=; b=eA6/Uk4Vv0ImABRkXSlji1otNELvWdiFBE1pEVN9N7IKGURafTATvMctU0O86N8feouuZJiNe5pd94/vWPY4PGqS0G4IJ9eWQi7HMGRBxT0Lgjgm4CLuuYlHM6B1cNN7JpXuRtAaIxcziUdrgsLaOjZu7Bwf3/NAIeuSZRwEMCA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1751389759060621.8183328756537; Tue, 1 Jul 2025 10:09:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uWeSY-0005ee-FT; Tue, 01 Jul 2025 13:07:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uWeST-0005Zp-S0 for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:07:49 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uWeSQ-0003Wo-6f for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:07:49 -0400 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-453643020bdso51658025e9.1 for ; Tue, 01 Jul 2025 10:07:45 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a88c80bb28sm13475658f8f.43.2025.07.01.10.07.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 10:07:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751389664; x=1751994464; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ZYrrLyr/saAOViaU/sbCgDnzy/SOE3ZpjXc7CElUC4s=; b=EyFF+sy8LOAozMRo1NnSA88M5nLGNZWBDY7z73cdG9XmlDKwM+8IFLAOYpWSCwIt1I m7zmcghTz1u+xtB1bswKAwna+H6GE9TusIMms7e+vReSAraV5gA+ahzDHKCSSodFzgmQ KE5m7Z+EDInDqiT68RG2XT3bHp3HWoYp77WYQhs8pTw0N82Qne9vpgEqFwYPJ89qLkV5 7pwf7WbyVEWV2PWWRU1snsChPqs/TUvy9aGmrNvjjNjnieCfZdnDF7/Jm9Raxtbw+5Pm Ln49DvcC7FzbAoTIQhPD84Nd8rWYjcRjNGm6xvahvAkJ4Md3ZdFS00QuKNz1T0jIKaLW Zggg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751389664; x=1751994464; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZYrrLyr/saAOViaU/sbCgDnzy/SOE3ZpjXc7CElUC4s=; b=W5IRppaSGTnBgvhrWL+qhODH7qjGA5l4bM2O9F15vu/Zfi73HKO/+Q2uEF+PFmThA8 Di0VGBITkcEAaGp0VtQAL0azlQz7Cy2Ck552T66VTQfXFTYsWHPx+Bym0r/ozXXK0OWw 85o2TjRasxuMdQgaa5RUbamSr+8Ml3b5GTWNo5/9Tx9s1s7oHAuo7WAgl2RaxQtEe2ya 1cuNJ2u5k69g9FGwsJVKK8zTZHxp/Z4k4grTlZm2k0RrGR/9RimbRGb9M+AonVO9Y5z9 ovTRh3VuE0p8WZfYirlratTJTll61lT1VC5LazWsxd3Emn9RagW4sGYZNrXiQNF/7QTC PrlA== X-Gm-Message-State: AOJu0Yyo6Y3yLQPHrH/d2TgjqzhXWrm/l6h2UZbV2gPfmMT8g551tTBz mLOXzEhY07O0/PmBuDAklAan71lEPoCKFVGKvhSdQyOa2mAlZYslLECA+8iMFWKO9Oa5BQWVOv0 pgolZ X-Gm-Gg: ASbGncuQLMMRuf5X3h4bxeWKV6z/uvGrHO7m5N3GFipcjkeB/FmmlC/3Xpnso213f5L LdDG3LKOgr8eAS+p0aJ6kuEMe0sNM1UKkuT+P2OXuBqLtOF57pV1PjAleg0ffW+Ge15hYdZQ6de +gES3UHnklNgw1rM3U5xfjPdY152A23foXrzlw+kTtUZzg+ALjrLD4KlhbOkBnDeXmLuMKAr1CX vMqt4SSWl4bZad0mCtDcckYlpnfmv8EQ46aJv9Ehb83OoCYTAGMlKWM23TELzMk67niTtrOSvHd rCe6BwuEQeX3ZGrgfyBC3Tmxq7hPcTgGLsbKorvzsn6Rll252hEQdDpCxtBOKTqA0fWS X-Google-Smtp-Source: AGHT+IEb8sYOFJO0HQ4qbN/YENnWqt06rTZ5PsFqEuVcblqnxl/dArKPniFsg99R+1uAaQXRPbE+Yg== X-Received: by 2002:a05:600c:4fd6:b0:442:e03b:58a9 with SMTP id 5b1f17b1804b1-4538ee8567cmr154624655e9.25.1751389663910; Tue, 01 Jul 2025 10:07:43 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/43] qtest/bios-tables-test: Add blobs for its=off test on aarch64 Date: Tue, 1 Jul 2025 18:06:57 +0100 Message-ID: <20250701170720.4072660-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751389761323116600 Content-Type: text/plain; charset="utf-8" From: Gustavo Romero Add blobs for test_acpi_aarch64_virt_tcg_its_off(), which introduces a new variant, .its_off, that requires variations of the MADT and IORT tables. MADT (aka APIC) diff: +[000h 0000 4] Signature : "APIC" [Multiple APIC De= scription Table (MADT)] +[004h 0004 4] Table Length : 000000B8 +[008h 0008 1] Revision : 04 +[009h 0009 1] Checksum : C1 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : 00000000 +[028h 0040 4] Flags (decoded below) : 00000000 + PC-AT Compatibility : 0 + +[02Ch 0044 1] Subtable Type : 0C [Generic Interrupt Distr= ibutor] +[02Dh 0045 1] Length : 18 +[02Eh 0046 2] Reserved : 0000 +[030h 0048 4] Local GIC Hardware ID : 00000000 +[034h 0052 8] Base Address : 0000000008000000 +[03Ch 0060 4] Interrupt Base : 00000000 +[040h 0064 1] Version : 03 +[041h 0065 3] Reserved : 000000 + +[044h 0068 1] Subtable Type : 0B [Generic Interrupt Contr= oller] +[045h 0069 1] Length : 50 +[046h 0070 2] Reserved : 0000 +[048h 0072 4] CPU Interface Number : 00000000 +[04Ch 0076 4] Processor UID : 00000000 +[050h 0080 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[054h 0084 4] Parking Protocol Version : 00000000 +[058h 0088 4] Performance Interrupt : 00000017 +[05Ch 0092 8] Parked Address : 0000000000000000 +[064h 0100 8] Base Address : 0000000000000000 +[06Ch 0108 8] Virtual GIC Base Address : 0000000000000000 +[074h 0116 8] Hypervisor GIC Base Address : 0000000000000000 +[07Ch 0124 4] Virtual GIC Interrupt : 00000000 +[080h 0128 8] Redistributor Base Address : 0000000000000000 +[088h 0136 8] ARM MPIDR : 0000000000000000 +[090h 0144 1] Efficiency Class : 00 +[091h 0145 1] Reserved : 00 +[092h 0146 2] SPE Overflow Interrupt : 0000 + +[094h 0148 1] Subtable Type : 0E [Generic Interrupt Redis= tributor] +[095h 0149 1] Length : 10 +[096h 0150 2] Reserved : 0000 +[098h 0152 8] Base Address : 00000000080A0000 +[0A0h 0160 4] Length : 00F60000 + +[0A4h 0164 1] Subtable Type : 0F [Generic Interrupt Trans= lator] +[0A5h 0165 1] Length : 14 +[0A6h 0166 2] Reserved : 0000 +[0A8h 0168 4] Translation ID : 00000000 +[0ACh 0172 8] Base Address : 0000000008080000 +[0B4h 0180 4] Reserved : 00000000 IORT diff: +[000h 0000 4] Signature : "IORT" [IO Remapping Tab= le] +[004h 0004 4] Table Length : 000000EC +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 57 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Node Count : 00000003 +[028h 0040 4] Node Offset : 00000030 +[02Ch 0044 4] Reserved : 00000000 + +[030h 0048 1] Type : 00 +[031h 0049 2] Length : 0018 +[033h 0051 1] Revision : 01 +[034h 0052 4] Reserved : 00000000 +[038h 0056 4] Mapping Count : 00000000 +[03Ch 0060 4] Mapping Offset : 00000000 + +[040h 0064 4] ItsCount : 00000001 +[044h 0068 4] Identifiers : 00000000 + +[048h 0072 1] Type : 04 +[049h 0073 2] Length : 0058 +[04Bh 0075 1] Revision : 04 +[04Ch 0076 4] Reserved : 00000001 +[050h 0080 4] Mapping Count : 00000001 +[054h 0084 4] Mapping Offset : 00000044 + +[058h 0088 8] Base Address : 0000000009050000 +[060h 0096 4] Flags (decoded below) : 00000001 + COHACC Override : 1 + HTTU Override : 0 + Proximity Domain Valid : 0 +[064h 0100 4] Reserved : 00000000 +[068h 0104 8] VATOS Address : 0000000000000000 +[070h 0112 4] Model : 00000000 +[074h 0116 4] Event GSIV : 0000006A +[078h 0120 4] PRI GSIV : 0000006B +[07Ch 0124 4] GERR GSIV : 0000006D +[080h 0128 4] Sync GSIV : 0000006C +[084h 0132 4] Proximity Domain : 00000000 +[088h 0136 4] Device ID Mapping Index : 00000000 + +[08Ch 0140 4] Input base : 00000000 +[090h 0144 4] ID Count : 0000FFFF +[094h 0148 4] Output Base : 00000000 +[098h 0152 4] Output Reference : 00000030 +[09Ch 0156 4] Flags (decoded below) : 00000000 + Single Mapping : 0 + +[0A0h 0160 1] Type : 02 +[0A1h 0161 2] Length : 004C +[0A3h 0163 1] Revision : 03 +[0A4h 0164 4] Reserved : 00000002 +[0A8h 0168 4] Mapping Count : 00000002 +[0ACh 0172 4] Mapping Offset : 00000024 + +[0B0h 0176 8] Memory Properties : [IORT Memory Access Propert= ies] +[0B0h 0176 4] Cache Coherency : 00000001 +[0B4h 0180 1] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0B5h 0181 2] Reserved : 0000 +[0B7h 0183 1] Memory Flags (decoded below) : 03 + Coherency : 1 + Device Attribute : 1 +[0B8h 0184 4] ATS Attribute : 00000000 +[0BCh 0188 4] PCI Segment Number : 00000000 +[0C0h 0192 1] Memory Size Limit : 40 +[0C1h 0193 3] Reserved : 000000 + +[0C4h 0196 4] Input base : 00000000 +[0C8h 0200 4] ID Count : 000000FF +[0CCh 0204 4] Output Base : 00000000 +[0D0h 0208 4] Output Reference : 00000048 +[0D4h 0212 4] Flags (decoded below) : 00000000 + Single Mapping : 0 + +[0D8h 0216 4] Input base : 00000100 +[0DCh 0220 4] ID Count : 0000FEFF +[0E0h 0224 4] Output Base : 00000100 +[0E4h 0228 4] Output Reference : 00000030 +[0E8h 0232 4] Flags (decoded below) : 00000000 + Single Mapping : 0 Signed-off-by: Gustavo Romero Reviewed-by: Eric Auger Message-id: 20250628195722.977078-8-gustavo.romero@linaro.org Signed-off-by: Peter Maydell --- tests/qtest/bios-tables-test-allowed-diff.h | 2 -- tests/data/acpi/aarch64/virt/APIC.its_off | Bin 0 -> 184 bytes tests/data/acpi/aarch64/virt/IORT.its_off | Bin 0 -> 236 bytes 3 files changed, 2 deletions(-) create mode 100644 tests/data/acpi/aarch64/virt/APIC.its_off create mode 100644 tests/data/acpi/aarch64/virt/IORT.its_off diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index a88198d5c2a..dfb8523c8bf 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,3 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/aarch64/virt/APIC.its_off", -"tests/data/acpi/aarch64/virt/IORT.its_off", diff --git a/tests/data/acpi/aarch64/virt/APIC.its_off b/tests/data/acpi/aa= rch64/virt/APIC.its_off new file mode 100644 index 0000000000000000000000000000000000000000..37d82e970b1331cb5b259f0bd2d= 3654bacb2d623 GIT binary patch literal 184 zcmZ<^@O0k6z`($A(8=3DG~BUr&HBEVSz2pEB4AU24G0Uik$i-7~iVg@p}17JJ`2AFzr Zgb>LrJ^_#xE~p*f82CkCMsUFG1ppOZ2>}2A literal 0 HcmV?d00001 diff --git a/tests/data/acpi/aarch64/virt/IORT.its_off b/tests/data/acpi/aa= rch64/virt/IORT.its_off new file mode 100644 index 0000000000000000000000000000000000000000..0fceb820d509e852ca0849baf56= 8a8e93e426738 GIT binary patch literal 236 zcmebD4+?q1z`(#9?&R<65v<@85#X!<1dKp25F11@1F-=3DRgMkDCNC*yK9F_TjFfcO#g+N#Zh@s|zoCF3AP#UU@ R!2`+%Dg6Hr$N|zYvjDIZ5CH%H literal 0 HcmV?d00001 --=20 2.43.0 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a88c80bb28sm13475658f8f.43.2025.07.01.10.07.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 10:07:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751389665; x=1751994465; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=8nJYMFQTTQlV3cPi/X87l7YEfQlAZXZ97oIiIECIivw=; b=lqwhjkphRRLj2UCn+1Vt7KwHwThtQA3cczOoHHUKSPmH0eO+DSAAOdysDtlXT3sATK BGAs6AC63VLoErrHhfHDHt2C5Y/LvYJ1I8iWBUaDkcEJs5z+HCAP2xzPXp6VnvwE+/Nn WVahvee8A0dnbI0roODSTNLtK57Ouc1ZqzaFupLKByTXEQW56XJP5VYIlOYCkPKPnSxc +YGzK/58zoZObNWpoRE/m9zfgdDrciHp27Ecv0H+G+8F53UkA4y5vkZ/W0GA+x5fdVtf 7X1/eW7xqv8JoRbPjrW9htdNFJcfB3gqTDunj7m2JqSWjsocZNY0rlYtJm8J/6LclVlL VBbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751389665; x=1751994465; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8nJYMFQTTQlV3cPi/X87l7YEfQlAZXZ97oIiIECIivw=; b=m+W/uoU5B5BQ9O/04k9LcETDcAr12VRPm7bfn5SSwO8J8AMjwjTjzSks9vPw2Dkcaj Myzh09wLjXKoNxkplUSH0SJUb5CAr1DfdLExMyKh3+SfKWH8e3+farJ+cNaVh8Venn8T DYkRP5pj9XCYylhq2+tBd13Ss/CROKYMblfvGbXnNC9P+XUduHxsyswReTt8jHNf0+Es 9Ft9A4aTO133oiVlgU7wS/zSzbR7fumKWscZ/JfvRGZIDe1CTS7hi47MOaGLfGbonbws +/NmCkjN/5QRV2LWBnxxb9cbTkCesNxfUTMainsZw1nsYHPzDHKoelTfaJHg2QTzPWuA bvXQ== X-Gm-Message-State: AOJu0YyMCApdpti1ed1YeiGEU+kcxY8HvJOVihtKbFVCWBvrZEZWI5bs Wy5NyI5HLbjTx/Mx5i2sdUGn+vFF/51OQRsJunZrw6kePEaWaor7lGVwbrcWoIESIQo5FPC2p05 LyaKY X-Gm-Gg: ASbGnctsaLqfsHUz9VsaA2BTYHquEBnY4zmPW7OiljHFGQa/r23O0zHHiICDh9m2iIC qhkBLgKpOdGTY6ivEfZboFax13SAzF2eq4sHoG+Q2N8BKEYn0hpWajTcTcXReYJNr8DAPe1C3Bd kOBA547iy6AmRpnCOeSqX/dJVsDk7O898XExFu3Ls0fMgv60NxzEp1vVluUv25/msue1YSOQ9sB kc+ERnzsBHsNyMqgX8SmQfWVCjSjtq3T2mmfNksEGTnGrSfBvn39Oa+RYo1UtzObW2x6SFP8TxN 15VPpw5HGhUjIugOK2uLihCMCz2tFxmFlRmi1IQjo0DyMH5PIv4mGO2uszjeDHkaXJd2 X-Google-Smtp-Source: AGHT+IG7C0fyAcYUoS/NQ70Cxzj+20uLHwxg8kI2njr5lE3zSdWGDO3fAdZvuh0yaEpQtRc8Qzm0/A== X-Received: by 2002:a05:600c:4f06:b0:442:e9eb:1b48 with SMTP id 5b1f17b1804b1-4539002c9f6mr178124175e9.24.1751389664872; Tue, 01 Jul 2025 10:07:44 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/43] hw/arm/virt-acpi-build: Fix ACPI IORT and MADT tables when its=off Date: Tue, 1 Jul 2025 18:06:58 +0100 Message-ID: <20250701170720.4072660-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751389880740116600 From: Gustavo Romero Currently, the ITS Group nodes in the IORT table and the GIC ITS Struct in the MADT table are always generated, even if GIC ITS is not available on the machine. This commit fixes it by not generating the ITS Group nodes, not mapping any other node to them, and not advertising the GIC ITS in the MADT table, when GIC ITS is not available on the machine. Since the fix changes the MADT and IORT tables, add the blobs for the "its=3Doff" test to the allow list and update them in the next commit. This commit also renames the smmu_idmaps and its_idmaps variables in build_iort() to rc_smmu_idmaps and rc_its_idmaps, respectively, to make it clearer which nodes are involved in the mappings associated with these variables. Reported-by: Udo Steinberg Signed-off-by: Gustavo Romero Message-id: 20250628195722.977078-9-gustavo.romero@linaro.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2886 Signed-off-by: Gustavo Romero Co-authored-by: Philippe Mathieu-Daud=C3=A9 [PMM: wrapped an overlong comment] Signed-off-by: Peter Maydell --- tests/qtest/bios-tables-test-allowed-diff.h | 2 + hw/arm/virt-acpi-build.c | 140 ++++++++++++-------- 2 files changed, 89 insertions(+), 53 deletions(-) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index dfb8523c8bf..a88198d5c2a 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,3 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/aarch64/virt/APIC.its_off", +"tests/data/acpi/aarch64/virt/IORT.its_off", diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 5886192fe3f..cd90c47976c 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -267,7 +267,7 @@ static int iort_idmap_compare(gconstpointer a, gconstpo= inter b) } =20 /* Compute ID ranges (RIDs) from RC that are directed to the ITS Group nod= e */ -static void create_its_idmaps(GArray *its_idmaps, GArray *smmu_idmaps) +static void create_rc_its_idmaps(GArray *its_idmaps, GArray *smmu_idmaps) { AcpiIortIdMapping *idmap; AcpiIortIdMapping next_range =3D {0}; @@ -314,8 +314,8 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) int i, nb_nodes, rc_mapping_count; size_t node_size, smmu_offset =3D 0; uint32_t id =3D 0; - GArray *smmu_idmaps =3D g_array_new(false, true, sizeof(AcpiIortIdMapp= ing)); - GArray *its_idmaps =3D g_array_new(false, true, sizeof(AcpiIortIdMappi= ng)); + GArray *rc_smmu_idmaps =3D g_array_new(false, true, sizeof(AcpiIortIdM= apping)); + GArray *rc_its_idmaps =3D g_array_new(false, true, sizeof(AcpiIortIdMa= pping)); =20 AcpiTable table =3D { .sig =3D "IORT", .rev =3D 3, .oem_id =3D vms->oe= m_id, .oem_table_id =3D vms->oem_table_id }; @@ -324,22 +324,38 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) =20 if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3) { object_child_foreach_recursive(object_get_root(), - iort_host_bridges, smmu_idmaps); + iort_host_bridges, rc_smmu_idmaps); =20 /* Sort the smmu idmap by input_base */ - g_array_sort(smmu_idmaps, iort_idmap_compare); + g_array_sort(rc_smmu_idmaps, iort_idmap_compare); =20 /* * Knowing the ID ranges from the RC to the SMMU, it's possible to * determine the ID ranges from RC that are directed to the ITS. */ - create_its_idmaps(its_idmaps, smmu_idmaps); + create_rc_its_idmaps(rc_its_idmaps, rc_smmu_idmaps); =20 - nb_nodes =3D 3; /* RC, ITS, SMMUv3 */ - rc_mapping_count =3D smmu_idmaps->len + its_idmaps->len; + nb_nodes =3D 2; /* RC and SMMUv3 */ + rc_mapping_count =3D rc_smmu_idmaps->len; + + if (vms->its) { + /* + * Knowing the ID ranges from the RC to the SMMU, it's possibl= e to + * determine the ID ranges from RC that go directly to ITS. + */ + create_rc_its_idmaps(rc_its_idmaps, rc_smmu_idmaps); + + nb_nodes++; /* ITS */ + rc_mapping_count +=3D rc_its_idmaps->len; + } } else { - nb_nodes =3D 2; /* RC, ITS */ - rc_mapping_count =3D 1; + if (vms->its) { + nb_nodes =3D 2; /* RC and ITS */ + rc_mapping_count =3D 1; /* Direct map to ITS */ + } else { + nb_nodes =3D 1; /* RC only */ + rc_mapping_count =3D 0; /* No output mapping */ + } } /* Number of IORT Nodes */ build_append_int_noprefix(table_data, nb_nodes, 4); @@ -348,31 +364,43 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) build_append_int_noprefix(table_data, IORT_NODE_OFFSET, 4); build_append_int_noprefix(table_data, 0, 4); /* Reserved */ =20 - /* Table 12 ITS Group Format */ - build_append_int_noprefix(table_data, 0 /* ITS Group */, 1); /* Type */ - node_size =3D 20 /* fixed header size */ + 4 /* 1 GIC ITS Identifier = */; - build_append_int_noprefix(table_data, node_size, 2); /* Length */ - build_append_int_noprefix(table_data, 1, 1); /* Revision */ - build_append_int_noprefix(table_data, id++, 4); /* Identifier */ - build_append_int_noprefix(table_data, 0, 4); /* Number of ID mappings = */ - build_append_int_noprefix(table_data, 0, 4); /* Reference to ID Array = */ - build_append_int_noprefix(table_data, 1, 4); /* Number of ITSs */ - /* GIC ITS Identifier Array */ - build_append_int_noprefix(table_data, 0 /* MADT translation_id */, 4); + if (vms->its) { + /* Table 12 ITS Group Format */ + build_append_int_noprefix(table_data, 0 /* ITS Group */, 1); /* Ty= pe */ + node_size =3D 20 /* fixed header size */ + 4 /* 1 GIC ITS Identif= ier */; + build_append_int_noprefix(table_data, node_size, 2); /* Length */ + build_append_int_noprefix(table_data, 1, 1); /* Revision */ + build_append_int_noprefix(table_data, id++, 4); /* Identifier */ + build_append_int_noprefix(table_data, 0, 4); /* Number of ID mappi= ngs */ + build_append_int_noprefix(table_data, 0, 4); /* Reference to ID Ar= ray */ + build_append_int_noprefix(table_data, 1, 4); /* Number of ITSs */ + /* GIC ITS Identifier Array */ + build_append_int_noprefix(table_data, 0 /* MADT translation_id */,= 4); + } =20 if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3) { int irq =3D vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; + int smmu_mapping_count, offset_to_id_array; =20 + if (vms->its) { + smmu_mapping_count =3D 1; /* ITS Group node */ + offset_to_id_array =3D SMMU_V3_ENTRY_SIZE; /* Just after the h= eader */ + } else { + smmu_mapping_count =3D 0; /* No ID mappings */ + offset_to_id_array =3D 0; /* No ID mappings array */ + } smmu_offset =3D table_data->len - table.table_offset; /* Table 9 SMMUv3 Format */ build_append_int_noprefix(table_data, 4 /* SMMUv3 */, 1); /* Type = */ - node_size =3D SMMU_V3_ENTRY_SIZE + ID_MAPPING_ENTRY_SIZE; + node_size =3D SMMU_V3_ENTRY_SIZE + + (ID_MAPPING_ENTRY_SIZE * smmu_mapping_count); build_append_int_noprefix(table_data, node_size, 2); /* Length */ build_append_int_noprefix(table_data, 4, 1); /* Revision */ build_append_int_noprefix(table_data, id++, 4); /* Identifier */ - build_append_int_noprefix(table_data, 1, 4); /* Number of ID mappi= ngs */ + /* Number of ID mappings */ + build_append_int_noprefix(table_data, smmu_mapping_count, 4); /* Reference to ID Array */ - build_append_int_noprefix(table_data, SMMU_V3_ENTRY_SIZE, 4); + build_append_int_noprefix(table_data, offset_to_id_array, 4); /* Base address */ build_append_int_noprefix(table_data, vms->memmap[VIRT_SMMU].base,= 8); /* Flags */ @@ -388,9 +416,11 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vir= tMachineState *vms) build_append_int_noprefix(table_data, 0, 4); /* Proximity domain */ /* DeviceID mapping index (ignored since interrupts are GSIV based= ) */ build_append_int_noprefix(table_data, 0, 4); - - /* Output IORT node is the ITS Group node (the first node) */ - build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET); + /* Array of ID mappings */ + if (smmu_mapping_count) { + /* Output IORT node is the ITS Group node (the first node). */ + build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET= ); + } } =20 /* Table 17 Root Complex Node */ @@ -431,24 +461,26 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) * * N.B.: The mapping from SMMUv3 to ITS Group node (SMMUv3 -> ITS)= is * defined in the SMMUv3 table, where all SMMUv3 IDs are mapped to= the - * ITS Group node. + * ITS Group node, if ITS is available. */ - for (i =3D 0; i < smmu_idmaps->len; i++) { - range =3D &g_array_index(smmu_idmaps, AcpiIortIdMapping, i); + for (i =3D 0; i < rc_smmu_idmaps->len; i++) { + range =3D &g_array_index(rc_smmu_idmaps, AcpiIortIdMapping, i); /* Output IORT node is the SMMUv3 node. */ build_iort_id_mapping(table_data, range->input_base, range->id_count, smmu_offset); } =20 - /* - * Map bypassed (don't go throught the SMMU) RIDs (input) to ITS G= roup - * node directly: RC -> ITS. - */ - for (i =3D 0; i < its_idmaps->len; i++) { - range =3D &g_array_index(its_idmaps, AcpiIortIdMapping, i); - /* Output IORT node is the ITS Group node (the first node). */ - build_iort_id_mapping(table_data, range->input_base, - range->id_count, IORT_NODE_OFFSET); + if (vms->its) { + /* + * Map bypassed (don't go through the SMMU) RIDs (input) to + * ITS Group node directly: RC -> ITS. + */ + for (i =3D 0; i < rc_its_idmaps->len; i++) { + range =3D &g_array_index(rc_its_idmaps, AcpiIortIdMapping,= i); + /* Output IORT node is the ITS Group node (the first node)= . */ + build_iort_id_mapping(table_data, range->input_base, + range->id_count, IORT_NODE_OFFSET); + } } } else { /* @@ -460,8 +492,8 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) } =20 acpi_table_end(linker, &table); - g_array_free(smmu_idmaps, true); - g_array_free(its_idmaps, true); + g_array_free(rc_smmu_idmaps, true); + g_array_free(rc_its_idmaps, true); } =20 /* @@ -769,18 +801,20 @@ build_madt(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) memmap[VIRT_HIGH_GIC_REDIST2].si= ze); } =20 - /* - * ACPI spec, Revision 6.0 Errata A - * (original 6.0 definition has invalid Length) - * 5.2.12.18 GIC ITS Structure - */ - build_append_int_noprefix(table_data, 0xF, 1); /* Type */ - build_append_int_noprefix(table_data, 20, 1); /* Length */ - build_append_int_noprefix(table_data, 0, 2); /* Reserved */ - build_append_int_noprefix(table_data, 0, 4); /* GIC ITS ID */ - /* Physical Base Address */ - build_append_int_noprefix(table_data, memmap[VIRT_GIC_ITS].base, 8= ); - build_append_int_noprefix(table_data, 0, 4); /* Reserved */ + if (vms->its) { + /* + * ACPI spec, Revision 6.0 Errata A + * (original 6.0 definition has invalid Length) + * 5.2.12.18 GIC ITS Structure + */ + build_append_int_noprefix(table_data, 0xF, 1); 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a88c80bb28sm13475658f8f.43.2025.07.01.10.07.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 10:07:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751389666; x=1751994466; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ZDxydh3BwBsE6Xm7nxnjb7DoJMVziFgfXOZ3LfN04E8=; b=YvACrXBF0hMt5li07aPdFWFM3vW1jusiJhe2nX/dEX9ai4WaT3yoWwaoG3liG3Tnlf paLNgDXR0/RlgzglTKTP+3btj/HkJ/UZ+twfyyuSioGqmAJV600XRpoXzW/bLZThvi/F BSrUfiVARomtAVk4wsoIMR6cjAax0sZwG318NtOnPK4j6GtYCmWls6Y026hCEnT1L/oY A5b/XB/3sH0dEHwhtsNxUouuUFnqIajTptA5v7HwJDZO8IDzYdFo08VbAAsiBxpnetHH 2YJA993EOFWWevZZ9+yeAis8p3F2rB+Me0aioYbprziK5JPfg/7daQVIwDJIwDrjNHgx /vJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751389666; x=1751994466; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZDxydh3BwBsE6Xm7nxnjb7DoJMVziFgfXOZ3LfN04E8=; b=SmzJTiUNQc47H562CIf/1SfhYakly1P6wvrVdvvubI2aX+VMBuZppeXlGmyS0Bo1p7 NdYT8+2fQATPrtoYVj89rlD5awOwA8eSY5ML/bLTM1YWofPG1Ai1/1KkozdJ0Ui5ETC8 LRb89Zc2fBDNM55nPZEfQX4880dVcfeEwBYtfko8aih2UQpIaPRtRAibJcvHj5XlJhhR B+c6KP+c4tjOUY4kKHeuNWGC3oikUzU/QVf5X6j296JBJ2PV+eaEW2e4KEQHGV6AA7rp NqAHgQ+bgM5qVoMTRdcRDAbUme+0O07IWwlTm4dCr55Nmu8UKkJjTbpsQzAE0XLtAvXM JOmA== X-Gm-Message-State: AOJu0YzyaMq+V50YNq0CATVrJZkpf4iJU7CEOHT7b5elDvieT629Qkdm Wyg1eZYr5BGLPYoCkEv4Qd2zGSomniEtfzLvhivEPICDRJVARVAXjHXNTzdtzmQRZU8B3Bajfdb LYX3u X-Gm-Gg: ASbGncuNq7v2fc1V9nZ3Dz/B08nQVYYGKgp+5vJicj9VScjsDYPb6kxJk6hLcFeTjRA OZfPMrirnsIxfldUXRQVZg7TIPRQ2b5BsyZUpj0RIGw6C8/VJS/xCZNbD6qh0s5ZgjAWhXv++Bh B5+F5XlsN7NPgz8ukGM5t7+lNcYC8pWBS60EV81Dgi4jTeURil4CN0uYLsJCXNGf+lWLBFvqKm0 Qa2adrN1tmqe1awVzF09I6MRM9iwQPzQ0+OpYbYlGOrFCAumKRp8Pa7sKYglJ1Vu6qNmowdU+DY 1i1SaeHnT5637F8InxhGvnulF+MYcxrbOVw8Gc5tjx3jkLecJ8TYlTWrf5AwM9LxXCaI X-Google-Smtp-Source: AGHT+IHK0m6wTFnA5LcnUqtTpxn4gKdPxGswG3oa/X0/SIj57kIMvl+pobbdAW/lqxCGKn6it9IcPA== X-Received: by 2002:a05:600c:45d0:b0:439:4b23:9e8e with SMTP id 5b1f17b1804b1-45422f306b3mr36737515e9.3.1751389665914; Tue, 01 Jul 2025 10:07:45 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/43] qtest/bios-tables-test: Update blobs for its=off test on aarch64 Date: Tue, 1 Jul 2025 18:06:59 +0100 Message-ID: <20250701170720.4072660-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751389856405116600 Content-Type: text/plain; charset="utf-8" From: Gustavo Romero Update blobs for the its=3Doff test on aarch64 after fix. Basically, all structs related to ITS are gone in MADT and IORT tables after the fix (previously ITS was not properly disabled when "its=3Doff" option was passed to the machine). MADT diff: [000h 0000 4] Signature : "APIC" [Multiple APIC De= scription Table (MADT)] -[004h 0004 4] Table Length : 000000B8 +[004h 0004 4] Table Length : 000000A4 [008h 0008 1] Revision : 04 -[009h 0009 1] Checksum : C1 +[009h 0009 1] Checksum : 08 [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 [024h 0036 4] Local Apic Address : 00000000 [028h 0040 4] Flags (decoded below) : 00000000 PC-AT Compatibility : 0 [02Ch 0044 1] Subtable Type : 0C [Generic Interrupt Distr= ibutor] [02Dh 0045 1] Length : 18 [02Eh 0046 2] Reserved : 0000 [030h 0048 4] Local GIC Hardware ID : 00000000 [034h 0052 8] Base Address : 0000000008000000 [03Ch 0060 4] Interrupt Base : 00000000 @@ -48,37 +48,29 @@ [064h 0100 8] Base Address : 0000000000000000 [06Ch 0108 8] Virtual GIC Base Address : 0000000000000000 [074h 0116 8] Hypervisor GIC Base Address : 0000000000000000 [07Ch 0124 4] Virtual GIC Interrupt : 00000000 [080h 0128 8] Redistributor Base Address : 0000000000000000 [088h 0136 8] ARM MPIDR : 0000000000000000 [090h 0144 1] Efficiency Class : 00 [091h 0145 1] Reserved : 00 [092h 0146 2] SPE Overflow Interrupt : 0000 [094h 0148 1] Subtable Type : 0E [Generic Interrupt Redis= tributor] [095h 0149 1] Length : 10 [096h 0150 2] Reserved : 0000 [098h 0152 8] Base Address : 00000000080A0000 [0A0h 0160 4] Length : 00F60000 -[0A4h 0164 1] Subtable Type : 0F [Generic Interrupt Trans= lator] -[0A5h 0165 1] Length : 14 -[0A6h 0166 2] Reserved : 0000 -[0A8h 0168 4] Translation ID : 00000000 -[0ACh 0172 8] Base Address : 0000000008080000 -[0B4h 0180 4] Reserved : 00000000 IORT diff: [000h 0000 4] Signature : "IORT" [IO Remapping Tab= le] -[004h 0004 4] Table Length : 000000EC +[004h 0004 4] Table Length : 000000AC [008h 0008 1] Revision : 03 -[009h 0009 1] Checksum : 57 +[009h 0009 1] Checksum : 97 [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 -[024h 0036 4] Node Count : 00000003 +[024h 0036 4] Node Count : 00000002 [028h 0040 4] Node Offset : 00000030 [02Ch 0044 4] Reserved : 00000000 -[030h 0048 1] Type : 00 -[031h 0049 2] Length : 0018 -[033h 0051 1] Revision : 01 +[030h 0048 1] Type : 04 +[031h 0049 2] Length : 0044 +[033h 0051 1] Revision : 04 [034h 0052 4] Reserved : 00000000 [038h 0056 4] Mapping Count : 00000000 [03Ch 0060 4] Mapping Offset : 00000000 -[040h 0064 4] ItsCount : 00000001 -[044h 0068 4] Identifiers : 00000000 - -[048h 0072 1] Type : 04 -[049h 0073 2] Length : 0058 -[04Bh 0075 1] Revision : 04 -[04Ch 0076 4] Reserved : 00000001 -[050h 0080 4] Mapping Count : 00000001 -[054h 0084 4] Mapping Offset : 00000044 - -[058h 0088 8] Base Address : 0000000009050000 -[060h 0096 4] Flags (decoded below) : 00000001 +[040h 0064 8] Base Address : 0000000009050000 +[048h 0072 4] Flags (decoded below) : 00000001 COHACC Override : 1 HTTU Override : 0 Proximity Domain Valid : 0 -[064h 0100 4] Reserved : 00000000 -[068h 0104 8] VATOS Address : 0000000000000000 -[070h 0112 4] Model : 00000000 -[074h 0116 4] Event GSIV : 0000006A -[078h 0120 4] PRI GSIV : 0000006B -[07Ch 0124 4] GERR GSIV : 0000006D -[080h 0128 4] Sync GSIV : 0000006C -[084h 0132 4] Proximity Domain : 00000000 -[088h 0136 4] Device ID Mapping Index : 00000000 - -[08Ch 0140 4] Input base : 00000000 -[090h 0144 4] ID Count : 0000FFFF -[094h 0148 4] Output Base : 00000000 -[098h 0152 4] Output Reference : 00000030 -[09Ch 0156 4] Flags (decoded below) : 00000000 - Single Mapping : 0 - -[0A0h 0160 1] Type : 02 -[0A1h 0161 2] Length : 004C -[0A3h 0163 1] Revision : 03 -[0A4h 0164 4] Reserved : 00000002 -[0A8h 0168 4] Mapping Count : 00000002 -[0ACh 0172 4] Mapping Offset : 00000024 - -[0B0h 0176 8] Memory Properties : [IORT Memory Access Propert= ies] -[0B0h 0176 4] Cache Coherency : 00000001 -[0B4h 0180 1] Hints (decoded below) : 00 +[04Ch 0076 4] Reserved : 00000000 +[050h 0080 8] VATOS Address : 0000000000000000 +[058h 0088 4] Model : 00000000 +[05Ch 0092 4] Event GSIV : 0000006A +[060h 0096 4] PRI GSIV : 0000006B +[064h 0100 4] GERR GSIV : 0000006D +[068h 0104 4] Sync GSIV : 0000006C +[06Ch 0108 4] Proximity Domain : 00000000 +[070h 0112 4] Device ID Mapping Index : 00000000 + +[074h 0116 1] Type : 02 +[075h 0117 2] Length : 0038 +[077h 0119 1] Revision : 03 +[078h 0120 4] Reserved : 00000001 +[07Ch 0124 4] Mapping Count : 00000001 +[080h 0128 4] Mapping Offset : 00000024 + +[084h 0132 8] Memory Properties : [IORT Memory Access Propert= ies] +[084h 0132 4] Cache Coherency : 00000001 +[088h 0136 1] Hints (decoded below) : 00 Transient : 0 Write Allocate : 0 Read Allocate : 0 Override : 0 -[0B5h 0181 2] Reserved : 0000 -[0B7h 0183 1] Memory Flags (decoded below) : 03 +[089h 0137 2] Reserved : 0000 +[08Bh 0139 1] Memory Flags (decoded below) : 03 Coherency : 1 Device Attribute : 1 -[0B8h 0184 4] ATS Attribute : 00000000 -[0BCh 0188 4] PCI Segment Number : 00000000 -[0C0h 0192 1] Memory Size Limit : 40 -[0C1h 0193 3] Reserved : 000000 - -[0C4h 0196 4] Input base : 00000000 -[0C8h 0200 4] ID Count : 000000FF -[0CCh 0204 4] Output Base : 00000000 -[0D0h 0208 4] Output Reference : 00000048 -[0D4h 0212 4] Flags (decoded below) : 00000000 - Single Mapping : 0 - -[0D8h 0216 4] Input base : 00000100 -[0DCh 0220 4] ID Count : 0000FEFF -[0E0h 0224 4] Output Base : 00000100 -[0E4h 0228 4] Output Reference : 00000030 -[0E8h 0232 4] Flags (decoded below) : 00000000 +[08Ch 0140 4] ATS Attribute : 00000000 +[090h 0144 4] PCI Segment Number : 00000000 +[094h 0148 1] Memory Size Limit : 40 +[095h 0149 3] Reserved : 000000 + +[098h 0152 4] Input base : 00000000 +[09Ch 0156 4] ID Count : 000000FF +[0A0h 0160 4] Output Base : 00000000 +[0A4h 0164 4] Output Reference : 00000030 +[0A8h 0168 4] Flags (decoded below) : 00000000 Single Mapping : 0 Signed-off-by: Gustavo Romero Reviewed-by: Eric Auger Message-id: 20250628195722.977078-10-gustavo.romero@linaro.org Signed-off-by: Peter Maydell --- tests/qtest/bios-tables-test-allowed-diff.h | 2 -- tests/data/acpi/aarch64/virt/APIC.its_off | Bin 184 -> 164 bytes tests/data/acpi/aarch64/virt/IORT.its_off | Bin 236 -> 172 bytes 3 files changed, 2 deletions(-) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index a88198d5c2a..dfb8523c8bf 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,3 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/aarch64/virt/APIC.its_off", -"tests/data/acpi/aarch64/virt/IORT.its_off", diff --git a/tests/data/acpi/aarch64/virt/APIC.its_off b/tests/data/acpi/aa= rch64/virt/APIC.its_off index 37d82e970b1331cb5b259f0bd2d3654bacb2d623..6130cb7d07103b326feb4dcd703= 4f85808bebadf 100644 GIT binary patch delta 18 ZcmdnNxP+0*F~HM#2?GNI3&%vRSpY2+1Zw~Q delta 39 jcmZ3&xPy_)F~HM#2Ll5G%fX3UvqbnsfJ`vp;DE6JqX7kf diff --git a/tests/data/acpi/aarch64/virt/IORT.its_off b/tests/data/acpi/aa= rch64/virt/IORT.its_off index 0fceb820d509e852ca0849baf568a8e93e426738..c10da4e61dd00e7eb062558a273= 5d49ca0b20620 100644 GIT binary patch delta 69 zcmaFExQ3C-(?2L=3D4FdxM^Yn>aQj$zSmH`lh0E-I)3xowECx)7HGFdP%GXmL+6IZHp Hz*GSMclZc% literal 236 zcmebD4+?q1z`(#9?&R<65v<@85#X!<1dKp25F11@1F-=3DRgMkDCNC*yK9F_TjFfcO#g+N#Zh@s|zoCF3AP#UU@ R!2`+%Dg6Hr$N|zYvjDIZ5CH%H --=20 2.43.0 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1751389856; cv=none; d=zohomail.com; s=zohoarc; b=ZEuhFRp3UIBdp0OAVsDirOtTomq3DqSNqIzPorTrNsSrs7y+U8pGh69p7SM6iEy04usTcTEVgDwE2BI3zMK2CrAPRYN4K42LJEzvCZSmCr+/4TfYDe1acK/sAVyXhx+8HI4tvoDX8ZY3Sb5fGPq/yNWcBlmRymvwQYidJbqUPuk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751389856; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=NkAj0AEskJHRUO2iJr99UKhDE0MC58f7E9SHfeTX+6I=; b=Eq7iRx/9+X6PtKKeknBkZgtL46K1icXewW1SnHtZWIz2F+4k72IRxYGt1EoPek5bu3/OO0NH+Ue/t43NBf0/hw6CpysBa6gpOUz9EMkEPSglD2865jhFcO2xX7uP8Xhgt9D+33zNaln1R5Q4btNrphz+5KOn6KqrVO0O/iX4634= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17513898566381.616267779907048; Tue, 1 Jul 2025 10:10:56 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uWeSZ-0005fk-IE; Tue, 01 Jul 2025 13:07:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uWeSW-0005bk-6n for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:07:52 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uWeSS-0003ZD-Nk for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:07:50 -0400 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-4539cd7990cso14794685e9.0 for ; Tue, 01 Jul 2025 10:07:48 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a88c80bb28sm13475658f8f.43.2025.07.01.10.07.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 10:07:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751389667; x=1751994467; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=NkAj0AEskJHRUO2iJr99UKhDE0MC58f7E9SHfeTX+6I=; b=junCE/Dn3xGDj4M5gJa0Z2FztUvwVwF4/QfuXZYvSt5bIP+8LArdQFqzG2FU5iLopP HlS5oTLlc9UywYFJ50TWz1AgzyPr3RaMz4TYbyKGG2mvWUyGpdO137alZ2Nz2/eSk1hr zXdBCIz3688v9EdQoLLmkec2JTFbQaD6DGYYmWW8CBmU6eqhHKXdDDNyzrbDrsUDFLHA XwXXV8zC6NhAHWAZir8QWegTv8OBQP0CX5ah47V4iB4OC+u3n+ypZHVVTOba/hQMg8Z0 kXBUp0MsFIs0ZnFTYOeVql1Y6shPBfuRUnBtz++obXVLRTAuMIoGhe4KkjXphP3HABrc npzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751389667; x=1751994467; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NkAj0AEskJHRUO2iJr99UKhDE0MC58f7E9SHfeTX+6I=; b=ZCY/82F60kjYUr+5PdpZTf+ZErizek8HxPI0osKqak+FQJ0l+J0bVsB7nRBu/oWHKh LCYzJKhII/7ibG/rQuBm/SWwBxduhuU4oMwe7eHsVC3zwmzNtzZAA7MK7BgBDHGABRg0 Vt6nHvVxZ1x80LO/LsjixK61ta28rXOorjHyGFa3zs3LT5r/2nA6y62k4EcCsDCPVql3 OY+F+P4xSmAtw2bEvExqkToBk6FP2BZ6Qx8IEVr3Ym9y23ojm2X56fzqMI4HGa6hnnQd vkUbhvFIpVdLOgSFRD3rYwalsvsGVI0r5Zm6hBPjBPTY72arplVrja+O2MWuelSqKG6B /q8A== X-Gm-Message-State: AOJu0YxneOYq+fy+OJf4Q8siMj8LNQ/DRuCOjGoon+0RfHo+jvj979pH Rx3FY9z/HTg+FlgMm0eExl9LsBbQKYSbpGG6tffKYmlYfQHB4d6MO07w0ZkgPjM/Hu84q+sxMtC LrZzX X-Gm-Gg: ASbGncuUY+dMous5tF3JXtzPtVTYWpkunLHYPb0iQMFo6rEzX9Je6DQ9GulBN9o/aoc +a1itIOAnU9XtgbRcGPvkEjSZ4Gw447UyT862rF9XKJdqZuzXshXQwV4PqSm2WNYYnHKRwJ5r4L 6DAgiz4YW0fM2dGMfnuHKxRYYKMfHhAShQEm/ALJE57hNd3yWUJMxvmJuC/bt4Ac7xX8NrHLUBw hECBuf3iVilMk0henSiygtkFc7po8LiNHr/i/q+tgmRLbnumehNnsroV2VFgGFmsB7npIQaoa99 y61DKAsh6kn6jj+RwThQdeHJtRpz6kRud8OlhOi4UbZqAVGIu6+iTA+TRg1HjQUedLoa X-Google-Smtp-Source: AGHT+IGPbfqymNcerVijn9RpKuTQ8RDZFYlNcTB6zlgZxHmAMYeUJfGZOH1UsP/XZZ8suYfNTJ/8KQ== X-Received: by 2002:a05:600c:35cc:b0:442:f4a3:a2c0 with SMTP id 5b1f17b1804b1-454a32d595dmr1812915e9.13.1751389666867; Tue, 01 Jul 2025 10:07:46 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/43] target/arm: Remove arm_handle_psci_call() stub Date: Tue, 1 Jul 2025 18:07:00 +0100 Message-ID: <20250701170720.4072660-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751389858384116600 From: Philippe Mathieu-Daud=C3=A9 Since commit 0c1aaa66c24 ("target/arm: wrap psci call with tcg_enabled") the arm_handle_psci_call() call is elided when TCG is disabled. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20250623121845.7214-2-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 6216f68c94f..21a8d67eddf 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -650,16 +650,12 @@ static inline bool arm_is_psci_call(ARMCPU *cpu, int = excp_type) { return false; } -static inline void arm_handle_psci_call(ARMCPU *cpu) -{ - g_assert_not_reached(); -} #else /* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI ca= ll. */ bool arm_is_psci_call(ARMCPU *cpu, int excp_type); +#endif /* Actually handle a PSCI call */ void arm_handle_psci_call(ARMCPU *cpu); -#endif =20 /** * arm_clear_exclusive: clear the exclusive monitor --=20 2.43.0 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1751389957; cv=none; d=zohomail.com; s=zohoarc; b=E4bc8WJIVmxAuR0O29PvEm8LmKxM0UaIE85ZSS2wKlh1SdZQrM/RPFFkPwTMAo3p8pJ3ftf2J5DAA065HFeCWbXTzW9j8bce1KSimSFaeqDx2xYkKdBoIhxk91nXtv0/niNKI5/wyizVsDQYp/YdVEgptEBwrCWZsGcdd3Gdr+I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751389957; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=LjPg1QfOBbDglyOlkTx99ANQnGLjk1OTG3KagRxzjyU=; b=ZqkAWNszWvEHVeCGU7/+xFlDB5uUq8k+hQoFb7u8a+HPw+ykFR8+5sfOHXrsSMY5kAoRtFtP41inTePvUljh79EzvxFDc5g3Wb090+VVwEcvPAh2w6Jvk3iVpDnU4gpXHavkUMSYm0Dwcd7I7z0oh6PyJ8K+WVt0DBnOLlA/MOg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17513899571551006.031662801262; Tue, 1 Jul 2025 10:12:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uWeSX-0005dd-R8; Tue, 01 Jul 2025 13:07:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uWeSV-0005b6-PS for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:07:51 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uWeST-0003a8-MX for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:07:51 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-453749aef9eso22607165e9.3 for ; Tue, 01 Jul 2025 10:07:49 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a88c80bb28sm13475658f8f.43.2025.07.01.10.07.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 10:07:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751389668; x=1751994468; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=LjPg1QfOBbDglyOlkTx99ANQnGLjk1OTG3KagRxzjyU=; b=u82T1diAzHUIYTCc15ih1IgDSa4qpfc3dNNEm6ffhf41Mccd+AJsVhc2mnIHQxyfyA 02CbQCH2yJUjQvAgryICwAM4mZhX2HmkfhfCJJiO7PDJcH8u2hkGKX8HFlKOlULkSDG9 1BfrslatFBcdioH4zW/67LbztsfigbUaGxTsSydnYMCdY6Y9P9gNuIYHGSongxwjwvAD H0kZy3RlM+qCExhCqn+K7H3FKq4kC03q3Yitln/JfJWJo2VxPWWa+HJLrqZISAfFeLhF u5VAUmCOPr+h7IQTyS9fwTEd7NSymk6lW2ifVnkw67ezzZ4N4PyVy6xrpfQ4lfWfBmsc WLyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751389668; x=1751994468; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LjPg1QfOBbDglyOlkTx99ANQnGLjk1OTG3KagRxzjyU=; b=M54/sFsWeAQ8tnNLVgJT0eeYYw0Z+o5Az6MbhjoyF9kUdk02VyzDa1aJTJTba9Wiv5 LrWyzYB1dJ8Jp3Xs7QBuq3w//MGLgDYkBeu+pX5EmmOV0/5QTE3QXF05AbQJmsYo5Nau bYOw1mgOGEp1l+xvdiH+YgtF80GfbsbGqetjuwISn1xpsbrzUYw8a46u5SCN/ekVLBSp Jcbl2s2gNEalXCtcrnvc3akAICF+GM9naZhrdd1UHaKY6dS2YE1MCq/RTskqJRQteXX8 kryhrVLyVEKnGo8j4RDevOm5DBxSlWn6xHeHOlSuwDNLlYb5kByWZDM7px1Lo0cshtCA N6Zw== X-Gm-Message-State: AOJu0YxBKaryYiICDG0q1YtVpvbIrEj08TfL8Zop6GHBgcSiyRawDMij d5zagZFNk7BQfA82FEVgBHSL+oQaP/THIYzz7Qk24b3FYiaCg4UrfSH1IRzYHuGCApR02J2PUDd jMusn X-Gm-Gg: ASbGncsszeMbxXRvOziF4J54Xbxn1JRRl/NjxHM+3m5qlYfBANoR6cUAn59VcyuZkPa g+TV6swRhGko6OcQxnJwkvFZW2yqbJAp06za7FNLPwMzs3TqmtJJine1Q4bCO29wLrJmouVgtb1 1Hs8qFhe6iMeKz0KBnUvBZbsJcJ3hCjwBFFjqUAIS2r8+QHQkfpt1Ds1+hoGpQCIysAPA45k28y Sn28Z+LUbDsNHS8TprKdb8OAOesqdEbmQDbBowgyhRsgyr6hTTlVh94eND9E6VvyohsXWhMKs7B 8/J3lX2V5oXgjenVxbE0BO30Eyh2GyGeQoR8HOKWaidipZ3WY20B8GjAeyLxZYl0zK3a X-Google-Smtp-Source: AGHT+IH58ODinTQdBnd3KpZikR9SXrkYNjVSN+N/eGSbAj4pJQDD2K71e5vuHRwlZqzHzoRVUloo9Q== X-Received: by 2002:a5d:4d11:0:b0:3a5:51a3:3a2 with SMTP id ffacd0b85a97d-3a90038ac3dmr14070867f8f.45.1751389667806; Tue, 01 Jul 2025 10:07:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/43] target/arm: Reduce arm_cpu_post_init() declaration scope Date: Tue, 1 Jul 2025 18:07:01 +0100 Message-ID: <20250701170720.4072660-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751389957944116600 From: Philippe Mathieu-Daud=C3=A9 arm_cpu_post_init() is only used within the same file unit. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20250623121845.7214-3-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 -- target/arm/cpu.c | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8744922330d..03381539238 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1168,8 +1168,6 @@ void arm_gt_sel2vtimer_cb(void *opaque); unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); void gt_rme_post_el_change(ARMCPU *cpu, void *opaque); =20 -void arm_cpu_post_init(Object *obj); - #define ARM_AFF0_SHIFT 0 #define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) #define ARM_AFF1_SHIFT 8 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 8e77414c2b9..7030540f91f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1713,7 +1713,7 @@ static void arm_cpu_propagate_feature_implications(AR= MCPU *cpu) } } =20 -void arm_cpu_post_init(Object *obj) +static void arm_cpu_post_init(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); =20 --=20 2.43.0 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1751390117; cv=none; d=zohomail.com; s=zohoarc; b=no5QnS8BGZHySVT1vsaCGONvqOmUgJGmOoRFwXtNaTG1s7u3wzC6hpkCYIGhh6EbJoqZEOYy118KcIaHmZS8lOOjGGcXAaggjAuG651ZwY5VrEy7wjSfQcTLpGN27mGc+LGHS4+PLtt1wkSaVD5FDRlxddov6xHPXALlrJ2B+Cw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751390117; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=h3fZQFPQ4yVXaabIEx5Nimz04SLji8Cx5nJ315vJZ3Y=; b=UcAWdI5OcDAjX0GCdtDDGKfVLnpuwdZ9khLkYCoX2IBF8xD1OF7i0wjwKJppqtICm+AmpVYBmaE71wfZ97/NRYe67r8gzxM/k3sE7n4p7/lnFwoOyVVO1FpGNYEUnacDv2xrkhyg2WMztwu+YEeMO51G1O6w1V6Gc/NflKblX2k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1751390117479527.7733382988059; Tue, 1 Jul 2025 10:15:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uWeSZ-0005fR-Db; Tue, 01 Jul 2025 13:07:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uWeSW-0005cd-Jm for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:07:52 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uWeSU-0003ap-NH for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:07:52 -0400 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-3a522224582so3131546f8f.3 for ; Tue, 01 Jul 2025 10:07:49 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a88c80bb28sm13475658f8f.43.2025.07.01.10.07.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 10:07:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751389669; x=1751994469; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=h3fZQFPQ4yVXaabIEx5Nimz04SLji8Cx5nJ315vJZ3Y=; b=Eujdbmao+kqJgWWahwmx3JY4DIpTMvCK9HAq5RHoZY986QchNXi5GdBeyps397ZgmP npOA4JJbyCs+IgacpmHvR3ZoRZOg21h9HkcAAxq7fbLglcWz5v4INE6WErNn6FEsBwpF 5eXqWIE9tV/lhMc6OOyl7+KMu4m96sq0rjokrKe+blHl9i3IW4yVXzRaEhsHCWFFhxRZ 2SPZhe/zvKxu7WyruteyvNJV6jN8yQAzlkw4gfSstVOCZelj2/vedaHsQvKwkQlqpNlN bRzDaWVrgauTxVNOXKBud0cwzBXisTVss67VYazghbUIfns8GpNHcVmwhOzelTm8D0kR iFRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751389669; x=1751994469; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=h3fZQFPQ4yVXaabIEx5Nimz04SLji8Cx5nJ315vJZ3Y=; b=u6nAHDH0T8z25K0kOyoF9vuEps7UbeR8HMrFhRDpqFHWqTEPARfbxFo7h8ttZnawZ6 6AqlmBLLlJM9N0gVMuIwAD+jJcvLddje0n9knPN8bPl48m08EVZBh23oYr1AbdiPsHAq Tnk1Ev2HzQVEeAfpngz9JfacIUB3BODnYfawUU1iR4OsUpQw32AFrOtLOazyndfvUFnx dp1X1EmPuaNeCXw1walKS3DEa1y2lVTd+3Ripy6RVkuoqbWnboWTN0s5eIDt/xwo834j UWUtmodtvG7fWupEjva5qKHlcY15aZHycxZOSb5BsPYXPFgmykGkeOC2jEzuRpqK1TBw f1Ow== X-Gm-Message-State: AOJu0YwrTvYtd3bnYGuq16Ti00c3aDpYnsGdjDVgPz8hrVXTBQhmlXpP 53EXwzcbZJv10mjQaGXxlwrH0eppLajdkAfFs3hgCoUuKaqa/xu0naN3phaz/pYRUSoKSoH/k2P udVPj X-Gm-Gg: ASbGncuVO6G+DiO0m+b0XbRP02ZewGmpZrE65cfgKIV35f38Ia4YxiqFCfxNr0wSQfW 0HGkToBErem8gT7pur7yDTWN/Nw7A8zYxDXHyIK/yds/zAnL2cJy3eaWFEHORRNXk+7lOkDnvWY hr4Xg4zRGy6Erms6+eTTioq2VYZcC1wqG8kLSAthu1gLtCuk1SjeK1de8KEtzRPYIKHzRBvD/GG 6O3L1Gj6mjmCpibiyFmuSNMOme3O/wj/kVUS6enHCUeOYa2TuhICWl2an8ZONu7UPDI4hX0tNWM vcrJB6DcM9pgF5WYlpSSsdkeVV5HJE/KTvZfX+L8wPHvSUt2m87yFgT9eBMepdp7hLY2 X-Google-Smtp-Source: AGHT+IGBwfJPcmOwPVVuX7A68FitwOCm++VkfzlPhC3Kd2oIquWByb4GOUscsVc1d1YNCl6NBisd1Q== X-Received: by 2002:a05:6000:4408:b0:3a4:d8b6:ca3f with SMTP id ffacd0b85a97d-3a8ffdbefd5mr11291532f8f.30.1751389668671; Tue, 01 Jul 2025 10:07:48 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/43] target/arm: Unify gen_exception_internal() Date: Tue, 1 Jul 2025 18:07:02 +0100 Message-ID: <20250701170720.4072660-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751390117948116600 From: Philippe Mathieu-Daud=C3=A9 Same code, use the generic variant. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20250623121845.7214-4-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/translate.h | 1 + target/arm/tcg/translate-a64.c | 6 ------ target/arm/tcg/translate.c | 2 +- 3 files changed, 2 insertions(+), 7 deletions(-) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 1bfdb0fb9bb..0004a97219b 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -347,6 +347,7 @@ void arm_jump_cc(DisasCompare *cmp, TCGLabel *label); void arm_gen_test_cc(int cc, TCGLabel *label); MemOp pow2_align(unsigned i); void unallocated_encoding(DisasContext *s); +void gen_exception_internal(int excp); void gen_exception_insn_el(DisasContext *s, target_long pc_diff, int excp, uint32_t syn, uint32_t target_el); void gen_exception_insn(DisasContext *s, target_long pc_diff, diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index d0719b5665f..815225b1301 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -433,12 +433,6 @@ static void gen_rebuild_hflags(DisasContext *s) gen_helper_rebuild_hflags_a64(tcg_env, tcg_constant_i32(s->current_el)= ); } =20 -static void gen_exception_internal(int excp) -{ - assert(excp_is_internal(excp)); - gen_helper_exception_internal(tcg_env, tcg_constant_i32(excp)); -} - static void gen_exception_internal_insn(DisasContext *s, int excp) { gen_a64_update_pc(s, 0); diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 9962f43b1d0..f7d6d8ce196 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -372,7 +372,7 @@ static void gen_rebuild_hflags(DisasContext *s, bool ne= w_el) } } =20 -static void gen_exception_internal(int excp) +void gen_exception_internal(int excp) { assert(excp_is_internal(excp)); gen_helper_exception_internal(tcg_env, tcg_constant_i32(excp)); --=20 2.43.0 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1751389916; cv=none; d=zohomail.com; s=zohoarc; b=NJ6K2zAGGI0dk5ucLzjI7cR/dTAHqOXNmOwns4ZIS/gdb5GWWeAIrJK5JYRWt7AcIytBWIjoIlGOU6mH0r66u5/Df7T1uf6WmVbQpLd3AZ70MFnGFXO2XnlNkDgzaOW8JjbtGIFOz8nFBxxMC2Dc/dB824nytvMpb1UWKZcwzYo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751389916; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=AzcsRGchl752kffQ5Y7VHDcNl2gOJzVVBkDGDtDpFlc=; b=hI2Vb1mmw2rWnsj/mZ8lSrNTNxkJOeSg2CBrjmy9NgYN0j5YSRmHwRQo8kwAKqMk0avbH76+rK1mgfU6HpiskU9ExoBJ3pZFue97L0B9hZNhPcHVea/t2VxraAW04+8y3bCwTuqeu/oO9+8Wc/RQPXDMi7JroJEk8HPlT3Mzqb8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1751389916501121.18796293668572; Tue, 1 Jul 2025 10:11:56 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uWeSa-0005gL-F3; Tue, 01 Jul 2025 13:07:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uWeSX-0005dX-J8 for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:07:53 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uWeSV-0003bf-Rs for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:07:53 -0400 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-3a5257748e1so2351973f8f.2 for ; Tue, 01 Jul 2025 10:07:51 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a88c80bb28sm13475658f8f.43.2025.07.01.10.07.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 10:07:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751389670; x=1751994470; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=AzcsRGchl752kffQ5Y7VHDcNl2gOJzVVBkDGDtDpFlc=; b=oK9tCB9Teu3ZpFpDL/qJvij2dGAXxqehR3fLM9wLiCcKgVcpv9Et1Q4YkKJ7uf/u7A bEYWIVb+4yHOh5Nm98WVo1tgKG2idGVfe/0nXKeLpPVzrYkqfoIun4kcM3JyYMVrdMR0 ef+7UZs0yN6Z1pqg+pynrQ5i4MGzQqGkNO8+iSuiEQbMIKT6YDENcPpC60A7JnUl/UJ1 YhIJ/LpNeFWYD47Dxr1glcM9kE9R5+88WBUYSykLhtKBvIhdni/GMNzLi4yQcxJANeXc t3eAqY0rN9Fha+FG82Rs7c5AEgu9QSmOfakqyYaGGMhucKtMP4aMg4xS+OSE99rxNexc clJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751389670; x=1751994470; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AzcsRGchl752kffQ5Y7VHDcNl2gOJzVVBkDGDtDpFlc=; b=vmllf7ejh18y9Lm6EQkeekc4GtUZPDHHU3Y/YTMbgFSZfZVcqUWjQhO9/4ZPZynOru 261uF6PM/WB80NPGelXYOvhcbpv0MqYgVAnA4HF9aGAsYpUzl0kKzFR7FjVFEjlYpKmF yzMIUbQ9UgLjtZAz8c+8FsZ6yQA8ud8lbM//75wZ8zsEyf/eM2aelWFSs/lTAJrSX93T eO+zJbisxqO5RYIjXBBVAhPOiExSh6xJz4JXFR3+b603VVN9OHJSaB0VjZyF7S+vgq4a 29mH1E53pF47NNVmrqZHAJyXAEDqxccwiMtDh8k6jJhA6p4dOdjgcsqJNLm1NudctZLk OlBA== X-Gm-Message-State: AOJu0YxPnKxlWF6VTmNOBysG5DXubf1iOiyBukDQWjIZziIhkHHWh2rB N0DaU4WSR+V1KsQvq2XJxBoQL8flrcamYbqOH6tVlhnxUlW4qjsR53O9vUk0OkLslsGvIAfhTAl DFiY3 X-Gm-Gg: ASbGncv6XXq66YjlAZLNEq10G5yBedGCrLS2p5fGBBc1ml6zMkfzrABsZuaVkDAyoDz a6ka8vrSzrDQlsEy1+jggpBFCGdyATopE5vKEgZ5LbkKEZzPx8Z1R4mE3ILIV1j0dQsb8N02h7u 1EFtEMz2lEZKV2q9IyP9q3XOOY9oMk+RnXA+UJ8iCLD8MB3Ub/ZSez1nqvjCY2afetunikMJoRg b7hGTFLjgTglTAzBbbkhJVfcfTHDaxCNNfezqhviePbHXDtIO4ZveNhU7xa3NqWQW+A4AszWkbA ZM6EEbXazHZiATgINXgRBQCi1+CTQn5QGGcJNXhyF+LHKY1rGRZnnxUXJeQSeqKdI7ez X-Google-Smtp-Source: AGHT+IHQtkRRRCB/uVDHo2GlbxTSd+JlM4ZSyjRA1JQ2FnITyZCmr1JUldG9cM/2DliwOown+KLNVg== X-Received: by 2002:a05:6000:4404:b0:3a4:f66a:9d31 with SMTP id ffacd0b85a97d-3a8fdb2a034mr11222132f8f.16.1751389669593; Tue, 01 Jul 2025 10:07:49 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/43] target/arm/hvf: Directly re-lock BQL after hv_vcpu_run() Date: Tue, 1 Jul 2025 18:07:03 +0100 Message-ID: <20250701170720.4072660-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751389917297116600 From: Philippe Mathieu-Daud=C3=A9 Keep bql_unlock() / bql_lock() close. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Richard Henderson Reviewed-by: Pierrick Bouvier Message-id: 20250623121845.7214-6-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/hvf/hvf.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 5c95ccc5b8d..3c234f7b112 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1915,7 +1915,9 @@ int hvf_vcpu_exec(CPUState *cpu) flush_cpu_state(cpu); =20 bql_unlock(); - assert_hvf_ok(hv_vcpu_run(cpu->accel->fd)); + r =3D hv_vcpu_run(cpu->accel->fd); + bql_lock(); + assert_hvf_ok(r); =20 /* handle VMEXIT */ uint64_t exit_reason =3D hvf_exit->reason; @@ -1923,7 +1925,6 @@ int hvf_vcpu_exec(CPUState *cpu) uint32_t ec =3D syn_get_ec(syndrome); =20 ret =3D 0; - bql_lock(); switch (exit_reason) { case HV_EXIT_REASON_EXCEPTION: /* This is the main one, handle below. */ --=20 2.43.0 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1751389911; cv=none; d=zohomail.com; s=zohoarc; b=N87mhiHxo0tbERzSYRhIsE8/jx/+YTZjPYZAW49tWrrIgVb9UXfZwSfVEryIMrldbgPCeHVNKukxLJQb0M6RMx+YFYU+vfL2f2TPYzw5bmaItIMRongFAQ1gPYRS8qNZEOXI4QreECfpqFei6DRswFkCuIw/y1lQveujGSjVeM0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751389911; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=il8MRx0ocqoWHUPwZJiya0xTcuVfrmMJ7yc2s+LkZk4=; b=AysH9ro8x2XxUwCaJsG6Sn5xpergZuH45jJz6ioydWDsMlRvqFY5WeXEP8Hv8OqR/Swl/bNneSrcQ9rwfEXxwUhcZ5cw8P8lgPb9rxkJQGWGfLbRtFDAxo1V35XehqDcvYJIwtR9SrXTxtsRV3Hq4qWQ6aHdz9FO3/KA+UfVf7I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1751389910970454.31838129796654; Tue, 1 Jul 2025 10:11:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uWeSb-0005ga-PD; Tue, 01 Jul 2025 13:07:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uWeSX-0005dl-V6 for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:07:53 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uWeSW-0003c6-8A for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:07:53 -0400 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-3a6d77b43c9so3260663f8f.3 for ; Tue, 01 Jul 2025 10:07:51 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a88c80bb28sm13475658f8f.43.2025.07.01.10.07.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 10:07:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751389670; x=1751994470; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=il8MRx0ocqoWHUPwZJiya0xTcuVfrmMJ7yc2s+LkZk4=; b=gNuRDoOwtGnPxfg6pnuw++6cEmVsvW19K/ffHt1Mqli8CMKZRITAYYOpIhIN3I0rRe E+1kTGpCk3qulu1wWHZ3244weFmNraMwao8bS1HDHQ9Cm5GbVdiQN4ZIphygRAHmK4ZM vvBix94XrvhAHFUEFh3pKdV3fWjhhrcipmE79i5f/i7S5trmQbeTkwPF2fin0uAN/PS/ xgWSzuWwIhxpYjkOuC5fJZ3aNEx6Hhg6Osq0oLElZdSIUBfVD3fjBoHOnf7G/ePCfB+x eNuk/zehfml9TT1gPa93ET7zogddJ/v8iDxpn5Gdfn6Uv9dy3bGrttEEYSsIyZml9Gmf 4UPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751389670; x=1751994470; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=il8MRx0ocqoWHUPwZJiya0xTcuVfrmMJ7yc2s+LkZk4=; b=waeF7y1IV3BN/Ba45P50fu/d8HJeTmhVgqtlkypUAu3aK52SH73YUGor6/V7EpfZaZ xTYb+5BQou6N/HoMOfy96ZlCe5ynpnaT5HubtZ8dBRXr9ZOGTA9hG/e9fOXF2kFHUmO2 dS6Zt4v0auwR/3Amggw7VTZF+VEV7lXrFuBE0VWTUgI3vPEOvw81Pu9hK/J0GRZIiTKw T/gpyZewKu3Qb0dr4p3bUmTYODkTYVblXgYTydiu0JFDkFzkwCnKnEAOZ3dWr2tuQufg pAlNEPSGE2O/b0JBHOA8M9i+yS7LCYFJoGFstiDcm/kw2fdhCGBZNuNgATFB9BddAxHy BgOA== X-Gm-Message-State: AOJu0YyHxOD79uZNcQ31RQNycM49SmupYXCghSzNpTrpmJiNpA4mJ0DI qZV/YBRn/vmhwL1OK+tdcXsnA0a445F6kFjlKkm9x7HpuyeKGfgnKFj+Ndo3xQM0by1gJj0Qdhg II0fp X-Gm-Gg: ASbGncstSTUpyTNK53+RvQYA8ta6ss0sQlRziZO7tBqV2LOfhjjZ5XUAObIU/K6eMUg e1DtpEEmEMsOuaZNFmDX0ov0+P3aXlLilbvlQyawGzOmk61MDTkqAS69c8K1uKWzyAJYQ/lkvAM lARMKSAx+9V/pQSKjcw9Q9FrVulq7Z7bdOU8wQPCSVZ5cSJ142FtSykl/xah3gaC1PyFC7vPZZ8 CADT0j0vmop2xfgZ8bmx5+SY7LZSR/k9zv5DdsEe8fOZNVCNB0jeVpgmREhXsrwmTd5nekzJ9tR 40rXN8osn+N35YM6iWWpqy+uNQpQM3/+NVJm+iqJukbkq9yX21wa2VTVi8rz4LtHQ4G+ X-Google-Smtp-Source: AGHT+IGkKkf4tOCZu4mKECBwrAIeXocZCtNnBQhoRgIA0HSbynB3LM2H8ULCay9YSujCnPGvxZk6xg== X-Received: by 2002:a05:6000:1a8c:b0:3a5:1240:6802 with SMTP id ffacd0b85a97d-3a90066a6e4mr16545566f8f.57.1751389670520; Tue, 01 Jul 2025 10:07:50 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/43] target/arm/hvf: Trace hv_vcpu_run() failures Date: Tue, 1 Jul 2025 18:07:04 +0100 Message-ID: <20250701170720.4072660-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751389913058116600 From: Philippe Mathieu-Daud=C3=A9 Allow distinguishing HV_ILLEGAL_GUEST_STATE in trace events. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20250623121845.7214-7-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/hvf/hvf.c | 10 +++++++++- target/arm/hvf/trace-events | 1 + 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 3c234f7b112..0943365a681 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1917,7 +1917,15 @@ int hvf_vcpu_exec(CPUState *cpu) bql_unlock(); r =3D hv_vcpu_run(cpu->accel->fd); bql_lock(); - assert_hvf_ok(r); + switch (r) { + case HV_SUCCESS: + break; + case HV_ILLEGAL_GUEST_STATE: + trace_hvf_illegal_guest_state(); + /* fall through */ + default: + g_assert_not_reached(); + } =20 /* handle VMEXIT */ uint64_t exit_reason =3D hvf_exit->reason; diff --git a/target/arm/hvf/trace-events b/target/arm/hvf/trace-events index 4fbbe4b45ec..a4870e0a5c4 100644 --- a/target/arm/hvf/trace-events +++ b/target/arm/hvf/trace-events @@ -11,3 +11,4 @@ hvf_exit(uint64_t syndrome, uint32_t ec, uint64_t pc) "ex= it: 0x%"PRIx64" [ec=3D0x% hvf_psci_call(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, uint32_t= cpuid) "PSCI Call x0=3D0x%016"PRIx64" x1=3D0x%016"PRIx64" x2=3D0x%016"PRIx= 64" x3=3D0x%016"PRIx64" cpu=3D0x%x" hvf_vgic_write(const char *name, uint64_t val) "vgic write to %s [val=3D0x= %016"PRIx64"]" hvf_vgic_read(const char *name, uint64_t val) "vgic read from %s [val=3D0x= %016"PRIx64"]" +hvf_illegal_guest_state(void) "HV_ILLEGAL_GUEST_STATE" --=20 2.43.0 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1751389794; cv=none; d=zohomail.com; s=zohoarc; b=VJfss7NktIVfC2xQ7evTpfS3pAgAFI2g+61MTSIOHmS953X7ezonnuj9ozQjRC72Nds7x3BbKfe72eRIYxTIwtmnkzYMzT8lR6ZIAZP1UPLxH1w2EtZcxo5TCXAwxTkrZ+Y4SGpz9XB6K6ZGzo9CBqQH889YddaNmi0sjkFLtfc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751389794; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=5oBh13H1TdU88xyMHvWj3WuPRavIjEcQBhtY7QPCsZ0=; b=jt6wIs7XxPGKajchpvBw3iDF/I349oQbHoKmAZDo2hZjZE5s4rYqHeY3dcl1nRRkjs6IYHw3qiLqW104pWN6YpLtkcADL5uw0uA9NIA6W/WXs4n9BYgHvoxdpyMTp97R0QiTvdZ5CiizZSq58x4Ni8oTHxJt2jv2EUNZuCk68/E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1751389794380700.1535639836983; Tue, 1 Jul 2025 10:09:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uWeSb-0005gX-Ez; Tue, 01 Jul 2025 13:07:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uWeSZ-0005fx-KD for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:07:55 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uWeSX-0003cs-N5 for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:07:55 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-450ccda1a6eso29782355e9.2 for ; Tue, 01 Jul 2025 10:07:52 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a88c80bb28sm13475658f8f.43.2025.07.01.10.07.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 10:07:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751389671; x=1751994471; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=5oBh13H1TdU88xyMHvWj3WuPRavIjEcQBhtY7QPCsZ0=; b=OZJwecNvY9f5fYIsGu3MXfkhlsV61p/blWi3cQo6RJ0cQD9pDoC9MN1DxFVla8zjPq VLxnQnXwRiLbzniIwLNale/ccTslAuyxMIlz3c7eabknQy8AF//xNzi12dT5GqzOj40+ CfLBtF6hGU8MNnNncgoGpxg8DcS9Ige0MCkMr07EUlby2lyfc370GMLkqWQculHCTmmu UkM9HoLJJhJCpuvI7w5Hq6TeHYU0Wz7tE8AAGZL6X/HnpQfEqCN2J6HsMqLmqPYai4Qc XvdnAUhdWn7FC8cYfZaTcQu765ohn4ryExUFeWfjxn42e8xWFdbvILEGoYs9BOckIwFu epZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751389671; x=1751994471; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5oBh13H1TdU88xyMHvWj3WuPRavIjEcQBhtY7QPCsZ0=; b=dR5ug0ZMN7HjIigpJHylG1A+OeYLwYLraGGKX3swqzQ/KGmMnY9mqQXNY68HV1flf0 ORYQAWixlMXeAbd5lZhZX3BOKe9vuMksHtQOZC+wL9LvcQ6KcAA0LLsLa1jDqknwNBvO q/R34BmkSzYvL2Q1/ou9t17qk8BaFZPRbkGf6AonIWq1IVzZq5Wrvj9ZeDTeGyjrkGKQ QHKk7A7DUOBGNnf+oHz4/342b5I0TixCZW2vI98vuNqnQJYTM/cb5mEZoJ5C/R4j90H+ jUdjXiBXuJ85BdwRrzlDtw3V4bBgIt369hQcew5yYsGgMhXOXw7PqHLunY8l7Pt0eh/m gXTg== X-Gm-Message-State: AOJu0YzsBzH0eDGkFuYfQGi02JMJB667zEsi9BYSxhrZevtNdSDYVZxF 8hcpRhNm/dESRrfUzAav4+CXRwDuoO9OHqsuEUbINB/sBSp7gnO7Ym4YZKBXgOu6rGRxQ2B2Dqo 7EpOu X-Gm-Gg: ASbGncv/6sx6D4J8X97LzzlEYfI+J8G+KRomCc4EXtEfkhuiOGg8Cp3WkdEbK1fYjdl jIgXgAuj44UcdoUkUiM41yfk+80ojk27h5T0m+hCbaFBDfOfaFrJmQIe4Uiia9os+5pQWiwFqw7 Nl0SAxPK1DTkgiaOtXIuHhcbFVuy+/fGCEImpr0mOu4yAmm7zm9HUiN8SRnJB8z35JQrfD/v1ou tuO2lyjkfgXUOm5yY1yLmvrCHPoqQBSrLgPXtsd7Tgc7u1uKPUbGA18ipZVTmDffB4jflfGHhH3 q9yHMqn4z1s7CMydN2aTjci07CYt0VXkyqBpjSNyuSyiPNsuOPXMruJB/tkLWVXwYXdL X-Google-Smtp-Source: AGHT+IH/Ua17eq+goyvC5ptbIe684OdpLiLI60DdX52B3BAO5zVOHM9CLR9O1XseRE/U9J9xBQ8E8A== X-Received: by 2002:a05:600c:1d18:b0:444:34c7:3ed9 with SMTP id 5b1f17b1804b1-4538ee7995emr172366715e9.26.1751389671365; Tue, 01 Jul 2025 10:07:51 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/43] accel/hvf: Trace VM memory mapping Date: Tue, 1 Jul 2025 18:07:05 +0100 Message-ID: <20250701170720.4072660-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751389795524116600 From: Philippe Mathieu-Daud=C3=A9 Trace memory mapped / unmapped in the guest. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20250623121845.7214-8-philmd@linaro.org Signed-off-by: Peter Maydell --- meson.build | 1 + accel/hvf/trace.h | 2 ++ accel/hvf/hvf-accel-ops.c | 6 ++++++ accel/hvf/trace-events | 7 +++++++ 4 files changed, 16 insertions(+) create mode 100644 accel/hvf/trace.h create mode 100644 accel/hvf/trace-events diff --git a/meson.build b/meson.build index dbc97bfdf7a..b5f74aa37a7 100644 --- a/meson.build +++ b/meson.build @@ -3630,6 +3630,7 @@ if have_block endif if have_system trace_events_subdirs +=3D [ + 'accel/hvf', 'accel/kvm', 'audio', 'backends', diff --git a/accel/hvf/trace.h b/accel/hvf/trace.h new file mode 100644 index 00000000000..83a1883343a --- /dev/null +++ b/accel/hvf/trace.h @@ -0,0 +1,2 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#include "trace/trace-accel_hvf.h" diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c index d60446b85b8..b38977207d2 100644 --- a/accel/hvf/hvf-accel-ops.c +++ b/accel/hvf/hvf-accel-ops.c @@ -59,6 +59,7 @@ #include "system/hvf_int.h" #include "system/runstate.h" #include "qemu/guest-random.h" +#include "trace.h" =20 HVFState *hvf_state; =20 @@ -97,6 +98,7 @@ static int do_hvf_set_memory(hvf_slot *slot, hv_memory_fl= ags_t flags) if (macslot->present) { if (macslot->size !=3D slot->size) { macslot->present =3D 0; + trace_hvf_vm_unmap(macslot->gpa_start, macslot->size); ret =3D hv_vm_unmap(macslot->gpa_start, macslot->size); assert_hvf_ok(ret); } @@ -109,6 +111,10 @@ static int do_hvf_set_memory(hvf_slot *slot, hv_memory= _flags_t flags) macslot->present =3D 1; macslot->gpa_start =3D slot->start; macslot->size =3D slot->size; + trace_hvf_vm_map(slot->start, slot->size, slot->mem, flags, + flags & HV_MEMORY_READ ? 'R' : '-', + flags & HV_MEMORY_WRITE ? 'W' : '-', + flags & HV_MEMORY_EXEC ? 'E' : '-'); ret =3D hv_vm_map(slot->mem, slot->start, slot->size, flags); assert_hvf_ok(ret); return 0; diff --git a/accel/hvf/trace-events b/accel/hvf/trace-events new file mode 100644 index 00000000000..2fd3e127c74 --- /dev/null +++ b/accel/hvf/trace-events @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# See docs/devel/tracing.rst for syntax documentation. + +# hvf-accel-ops.c +hvf_vm_map(uint64_t paddr, uint64_t size, void *vaddr, uint8_t flags, cons= t char r, const char w, const char e) "paddr:0x%016"PRIx64" size:0x%08"PRIx= 64" vaddr:%p flags:0x%02x/%c%c%c" +hvf_vm_unmap(uint64_t paddr, uint64_t size) "paddr:0x%016"PRIx64" size:0x%= 08"PRIx64 --=20 2.43.0 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1751389820; cv=none; d=zohomail.com; s=zohoarc; b=H1E6vulSvCM8D220LdO6tG0E/eoWEo/ySEqoScmgpf1pOtXZBgSi4F5cOdxxYDUCrLhMYg3YMesZi59bJxRdaxjQwBxTyvBmaiSdlemKNOO3JjTdX64VnbCfz386Z5U4vEx6X/X9aeovgRt+B54oNadEmpK0Nimk4obNqwpLs6w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751389820; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=lu+dhy8iYnnYk+OhSlOhY3EbkuSfbLX8WS//TkMmK/k=; b=YC8dF1GU0avwKIsk3IEbYVzGZAc25dGzDmFds+5dOOv+w3jTTo1FNI+whxBdfMbDWSQlxvRy2p+saIR2i6aALVJQhY22exLonJinuXNhihGSPHVZ4qFWINpW0jDqs39p/h9wB8TWe1his8J9GYKpN6RMB3uyb2uKSAcCqarNGFg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175138982016632.43593883087931; Tue, 1 Jul 2025 10:10:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uWeSh-0005kg-Pt; Tue, 01 Jul 2025 13:08:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uWeSb-0005gT-3V for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:07:57 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uWeSY-0003da-09 for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:07:56 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-4530921461aso39393075e9.0 for ; Tue, 01 Jul 2025 10:07:53 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a88c80bb28sm13475658f8f.43.2025.07.01.10.07.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 10:07:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751389672; x=1751994472; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=lu+dhy8iYnnYk+OhSlOhY3EbkuSfbLX8WS//TkMmK/k=; b=nv3THcCsQ1ifJwASqqj6d3A0RuwwNglJhWZyAc/5uLYxpnh+Kvx1zEXrYiFyQIYVnQ GXbtZrvL4UtK5Ivhr2E6FNo5wdwFwmQLINvakFvVVKL0doYEfDVIM7h67sF39mnX21fR ve8NkbkzyWpXL8kcP2s6L/UBwslmxifoG6BGDeV22T57kj1CuJv6ZkbDunDREfaTkyRf xZYZyayzx4s96jFi+lE1ffKEqG7uaJPEbdcFhITBD174YT2DO3gdgc9B0vMWmdmvkdlw qDUKxUbdSZUU6O7yDOYoLfuaazVEpAMitQh/xq+deQ7Ya9TV2FLButUf/OTUEUwsuMmf QkpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751389672; x=1751994472; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lu+dhy8iYnnYk+OhSlOhY3EbkuSfbLX8WS//TkMmK/k=; b=krhX//KvDLIS5by6yoxOYp9rckbvdAEdft90ZALDBchZgxuar8K92kriuCIAIeHOqG aVT043F6nBt8JJewmgPhGOeuAVTkpTceISXlml52E712EkgW+UkihI68EZVbZuiKbqpm d0DqsGsU+e9W5n8zg2DDIWQd9UrOby6Kf1UKMHe0BNoa5UjyrPT7ZiOCq3aqq5WoNZzG y/e6pJget9+O9GjeTieT0NRIhied66hbRKswECUoy6kYdhke2aYEJ4ZrLAICvmPLhY40 XgnhLR7S70ZVRm3gHdncrLXtWYc1p6JUTFHld2RwFPXBarKrflZPu3/gmjZsraVx94cI A3NQ== X-Gm-Message-State: AOJu0YygQYbZzPFfFH2y+3HAl6ohcy8ig3Td/D9kD3cPYqOvTOk3DzL0 qk5cu8+VImb1Dm1a/0T5ZYH1E+7qDIhvZCH4lGvgDaSrvvPRIFbQZUdVwxaIrFYH70znTHHaNwZ 97d9e X-Gm-Gg: ASbGnctxbNVh8iguhxKgGkBsSHu2cVbS/lduJSZPU0gl5Pvxfbb9RJ96zHTNIM1JOb4 T3XogxegyvmkOsJrFEKIe9J6FI1jfk9pGxjNENdepkuuxPcRVcCSqpCAjWZLE2hHIveZ6RrTiU6 WNxHwjtncOghazKEFYYjyKnrJi4u3ounQR1CCqNQPYMyphut0yRV/jA7xK7VJ2Lsc/auORvDIgZ 1C3LCIssKLEiTiIT/6zZDjpzikn3wPf7rsiSfpPyFITR/pWQg2c2B56hspRea7143GZSndP9biQ mfRx1t5pYFTQgN96NnuTFWEmUkhpXpozPwh7wEde9x3/6qOsGXP0btRWPCs6aVWhHzmW X-Google-Smtp-Source: AGHT+IF1iW576U9wQl2v3l/A39HPtB+dawMBh74KE+hTTjbYB/60I0cGnKmXzAnGJNQbvljoQs8Scw== X-Received: by 2002:a05:600c:c4ac:b0:442:d9fc:7de with SMTP id 5b1f17b1804b1-4538ee85615mr163266255e9.22.1751389672270; Tue, 01 Jul 2025 10:07:52 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/43] target/arm/hvf: Log $pc in hvf_unknown_hvc() trace event Date: Tue, 1 Jul 2025 18:07:06 +0100 Message-ID: <20250701170720.4072660-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751389821833116600 From: Philippe Mathieu-Daud=C3=A9 Tracing $PC for unknown HVC instructions to not have to look at the disassembled flow of instructions. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20250623121845.7214-9-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/hvf/hvf.c | 4 ++-- target/arm/hvf/trace-events | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 0943365a681..f36973a32eb 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -2072,12 +2072,12 @@ int hvf_vcpu_exec(CPUState *cpu) cpu_synchronize_state(cpu); if (arm_cpu->psci_conduit =3D=3D QEMU_PSCI_CONDUIT_HVC) { if (!hvf_handle_psci_call(cpu)) { - trace_hvf_unknown_hvc(env->xregs[0]); + trace_hvf_unknown_hvc(env->pc, env->xregs[0]); /* SMCCC 1.3 section 5.2 says every unknown SMCCC call ret= urns -1 */ env->xregs[0] =3D -1; } } else { - trace_hvf_unknown_hvc(env->xregs[0]); + trace_hvf_unknown_hvc(env->pc, env->xregs[0]); hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); } break; diff --git a/target/arm/hvf/trace-events b/target/arm/hvf/trace-events index a4870e0a5c4..b49746f28d1 100644 --- a/target/arm/hvf/trace-events +++ b/target/arm/hvf/trace-events @@ -5,10 +5,10 @@ hvf_inject_irq(void) "injecting IRQ" hvf_data_abort(uint64_t pc, uint64_t va, uint64_t pa, bool isv, bool iswri= te, bool s1ptw, uint32_t len, uint32_t srt) "data abort: [pc=3D0x%"PRIx64" = va=3D0x%016"PRIx64" pa=3D0x%016"PRIx64" isv=3D%d iswrite=3D%d s1ptw=3D%d le= n=3D%d srt=3D%d]" hvf_sysreg_read(uint32_t reg, uint32_t op0, uint32_t op1, uint32_t crn, ui= nt32_t crm, uint32_t op2, uint64_t val) "sysreg read 0x%08x (op0=3D%d op1= =3D%d crn=3D%d crm=3D%d op2=3D%d) =3D 0x%016"PRIx64 hvf_sysreg_write(uint32_t reg, uint32_t op0, uint32_t op1, uint32_t crn, u= int32_t crm, uint32_t op2, uint64_t val) "sysreg write 0x%08x (op0=3D%d op1= =3D%d crn=3D%d crm=3D%d op2=3D%d, val=3D0x%016"PRIx64")" -hvf_unknown_hvc(uint64_t x0) "unknown HVC! 0x%016"PRIx64 +hvf_unknown_hvc(uint64_t pc, uint64_t x0) "pc=3D0x%"PRIx64" unknown HVC! 0= x%016"PRIx64 hvf_unknown_smc(uint64_t x0) "unknown SMC! 0x%016"PRIx64 hvf_exit(uint64_t syndrome, uint32_t ec, uint64_t pc) "exit: 0x%"PRIx64" [= ec=3D0x%x pc=3D0x%"PRIx64"]" -hvf_psci_call(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, uint32_t= cpuid) "PSCI Call x0=3D0x%016"PRIx64" x1=3D0x%016"PRIx64" x2=3D0x%016"PRIx= 64" x3=3D0x%016"PRIx64" cpu=3D0x%x" +hvf_psci_call(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, uint32_t= cpuid) "PSCI Call x0=3D0x%016"PRIx64" x1=3D0x%016"PRIx64" x2=3D0x%016"PRIx= 64" x3=3D0x%016"PRIx64" cpuid=3D0x%x" hvf_vgic_write(const char *name, uint64_t val) "vgic write to %s [val=3D0x= %016"PRIx64"]" hvf_vgic_read(const char *name, uint64_t val) "vgic read from %s [val=3D0x= %016"PRIx64"]" hvf_illegal_guest_state(void) "HV_ILLEGAL_GUEST_STATE" --=20 2.43.0 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1751389722; cv=none; d=zohomail.com; s=zohoarc; b=Ys1Tz1tnx7d+sJAyvbrfOO0as9OOfv/Q96hnI+EQh3vTJqyVZVREFsaWIJyompc7unjYdXhWUb8KZ7cCh90kYLkTHmhn8YoLzpP3VX/TXteMc7LaWZKg46abn/GBavaIcB7FeLoY/ix1olEd2KHajoIWwElXiwal6CUv/oR8Gvk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751389722; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=SK6A8clbB22J0MzblVefPn0yu0hM761EUxAP6vsqlrI=; b=dj9tE/1giaSduVXs6ZUToqfWECHpueFAKy9T/svDi7rv9LVshFIokcRcH0wn4Cnpwr/cgK3msZ+ZV0J8f8Hrx+8igTSk4BuuTAncz6+eRJhurMcXLa1T11MlH2XeqEcfauk0q4YY78yOHB3Pxr+w5a4Gq1qmylX4yppMlEviVlE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1751389722191109.79525980885319; Tue, 1 Jul 2025 10:08:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uWeSg-0005jU-Ec; Tue, 01 Jul 2025 13:08:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uWeSc-0005hj-9K for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:07:58 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uWeSY-0003eG-VN for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:07:56 -0400 Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-3a582e09144so2659673f8f.1 for ; Tue, 01 Jul 2025 10:07:54 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a88c80bb28sm13475658f8f.43.2025.07.01.10.07.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 10:07:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751389673; x=1751994473; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=SK6A8clbB22J0MzblVefPn0yu0hM761EUxAP6vsqlrI=; b=W6v+t8Hqwzi0uPyPdMBoj4fE8Y3LJSHMsdQj1LPX3yHJOpCpdc3Mu+5VGVbLGNGD2X 9pMH0i9ufAJ90TklGyUAbWbqQS1Pl1obphKPOOSgYTX0zVilCC2NJ6JWunWFOl0QK02f vRNPM8BTVQ9zn2Ee7XF5UModkBLx57oAjDwZjps6gnG6ie+R6tOqViHDVKIqEcwZpHqx 7Y4By+y7b92JAMMAlEh/F5y0idNpLxN+lv/KxS2BE4Rd/65wQas0DJxPFM8yqt2IzSyO USifhILI0VfLwe4viDFNGeQaSPP91LMOBhkafEsptLYnCAwSVFyCVvs/6kFPsvu3UzaN TA9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751389673; x=1751994473; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SK6A8clbB22J0MzblVefPn0yu0hM761EUxAP6vsqlrI=; b=vS6XD3FM+qq3joetHAD96aOY7lVVhVxoMWySlOeSI68vLNzpX5e48craWVDm+Muc9/ 7WkEegplW6CBaMTzhE3dUs51UUSeqsp9Yc9TEOX48+yZ/Y/s8AxPrYpY4DK9oBeNzu3q JKifQUwKUyROyPX0i6g9K+vwIGdfjI67CS7mLA+pUBsdMqQPCnX6sOilyayZ12LT6m9X On+7LiNnvjITtgTutUGOj/WcVjrvNg6KqdPwlhFdAWJBgKW1zVU1fUXU1WXkduo+tnKQ Hl4wphlq3gbcfwpYu/f5iIz2JQgT6cyNU2xE3rgNtC1ptCUZln1IgCNJYfKa0XzmN+EO qn1Q== X-Gm-Message-State: AOJu0YyRU4Su3g1Xxh0KpBBSRZjfq7A5O4MLPKibXa9nGhqpKQ7rrih/ lJagczaR1ck4h6gCG0RWulaSgXH/CqtdEJUPhgwcEsLuivIHqh18mhfWtzoPy+3yp5fjLMP4Xib k7bhX X-Gm-Gg: ASbGnctDVgiojHZcX1sqzOJEtskgM4V/ZU97hzCwtbz4UpkPuKaWXFew7pWM+MNxjDv qU48HrB2dAyEzswjC4QHG2gXDkH/jZ1oRG62jFdIONkNYJ5GSwv9xhp8OZvoViDlNA/Fd/1Y1o+ tzQ2S9Xe5yBxmOwBScDDLBLton1VZe135IuUNs23bkHd6mhg2sHKzHQwOZj/ruElaytvTiWVgHF mBMqNy/tRV0Mk/qZ1Xz0wULBJIU5DNXxCvVQblatIs/qAMPoH2JVv6dUH7AN75lsNW05hQ8lcM8 kdYSR/AVC32lx0hjfCWW0XyMZieHqaqG1MvQTkJKKz90rfx/kfRZDIi9tIh0sphmyW3X X-Google-Smtp-Source: AGHT+IH+nUKcV7dcFCdWh8V1SAwwkrk/oD/Hrb0FSK16CKo87eY9/stOHfAfAv3XL5WbDTgRl4V3UA== X-Received: by 2002:adf:fccb:0:b0:3a5:3930:f57 with SMTP id ffacd0b85a97d-3a9004801acmr13424825f8f.51.1751389673232; Tue, 01 Jul 2025 10:07:53 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/43] target/arm: Correct KVM & HVF dtb_compatible value Date: Tue, 1 Jul 2025 18:07:07 +0100 Message-ID: <20250701170720.4072660-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751389724607116600 From: Philippe Mathieu-Daud=C3=A9 Linux kernel knows how to parse "arm,armv8", not "arm,arm-v8". See arch/arm64/boot/dts/foundation-v8.dts: https://github.com/torvalds/linux/commit/90556ca1ebdd Cc: qemu-stable@nongnu.org Fixes: 26861c7ce06 ("target-arm: Add minimal KVM AArch64 support") Fixes: 585df85efea ("hvf: arm: Implement -cpu host") Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20250623121845.7214-10-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/hvf/hvf.c | 2 +- target/arm/kvm.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index f36973a32eb..ebde4c6f183 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -883,7 +883,7 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) hv_vcpu_exit_t *exit; int i; =20 - ahcf->dtb_compatible =3D "arm,arm-v8"; + ahcf->dtb_compatible =3D "arm,armv8"; ahcf->features =3D (1ULL << ARM_FEATURE_V8) | (1ULL << ARM_FEATURE_NEON) | (1ULL << ARM_FEATURE_AARCH64) | diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 70919aedd0a..426f8b159e8 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -289,7 +289,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) } =20 ahcf->target =3D init.target; - ahcf->dtb_compatible =3D "arm,arm-v8"; + ahcf->dtb_compatible =3D "arm,armv8"; int fd =3D fdarray[2]; =20 err =3D get_host_cpu_reg(fd, ahcf, ID_AA64PFR0_EL1_IDX); --=20 2.43.0 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1751389784; cv=none; d=zohomail.com; s=zohoarc; b=HrhxDY4IdI4QYheA1m3tRki6sjbcKVA9QIBHxDcqvlHGuhdir6iD38wc7pkm06g+HHPBWr2XNFPaOvuvAhbZzPZ2CrElMClWiXC7NsaVX+lVANy1rW27FiEd4dH5vhEHCWGX/T5jaJHJeDMIIE7yotvoXGnykEphB1OwULAtMhc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751389784; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=oWq+MsMuHkvLIcOj3T9lPNr1c6oazCfcCQPJVuth2lo=; b=Bj4ZiEpNpPaJVR9ESC3LMO+bmtEsxPs4ufUjg3xA03MbHfi3r9Bzcu3qYuR8WqImCcqKo5nCJ/vFzuO6ruYXMWokHxgMtY/e+7ifMQgZ1iZXGC7ZHQVdDESWXmrRbtNyT22aZnjZNsJzMEjT8XcUKgZwMFcjiCShVsyC6YmsoI0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1751389784490883.8665991713343; Tue, 1 Jul 2025 10:09:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uWeSi-0005lX-NX; Tue, 01 Jul 2025 13:08:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uWeSb-0005h9-UC for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:07:57 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uWeSZ-0003eu-WD for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:07:57 -0400 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-3a4fd1ba177so3890463f8f.0 for ; Tue, 01 Jul 2025 10:07:55 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a88c80bb28sm13475658f8f.43.2025.07.01.10.07.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 10:07:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751389674; x=1751994474; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=oWq+MsMuHkvLIcOj3T9lPNr1c6oazCfcCQPJVuth2lo=; b=waegaM7lIf7kQwnhsxpVghq8AQYTLCDCK5dmS8TYujUr1iDp0t7VtAWUK6euUOafMk ZI3qSRuc74mByfwkGRHhTFQ1ie6rMPkbyIbEDQ7Fq2kfzGkpS7djw1jksMqZVKKaauk+ volHygp2G6NU/8zrI+D8gVEPWawyj7vnb5D80GEit6Ly3hhvS8O+J0x3BgC8Cp466cyI mwEk+Fd3cC8H0PxMDIU7wrjQtYU+/3pBQf/nXn6FrZYkE5K6onA49PeJEER6frcIA2UN +eL0Z204pjUtd44/b2+VbDEiPLjtnWBJe/k6vaAZIdawpfFCbo5KqHk4FyYWMR51ztDg Z7+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751389674; x=1751994474; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oWq+MsMuHkvLIcOj3T9lPNr1c6oazCfcCQPJVuth2lo=; b=m9T4s28NxUwOYPmoRQg/kOJrtE01mNzEL4j4/G+resHwG6rxWDqLfxzidq3naTqUS8 BYlXDaz5RPynMus3YuaEST1isZrKP3T7gWjaGoF0m5otqheqql2Nbk/3tppmVHOeZeae HwcbO/cKiig6XjhzFELFMqUDHkUdjWGjhXDk4mbD6plRrpvhrjlkMj3DGz2Rxw1+JdAE MGJY36qyyYpoHdYuceTJ64vYJ9Ts7t840W/Owq8QXGt6PpCgZeWR7Yz4MYB5JeNwLSJe RAlXq6usZvqtD3ryoaIjng+F+wdBAQTDyJPGDzh/NcSLHauoHDu8tGlQzpJLuQJhgecK k03Q== X-Gm-Message-State: AOJu0YzxSYklGhbKMq9VPevngvQX87iDCSd4yvHFaYJ+kFkYqAw/RtSZ 2g0zViM7v6DkJ61GIep4pdapDVQzJ/6aI+F0tGr/YYllIS7EejP3n8tYFREqnNOaOw9OUNEqtrQ KeQTA X-Gm-Gg: ASbGnctSoy8zvafozKATvDsYTfiQGd1B7aeByb9hpeMUY5ePx/V8o/533xD+0Rn8HJd UL/0NrP+6ylXFBiCeBE4E4yOk9gv93ciAbuKdfS9wqCF+goXa1TJUPuyrR8q3O3j3nu+GOq0l5w 35P2P0LI7sEHmGZAoqPGi5iQZtwruNRn5nm328V7tXnUPfLWNa+dTqZ2f5WrOuVYWqcy6OnJy9H e4SAql8KqKp0Al/aMmJGRy84XKtEK0EuW1285kxZbTqVDpjslgpwRyNXJgdJmSx/qskXv58brRo 5nSvJ/CxfYG0kj9vZCaJ57nXQYAoewMlcweC4R2DNFG1hNhhIkiLlwigSIUwGEZ93W21 X-Google-Smtp-Source: AGHT+IEjCua3g+eRN9RRwvt7X7Zka/gtKuJq55wiER3xWTmLwkc0k3ohJOeW2OxLadzbBGJvvUVSBg== X-Received: by 2002:a05:6000:643:b0:3a6:d95e:f37c with SMTP id ffacd0b85a97d-3afa162e3eamr2732776f8f.2.1751389674151; Tue, 01 Jul 2025 10:07:54 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/43] target/arm/hvf: Pass @target_el argument to hvf_raise_exception() Date: Tue, 1 Jul 2025 18:07:08 +0100 Message-ID: <20250701170720.4072660-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751389787753116600 From: Philippe Mathieu-Daud=C3=A9 In preparation of raising exceptions at EL2, add the 'target_el' argument to hvf_raise_exception(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20250623121845.7214-12-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/hvf/hvf.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index ebde4c6f183..7b6d291e79c 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1088,13 +1088,13 @@ void hvf_kick_vcpu_thread(CPUState *cpu) } =20 static void hvf_raise_exception(CPUState *cpu, uint32_t excp, - uint32_t syndrome) + uint32_t syndrome, int target_el) { ARMCPU *arm_cpu =3D ARM_CPU(cpu); CPUARMState *env =3D &arm_cpu->env; =20 cpu->exception_index =3D excp; - env->exception.target_el =3D 1; + env->exception.target_el =3D target_el; env->exception.syndrome =3D syndrome; =20 arm_cpu_do_interrupt(cpu); @@ -1454,7 +1454,7 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t re= g, uint64_t *val) SYSREG_CRN(reg), SYSREG_CRM(reg), SYSREG_OP2(reg)); - hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); + hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized(), 1); return 1; } =20 @@ -1764,7 +1764,7 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t r= eg, uint64_t val) SYSREG_CRN(reg), SYSREG_CRM(reg), SYSREG_OP2(reg)); - hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); + hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized(), 1); return 1; } =20 @@ -1967,7 +1967,7 @@ int hvf_vcpu_exec(CPUState *cpu) if (!hvf_find_sw_breakpoint(cpu, env->pc)) { /* Re-inject into the guest */ ret =3D 0; - hvf_raise_exception(cpu, EXCP_BKPT, syn_aa64_bkpt(0)); + hvf_raise_exception(cpu, EXCP_BKPT, syn_aa64_bkpt(0), 1); } break; } @@ -2078,7 +2078,7 @@ int hvf_vcpu_exec(CPUState *cpu) } } else { trace_hvf_unknown_hvc(env->pc, env->xregs[0]); - hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); + hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized(), 1); } break; case EC_AA64_SMC: @@ -2093,7 +2093,7 @@ int hvf_vcpu_exec(CPUState *cpu) } } else { trace_hvf_unknown_smc(env->xregs[0]); - hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); + hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized(), 1); } break; default: --=20 2.43.0 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1751390101; cv=none; d=zohomail.com; s=zohoarc; b=YjWjgC8xhBmGBgG4levBIUADZEVFhW/bewDQjMnB1UYDm50iYr9GfzT6CecNOH3dTw2VtbmVlEN10Jx6BjyxLy2aACAMFkkOJkrHFhm7fGBKt+ZQtlEZFfOwiji8MwQ8attQzax3S9P+7Bdq3brh3aMB8XgUrEVG7CtmyfXt2Es= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751390101; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=KRmd9q8SI1/2SMrlX261n/ejf2J7y88+dRZ3yJXd/34=; b=YBqIZFzo15C7Eo+5vbw8Y8BiVsoRhBkJOWffJ/5Mt72FJ4Pu0Q900kqBkaOKFm+qSQcLP4etawD382tqT4LkjT++jPben7sbLIUyuvVzmURkLRr0yF82Y3Q1XzYeVZIRH1JeRG4GSCSPnx3YWRMP1dvT9YrDsTTNoJEptv0gLE4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1751390101083190.74282703354675; Tue, 1 Jul 2025 10:15:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uWeSi-0005lN-Fu; Tue, 01 Jul 2025 13:08:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uWeSd-0005iR-Ab for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:08:00 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uWeSa-0003fq-Rs for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:07:59 -0400 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-3a50fc819f2so4252358f8f.2 for ; Tue, 01 Jul 2025 10:07:56 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a88c80bb28sm13475658f8f.43.2025.07.01.10.07.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 10:07:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751389675; x=1751994475; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=KRmd9q8SI1/2SMrlX261n/ejf2J7y88+dRZ3yJXd/34=; b=WnYNqGe3wG4n3GAGpD8b5FIYXLx8qXX8pEZCvS5Xw3Ggk+BDoI+8xT5VpKN5uEwWLf QbV8x4iy6JpBY46GGuuP+xauaz8g1D2VfB0gmi/3uRAubahcF8QzQmLLcA8cVOAX4jrD kXysgLGIO7C4fL13OWvwFDyrspgDV54O9l6Nvv0C/f61ltalEcf39Wy6fTFRDYJZtspE AktV3vtJHxkWmRJBjijCiBYcu3GrkaV//oHKPomzWYg10IiBg4/h/wMyFO2LZsYqB/XP 4+hV1WgkBqXhReXjtpe4jqPvsM/VUgOeBzs5olxVJaBAC779tgMGksgm76EbuqbSA2CX VcHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751389675; x=1751994475; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KRmd9q8SI1/2SMrlX261n/ejf2J7y88+dRZ3yJXd/34=; b=Z1X8GLH6t6Ra2AowC1Iwr5qJNJ/vy/5R/TGUhyxGyrXJLNBj9QztHK9sbCHiTNwp40 rrGuqL6IZLCeL7ncShWiTsAWGr6t6cMThhH1B5Ai2oj8W5m93ieigQp4+VsghHyWu2sI C9cFe+UE4zKfaK6hsTYyvr4gPOhkSk6IrcNomrELfUJHJ3XP3GT6eqEEdQZHSPP55jQo 5AQTz6AbJnwkn7UNsJLfFMUv53Ttg6gOii8bHSvj4ZqvniNfBM5vcgiWGOpmAkUFlHU1 1eh/+Ryk4iCG92DyBq8tKt1g7X+gMruiq1c+bzzDpFSLsLZ8fSjhjMI15fDWHhY32Ohs xRFA== X-Gm-Message-State: AOJu0YyfwpDUN2SkF0URyFJd09G3MUUvu2NzU/jxkgkeGKWXq03qKV/R 0S1BDwP1IoK10JUUF2l03aFG9yq0uZ+NkW9mZgzgoeLi9AlJbY4cXEWPQBPafI5hoOfbUTpMeWh yOcL2 X-Gm-Gg: ASbGncvMo2WVUZYrzVooDoaeo05cPsGZxUaiXGPvXK5S0bbrlyFl2XRp7PMStpZX50J 5+r6WAlcYfe7jwTk0gOBP9soHYcJ436crU5l+GDsUyVV2gLWN4iLzZlmWa+nxB1ln+RuoxdrvF5 CBJFpXTp0GxphjLdFLgdD2INkPlakm3GrdgNSnA9gytf4WykicJHURVrjxDOEFaf5EkaN2LlLi0 6gQb21KUsKuFcF/79LsI58zZZojx11WzyV3D+1cSKA/AM3NQgpN9maEGB7TX03Fdev1L88W9SKy xqy9R55qixiuuWHCsrTnuXKzTOKGbfbSSdTqUhqlXuKAiuUxhk85KYZhUaCYep1u1Atq X-Google-Smtp-Source: AGHT+IG2vLea3YAAIuKFofkC3j1JjzjVo0YC220k2/tDIg4yKhxrw4nMsr8cI0cv1t+Ji5qNtRiPXg== X-Received: by 2002:a05:6000:e0f:b0:3a6:ec1b:5742 with SMTP id ffacd0b85a97d-3a90d69c82dmr12504896f8f.22.1751389675199; Tue, 01 Jul 2025 10:07:55 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/43] target/arm: Restrict system register properties to system binary Date: Tue, 1 Jul 2025 18:07:09 +0100 Message-ID: <20250701170720.4072660-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751390101704116600 From: Philippe Mathieu-Daud=C3=A9 Do not expose the following system-specific properties on user-mode binaries: - psci-conduit - cntfrq (ARM_FEATURE_GENERIC_TIMER) - rvbar (ARM_FEATURE_V8) - has-mpu (ARM_FEATURE_PMSA) - pmsav7-dregion (ARM_FEATURE_PMSA) - reset-cbar (ARM_FEATURE_CBAR) - reset-hivecs (ARM_FEATURE_M) - init-nsvtor (ARM_FEATURE_M) - init-svtor (ARM_FEATURE_M_SECURITY) - idau (ARM_FEATURE_M_SECURITY) Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20250623121845.7214-13-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7030540f91f..a59a5b57af6 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1500,6 +1500,7 @@ static void arm_cpu_initfn(Object *obj) * 0 means "unset, use the default value". That default might vary dependi= ng * on the CPU type, and is set in the realize fn. */ +#ifndef CONFIG_USER_ONLY static const Property arm_cpu_gt_cntfrq_property =3D DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 0); =20 @@ -1509,7 +1510,6 @@ static const Property arm_cpu_reset_cbar_property =3D static const Property arm_cpu_reset_hivecs_property =3D DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); =20 -#ifndef CONFIG_USER_ONLY static const Property arm_cpu_has_el2_property =3D DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); =20 @@ -1532,6 +1532,7 @@ static const Property arm_cpu_has_neon_property =3D static const Property arm_cpu_has_dsp_property =3D DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); =20 +#ifndef CONFIG_USER_ONLY static const Property arm_cpu_has_mpu_property =3D DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); =20 @@ -1544,6 +1545,7 @@ static const Property arm_cpu_pmsav7_dregion_property= =3D DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, pmsav7_dregion, qdev_prop_uint32, uint32_t); +#endif =20 static bool arm_get_pmu(Object *obj, Error **errp) { @@ -1731,6 +1733,7 @@ static void arm_cpu_post_init(Object *obj) "Set on/off to enable/disable aarc= h64 " "execution state "); } +#ifndef CONFIG_USER_ONLY if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property= ); @@ -1746,7 +1749,6 @@ static void arm_cpu_post_init(Object *obj) OBJ_PROP_FLAG_READWRITE); } =20 -#ifndef CONFIG_USER_ONLY if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { /* Add the has_el3 state CPU property only if EL3 is allowed. Thi= s will * prevent "has_el3" from existing on CPUs which cannot support EL= 3. @@ -1818,6 +1820,7 @@ static void arm_cpu_post_init(Object *obj) qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); } =20 +#ifndef CONFIG_USER_ONLY if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { @@ -1854,8 +1857,6 @@ static void arm_cpu_post_init(Object *obj) &cpu->psci_conduit, OBJ_PROP_FLAG_READWRITE); =20 - qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); - if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); } @@ -1864,7 +1865,6 @@ static void arm_cpu_post_init(Object *obj) kvm_arm_add_vcpu_properties(cpu); } =20 -#ifndef CONFIG_USER_ONLY if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && cpu_isar_feature(aa64_mte, cpu)) { object_property_add_link(obj, "tag-memory", @@ -1882,6 +1882,7 @@ static void arm_cpu_post_init(Object *obj) } } #endif + qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); } =20 static void arm_cpu_finalizefn(Object *obj) --=20 2.43.0 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1751389886; cv=none; d=zohomail.com; s=zohoarc; b=V1ETdU3oGvXhUCGpAYXhkOI+IJKUh0JCrKFZrrWHJx7IUtm4VKh/lpARnWWJCSsf0E0zf9V0oOWNzJiiEOcHcnnpv+Vmqf3NkXn6lOw6DFIa0aVRqSiTlLGVYo0HuYgaFnef+422BN6CgAXSl2luaq9Ugf8bZFq9YdUKJtHb41M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751389886; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Mdqrq8TNiJgbQe6RUl9ahMIeb4dG8atTY9r/8PfJiic=; b=Vsq4E1w9/iPAMu9leroVvauaFZgzBSlZuB8y5+XJhESM/KBk1/12fS4i2lNKyPeDR76zZndLOaN5yqJpaGkF0sjkDDZ08Hdbl4rdf63TX21zyWZmCQy+zsPrMXBpgr1QUuwOGxs+ix21wqlfGTYmzRQ6wHhRhFb/o4btlecKPqY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1751389885725870.9529538596216; Tue, 1 Jul 2025 10:11:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uWeSj-0005m3-5n; Tue, 01 Jul 2025 13:08:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uWeSg-0005jS-86 for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:08:02 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uWeSe-0003gS-4j for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:08:01 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-453398e90e9so29243035e9.1 for ; Tue, 01 Jul 2025 10:07:57 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a88c80bb28sm13475658f8f.43.2025.07.01.10.07.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 10:07:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751389676; x=1751994476; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Mdqrq8TNiJgbQe6RUl9ahMIeb4dG8atTY9r/8PfJiic=; b=nFL0irx/Q0EYB+QdkjHr8NKcTgVyV/281mC9Oc9mvH87ZaNb8n6sISXuwODrEhLxgO Uf+P1KhhYizeRvq/bELKsemCW3T0x8bPx7mdhvjoru89LbUTERpqVHGpl9Umuwmqq/7+ sFuCaiQoCBDtMfih9cQNtro1ZbIrYTxVqib+Mevc7seOYbm3tJFCor/ijsGq5xdbExgx maDzN8RLxH0xlCvnBeovsF5yQR44BOlEG6lt+G2OGqzazKXj3PqzOzwFEPV+rPuyhiYW ZS+F1IKTHJLIkkukQSQPDBhAQgDqZkVXO89JU2tzPvsy7oQjxRtjodynjZQa5gey765k 7fgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751389676; x=1751994476; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Mdqrq8TNiJgbQe6RUl9ahMIeb4dG8atTY9r/8PfJiic=; b=mqW4HRh62NQ7Sd+b2VXQwt4c9FAJkcpFL6ksmAaYWQaE4rjO2a+ajN9ewl+l4hm66G dxeX4hUBdCukFaOriwCGVoyV98l1a4EImjFVfM7STMEf37BKnZ+jJQRsXz1vEfd5dfNY LasMDO4AMN3mSWgo2ShoHHeLpPkpkIr0zka7KRFfIh8xgs8KAe5vuTv66VIgZ9UG4yRq eNxfb/9u5ykX0wdi3nXRRkRiJWADu2gYSf5BIuxu7bv5bU3DmtVDuKi2OT0jQiZdyFjv Cyqpps9/QH9bQUTNH/UE3S9SBQen16hzHvWEj7fwaUnSOJfWFlVOIqDzYD0S1gSvZlAg Nesw== X-Gm-Message-State: AOJu0Yxcv8FYGNLOntQZZQrYDR5r64/RySyhu4oY1mfegka+zGKsP/l5 68OORTwLSuyzKZv1U7JNgP5BKoCMZZojn204w4v4fnTk7GKn2n1wlV5vhW7gaO5os86K1t5gN91 YIpjG X-Gm-Gg: ASbGncvgeVUgg0FXAv9God8min6+jilOrBj0Pzna7vaeu97/vubivXjC0g3CusmU8CL 90F7Xrqv/C6wx1RiZYo1mWER6xV45g7KD0YDEOgIA9uNJNdd9WlBgt8oZu4mnY5LhsaOFHDMsHQ wV/OxJdZH5VH+5fvOwUOU8RM9QN4tXqtjohdRgwr6SGggfO/sIyF7Rodt/TM3gF+W7IqdXhuQwN 06cq99ejAP3QVf6cM+9jhMDGR2PPVuAH4VCHpaH1R4HQpYTX3diaQnc1DJr+DQhTv1aMX8TjsX8 PStWleBU9kp//dxWGRDBPy9jgDXKvMYXWlUatm5ItKzZeEgxeQ1dN/oM+lv6SdlN3QSy X-Google-Smtp-Source: AGHT+IEJYqH6c0HsuFnihQ9hVW9cXskyC2oGb+7s+AJtCfFffBtElBF8jVJaqM8r1R8AnxRK6X+FPg== X-Received: by 2002:a05:6000:248a:b0:3a4:c9d4:2fb2 with SMTP id ffacd0b85a97d-3a8ff149554mr14492102f8f.46.1751389676134; Tue, 01 Jul 2025 10:07:56 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 34/43] hw/arm/virt: Make EL3-guest accel check an accept-list Date: Tue, 1 Jul 2025 18:07:10 +0100 Message-ID: <20250701170720.4072660-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751389888558116600 From: Philippe Mathieu-Daud=C3=A9 Currently only the TCG and qtest accelerators can handle an EL3 guest. Instead of making the condition check be "fail if KVM or HVF" (an exclude-list), make it a be "allow if TCG or qtest" (an accept-list). This is better for if/when we add new accelerators, as it makes the default be that we forbid an EL3 guest. This is the most likely to be correct and also "fails safe"; if the new accelerator really can support EL3 guests then the implementor will see that they need to add it to the accept-list. Reported-by: Alex Benn=C3=A9e Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20250623121845.7214-19-philmd@linaro.org [PMM: rewrote commit message] Signed-off-by: Peter Maydell --- hw/arm/virt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index ae419e86712..b3b1c6df7fa 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2200,7 +2200,7 @@ static void machvirt_init(MachineState *machine) exit(1); } =20 - if (vms->secure && (kvm_enabled() || hvf_enabled())) { + if (vms->secure && !tcg_enabled() && !qtest_enabled()) { error_report("mach-virt: %s does not support providing " "Security extensions (TrustZone) to the guest CPU", current_accel_name()); --=20 2.43.0 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1751390041; cv=none; d=zohomail.com; s=zohoarc; b=kENYcvG0D+H2QlgecVXS6fGhTRB/92Iy3odOPUZOpxriCCvO+yjvaurCRBbIn6qh0SQ3THpk6vJyXezd20JppoRcZcxfrfN1mCyXFtlJ+faPmwINtzTmXY7TVhuFEbmrLiTAJTsY5GshDUjTgRExjB+u8wV+Wa0dKmf2uLxPtgE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751390041; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=r7p0sPnBcRmvM4bd4jbXz1OCAH6iKswXTMPYh8eLjyw=; b=MrIvTvEJi//VaRi6jwNP5zT8UVBNdUhpQRDbXRXI+vMdeOjOfKi4M1HxVSodGJKGMZqx+hUVgZMEka9ugjFAKvwiUVQrhe3RtsBUPucQONfG/qemJpNHFVjF9nsaeL84/FTbprX0M41Z29tPtX6jxI67DCGrnHXwmDclLzn9sEk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1751390041780444.33553365973546; Tue, 1 Jul 2025 10:14:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uWeSo-0005rJ-6o; Tue, 01 Jul 2025 13:08:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uWeSl-0005oo-1k for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:08:07 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uWeSd-0003h2-7K for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:08:06 -0400 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-3a588da60dfso2268261f8f.1 for ; Tue, 01 Jul 2025 10:07:58 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a88c80bb28sm13475658f8f.43.2025.07.01.10.07.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 10:07:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751389677; x=1751994477; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=r7p0sPnBcRmvM4bd4jbXz1OCAH6iKswXTMPYh8eLjyw=; b=NrJohOVudVAh3HLIFxAtdU/FW1Dw5Kl/MpJMsMh6Njw74xD5itH2brjV0aoaKjIHis /cRAO3YmoFl27cdUXSoZspdDZ1WXmPinf45R677XY8tFGT+NtSUgCMA5j+zBVMuZX1SO VOxXWKnOeigQb9tp6aFISx8Gu6z+pTSFQHLa9FQ0soGh7eQ19/TKMwHss4j3ENMCsHDM To24BGqSmXibRycvABfJ0UJcvyE/OSL1Dn1StZa+jAPe5KTV/Htj6HSTng7aRL8NjD+u u74lPjAamnI1UCheb5BTyko44Lm7ru6pUpGGjtA6aOYz8wRgfsAQWC0Ksx9yxaub/4++ T9Xg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751389677; x=1751994477; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r7p0sPnBcRmvM4bd4jbXz1OCAH6iKswXTMPYh8eLjyw=; b=XjzltG7Ci81UtFDyn3NpgMLc9QzPJFByc6xLHP679Lrc47XKTXaGL6l4qxBdjCNC82 kC/r22pZx3pbL4Rwij/9AoCUco16eQMB6M2Eq03SI8Pnh+5EAVdclgT2inUpEbrbexxV HzNr5dbkavSmFZqAqo/W9O+Y03tOVD80BV6uZwlVWEheE7tpphbJaoAWHhvDuX3Hzwvn LjM0TCIs+GRVoHyrgz1CW8YszOQZOk58Dpl4qfPXNXjeUi21scBP4MpJJQ9Gl+n6pp/U J63eAGZU8uns5lk5rvZy/u2sfjiSV5Mex3QKrd0ILD5btDSlrLttGz/Hy7m3Fli1cFa2 T8LA== X-Gm-Message-State: AOJu0Yyqie8hH5rznyn8GotVUfGOx87s/m8+LpraJMkGEHwIttNCfpdH mvJAS3fmGXi+KZN57nkVssUCd14g29CHCF6poEXc32maPa1v/av2td07VAF+HI48ncJrt1TZdpw 50oCQ X-Gm-Gg: ASbGnctEsgqUSEwx+pEF6U0aLxAXZA++v5KrjFBXPn0wGvQSHKA9r08ALfVZD1h0seS ZkRu+z1kES8j2PBMs8m7HleH3gD0S+JxW5XQrqzSZnNIJbiwIfZRHyzUPYS5fYKfvU0R3XPPohA twscStsM6mKLVF4bI3SiCwwmPqnm1wBCi7KuiI71HhAtr+PvccJOSoXo4Q84vWHFiQKVJQZ/p+G Wit33m/ZeA22o0maHqfDzW0ONrIgSlYv1rr0CoYkTLSowjVgSxiTrz2pajbZCTW51y2P6HorZ5u kMmxcUFQX7gbTgHLjI3EW6tuaPvdHc/O+YWdu/l4oO782eM8xdEbzgjuUvw34ehBfcDj X-Google-Smtp-Source: AGHT+IHqhlsfKbTnlHveeKhO0MPD0gHoL/1LO51nUOXa1O1/JQyFtn2+bh8ziX348ThoGlqhZ6FC4w== X-Received: by 2002:a5d:4a12:0:b0:3a4:eb92:b5eb with SMTP id ffacd0b85a97d-3a8ff8f4ddamr12380547f8f.50.1751389677023; Tue, 01 Jul 2025 10:07:57 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 35/43] hw/arm/virt: Make EL2 accelerator check an accept-list Date: Tue, 1 Jul 2025 18:07:11 +0100 Message-ID: <20250701170720.4072660-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751390042923116600 From: Philippe Mathieu-Daud=C3=A9 Currently only the TCG and qtest accelerators can handle an EL2 guest. Instead of making the condition check be "fail if KVM or HVF" (an exclude-list), make it a be "allow if TCG or qtest" (an accept-list). This is better for if/when we add new accelerators, as it makes the default be that we forbid an EL2 guest. This is the most likely to be correct and also "fails safe"; if the new accelerator really can support EL2 guests then the implementor will see that they need to add it to the accept-list. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Message-id: 20250623121845.7214-20-philmd@linaro.org [PMM: rewrote commit message] Signed-off-by: Peter Maydell --- hw/arm/virt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index b3b1c6df7fa..30f91bcfb3c 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2207,7 +2207,7 @@ static void machvirt_init(MachineState *machine) exit(1); } =20 - if (vms->virt && (kvm_enabled() || hvf_enabled())) { + if (vms->virt && !tcg_enabled() && !qtest_enabled()) { error_report("mach-virt: %s does not support providing " "Virtualization extensions to the guest CPU", current_accel_name()); --=20 2.43.0 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1751389916; cv=none; d=zohomail.com; s=zohoarc; b=gRbRkEGlu+QR/CxooLAnLEf60JW1LKP2HtV0gcQ7k40BOTpahDRp0cEaQoCsLOv2gTq+gNBbR0bcrOq9PR9g+3aJvnqS3CGjofqVG5aF7jHjzcthDx37mqYubUk/rh5KqF5axwJTLOtfJcFx5NBOkcHHH+SC/Uf+l3Dg9UgUFKc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751389916; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=/DJBJh8TrP9nUNYIuMCuVv0lIVyAFjDZ5LeEIS1A2hs=; b=hzB9w4MKRlTRkxp69pkD8PioMGoDbcPp6+tyqTpguIE8IswPVMn6+srJDLGJzBMOuBRnWOjaRSNonK6xN8l8ZlgX/p2RdUuxWEjtA3RlmEYYfxvxMQ+p/phiF64KdiADJ9vhlNOfNbQWysqOllq4i+ZsjvLc9GNJqtGBnYVDwFk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1751389916177331.34562885070204; Tue, 1 Jul 2025 10:11:56 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uWeSi-0005lP-HC; Tue, 01 Jul 2025 13:08:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uWeSf-0005jP-P6 for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:08:02 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uWeSd-0003hW-J9 for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:08:01 -0400 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-4537edf2c3cso59055445e9.3 for ; Tue, 01 Jul 2025 10:07:59 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a88c80bb28sm13475658f8f.43.2025.07.01.10.07.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 10:07:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751389678; x=1751994478; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=/DJBJh8TrP9nUNYIuMCuVv0lIVyAFjDZ5LeEIS1A2hs=; b=NP+On352uk9XxY5EWB6SyeR7lIwaft4AwmaYHacGk0jrrOVemV4FNBM4SYWvv/WGjD h0pVwwcUk8KjEijjDBjDjek2rtxXs3knnDyRUG9eUWB9scX8nWm0gE5NkmQH8J5LU16d RL2cvIJk/2GTB9MXg0EPhxCH+03kIt4z2ZU0s7vumFepJ+EwfttA1FFsuiUEuCsZrZmi PCN7dijsXqOIvs80e0i42X//PfOauqHmVN02Z4SUCte56/HOuiv/QPGOxjCdP6d6rJwq c/nHTqIKe+s8l462Il2dtmHhSVW/sa9LtX0sKSPMb/8v/vRmIR9IDDyEx9qbPFKK0AFM MNnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751389678; x=1751994478; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/DJBJh8TrP9nUNYIuMCuVv0lIVyAFjDZ5LeEIS1A2hs=; b=ONUl+PILRFmEThc+6RiHNu1ePJUDRxhSUqhdUDwVtqiHUM0iqGgPVRQxIU/bRqRJSy v91lmzEfhTv6zeVhtd03m7iutPWR6WnGHsc0ZvuFUDDjhxP1HDNE2q+Be3KBK2t+bvwe zL26NfiwwyaP22dqWWbheFOOrwPAVqu9vODVfdGlDCHk2eKKITGLA2Tzfa8G0LnrdND7 Rdg5v3y0GNmEFcFRGugUaQhKY2jpzE3kw1fXmfRv4c7XJytchtEXLA9MWmigzlF5VMx8 N4n2wPcK5+dYHL+mNbME7bXl+ZYYkjmL6C/A8Iw1UH5hJpkffrTt5ICjSTwA1NNrWX26 PCxA== X-Gm-Message-State: AOJu0YwsypsqlTvUx90VCtir3Qyc5LeJl1/fX0XNlQJ89kyJRcz3hkfn VfghXkjTpyenne4nNKwYqfGNpCrJMDaIzb7SqPBrueR7kkoKzgg2qHMA4lzRRjgGymmuwygnQKN WHw8M X-Gm-Gg: ASbGncsqPAvzINgnFTjLA4BBuTJiTTtXX0+eJVh0c/YRKNQ22q7zFZGTTU70lqZsKTC HYzf+QpDxstI3ZZKkjXgzNrXuFHtiUW8+HKg2FI4R7jIHUKV2Ww5Utj/8LMGFFYPI34P6B8l5/+ L8GZhCnrrFipDeF5AzrLRsG5IyEc+t22+TvaS8IjXPpbK0PNhSJ8iV7RvYGMn4E3kKBc1xPIqXP Jjw/F6wfWhP5r8bMZeNEHYfUODgU9qJuraJvyYUU2j3e1OvnBhwB4Na+NCZDlHYvAUStxQzZ5vU M0yJHV50YgfMUZUtSqlK7Q+iwIpwxyPGPED1y3oVXLlTnIe8cG1QJZRpZgZyMxjLpUaZ X-Google-Smtp-Source: AGHT+IGP43PWGmrE7psT6MXrxh+XXLSx++nBtTqW3Zd0Zyfz8u3MDnK4G0F3SHHYbSqZmyGd492Z2g== X-Received: by 2002:a5d:58d5:0:b0:3a5:8cc2:10aa with SMTP id ffacd0b85a97d-3a917603a95mr12757804f8f.32.1751389677919; Tue, 01 Jul 2025 10:07:57 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 36/43] hw/arm/virt: Rename cpu_post_init() -> post_cpus_gic_realized() Date: Tue, 1 Jul 2025 18:07:12 +0100 Message-ID: <20250701170720.4072660-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751389917395116600 From: Philippe Mathieu-Daud=C3=A9 QDev uses _post_init() during instance creation, before being realized. Since here both vCPUs and GIC are REALIZED, rename as virt_post_cpus_gic_realized() for clarity. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20250623121845.7214-21-philmd@linaro.org [PMM: also fixed up comment] Signed-off-by: Peter Maydell --- hw/arm/virt.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 30f91bcfb3c..3bcdf92e2ff 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2026,10 +2026,11 @@ static void finalize_gic_version(VirtMachineState *= vms) } =20 /* - * virt_cpu_post_init() must be called after the CPUs have - * been realized and the GIC has been created. + * virt_post_cpus_gic_realized() must be called after the CPUs and + * the GIC have both been realized. */ -static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem) +static void virt_post_cpus_gic_realized(VirtMachineState *vms, + MemoryRegion *sysmem) { int max_cpus =3D MACHINE(vms)->smp.max_cpus; bool aarch64, pmu, steal_time; @@ -2346,7 +2347,7 @@ static void machvirt_init(MachineState *machine) =20 create_gic(vms, sysmem); =20 - virt_cpu_post_init(vms, sysmem); + virt_post_cpus_gic_realized(vms, sysmem); =20 fdt_add_pmu_nodes(vms); =20 --=20 2.43.0 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1751390146; cv=none; d=zohomail.com; s=zohoarc; b=PNjYPoJ7dYUSXuNW4WNCIie13x3mNtTlrrjLTRCzse0wsy5Hu6zJLmStUH68PqyTKKVkZ46KFhnNhCGVri0fPEechY/zqjNnaoUtngaSGCX1dTkX+eIxMZpkBA7lB2AA/X+AsPcUAoES2E/6oqlCkItyvnf8WZsgTUZPdCsBAig= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751390146; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=6rHpAA90Bjb+Ii0ByCKVJS29gi/VuqiHc6GuPotvdhc=; b=KyLj49YOYLDMCBFAwQghZf8zlhpPSArXSPY3sqL4ZHzA4kwdRzxAxSmgnGtJeAh0b3pJcuP7oyPCBKWo7v9ZCQOUxYdVCWLBse1AUMstNED1q9B24MBACjnK8LZ6ahDsTqN2k0CfZ6xcv93G2RZ+d2Hm4p2HISAv6TIm1P7zO0A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1751390146202908.2788578919618; Tue, 1 Jul 2025 10:15:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uWeSj-0005mN-Rp; Tue, 01 Jul 2025 13:08:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uWeSh-0005kH-6k for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:08:03 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uWeSf-0003iY-5L for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:08:02 -0400 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-3a548a73ff2so5264928f8f.0 for ; Tue, 01 Jul 2025 10:08:00 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Tue, 01 Jul 2025 10:07:58 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 37/43] hw/arm/sbsa-ref: Tidy up use of RAMLIMIT_GB definition Date: Tue, 1 Jul 2025 18:07:13 +0100 Message-ID: <20250701170720.4072660-38-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751390148397116600 From: Philippe Mathieu-Daud=C3=A9 Define RAMLIMIT_BYTES using the TiB definition and display the error parsed with size_to_str(): $ qemu-system-aarch64-unsigned -M sbsa-ref -m 9T qemu-system-aarch64-unsigned: sbsa-ref: cannot model more than 8 TiB of R= AM Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20250623121845.7214-22-philmd@linaro.org Signed-off-by: Peter Maydell --- hw/arm/sbsa-ref.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index deae5cf9861..15c1ff4b140 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -19,6 +19,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/cutils.h" #include "qemu/datadir.h" #include "qapi/error.h" #include "qemu/error-report.h" @@ -53,8 +54,7 @@ #include "target/arm/cpu-qom.h" #include "target/arm/gtimer.h" =20 -#define RAMLIMIT_GB 8192 -#define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) +#define RAMLIMIT_BYTES (8 * TiB) =20 #define NUM_IRQS 256 #define NUM_SMMU_IRQS 4 @@ -756,7 +756,9 @@ static void sbsa_ref_init(MachineState *machine) sms->smp_cpus =3D smp_cpus; =20 if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) { - error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT= _GB); + char *size_str =3D size_to_str(RAMLIMIT_BYTES); + + error_report("sbsa-ref: cannot model more than %s of RAM", size_st= r); exit(1); } =20 --=20 2.43.0 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1751389873; cv=none; d=zohomail.com; s=zohoarc; b=U7qNDh2CoBTrCGle8Qxy0IVZINqWrO63ijK90GrpxRaFw95O57j6yoZna1ix/j+QjsJ+hY6Cx9zMWEc6v0XPywy79KH6gVt0pkPAqmqERI+YrBdeqKrI3H9NJI5mcOsSmSgSdsE4u9/MWjdXPLN6XeGwFEVhqw8QYK+m6lD6rfw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751389873; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a88c80bb28sm13475658f8f.43.2025.07.01.10.07.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 10:07:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751389680; x=1751994480; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=HBsbE/TrRmGaC5yb0jy251zZHsHyCp+NU1gxrZ4fEQc=; b=dk1faEvkJn0n191P5mUjvN3EtCG8SXBkPoKlfQYMPKQYfCGU9lTM2z4Dtx+FPYaMpy w80jkd3EDQDcpFhPsQZarraj/0IvqKqg+h19ImS3neytaBJ0/pgEhLEbk8ZEErXK34NB g1jbli9KBLTK6voyRVTSTfe4O5hQNbxtFqRvZpxX3MhOdl5f6G3Lc48XYlTuWalupnnh kUrHr7TEm9KgiL95HnnvAS881maolQ16zzEhP0G2I967RQWLMHiIYUiJXX8YJt3MR5VQ j2gcJiTe8r897Osqbm0N76eAkfd3pkyzlyTHw0HZOZ91Zpwj4mBuuZ+5q4XzNj/0xeSj UO1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751389680; x=1751994480; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HBsbE/TrRmGaC5yb0jy251zZHsHyCp+NU1gxrZ4fEQc=; b=hhpc2CP9wAqJ4KtO2xMpAoBgIbTkyKXggPo92+/o1+6dh1tj8Ybs69s1qv/cygZ+3/ 5BgN7E1fNg8zngqDgh3oz+8LkJmozhnACCG+V/n4blnkZdcPRbMUAyMt/3vbpbTmaiZ3 wXqB+9khAkyFYDYpDJtgHu8hWtUW9Ve1DoFenO9q6iE+4ci2UyBTfauMNidmL5Y3MAp3 7yUmlu4T2j6yOLMS2ZbW6qNljohiiEyhLj2V3UZ+mra1NknGjlio+Qx5zG3EZVI9IPD3 7BPyuBXr8AdnupGDG8S2/7W0s8Xa7ODJHRLNJ5n5Cddoo+vo/V3vQex92kLS1oR44Avn AQQg== X-Gm-Message-State: AOJu0YzCE9eQtw+PdEu/B9XUYcEEL1lYbYWMTbJF4BoqPP/c2MCKn4GH 3Rh3Fe0LcOMR6SSmGdlEPzLaSvSGZYY5ZKsy9EVR3j8QJXBc/8LJvHtWazySyYkP7w3OReh/Rsk +DqCm X-Gm-Gg: ASbGncvnimci7Q+CerRCagSS78635eMoY6WJEyRfDDWN89jSvor1eXXG/SVigrlfMF2 6lCPPfC1mY90bLKxgVw5rHMhQ5IWZY3o6l/FaEUQx2whXSHCNDuSps4o1ReSMCIfZkIJSLRxg7o MwvHP+x6bxq8WYw8prgDRFU2WlESKfgPnPUkXHIXGMk18S9kvWPyTm/c4xzyPl+N8FKCzin8jag 7vwphXtXEdgJWiidyS+0JliEAKdtq23QtffmGsDV8F9V6J3BIx9NRE0SY6W7KbBNz+Y9sffyyvP mACnPlYcNhZJUgfCwGCVD1EDtfr2LaavRDJjx8pZzia0uB2ziRZ/+IbLgrswoZX1pCtJ X-Google-Smtp-Source: AGHT+IGSZnTZogZAyPgZhEeHePSmiz0VLWq9qw/f0pkMc1JFKNcAJY5Y4w6IolKl/peXK2qaKfGfEQ== X-Received: by 2002:a05:6000:4a09:b0:3a4:f7dd:234b with SMTP id ffacd0b85a97d-3a8e842ffdbmr14608690f8f.0.1751389679806; Tue, 01 Jul 2025 10:07:59 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 38/43] tests/functional: Set sbsa-ref machine type in each test function Date: Tue, 1 Jul 2025 18:07:14 +0100 Message-ID: <20250701170720.4072660-39-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751389874427116600 From: Philippe Mathieu-Daud=C3=A9 fetch_firmware() is only about fetching firmware. Set the machine type and its default console in test_sbsaref_edk2_firmware(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Leif Lindholm Message-id: 20250623121845.7214-23-philmd@linaro.org Signed-off-by: Peter Maydell --- tests/functional/test_aarch64_sbsaref.py | 5 +++-- tests/functional/test_aarch64_sbsaref_alpine.py | 3 ++- tests/functional/test_aarch64_sbsaref_freebsd.py | 3 ++- 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/tests/functional/test_aarch64_sbsaref.py b/tests/functional/te= st_aarch64_sbsaref.py index e6a55aecfac..d3402f5080a 100755 --- a/tests/functional/test_aarch64_sbsaref.py +++ b/tests/functional/test_aarch64_sbsaref.py @@ -40,8 +40,6 @@ def fetch_firmware(test): with open(path, "ab+") as fd: fd.truncate(256 << 20) # Expand volumes to 256MiB =20 - test.set_machine('sbsa-ref') - test.vm.set_console() test.vm.add_args( "-drive", f"if=3Dpflash,file=3D{fs0_path},format=3Draw", "-drive", f"if=3Dpflash,file=3D{fs1_path},format=3Draw", @@ -68,8 +66,11 @@ class Aarch64SbsarefMachine(QemuSystemTest): =20 def test_sbsaref_edk2_firmware(self): =20 + self.set_machine('sbsa-ref') + fetch_firmware(self) =20 + self.vm.set_console() self.vm.add_args('-cpu', 'cortex-a57') self.vm.launch() =20 diff --git a/tests/functional/test_aarch64_sbsaref_alpine.py b/tests/functi= onal/test_aarch64_sbsaref_alpine.py index 6108ec65a54..87769993831 100755 --- a/tests/functional/test_aarch64_sbsaref_alpine.py +++ b/tests/functional/test_aarch64_sbsaref_alpine.py @@ -26,8 +26,9 @@ class Aarch64SbsarefAlpine(QemuSystemTest): # We only boot a whole OS for the current top level CPU and GIC # Other test profiles should use more minimal boots def boot_alpine_linux(self, cpu=3DNone): - fetch_firmware(self) + self.set_machine('sbsa-ref') =20 + fetch_firmware(self) iso_path =3D self.ASSET_ALPINE_ISO.fetch() =20 self.vm.set_console() diff --git a/tests/functional/test_aarch64_sbsaref_freebsd.py b/tests/funct= ional/test_aarch64_sbsaref_freebsd.py index 26dfc5878bb..3cddc082f3b 100755 --- a/tests/functional/test_aarch64_sbsaref_freebsd.py +++ b/tests/functional/test_aarch64_sbsaref_freebsd.py @@ -26,8 +26,9 @@ class Aarch64SbsarefFreeBSD(QemuSystemTest): # We only boot a whole OS for the current top level CPU and GIC # Other test profiles should use more minimal boots def boot_freebsd14(self, cpu=3DNone): - fetch_firmware(self) + self.set_machine('sbsa-ref') =20 + fetch_firmware(self) img_path =3D self.ASSET_FREEBSD_ISO.fetch() =20 self.vm.set_console() --=20 2.43.0 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1751389985; cv=none; d=zohomail.com; s=zohoarc; b=XayHF2NU1IcFoziofEji4qCLlPGOJXNqcWCQGb6RuVGayA+nsJm/+t0jQ4CvXRALQHMy6p4u/U+ibS91mDFZT1kjs+bJFyZqZfD0+nhhltctdnXfvt9Sy64JTpXyJpAFwyhrbL9+ClZ6+ihP+1UFD5Bde145edoFIlkrDEDTie4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751389985; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=EGJGSXijrkKuptWT9xhB3UrOoEMpHnMUKPvnMJKERYM=; b=eqpbD2XRKf8M7phbk/wvkXt18ni82y5qpr7lUyQJZUSwUQO1qmBW3bq1cpfTQcLfSuvkwxQ0PEerwGcfwikOwr3qkE8wZLT3q8472Hc4WrdOIFFKJiOZQwn3bRqgPDywA/eXupSlAx1WkigtbSU+F5rtyoQYipUwJ09Svl6qHcs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1751389985886164.99588200308324; Tue, 1 Jul 2025 10:13:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uWeSk-0005n4-CX; Tue, 01 Jul 2025 13:08:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uWeSi-0005lQ-GC for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:08:04 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uWeSg-0003jk-KW for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:08:04 -0400 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-3a54700a463so3623242f8f.1 for ; Tue, 01 Jul 2025 10:08:02 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a88c80bb28sm13475658f8f.43.2025.07.01.10.07.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 10:08:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751389681; x=1751994481; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=EGJGSXijrkKuptWT9xhB3UrOoEMpHnMUKPvnMJKERYM=; b=ClQNmybHexf+y5Xap7x/VITtLGkWk8N5mDNiK00qRpfVQg0ezUiafG2KaTS6tlT0vR ctblPPuLKutv59gtP6gDnglFtAvFbaxMBxDsoF34J2bVTARkQcZXvSduwhymCoHUEORI 1jRHgVSvKQ3auyk9mhLu94NTLUj3ikpBtfZrc5g8x7dnKqygGqUK4nhIYLf0R3FbBw8C M1INzQUECHl5Ocf5NweENW1bfYeXkmBhUu+TKyzj2k1jOJJLSGnCqjSXNx3C6ZtSSsu7 Z5wM0N65jDv3HtxoBGsGVI7bOd8rNLmlPLu8xT3hDPbgeJ5T5dk3LcCL8SSQzaMbKa+z LnCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751389681; x=1751994481; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EGJGSXijrkKuptWT9xhB3UrOoEMpHnMUKPvnMJKERYM=; b=R9M2acXHkegKa64n40cZRH3U4PGjsYKvvlve+XQ7Zgxn5XV7QS4cFWXHwSVqXIR37a 0ZgREYN+3pvN9nAEfLrYKVftXp9TZBdlrUcnsUrsrO2Vt/yltfN3tINbzPYoSQN0o9yf qUfseiJWpLPep4/iA1nLmpCDwZhDzEhIur+iWf8+BdctMfp6hqp3CnH+SQhF+wG1N2au ao/zVy2TE3onAlrWoeP7D0MHE+nkxn5FEsVhNBpKMKhIT9ILFzapa5FJL9IftRJjtTxF 9quctFgz4KflL+/N0xGquAWdBh6vnOMMEo9sNUI0aYa2mAwbJtN84KSJ+0F9PlXLfc/t DYxg== X-Gm-Message-State: AOJu0YzCSVX76wXhujjMZ0Ye4ctn/Bp7xZgUfL6xdz/6eSM17kYLm0mU EzNM7i3EJPImY25AnEiLsGeWQJPdNOFjMwgQl+vmgyMjarw5q9uh2m0oMT5+wif5wO5h6UbO9AS xzZUm X-Gm-Gg: ASbGncvW+KvTYHQiUJ23GqoNd6zXdhu9exvS42LtKkZeMpRtj+OVZTkWaeX+XHipcK+ o09jcIAldLDFjgp2jD1T18ytUMlTp5eoPr1JLIJFS2PNmol5D5EwF7IcFNuIKIaA4WvinXts4+7 2NJ6rcNIypHHjRWjy1mL6F/tIdcAInHQ182z+IRWfhMWTGDtb8y/8a3uZjMrKK2qesnQguRvJ+p LJ4f0CdJ1xHoKPpksmnBAaDSH+NhktsjiADhl025C+AG+CQl+krNOrzaRXjaEjIDxF+9y8VEKgp JP+Ai58vxLxNryHBo0DWh6Bqme/HiNmHtF8ev2daqdbEYV0pFvx02H01CWpVkyvBelcseShlJ0K ZxKw= X-Google-Smtp-Source: AGHT+IGteTB8Oar82/5wnE99Mnhrc7sz9iunpmpGaWEzwXNvQtLtUHOfS7IR1RdBq6whMlhGcH+UgQ== X-Received: by 2002:adf:ea10:0:b0:3a5:270e:7d3 with SMTP id ffacd0b85a97d-3af100ae56cmr3282079f8f.13.1751389680645; Tue, 01 Jul 2025 10:08:00 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 39/43] tests/functional: Restrict nested Aarch64 Xen test to TCG Date: Tue, 1 Jul 2025 18:07:15 +0100 Message-ID: <20250701170720.4072660-40-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751389988342116600 From: Philippe Mathieu-Daud=C3=A9 Currently QEMU only support accelerating EL0 and EL1, so features requiring EL2 (like virtualization) or EL3 must be emulated with TCG. On macOS this test fails: qemu-system-aarch64: mach-virt: HVF does not support providing Virtualiza= tion extensions to the guest CPU Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20250623121845.7214-24-philmd@linaro.org Signed-off-by: Peter Maydell --- tests/functional/test_aarch64_xen.py | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/functional/test_aarch64_xen.py b/tests/functional/test_a= arch64_xen.py index 339904221b0..261d796540d 100755 --- a/tests/functional/test_aarch64_xen.py +++ b/tests/functional/test_aarch64_xen.py @@ -33,6 +33,7 @@ def launch_xen(self, xen_path): """ Launch Xen with a dom0 guest kernel """ + self.require_accelerator("tcg") # virtualization=3Don self.set_machine('virt') self.cpu =3D "cortex-a57" self.kernel_path =3D self.ASSET_KERNEL.fetch() --=20 2.43.0 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1751389912; cv=none; d=zohomail.com; s=zohoarc; b=gFGUH7u2av6m1iQGsYCsX1qG9m9npKaXL+beRuMMpEtHGfHOw2IKZrXW8Wx8N81hiBf9lt1VD9N37+H64egA+yh8DH9a9fCConPaLHLhGzy8sGfrAs36z7k/HcWng0eFsXwiBQ+0P3re3nMK1tOaxNuDvvqxXdTBzX+ZRrfSn0k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751389912; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=KxWPsSs+27QX8v3jrIStt0DlCSv+fp9Zyr2gtQ2zORA=; b=BUYDjEGhnfZ1Gx2a3CIJ8S3NdtoENr0aGUL6GzcjYjTYJWPx4NhqZfGNkp53A9rJqgyCaszh3RjV28jlNNUnLCGnHAwF5fO/VZZUtUf1NemrnNi5N9VhsDQFQDFc7UdGY2mitVhUZsFIaAqyzeCk5/FaxipzPafGcT15tB2TIgo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1751389912005239.51520751768896; Tue, 1 Jul 2025 10:11:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uWeSo-0005rP-Ts; Tue, 01 Jul 2025 13:08:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uWeSj-0005mP-Sf for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:08:05 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uWeSh-0003kK-7Z for qemu-devel@nongnu.org; Tue, 01 Jul 2025 13:08:05 -0400 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-3a4f72cba73so4483663f8f.1 for ; Tue, 01 Jul 2025 10:08:02 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a88c80bb28sm13475658f8f.43.2025.07.01.10.08.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 10:08:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751389681; x=1751994481; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=KxWPsSs+27QX8v3jrIStt0DlCSv+fp9Zyr2gtQ2zORA=; b=fhpz7Jwrsu5+zyIqeiU0I2znLfvM1Kpj/86ubQzp7Aomx1dpbFX9Qan9neyrPHuZSv hxiVKVuqxMkmXcB/OTaAxpZt4CGatg4ugtsEGHrEQtkGbTrxhT4xNWt4gLOWXIlIPZKb /ZyIKkU8cd0xCh7gHxXHZo/RZhLpREgPiUtlFuLYwyOCfsO23gzztCoFHwVl/wKrxDyj f7JomEGNDhZoC73kfhyOBfs3fRkm3aiCClHsr1mBUxL6oko83lAvS9Y6BIix4Hd6XG29 Co7W/g461HJjqmEM5hHH+NFfr18Qq3gFd+8b9lFWVcK0v26nx3UaH/ZBkh7K84E7wXv7 LBIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751389681; x=1751994481; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KxWPsSs+27QX8v3jrIStt0DlCSv+fp9Zyr2gtQ2zORA=; b=ooMA9702mYjKzXA6G++SqANGZbKXhAdJ8KbHO9oIy3nVofU/tEU4q5PvaNaBf/ex9j ZjMg+5MQf9hOkvUDG9Spjois9dDSOoDT+O9DkGD0jm+k/6IKnnraPn5ObSBYqgw1reow 08wx5sgkuUF5K7h++eEuOUxwJ86rhKSsxZwPVaQYNvtH9m+a95t5glx6MygtJY0LYsHU fF2SOI+1y75Syd7f8mFbk4LgHtQ9iKRCkNS4Ywf8FPUlOcE3G426eBYWLdo9bOAz1Tnt lSNuA01ACGKnnqCoyQPvBD1IvvnL2PK+FYCrPg6j/f4RF7ju78pgl47iGlSGYjyOt4Ng D0sA== X-Gm-Message-State: AOJu0Yxcq27QeXBgnNJ5vqfE4SoNb9I6bs8r7WFGpLI34z9Jfh3KYp6Y fWCRa60Gr5exqNeKJONMlgffcqDHSKgpyTCTcDjplNkvwNkar0D3My7CYuVkhHFyLHP1qa0VMHs j2wZs X-Gm-Gg: ASbGncvRbKbavdcOmymp8Gqih74sz0dcNVSxL0/guUqWLjyNmJfuXDEGRSF7FTl/x2E hyLeo6KvtjMgFT6zJNzzy+8MNSdKubUf0Hlfn1kVl39pTHOjqff/N3TLmdXKVLlxRMpGce4VA+4 0aL4NcYfzHq/XzcTGkCstf47A9j+3XLmouwBSrWQKWoeAKhsE/42e8jcwUPC0V4fpngBemUtKuI V0z3wJDGAHR8Boxc6Y7ZBF0umV2XEAVpbFsTlQsCYs+HBWdHRjvnxTMjYiF5eQYcemd9WgzbJAB ZMa6NP4PO/XdbNDFaIwInpDRxHkNvsWzcdjHp93bSQRIFli4j5OVKWHww35IrbX3/dFh X-Google-Smtp-Source: AGHT+IGPziVZyr6NmYXTa6ceJM2mT0A2T4ru/RVIM22EqpWq/JB6oRMRrcdJBZDmvfVmqMZLpei7Xg== X-Received: by 2002:a05:6000:290f:b0:3a4:e624:4ec9 with SMTP id ffacd0b85a97d-3afa162b562mr3259577f8f.3.1751389681491; Tue, 01 Jul 2025 10:08:01 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 40/43] tests/functional: Require TCG to run Aarch64 imx8mp-evk test Date: Tue, 1 Jul 2025 18:07:16 +0100 Message-ID: <20250701170720.4072660-41-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751389913075116600 From: Philippe Mathieu-Daud=C3=A9 The imx8mp-evk machine can only run with the TCG accelerator. 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Tue, 01 Jul 2025 10:08:02 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 41/43] tests/functional: Add hvf_available() helper Date: Tue, 1 Jul 2025 18:07:17 +0100 Message-ID: <20250701170720.4072660-42-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751390389406116600 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Thomas Huth Message-id: 20250623121845.7214-26-philmd@linaro.org [PMM: tweaks to satisfy the python linter CI job] Signed-off-by: Peter Maydell --- python/qemu/utils/__init__.py | 8 +++++++- python/qemu/utils/accel.py | 9 +++++++++ tests/functional/qemu_test/testcase.py | 6 ++++-- 3 files changed, 20 insertions(+), 3 deletions(-) diff --git a/python/qemu/utils/__init__.py b/python/qemu/utils/__init__.py index 017cfdcda75..be5daa83634 100644 --- a/python/qemu/utils/__init__.py +++ b/python/qemu/utils/__init__.py @@ -23,13 +23,19 @@ from typing import Optional =20 # pylint: disable=3Dimport-error -from .accel import kvm_available, list_accel, tcg_available +from .accel import ( + hvf_available, + kvm_available, + list_accel, + tcg_available, +) =20 =20 __all__ =3D ( 'VerboseProcessError', 'add_visual_margin', 'get_info_usernet_hostfwd_port', + 'hvf_available', 'kvm_available', 'list_accel', 'tcg_available', diff --git a/python/qemu/utils/accel.py b/python/qemu/utils/accel.py index 386ff640ca8..f915b646692 100644 --- a/python/qemu/utils/accel.py +++ b/python/qemu/utils/accel.py @@ -82,3 +82,12 @@ def tcg_available(qemu_bin: str) -> bool: @param qemu_bin (str): path to the QEMU binary """ return 'tcg' in list_accel(qemu_bin) + + +def hvf_available(qemu_bin: str) -> bool: + """ + Check if HVF is available. + + @param qemu_bin (str): path to the QEMU binary + """ + return 'hvf' in list_accel(qemu_bin) diff --git a/tests/functional/qemu_test/testcase.py b/tests/functional/qemu= _test/testcase.py index 50c401b8c3c..2082c6fce43 100644 --- a/tests/functional/qemu_test/testcase.py +++ b/tests/functional/qemu_test/testcase.py @@ -23,7 +23,7 @@ import uuid =20 from qemu.machine import QEMUMachine -from qemu.utils import kvm_available, tcg_available +from qemu.utils import hvf_available, kvm_available, tcg_available =20 from .archive import archive_extract from .asset import Asset @@ -317,7 +317,9 @@ def require_accelerator(self, accelerator): :type accelerator: str """ checker =3D {'tcg': tcg_available, - 'kvm': kvm_available}.get(accelerator) + 'kvm': kvm_available, + 'hvf': hvf_available, + }.get(accelerator) if checker is None: self.skipTest("Don't know how to check for the presence " "of accelerator %s" % accelerator) --=20 2.43.0 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 01 Jul 2025 10:08:03 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 42/43] tests/functional: Expand Aarch64 SMMU tests to run on HVF accelerator Date: Tue, 1 Jul 2025 18:07:18 +0100 Message-ID: <20250701170720.4072660-43-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751390350559116600 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Thomas Huth Reviewed-by: Alex Benn=C3=A9e Message-id: 20250623121845.7214-27-philmd@linaro.org Signed-off-by: Peter Maydell --- tests/functional/test_aarch64_smmu.py | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/tests/functional/test_aarch64_smmu.py b/tests/functional/test_= aarch64_smmu.py index c65d0f28178..e0f4a922176 100755 --- a/tests/functional/test_aarch64_smmu.py +++ b/tests/functional/test_aarch64_smmu.py @@ -17,7 +17,7 @@ =20 from qemu_test import LinuxKernelTest, Asset, exec_command_and_wait_for_pa= ttern from qemu_test import BUILD_DIR -from qemu.utils import kvm_available +from qemu.utils import kvm_available, hvf_available =20 =20 class SMMU(LinuxKernelTest): @@ -45,11 +45,17 @@ def set_up_boot(self, path): self.vm.add_args('-device', 'virtio-net,netdev=3Dn1' + self.IOMMU_= ADDON) =20 def common_vm_setup(self, kernel, initrd, disk): - self.require_accelerator("kvm") + if hvf_available(self.qemu_bin): + accel =3D "hvf" + elif kvm_available(self.qemu_bin): + accel =3D "kvm" + else: + self.skipTest("Neither HVF nor KVM accelerator is available") + self.require_accelerator(accel) self.require_netdev('user') self.set_machine("virt") self.vm.add_args('-m', '1G') - self.vm.add_args("-accel", "kvm") + self.vm.add_args("-accel", accel) self.vm.add_args("-cpu", "host") self.vm.add_args("-machine", "iommu=3Dsmmuv3") self.vm.add_args("-d", "guest_errors") --=20 2.43.0 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a88c80bb28sm13475658f8f.43.2025.07.01.10.08.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 10:08:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751389685; x=1751994485; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=BLbP+hENQzPCP4H10W/ZiFi144I0pbRy1dph6k1wkAE=; b=qnWD9rWJbeQNM/juUekaH4z/g6N4ArvMrjgbjTQuZwfLrbpkWSYGGoctEIwOI0EGRv YeGHC+SgLZ2iAjxFmpN9Tam/+qsab6j2oFWycQIftIdLtEM0nXKKyBmNcnGr2TqJK26p pnAhBCW3x6ek4pRdCfLARtzYki1FhAkDUxppHICDBval4s3ItUAXSZVt6RSBkBuY1BTv x3p8TMtiUZtFe+b9ULNHTqSWNWGaGhiqDVGppYn0YnvfnovfudjVbh2tT9K6DkTztlwf I1phlFg1xXoIECKZjjcYpurQ80ywhPN/HvmTw6n5XQo7iJxlgPE3sFzbsh9kYNxEFgAy /09g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751389685; x=1751994485; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BLbP+hENQzPCP4H10W/ZiFi144I0pbRy1dph6k1wkAE=; b=Z+vpUf/V/JffyW5KTBZfDRRFcmjDc6ozxYYA03leKrwnvU6i85gMP4XYfLyflKd2gd G2RDSnVzWpakvqPjeQv0nVydoIhY+e/CuPmNLxVl7XyXBag1T0OjMDvKbrhblC2fbrgz GoZ6VTnlxz82KK8ATkfn9nujmoju0ewtPGGM0v8DAx+v6hnENz1Tzj9BSOsAGh3eGQ3c hRZN0JMi50wrjgZ15OgSOc4rZg1u+k2usRIJcj/CZdbV/0c4sJ64thbGgrz918jP5W/q ROqwtjyn+R6llI3sde8MTwzwbeRs19CjekHHyPyvrRdP78uZ5P3QJG/a8oCaqahQLlvA kEUQ== X-Gm-Message-State: AOJu0YxA86yjOH0bZe+lYPgkzmmXFicoPCR9Yjl7NyCkKRl4qkGvhsJo UjE+6lh7xvHe1Le40rolS6eSXVf1PlFb40OlF2FZY0wt5aCWaDa5h3tSk8J0xQQaLjgJom/KHm+ gPlGt X-Gm-Gg: ASbGncuOUPZXv1uNN9q1FxllnM23TY/VDM0ZEE0GBHjezdaA0VxNLTpcz0q93ujgtAI ZKI135kimjgrbHCwY8+hQlIUkFhNercFVKgE7oYvpNEiCQFilsS4xUgPzwFVLbzQ7n7+9yEyBKV mOB0bUZaPPOQhE5LKeh+D65mdr6yV/1ydSi6zAz9dpyU3zwVpgoV+aZNOHBw3sft/feDAInByxt fX4Pm9gbQ7Bw6Z4LX31+fYdxBufvx1Q0mz8rMvZn8daUsWBKy4i+h757vWWNllIlRUFFrTdj46b nWgcdP2CkFUS11++JKQAGCPWooQ18QiXoiGqeSmyvjy1Qsvs+T/D5eOJWSgVvIB+4xsp X-Google-Smtp-Source: AGHT+IG2n6sFi/V+Gzxippi+6k/c/sLTak68V7kLLXyrvTGc8+DUZZj5Gi5BhVAOE2FIg5jQJM2Nqw== X-Received: by 2002:a05:6000:1789:b0:3a4:dbdf:7154 with SMTP id ffacd0b85a97d-3a90be88de8mr16820277f8f.54.1751389684447; Tue, 01 Jul 2025 10:08:04 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 43/43] tests/functional: test device passthrough on aarch64 Date: Tue, 1 Jul 2025 18:07:19 +0100 Message-ID: <20250701170720.4072660-44-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250701170720.4072660-1-peter.maydell@linaro.org> References: <20250701170720.4072660-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751389958190116600 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier This test allows to document and exercise device passthrough, using a nested virtual machine setup. Two disks are generated and passed to the VM, and their content is compared to original images. Guest and nested guests commands are executed through two scripts, and init used in both system is configured to trigger a kernel panic in case any command fails. This is more reliable and readable than executing all commands through prompt injection and trying to guess what failed. Initially, this test was supposed to test smmuv3 nested emulation (combining both stages of translation), but I could not find any setup (kernel + vmm) able to do the passthrough correctly, despite several tries. Signed-off-by: Pierrick Bouvier Message-id: 20250627200222.5172-1-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- tests/functional/meson.build | 2 + .../test_aarch64_device_passthrough.py | 142 ++++++++++++++++++ 2 files changed, 144 insertions(+) create mode 100755 tests/functional/test_aarch64_device_passthrough.py diff --git a/tests/functional/meson.build b/tests/functional/meson.build index e9f19d54a27..85158562a2f 100644 --- a/tests/functional/meson.build +++ b/tests/functional/meson.build @@ -13,6 +13,7 @@ endif test_timeouts =3D { 'aarch64_aspeed_ast2700' : 600, 'aarch64_aspeed_ast2700fc' : 600, + 'aarch64_device_passthrough' : 720, 'aarch64_imx8mp_evk' : 240, 'aarch64_raspi4' : 480, 'aarch64_reverse_debug' : 180, @@ -83,6 +84,7 @@ tests_aarch64_system_quick =3D [ tests_aarch64_system_thorough =3D [ 'aarch64_aspeed_ast2700', 'aarch64_aspeed_ast2700fc', + 'aarch64_device_passthrough', 'aarch64_imx8mp_evk', 'aarch64_raspi3', 'aarch64_raspi4', diff --git a/tests/functional/test_aarch64_device_passthrough.py b/tests/fu= nctional/test_aarch64_device_passthrough.py new file mode 100755 index 00000000000..1f3f158a9ff --- /dev/null +++ b/tests/functional/test_aarch64_device_passthrough.py @@ -0,0 +1,142 @@ +#!/usr/bin/env python3 +# +# Boots a nested guest and compare content of a device (passthrough) to a +# reference image. Both vfio group and iommufd passthrough methods are tes= ted. +# +# Copyright (c) 2025 Linaro Ltd. +# +# Author: Pierrick Bouvier +# +# SPDX-License-Identifier: GPL-2.0-or-later + +import os + +from qemu_test import QemuSystemTest, Asset +from qemu_test import exec_command, wait_for_console_pattern +from qemu_test import exec_command_and_wait_for_pattern +from random import randbytes + +guest_script =3D ''' +#!/usr/bin/env bash + +set -euo pipefail +set -x + +# find disks from nvme serial +dev_vfio=3D$(lsblk --nvme | grep vfio | cut -f 1 -d ' ') +dev_iommufd=3D$(lsblk --nvme | grep iommufd | cut -f 1 -d ' ') +pci_vfio=3D$(basename $(readlink -f /sys/block/$dev_vfio/../../../)) +pci_iommufd=3D$(basename $(readlink -f /sys/block/$dev_iommufd/../../../)) + +# bind disks to vfio +for p in "$pci_vfio" "$pci_iommufd"; do + if [ "$(cat /sys/bus/pci/devices/$p/driver_override)" =3D=3D vfio-pci = ]; then + continue + fi + echo $p > /sys/bus/pci/drivers/nvme/unbind + echo vfio-pci > /sys/bus/pci/devices/$p/driver_override + echo $p > /sys/bus/pci/drivers/vfio-pci/bind +done + +# boot nested guest and execute /host/nested_guest.sh +# one disk is passed through vfio group, the other, through iommufd +qemu-system-aarch64 \ +-M virt \ +-display none \ +-serial stdio \ +-cpu host \ +-enable-kvm \ +-m 1G \ +-kernel /host/Image.gz \ +-drive format=3Draw,file=3D/host/guest.ext4,if=3Dvirtio \ +-append "root=3D/dev/vda init=3D/init -- bash /host/nested_guest.sh" \ +-virtfs local,path=3D/host,mount_tag=3Dhost,security_model=3Dmapped,readon= ly=3Doff \ +-device vfio-pci,host=3D$pci_vfio \ +-object iommufd,id=3Diommufd0 \ +-device vfio-pci,host=3D$pci_iommufd,iommufd=3Diommufd0 +''' + +nested_guest_script =3D ''' +#!/usr/bin/env bash + +set -euo pipefail +set -x + +image_vfio=3D/host/disk_vfio +image_iommufd=3D/host/disk_iommufd + +dev_vfio=3D$(lsblk --nvme | grep vfio | cut -f 1 -d ' ') +dev_iommufd=3D$(lsblk --nvme | grep iommufd | cut -f 1 -d ' ') + +# compare if devices are identical to original images +diff $image_vfio /dev/$dev_vfio +diff $image_iommufd /dev/$dev_iommufd + +echo device_passthrough_test_ok +''' + +class Aarch64DevicePassthrough(QemuSystemTest): + + # https://github.com/pbo-linaro/qemu-linux-stack + # + # Linux kernel is compiled with defconfig + + # IOMMUFD + VFIO_DEVICE_CDEV + ARM_SMMU_V3_IOMMUFD + # https://docs.kernel.org/driver-api/vfio.html#vfio-device-cde + ASSET_DEVICE_PASSTHROUGH_STACK =3D Asset( + ('https://fileserver.linaro.org/s/fx5DXxBYme8dw2G/' + 'download/device_passthrough.tar.xz'), + '812750b664d61c2986f2b149939ae28cafbd60d53e9c7e4b16e97143845e196d= ') + + # This tests the device passthrough implementation, by booting a VM + # supporting it with two nvme disks attached, and launching a nested VM + # reading their content. + def test_aarch64_device_passthrough(self): + self.set_machine('virt') + self.require_accelerator('tcg') + + self.vm.set_console() + + stack_path_tar_gz =3D self.ASSET_DEVICE_PASSTHROUGH_STACK.fetch() + self.archive_extract(stack_path_tar_gz, format=3D"tar") + + stack =3D self.scratch_file('out') + kernel =3D os.path.join(stack, 'Image.gz') + rootfs_host =3D os.path.join(stack, 'host.ext4') + disk_vfio =3D os.path.join(stack, 'disk_vfio') + disk_iommufd =3D os.path.join(stack, 'disk_iommufd') + guest_cmd =3D os.path.join(stack, 'guest.sh') + nested_guest_cmd =3D os.path.join(stack, 'nested_guest.sh') + # we generate two random disks + with open(disk_vfio, "wb") as d: d.write(randbytes(512)) + with open(disk_iommufd, "wb") as d: d.write(randbytes(1024)) + with open(guest_cmd, 'w') as s: s.write(guest_script) + with open(nested_guest_cmd, 'w') as s: s.write(nested_guest_script) + + self.vm.add_args('-cpu', 'max') + self.vm.add_args('-m', '2G') + self.vm.add_args('-M', 'virt,' + 'virtualization=3Don,' + 'gic-version=3Dmax,' + 'iommu=3Dsmmuv3') + self.vm.add_args('-kernel', kernel) + self.vm.add_args('-drive', f'format=3Draw,file=3D{rootfs_host}') + self.vm.add_args('-drive', + f'file=3D{disk_vfio},if=3Dnone,id=3Dvfio,format= =3Draw') + self.vm.add_args('-device', 'nvme,serial=3Dvfio,drive=3Dvfio') + self.vm.add_args('-drive', + f'file=3D{disk_iommufd},if=3Dnone,id=3Diommufd,fo= rmat=3Draw') + self.vm.add_args('-device', 'nvme,serial=3Diommufd,drive=3Diommufd= ') + self.vm.add_args('-virtfs', + f'local,path=3D{stack}/,mount_tag=3Dhost,' + 'security_model=3Dmapped,readonly=3Doff') + # boot and execute guest script + # init will trigger a kernel panic if script fails + self.vm.add_args('-append', + 'root=3D/dev/vda init=3D/init -- bash /host/guest= .sh') + + self.vm.launch() + wait_for_console_pattern(self, 'device_passthrough_test_ok', + failure_message=3D'Kernel panic') + +if __name__ =3D=3D '__main__': + QemuSystemTest.main() --=20 2.43.0