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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a88c7ec6aesm13453631f8f.5.2025.07.01.07.42.02 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 01 Jul 2025 07:42:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751380924; x=1751985724; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LFRxRvBg/Kw+lCEJUMnsPGlqNMegEysmKneUwCu7PxI=; b=t64ScGOKqx7l/2Z3n6TxcfqOIWjiaUOEVOeCw611W05tYQn1y9MnbiRbX/NjZ8V0GX UDld39GOOf5BUDJvyVH9KLnddpUMfxPKOTkKYw7jlRGCc8nw4ekhqMc9JtQm7LQpt+8N nuqZ1hejEC+KY2JYKwMRYDhRStuggxAu/kP7+fv/TQvFZ8e9VDGsiADQ4pZj8bnsLAZn rle1whYJMRAR06iv9oVABKYWp4hyiN4XL1BsZRjutcMM9Fd47BI1p7evwQ2PZUbKJCHO VOaP9shzzQU7BoGyDpR+P4UaIxY9mNs7WbeWT3L5dsdeQP1BgblL7xaU/url+PkPcC1w ldKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751380925; x=1751985725; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LFRxRvBg/Kw+lCEJUMnsPGlqNMegEysmKneUwCu7PxI=; b=oS04UYgtfRv/gDKEI7FElV2bJI8BVRE2kDHzydxmBX+NFywZBkn/DjZIDbZpuyqEaD d5EA0xgsWCp5m5iW0iHZfqUzj/t9ukS/KrQz+/vFgC/6sJwPmBPcK27tp5icsG1Nd29+ gwMCovoXUNZtx0FKFiuLScB/+IUx4DhQaOYP3o8RDWDmanlYlzrywbQzEODmMpKuIXLV lNDPkpKfyVGlbOjvgj0JRrR88Fh6/renLP2ktXd+UDcWw2Txt1NWv4up9ezcUyhJOMUV 25UMJWPEDXvBHWCPtb21IEmgz01IJiSiFxrd7PgBtnbaDDbQV+J0VD4NEYOdXuTKP6rd RYXg== X-Gm-Message-State: AOJu0Ywvb8swZuuy5aX8iJWGMS+1QF8XezBaS2+5M2xYvWDFTOfi2bpX w2WKg0E+qEKa/37bt8O9wNQxPhcAPgQCtxnKxbQyeApybuWybOKR0Mh8EmPyQHZrcPWQ8Ux6nmt miqG9 X-Gm-Gg: ASbGncvVyz/UlWUlTQl6N6xN8yVQ++xDG9GK4KKGQ8+6RZz/8UGeF4u8nxyDeqCXK1D 6EEYwrcs4mXL/OzJzJq0LcOy7yGP0x8WIIZxQwPGaiMoKBqL/VomGneqdXO/WDD+W4cmQThFI22 QMvrx1cukt27iFbalJpHMi6IlZv9zLg/dm6O2VJGMbGB+Ci7AS3sg0kfY5zrjD5vUSgoufFCvNW qsx7xkdHF7Ou1UHE+DK9rxGBXGHW8m2wluTx07GeEbGNSaZ5Lj2+aRWeBxLYmCIGYI9Kk6CJpUm rbIxfVaWM3ik8+t1lSlKTzD0a/P6I+NN8H87SgfLYtWWNn8/nSVakbhpS4CV2D6BQzqwE83XdBm cFen9Cp5akdtV0jHoWm2JTxvZspC/zYEpKILM X-Google-Smtp-Source: AGHT+IF93A9KwT/lUdcnOGKDkHe1rS81T1pd/gHS1KwzdA1SIql09KPq0erhR6pRIH+B1EWZ+HdpYg== X-Received: by 2002:a5d:5849:0:b0:3a5:8934:4940 with SMTP id ffacd0b85a97d-3a8feb70269mr15510902f8f.50.1751380924437; Tue, 01 Jul 2025 07:42:04 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Pierrick Bouvier , Julian Armistead , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 19/68] accel: Move cpu_common_[un]realize() declarations to AccelOpsClass Date: Tue, 1 Jul 2025 16:39:27 +0200 Message-ID: <20250701144017.43487-20-philmd@linaro.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250701144017.43487-1-philmd@linaro.org> References: <20250701144017.43487-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751381370658116600 AccelClass is for methods dealing with AccelState. When dealing with vCPUs, we want AccelOpsClass. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/qemu/accel.h | 2 -- include/system/accel-ops.h | 2 ++ accel/accel-common.c | 10 ++++++---- accel/tcg/tcg-accel-ops.c | 3 +++ accel/tcg/tcg-all.c | 2 -- 5 files changed, 11 insertions(+), 8 deletions(-) diff --git a/include/qemu/accel.h b/include/qemu/accel.h index 3c6350d6d63..518c99ab643 100644 --- a/include/qemu/accel.h +++ b/include/qemu/accel.h @@ -41,8 +41,6 @@ typedef struct AccelClass { AccelOpsClass *ops; =20 int (*init_machine)(AccelState *as, MachineState *ms); - bool (*cpu_common_realize)(CPUState *cpu, Error **errp); - void (*cpu_common_unrealize)(CPUState *cpu); =20 /* system related hooks */ void (*setup_post)(AccelState *as); diff --git a/include/system/accel-ops.h b/include/system/accel-ops.h index d854b84a66a..fb199dc78f0 100644 --- a/include/system/accel-ops.h +++ b/include/system/accel-ops.h @@ -34,6 +34,8 @@ struct AccelOpsClass { /* initialization function called when accel is chosen */ void (*ops_init)(AccelClass *ac); =20 + bool (*cpu_common_realize)(CPUState *cpu, Error **errp); + void (*cpu_common_unrealize)(CPUState *cpu); bool (*cpu_target_realize)(CPUState *cpu, Error **errp); void (*cpu_reset_hold)(CPUState *cpu); =20 diff --git a/accel/accel-common.c b/accel/accel-common.c index 1d04610f55e..d1a5f3ca3df 100644 --- a/accel/accel-common.c +++ b/accel/accel-common.c @@ -102,10 +102,12 @@ bool accel_cpu_common_realize(CPUState *cpu, Error **= errp) } =20 /* generic realization */ - if (acc->cpu_common_realize && !acc->cpu_common_realize(cpu, errp)) { + if (acc->ops->cpu_common_realize + && !acc->ops->cpu_common_realize(cpu, errp)) { return false; } - if (acc->ops->cpu_target_realize && !acc->ops->cpu_target_realize(cpu,= errp)) { + if (acc->ops->cpu_target_realize + && !acc->ops->cpu_target_realize(cpu, errp)) { return false; } =20 @@ -118,8 +120,8 @@ void accel_cpu_common_unrealize(CPUState *cpu) AccelClass *acc =3D ACCEL_GET_CLASS(accel); =20 /* generic unrealization */ - if (acc->cpu_common_unrealize) { - acc->cpu_common_unrealize(cpu); + if (acc->ops->cpu_common_unrealize) { + acc->ops->cpu_common_unrealize(cpu); } } =20 diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 07b1ec4ea50..95ff451c148 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -46,6 +46,7 @@ #include "tcg-accel-ops-mttcg.h" #include "tcg-accel-ops-rr.h" #include "tcg-accel-ops-icount.h" +#include "internal-common.h" =20 /* common functionality among all TCG variants */ =20 @@ -212,6 +213,8 @@ static void tcg_accel_ops_init(AccelClass *ac) } } =20 + ops->cpu_common_realize =3D tcg_exec_realizefn; + ops->cpu_common_unrealize =3D tcg_exec_unrealizefn; ops->cpu_reset_hold =3D tcg_cpu_reset_hold; ops->insert_breakpoint =3D tcg_insert_breakpoint; ops->remove_breakpoint =3D tcg_remove_breakpoint; diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index 93972bc0919..ae83ca0bd10 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -244,8 +244,6 @@ static void tcg_accel_class_init(ObjectClass *oc, const= void *data) AccelClass *ac =3D ACCEL_CLASS(oc); ac->name =3D "tcg"; ac->init_machine =3D tcg_init_machine; - ac->cpu_common_realize =3D tcg_exec_realizefn; - ac->cpu_common_unrealize =3D tcg_exec_unrealizefn; ac->allowed =3D &tcg_allowed; ac->supports_guest_debug =3D tcg_supports_guest_debug; ac->gdbstub_supported_sstep_flags =3D tcg_gdbstub_supported_sstep_flag= s; --=20 2.49.0