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([179.93.20.232]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7d45a7b35edsm203807785a.13.2025.06.30.06.22.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jun 2025 06:22:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1751290473; x=1751895273; darn=nongnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=BJHmyagZgSRthH9fu6ABDOGhNEkejt6dd0IXbVCsbQo=; b=V8yGCdr11XNig2/np5k5G2E7YY5ZlonS3OZMikYz/Z8c5efHBkN+YtxyDQj6gZUcPZ eLoC26tBKDSqEEgD2uXZyZp5kc0tE2+Yxomt7FXQPEu36DTRO9Dq033iJntMZSpupg+/ a5bXqR4j5Hsw3LnxxeJ4P6O42anO0kFUxPpJlpaCUYjJw0Asid2Yw3HOeWbubsQb6zFZ t7TZ1f/SzTz64D8eHYAQw03+imAVXOhOXsSSUERLLxwEOlaKgmMfGPgH1HtyN1/yqsFN 8G1APNSfsbCbNNd2E6Zi9sGHLGWxup9wDDdvrjiL7/OxHSldHyuBRzeUiYhNOWYwgiGv +2eA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751290473; x=1751895273; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=BJHmyagZgSRthH9fu6ABDOGhNEkejt6dd0IXbVCsbQo=; b=sGsEHXigerqX/8kGMqX6W6Z+s64p3nx+X/Lk2TpYeE5GhlanwTqf9LzXYZddF7tcd8 MbVYG2AJvqThHztF7SVlUVPm/VyvL3iducCoDFLRLWvlgWRUofLD1qrylMFDlTQnDjEc d/jgpHtUSeW5F5RjwDdOLWiJbCtfGJ2SWHcL9KAJCetH31QkL6/03Uool/IG7K+vTvcX EfjVqT+LxwWcHnsvifuuSnuSFWSsxDdmGKFgBMhCw+UMBvUEYRESY43nqBNu6/j70wZz ENMbrUh1/23A/hYY5pM9IMx++hJ+1z8bfsD6/2KP13uKuIYqDJOOtnMNWMyD6Aypzf1i b6TA== X-Gm-Message-State: AOJu0YywyKUaM/QhvtbndJyq8oSrxyO7hbtnOgsn5o34M2KOna6xXpNo 0Ip6b0SK40Y9+3xMLr+o1J5dCpy1S2A7SYmRvx5fhvNrM48OuQP5fdskYv02VUFC3aU3/ot2Jph 4kMGt X-Gm-Gg: ASbGnctRylRjyzFY3YGzvL0VnlA6UtnqnOZUl9LbOuj8mqga2VRBGz/3SoLXfClO7bE 3bWecOocQ0WZogl/kdysx0TpEFZgV2WicX9fQoP6Nlm78zLBK+KKFjnaUd1M7JvnOU7mjHcCwAN +5XGzmmVVyoFaYbjX177GuTVrPgyBo6/RAEvCKvsnQ2pvi7TPes+AMgIZtD+cuzpDcQ2GluE8gs 9THzKDowhuffIpP72HHw3Fm7DXG1x2crItnVULj4ze5Rl9XihIq03JbY9L+m0nhXWjaFdSRvwwl WUDe9PuKQG6ksx9gJ8vNpFNy95hBGOB7pM6vzCQj12nj7rhsqDTh9ePZKefNriQ= X-Google-Smtp-Source: AGHT+IF/rkADL2Gvk3VHHG/Fl4omjLMNoohJZT5PxXM5S+otftNQYDBLH3OsM85JKpPCZVyEMh7YOg== X-Received: by 2002:a05:620a:3f85:b0:7d2:265:c2c1 with SMTP id af79cd13be357-7d443969610mr2056103485a.27.1751289755138; Mon, 30 Jun 2025 06:22:35 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@dabbelt.com, Daniel Henrique Barboza , "Dr. David Alan Gilbert" , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH] hmp-cmds-target, target/riscv: add 'info register' Date: Mon, 30 Jun 2025 10:22:28 -0300 Message-ID: <20250630132228.1276838-1-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.49.0 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::729; envelope-from=dbarboza@ventanamicro.com; helo=mail-qk1-x729.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1751290544257116600 The RISC-V target has *a lot* of CPU registers, with more registers being added along the way when new extensions are added. In this world, 'info registers' will throw a wall of text that can be annoying to deal with when the user wants to verify the value of just a couple of registers. Add a new 'info register' HMP command that prints a specific register. The semantics, and implementation, is similar to what 'info registers' already does, i.e. '-a' will print a register for all VCPUs and it's possible to print a reg for a specific VCPU. A RISC-V implementation is included via riscv_cpu_dump_register(). Here's an example: Welcome to Buildroot buildroot login: QEMU 10.0.50 monitor - type 'help' for more information (qemu) info register mstatus CPU#0 mstatus 0000000a000000a0 (qemu) info register mstatus -a CPU#0 mstatus 0000000a000000a0 CPU#1 mstatus 0000000a000000a0 (qemu) The API is introduced as TARGET_RISCV only. Cc: Dr. David Alan Gilbert Cc: Marcel Apfelbaum Cc: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Daniel Henrique Barboza --- hmp-commands-info.hx | 17 +++++++++++++ hw/core/cpu-common.c | 8 ++++++ include/hw/core/cpu.h | 11 +++++++++ include/monitor/hmp-target.h | 1 + monitor/hmp-cmds-target.c | 30 ++++++++++++++++++++++ target/riscv/cpu.c | 48 ++++++++++++++++++++++++++++++++++++ 6 files changed, 115 insertions(+) diff --git a/hmp-commands-info.hx b/hmp-commands-info.hx index 639a450ee5..f3561e4a02 100644 --- a/hmp-commands-info.hx +++ b/hmp-commands-info.hx @@ -113,6 +113,23 @@ SRST Show the cpu registers. ERST =20 +#if defined(TARGET_RISCV) + { + .name =3D "register", + .args_type =3D "register:s,cpustate_all:-a,vcpu:i?", + .params =3D "[register|-a|vcpu]", + .help =3D "show a cpu register (-a: show the register value = for all cpus;" + " vcpu: specific vCPU to query; show the current CPU= 's register if" + " no vcpu is specified)", + .cmd =3D hmp_info_register, + }, + +SRST + ``info register`` + Show a cpu register. +ERST +#endif + #if defined(TARGET_I386) { .name =3D "lapic", diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index 39e674aca2..9c65ce1537 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -108,6 +108,14 @@ void cpu_dump_state(CPUState *cpu, FILE *f, int flags) } } =20 +void cpu_dump_register(CPUState *cpu, const char *reg, FILE *f) +{ + if (cpu->cc->dump_register) { + cpu_synchronize_state(cpu); + cpu->cc->dump_register(cpu, reg, f); + } +} + void cpu_reset(CPUState *cpu) { device_cold_reset(DEVICE(cpu)); diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 33296a1c08..b9ddce22bd 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -160,6 +160,7 @@ struct CPUClass { int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, size_t len, bool is_write); void (*dump_state)(CPUState *cpu, FILE *, int flags); + void (*dump_register)(CPUState *cpu, const char *reg, FILE *); void (*query_cpu_fast)(CPUState *cpu, CpuInfoFast *value); int64_t (*get_arch_id)(CPUState *cpu); void (*set_pc)(CPUState *cpu, vaddr value); @@ -693,6 +694,16 @@ enum CPUDumpFlags { */ void cpu_dump_state(CPUState *cpu, FILE *f, int flags); =20 +/** + * cpu_dump_register: + * @cpu: The CPU whose register state is to be dumped. + * @reg: CPU register name to be dumped. + * @f: If non-null, dump to this stream, else to current print sink. + * + * Dumps CPU register state. + */ +void cpu_dump_register(CPUState *cpu, const char *reg, FILE *f); + /** * cpu_get_phys_page_attrs_debug: * @cpu: The CPU to obtain the physical page address for. diff --git a/include/monitor/hmp-target.h b/include/monitor/hmp-target.h index b679aaebbf..da9d690f89 100644 --- a/include/monitor/hmp-target.h +++ b/include/monitor/hmp-target.h @@ -57,6 +57,7 @@ void hmp_info_via(Monitor *mon, const QDict *qdict); void hmp_memory_dump(Monitor *mon, const QDict *qdict); void hmp_physical_memory_dump(Monitor *mon, const QDict *qdict); void hmp_info_registers(Monitor *mon, const QDict *qdict); +void hmp_info_register(Monitor *mon, const QDict *qdict); void hmp_gva2gpa(Monitor *mon, const QDict *qdict); void hmp_gpa2hva(Monitor *mon, const QDict *qdict); void hmp_gpa2hpa(Monitor *mon, const QDict *qdict); diff --git a/monitor/hmp-cmds-target.c b/monitor/hmp-cmds-target.c index 8eaf70d9c9..43f509aa60 100644 --- a/monitor/hmp-cmds-target.c +++ b/monitor/hmp-cmds-target.c @@ -121,6 +121,36 @@ void hmp_info_registers(Monitor *mon, const QDict *qdi= ct) } } =20 +/* + * Based on hmp_info_registers(). + */ +void hmp_info_register(Monitor *mon, const QDict *qdict) +{ + const char *reg =3D qdict_get_try_str(qdict, "register"); + bool all_cpus =3D qdict_get_try_bool(qdict, "cpustate_all", false); + int vcpu =3D qdict_get_try_int(qdict, "vcpu", -1); + CPUState *cs; + + if (all_cpus) { + CPU_FOREACH(cs) { + cpu_dump_register(cs, reg, NULL); + } + } else { + cs =3D vcpu >=3D 0 ? qemu_get_cpu(vcpu) : mon_get_cpu(mon); + + if (!cs) { + if (vcpu >=3D 0) { + monitor_printf(mon, "CPU#%d not available\n", vcpu); + } else { + monitor_printf(mon, "No CPU available\n"); + } + return; + } + + cpu_dump_register(cs, reg, NULL); + } +} + static void memory_dump(Monitor *mon, int count, int format, int wsize, hwaddr addr, int is_physical) { diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e3f8ecef68..8b3edf7b23 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -640,6 +640,53 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f= , int flags) } } =20 +static void riscv_cpu_dump_register(CPUState *cs, const char *reg, FILE *f) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + bool match_found =3D false; + int i; + + for (i =3D 0; i < ARRAY_SIZE(csr_ops); i++) { + RISCVException res; + target_ulong val =3D 0; + int csrno =3D i; + + /* + * Early skip when possible since we're going + * through a lot of NULL entries. + */ + if (csr_ops[csrno].predicate =3D=3D NULL) { + continue; + } + + /* + * We're doing partial register name matching, + * e.g. 'mhpm' will match all registers that + * starts with 'mhpm'. + */ + if (strncasecmp(csr_ops[csrno].name, reg, strlen(reg)) !=3D 0) { + continue; + } + + res =3D riscv_csrrw_debug(env, csrno, &val, 0, 0); + + /* + * Rely on the smode, hmode, etc, predicates within csr.c + * to do the filtering of the registers that are present. + */ + if (res =3D=3D RISCV_EXCP_NONE) { + if (!match_found) { + match_found =3D true; + qemu_fprintf(f, "\nCPU#%d\n", cs->cpu_index); + } + + qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", + csr_ops[csrno].name, val); + } + } +} + static void riscv_cpu_set_pc(CPUState *cs, vaddr value) { RISCVCPU *cpu =3D RISCV_CPU(cs); @@ -2690,6 +2737,7 @@ static void riscv_cpu_common_class_init(ObjectClass *= c, const void *data) =20 cc->class_by_name =3D riscv_cpu_class_by_name; cc->dump_state =3D riscv_cpu_dump_state; + cc->dump_register =3D riscv_cpu_dump_register; cc->set_pc =3D riscv_cpu_set_pc; cc->get_pc =3D riscv_cpu_get_pc; cc->gdb_read_register =3D riscv_cpu_gdb_read_register; --=20 2.49.0