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Mon, 30 Jun 2025 04:13:52 -0400 Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jun 2025 01:13:43 -0700 Received: from lxy-clx-4s.sh.intel.com ([10.239.48.52]) by orviesa010.jf.intel.com with ESMTP; 30 Jun 2025 01:13:41 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1751271230; x=1782807230; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wbnYOcHpb08DaNDk4xqwBS52v0jf+Fk+vZfKyddt4bk=; b=jMcgLZE5hLx3jKteij4dhAxaOhqHmyRPd0QjcLHEBKjFjJhuktBO3WuG z/CRSYg0XnzmeDvdjXazKukS/nltDboSjdJ8WG91vBoBpxhg/1Yy8PHHo WKHbkihIqgMD2TCmsfgssAewKMHX6bWrKam8xkpeGm2VnVq6YbvOFUNrf MIDcKQ/37QlSYwhbElXKWHEeTm35Fc5GsCycbi32ioGBUCSWVPLllFZQQ pX/BJ+XNRdXMt9VsZcxV3mJNNAGQjxPAEMG/HG5HZmc4uG2GY+jMQj12h gC0WTwP54+12KRMlTjsROdMdW8h9+gYn+WaOmwOM5+yD14yobNlkGh89w A==; X-CSE-ConnectionGUID: kzNr7SKRT1iL6ykjtFX4dw== X-CSE-MsgGUID: dvPhy3c7SFiE0DPXUeL7WA== X-IronPort-AV: E=McAfee;i="6800,10657,11479"; a="53637410" X-IronPort-AV: E=Sophos;i="6.16,277,1744095600"; d="scan'208";a="53637410" X-CSE-ConnectionGUID: MNl0pe2VTpy75SF2gQiotg== X-CSE-MsgGUID: NZNABDqURWixCRQd3azYkw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,277,1744095600"; d="scan'208";a="152777301" From: Xiaoyao Li To: Paolo Bonzini Cc: Zhao Liu , Marcelo Tosatti , Richard Henderson , qemu-devel@nongnu.org, xiaoyao.li@intel.com Subject: [PATCH 4/4] i386/cpu: Unify family, model and stepping calculation for x86 CPU Date: Mon, 30 Jun 2025 16:06:10 +0800 Message-ID: <20250630080610.3151956-5-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250630080610.3151956-1-xiaoyao.li@intel.com> References: <20250630080610.3151956-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.15; envelope-from=xiaoyao.li@intel.com; helo=mgamail.intel.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.999, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1751271287778116600 Content-Type: text/plain; charset="utf-8" There are multiple places where CPUID family/model/stepping info are retrieved from env->cpuid_version. Besides, the calculation of family and model inside host_cpu_vendor_fms() doesn't comply to what Intel and AMD define. For family, both Intel and AMD define that Extended Family ID needs to be counted only when (base) Family is 0xF. For model, Intel counts Extended Model when (base) Family is 0x6 or 0xF, while AMD counts EXtended MOdel when (base) Family is 0xF. Introduce generic helper functions to get family, model and stepping from the EAX value of CPUID leaf 1, with the correct calculation formula. Signed-off-by: Xiaoyao Li --- Note, for the calculation of model, it uses the same algorithm as Linux kernel that counts Extended model when (base) Family is >=3D 6. To me, this has the assumption that AMD always has a (base) Family of 0xF and Intel doens't have processor with (base) Family between (0x6, 0xF). I'm not sure about the rule on Zhaoxin and Hygon so that not sure if the contidition of base Family >=3D 6 works for them or not. For Zhaoxin, there is "YongFeng" defined in QEMU, which has Family 7 and model 11. The model 11 doesn't require the Extended model field. So I'm not sure the rule on Zhaoxin. For Hygon, there is "Dhyana" defined in QEMU, which has Family 24 and model 0. The model 0 doens't requrie the Extended model field as well. --- target/i386/cpu.c | 12 ++++-------- target/i386/cpu.h | 30 ++++++++++++++++++++++++++++++ target/i386/host-cpu.c | 6 +++--- target/i386/kvm/kvm.c | 2 +- 4 files changed, 38 insertions(+), 12 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 83858358f5ec..51fcc8ba9867 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6324,10 +6324,7 @@ static void x86_cpuid_version_get_family(Object *obj= , Visitor *v, CPUX86State *env =3D &cpu->env; uint64_t value; =20 - value =3D (env->cpuid_version >> 8) & 0xf; - if (value =3D=3D 0xf) { - value +=3D (env->cpuid_version >> 20) & 0xff; - } + value =3D x86_cpu_family(env->cpuid_version); visit_type_uint64(v, name, &value, errp); } =20 @@ -6365,8 +6362,7 @@ static void x86_cpuid_version_get_model(Object *obj, = Visitor *v, CPUX86State *env =3D &cpu->env; uint64_t value; =20 - value =3D (env->cpuid_version >> 4) & 0xf; - value |=3D ((env->cpuid_version >> 16) & 0xf) << 4; + value =3D x86_cpu_model(env->cpuid_version); visit_type_uint64(v, name, &value, errp); } =20 @@ -6400,7 +6396,7 @@ static void x86_cpuid_version_get_stepping(Object *ob= j, Visitor *v, CPUX86State *env =3D &cpu->env; uint64_t value; =20 - value =3D env->cpuid_version & 0xf; + value =3D x86_cpu_stepping(env->cpuid_version); visit_type_uint64(v, name, &value, errp); } =20 @@ -8154,7 +8150,7 @@ static void mce_init(X86CPU *cpu) CPUX86State *cenv =3D &cpu->env; unsigned int bank; =20 - if (((cenv->cpuid_version >> 8) & 0xf) >=3D 6 + if (x86_cpu_family(cenv->cpuid_version) >=3D 6 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) =3D=3D (CPUID_MCE | CPUID_MCA)) { cenv->mcg_cap =3D MCE_CAP_DEF | MCE_BANKS_DEF | diff --git a/target/i386/cpu.h b/target/i386/cpu.h index b83c521d9fbb..b589a00c80d7 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2671,6 +2671,36 @@ static inline int32_t x86_get_a20_mask(CPUX86State *= env) } } =20 +static inline uint32_t x86_cpu_family(uint32_t eax) +{ + uint32_t family =3D (eax >> 8) & 0xf; + + if (family =3D=3D 0xf) { + family +=3D (eax >> 20) & 0xff; + } + + return family; +} + +static inline uint32_t x86_cpu_model(uint32_t eax) +{ + uint32_t family, model; + + family =3D x86_cpu_family(eax); + model =3D (eax >> 4) & 0xf; + + if (family >=3D 0x6) { + model +=3D ((eax >> 16) & 0xf) << 4; + } + + return model; +} + +static inline uint32_t x86_cpu_stepping(uint32_t eax) +{ + return eax & 0xf; +} + static inline bool cpu_has_vmx(CPUX86State *env) { return env->features[FEAT_1_ECX] & CPUID_EXT_VMX; diff --git a/target/i386/host-cpu.c b/target/i386/host-cpu.c index 16c236478e2b..383c42d4ae3d 100644 --- a/target/i386/host-cpu.c +++ b/target/i386/host-cpu.c @@ -117,13 +117,13 @@ void host_cpu_vendor_fms(char *vendor, int *family, i= nt *model, int *stepping) =20 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx); if (family) { - *family =3D ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF); + *family =3D x86_cpu_family(eax); } if (model) { - *model =3D ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12); + *model =3D x86_cpu_model(eax); } if (stepping) { - *stepping =3D eax & 0x0F; + *stepping =3D x86_cpu_stepping(eax); } } =20 diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 234878c613f6..650d96210192 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -2259,7 +2259,7 @@ int kvm_arch_init_vcpu(CPUState *cs) cpuid_i =3D kvm_x86_build_cpuid(env, cpuid_data.entries, cpuid_i); cpuid_data.cpuid.nent =3D cpuid_i; =20 - if (((env->cpuid_version >> 8)&0xF) >=3D 6 + if (x86_cpu_family(env->cpuid_version) >=3D 6 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) =3D=3D (CPUID_MCE | CPUID_MCA)) { uint64_t mcg_cap, unsupported_caps; --=20 2.43.0