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([186.215.58.88]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4a7fc13971fsm53470171cf.20.2025.06.29.21.32.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Jun 2025 21:33:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751257981; x=1751862781; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NElkJwQRf1CyYZ1pLfGMEkRff1YKnUUmnNhqdv4yZE4=; b=iuxfAfzs7q3dQts3Y2Jz7aFBUJMIZSSY9613x1t8miYCqXKHjE2QhZGHSNsScYJh8M 6vnebPDqqM5Nh/TVt53SFRhmyqVuPKDIQFAEJJDT8pl41YmvUY0h7F0QHTZIMXwQkmFZ nHzqqLqDSgHwj4L9Oac0cdq5tP01THUICvDcFRM2CsGb0H4EJn3eS56cNWKGVcjwOH4H YuIHh3kcrHVfw/eCoFWdNzIk2D8lx7YLj3OUKgal6NWlcM7LNrF/k1zppKuvaMiEu5iw kodt3uKQj6dxhdYrEl3wZp1DHkidkm7VgBikrtk6FxRR3k2uScgh3nRSinvtYNhXJvv6 sUSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751257981; x=1751862781; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NElkJwQRf1CyYZ1pLfGMEkRff1YKnUUmnNhqdv4yZE4=; b=r2Ckvfjs2dJRjmGIAN0GwcfqvJDiYza3fK/S8ggI+sPY8yEyWfdEP+SxQB3TeFJDQ9 Z/IRhp+wNh/p3BC6VbGCJglxLqaKOhr1jNchWqlKtPGnnI39eLO1fbGKcPHpLumsHaUT 4ddn2Y2u3fEcQTeiOF+UrVbo1u8gD7OwQbpZurtd3ahwcQqx2tZq71diP8D5REoSmNgf g2VdzOtlmO8CSXhOPMVNHQA91W8mlixEscoM9qe57t9OgdWznuwcoO/n5bDoCl4W/ux7 mmd2ovPLUkZ/pHZE0OTvek9zK2pyJHSSAGtZ8c6VpveWGq/R64HelpM26faPN1C2jxmx ECMg== X-Gm-Message-State: AOJu0YzT344ZH5MXH3v5Nsj5YCgW0CVFu1uEXBplP9ML2XW0J53udCtS XpPJl6sluso5LzhdGB5KS8TkmexkglTE8Q5ufzJlFJX/OC0+iVNULJ6pR0YDaAaXFP2H1Yiy5d9 sSb4N X-Gm-Gg: ASbGncs3eo8IAI8/c/nIKjZ3Yvyahb+H9dUZxu8fH39ZgZXV/pWb9PFa54ggn7R+AvG Ircx8MECtx5PAScaNOR8/tTruMBSkMmL8cPFGYf5xip8crATyoz9YYmqS7DQWPqyfk5mz7s01vH yidnCIR2Vg7oCjIKaWOmWqnVaFsBNFQnRrMH0MqFu/KjNuujeZ7pwXCm6DJ7V7Cx6NXyR9c7pi7 L6j8S7iIq+Oh2v6oIEWMA+VsUPtOVqub58G/n6e9tvECibIqGsJFFj+NAPixxGMNIFSHgFh5wPi XLiOiJInadu5Y9mBd+O1w19LLYJz6tmHQbtkajA+ZpuwGFEU81OIk7u0dMA79UcIkho= X-Google-Smtp-Source: AGHT+IHVfyDFenWheXr6gxrFqO5swCx1BFaOdEsGs+vJnNU4yAPok30BqXoy6P++i6BxgdOU9F1tLA== X-Received: by 2002:ac8:7d0d:0:b0:476:95dd:521c with SMTP id d75a77b69052e-4a814226439mr58055621cf.45.1751257980989; Sun, 29 Jun 2025 21:33:00 -0700 (PDT) From: Gustavo Romero To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, alex.bennee@linaro.org, gustavo.romero@linaro.org Subject: [PATCH 1/3] target/arm: Add the MECEn SCR_EL3 bit Date: Mon, 30 Jun 2025 04:32:35 +0000 Message-Id: <20250630043237.996788-2-gustavo.romero@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250630043237.996788-1-gustavo.romero@linaro.org> References: <20250630043237.996788-1-gustavo.romero@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::82d; envelope-from=gustavo.romero@linaro.org; helo=mail-qt1-x82d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751258092040116600 Content-Type: text/plain; charset="utf-8" The MECEn bit in SCR_EL3 enables access to the EL2 MECID registers from EL2, so add it to the SCR mask list to use it later on. Signed-off-by: Gustavo Romero --- target/arm/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 302c24e232..8ce30ca857 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1683,6 +1683,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) #define SCR_TRNDR (1ULL << 40) #define SCR_ENTP2 (1ULL << 41) #define SCR_GPF (1ULL << 48) +#define SCR_MECEN (1ULL << 49) #define SCR_NSE (1ULL << 62) =20 /* Return the current FPSCR value. */ --=20 2.34.1