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([186.215.58.88]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4a7fc13971fsm53470171cf.20.2025.06.29.21.32.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Jun 2025 21:33:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751257981; x=1751862781; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NElkJwQRf1CyYZ1pLfGMEkRff1YKnUUmnNhqdv4yZE4=; b=iuxfAfzs7q3dQts3Y2Jz7aFBUJMIZSSY9613x1t8miYCqXKHjE2QhZGHSNsScYJh8M 6vnebPDqqM5Nh/TVt53SFRhmyqVuPKDIQFAEJJDT8pl41YmvUY0h7F0QHTZIMXwQkmFZ nHzqqLqDSgHwj4L9Oac0cdq5tP01THUICvDcFRM2CsGb0H4EJn3eS56cNWKGVcjwOH4H YuIHh3kcrHVfw/eCoFWdNzIk2D8lx7YLj3OUKgal6NWlcM7LNrF/k1zppKuvaMiEu5iw kodt3uKQj6dxhdYrEl3wZp1DHkidkm7VgBikrtk6FxRR3k2uScgh3nRSinvtYNhXJvv6 sUSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751257981; x=1751862781; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NElkJwQRf1CyYZ1pLfGMEkRff1YKnUUmnNhqdv4yZE4=; b=r2Ckvfjs2dJRjmGIAN0GwcfqvJDiYza3fK/S8ggI+sPY8yEyWfdEP+SxQB3TeFJDQ9 Z/IRhp+wNh/p3BC6VbGCJglxLqaKOhr1jNchWqlKtPGnnI39eLO1fbGKcPHpLumsHaUT 4ddn2Y2u3fEcQTeiOF+UrVbo1u8gD7OwQbpZurtd3ahwcQqx2tZq71diP8D5REoSmNgf g2VdzOtlmO8CSXhOPMVNHQA91W8mlixEscoM9qe57t9OgdWznuwcoO/n5bDoCl4W/ux7 mmd2ovPLUkZ/pHZE0OTvek9zK2pyJHSSAGtZ8c6VpveWGq/R64HelpM26faPN1C2jxmx ECMg== X-Gm-Message-State: AOJu0YzT344ZH5MXH3v5Nsj5YCgW0CVFu1uEXBplP9ML2XW0J53udCtS XpPJl6sluso5LzhdGB5KS8TkmexkglTE8Q5ufzJlFJX/OC0+iVNULJ6pR0YDaAaXFP2H1Yiy5d9 sSb4N X-Gm-Gg: ASbGncs3eo8IAI8/c/nIKjZ3Yvyahb+H9dUZxu8fH39ZgZXV/pWb9PFa54ggn7R+AvG Ircx8MECtx5PAScaNOR8/tTruMBSkMmL8cPFGYf5xip8crATyoz9YYmqS7DQWPqyfk5mz7s01vH yidnCIR2Vg7oCjIKaWOmWqnVaFsBNFQnRrMH0MqFu/KjNuujeZ7pwXCm6DJ7V7Cx6NXyR9c7pi7 L6j8S7iIq+Oh2v6oIEWMA+VsUPtOVqub58G/n6e9tvECibIqGsJFFj+NAPixxGMNIFSHgFh5wPi XLiOiJInadu5Y9mBd+O1w19LLYJz6tmHQbtkajA+ZpuwGFEU81OIk7u0dMA79UcIkho= X-Google-Smtp-Source: AGHT+IHVfyDFenWheXr6gxrFqO5swCx1BFaOdEsGs+vJnNU4yAPok30BqXoy6P++i6BxgdOU9F1tLA== X-Received: by 2002:ac8:7d0d:0:b0:476:95dd:521c with SMTP id d75a77b69052e-4a814226439mr58055621cf.45.1751257980989; Sun, 29 Jun 2025 21:33:00 -0700 (PDT) From: Gustavo Romero To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, alex.bennee@linaro.org, gustavo.romero@linaro.org Subject: [PATCH 1/3] target/arm: Add the MECEn SCR_EL3 bit Date: Mon, 30 Jun 2025 04:32:35 +0000 Message-Id: <20250630043237.996788-2-gustavo.romero@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250630043237.996788-1-gustavo.romero@linaro.org> References: <20250630043237.996788-1-gustavo.romero@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::82d; envelope-from=gustavo.romero@linaro.org; helo=mail-qt1-x82d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751258092040116600 Content-Type: text/plain; charset="utf-8" The MECEn bit in SCR_EL3 enables access to the EL2 MECID registers from EL2, so add it to the SCR mask list to use it later on. Signed-off-by: Gustavo Romero --- target/arm/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 302c24e232..8ce30ca857 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1683,6 +1683,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) #define SCR_TRNDR (1ULL << 40) #define SCR_ENTP2 (1ULL << 41) #define SCR_GPF (1ULL << 48) +#define SCR_MECEN (1ULL << 49) #define SCR_NSE (1ULL << 62) =20 /* Return the current FPSCR value. */ --=20 2.34.1 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1751258049; cv=none; d=zohomail.com; s=zohoarc; b=BB5oI86zSbX+iWFaDantiLmZVK34d+7izgpbk5AcHvBad9jXOoYMy1Wf9pYSOncU3d3tFT3U6YkigFdkbZwyCpAIobMLvt2Zco/cHc9Mp/1OXx0Trv1zkkfQvleEig/1X9lO7ysTOZzaESXiuVU5t5HY5Q7LfOYTQuoQa7kMzEA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751258049; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=m7p1tDIFwTjQb2kYrEx8VXYNJTLr+20o3ghBktTtRy4=; b=RGpAYnA4vCf4HCu4sNR3ddKl12XMjbLXuwGm0Fk+XbjN4OAAIYh/ChPo2aqekHpc82twmnaDHU2iPun70HrwntVjPOVfA5Vmw62TXxp1/zkdbOdyclhA4Sbe6bMPf0J3K2EeHVX2+n4q6tUVqJ4fF5owGnhKNAQJc+LELIVuiOM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1751258048939624.3861276000207; Sun, 29 Jun 2025 21:34:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uW6Cm-0004XS-Gf; Mon, 30 Jun 2025 00:33:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uW6Cc-0004Uc-KZ for qemu-devel@nongnu.org; Mon, 30 Jun 2025 00:33:10 -0400 Received: from mail-qt1-x836.google.com ([2607:f8b0:4864:20::836]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uW6CZ-00054a-OF for qemu-devel@nongnu.org; Mon, 30 Jun 2025 00:33:10 -0400 Received: by mail-qt1-x836.google.com with SMTP id d75a77b69052e-4a5903bceffso55177571cf.3 for ; Sun, 29 Jun 2025 21:33:04 -0700 (PDT) Received: from gromero0.. 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The FEAT_MEC is an extension to FEAT_RME that implements multiple Memory Encryption Contexts (MEC) so the memory in a realm can be encrypted and accessing it from the wrong encryption context is not possible. An encryption context allow the selection of a memory encryption engine. Signed-off-by: Gustavo Romero --- docs/system/arm/emulation.rst | 1 + target/arm/cpu-features.h | 5 +++++ target/arm/tcg/cpu64.c | 1 + 3 files changed, 7 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 78c2fd2113..68acb49825 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -89,6 +89,7 @@ the following architecture extensions: - FEAT_LSE (Large System Extensions) - FEAT_LSE2 (Large System Extensions v2) - FEAT_LVA (Large Virtual Address space) +- FEAT_MEC (Memory Encryption Contexts) - FEAT_MixedEnd (Mixed-endian support) - FEAT_MixedEndEL0 (Mixed-endian support at EL0) - FEAT_MOPS (Standardization of memory operations) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 4452e7c21e..128d75e68f 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -593,6 +593,11 @@ static inline bool isar_feature_aa64_hbc(const ARMISAR= egisters *id) return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, BC) !=3D 0; } =20 +static inline bool isar_feature_aa64_mec(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr3, ID_AA64MMFR3, MEC); +} + static inline bool isar_feature_aa64_mops(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, MOPS); diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 5d8ed2794d..66c4d1d789 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1242,6 +1242,7 @@ void aarch64_max_tcg_initfn(Object *obj) =20 t =3D cpu->isar.id_aa64mmfr3; t =3D FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */ + t =3D FIELD_DP64(t, ID_AA64MMFR3, MEC, 1); /* FEAT_MEC */ cpu->isar.id_aa64mmfr3 =3D t; =20 t =3D cpu->isar.id_aa64zfr0; --=20 2.34.1 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1751258061; cv=none; d=zohomail.com; s=zohoarc; b=Sx847WwVsMnrcVIAQIYf7zT/R/QnQHPVvCS1PNmsWp+gmtXyV7i346kr5PkUuob8V/LVdWIXG3BOLgTAzwrgaj68DF+B58+499rtwvjYRSLhnQFsYirB7uQB2Wy/7+qgjlsY1uUH/03K1PUNYgq8A3cbBz/f75rR5gGZp1T1bNs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751258061; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ac/L14+pskdVO/8psuhLq/nvDUBkV5afYQiukb3LTRs=; b=IHg11AsPYZBkjFmw5aUsMX7BYpURRm8AzxCOwo2V53CY5ZEdnPrdQnLoLfklF3AooWRoMJ+yqWzpfmRDKP9sMeEPoCbG+uy1uSquFISBHeN0V/cd0FA2mKb7gofUXiCyHwmuiq4S5VPAduVL5p3tvq0Yb3rUdB1pTeCa9yiDQiw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1751258061364927.4327932890067; Sun, 29 Jun 2025 21:34:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uW6Cn-0004YV-Dq; Mon, 30 Jun 2025 00:33:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uW6Cg-0004W0-Tm for qemu-devel@nongnu.org; Mon, 30 Jun 2025 00:33:14 -0400 Received: from mail-qt1-x82c.google.com ([2607:f8b0:4864:20::82c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uW6Cc-00055E-DK for qemu-devel@nongnu.org; Mon, 30 Jun 2025 00:33:12 -0400 Received: by mail-qt1-x82c.google.com with SMTP id d75a77b69052e-4a58e0b26c4so31942591cf.3 for ; Sun, 29 Jun 2025 21:33:06 -0700 (PDT) Received: from gromero0.. ([186.215.58.88]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4a7fc13971fsm53470171cf.20.2025.06.29.21.33.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Jun 2025 21:33:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751257986; x=1751862786; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ac/L14+pskdVO/8psuhLq/nvDUBkV5afYQiukb3LTRs=; b=FfiD34Gw6lw4uNyWO5QnOkPBN6q2IpoYbBUmqNAUKQbhHEFQXPyBAagqlWRKbCsLc3 kC3YXjcFw40BXdwF2BA7soe0Ni9j51F1JKj5aFECC++AqVQAooWDq7ueINhUwWozBgLt +xSfxexHNoEf0O6uzv/9veOrsxpJSVI/aTusbJxIyqTxkou8G/kwWThXLIIkdSsu8jFG g7O/3iabINnkCf5IbYQJ8bhgXt+Tnx3dSDWeOK/lhQfMdMMPKPVTx6DZDtTyi9cU2oGc RUcMsM+3+ko5keF0QkLud/k5NlYYqBrH/A9QeHvJ5Up2pEVljJq1muZNybQN5g7WLv9U g/bA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751257986; x=1751862786; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ac/L14+pskdVO/8psuhLq/nvDUBkV5afYQiukb3LTRs=; b=VzHHImfgs4yrwNLT9Qp9Vz7fW/tn2RxkyupfKt1xpQw8xi6HEtXBeVhHSXLY1aRaCG nYs+zh8zk8s4+2bljMTV82YviUt/rdEnuwtVGpn7S49MEdnvnBE6cCcwNYThkoxKv7Xf CAdgxrsQ410/j3dJK58L9qQFI9BO2pc4DB6qeYlc/TwiWKzATgSRKOuWNCDbhHWrehDd BJ0Rk0kTGnqm98nwcRNU0927dT+G50X76AeLS+U7VwNZfNEDWDtFUME8KtCw32sCQgmg k1BqRhaQ+AcfuwFazKytIvsrCe6r/biLqPfJyApiD6L6/iN3uNPeH/3hK4KmxsYa18Vo VvoA== X-Gm-Message-State: AOJu0Yw8IeTONPQ42ZGUEreopAb7ysPkdLAt3Qrbz1yBJg/o+6/Fr+on FuLhaHW/Rv9UkFov018i+qDIYTE1CsR8bQOnVPyBrR9CIE5MbK89As6uRf3zJGv5W9k= X-Gm-Gg: ASbGncsZZGIcKB5Ebm6IfmZ/M9sQo+UMvx9khgyS29ItYvjEiMAgXMROB3mwil2bbwk SQGVlk27kSNwPk03+eWAJadzrPE8ZT8ElLsD720WRqbIg+5HXiVk66PHUVzWmT2b3+spqoXlBKW cSA7qYtONeRJHha3/nTPZpUVyA96LurWm4hYDp/yRpTQvzIkN4IXSV4MHWUJKmroF0+Tp5g02ok LnDiEC0hX9Nui3y3pL1YzP+o2iAMXTkhamPssuC0C4IZjQoXAbygAjk5ERxisPZSHyJNjsUKQ8O oBNmVhjJw4lUgY6Da75O3XkdfPzpi9oZQHdg26QvAIbiiBqmsRwmLK27PDo+Wa8UadM= X-Google-Smtp-Source: AGHT+IG0+6eUU7nIhJ/CuImTG1xLG3cPeCWy7xmdAbw1mWBudBCO1TE469WoXtur1MoIfdNnEd9hyA== X-Received: by 2002:a05:622a:2c43:b0:4a7:234e:6c00 with SMTP id d75a77b69052e-4a7fd683b3dmr139092151cf.2.1751257985650; Sun, 29 Jun 2025 21:33:05 -0700 (PDT) From: Gustavo Romero To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, alex.bennee@linaro.org, gustavo.romero@linaro.org Subject: [PATCH 3/3] target/arm: Add FEAT_MEC registers Date: Mon, 30 Jun 2025 04:32:37 +0000 Message-Id: <20250630043237.996788-4-gustavo.romero@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250630043237.996788-1-gustavo.romero@linaro.org> References: <20250630043237.996788-1-gustavo.romero@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::82c; envelope-from=gustavo.romero@linaro.org; helo=mail-qt1-x82c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751258063688116600 Content-Type: text/plain; charset="utf-8" Add FEAT_MEC registers to the arm max cpu. To work properly, FEAT_MEC also depends on FEAT_SCTLR2 and FEAT_TCR2, which= are not implemented in this commit. The bits in SCTLR2 and TCR2 control which translation regimes use MECIDs, and determine which MECID is selected. Signed-off-by: Gustavo Romero --- target/arm/cpu.h | 14 +++++++ target/arm/helper.c | 98 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 112 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8ce30ca857..9509217486 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -565,6 +565,16 @@ typedef struct CPUArchState { =20 /* NV2 register */ uint64_t vncr_el2; + + /* MEC registers */ + uint64_t mecidr_el2; + uint64_t mecid_p0_el2; + uint64_t mecid_a0_el2; + uint64_t mecid_p1_el2; + uint64_t mecid_a1_el2; + uint64_t mecid_rl_a_el3; + uint64_t vmecid_p_el2; + uint64_t vmecid_a_el2; } cp15; =20 struct { @@ -2389,6 +2399,10 @@ FIELD(MFAR, FPA, 12, 40) FIELD(MFAR, NSE, 62, 1) FIELD(MFAR, NS, 63, 1) =20 +FIELD(MECIDR, MECIDW, 0, 4) +FIELD(MECID, MECID, 0, 16) +FIELD(VMECID, MECID, 0, 16) + QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <=3D R_V7M_CSSELR_INDE= X_MASK); =20 /* If adding a feature bit which corresponds to a Linux ELF diff --git a/target/arm/helper.c b/target/arm/helper.c index 889d308807..9f8a284261 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6823,6 +6823,100 @@ static const ARMCPRegInfo nmi_reginfo[] =3D { .resetfn =3D arm_cp_reset_ignore }, }; =20 +static void mecidr_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + /* MECIDWidthm1 =3D 15, i.e. 16 bits is the width of a MECID. */ + env->cp15.mecidr_el2 =3D FIELD_DP64(0, MECIDR, MECIDW, 15); +} + +static uint64_t mecidr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint64_t valid_mask; + + if (!arm_is_el2_enabled(env)) { + /* All bits are RES0. */ + return 0ULL; + } + + valid_mask =3D R_MECIDR_MECIDW_MASK; + return env->cp15.mecidr_el2 & valid_mask; +} + +static CPAccessResult mecid_access(CPUARMState *env, + const ARMCPRegInfo *ri, bool isread) +{ + int el; + + el =3D arm_current_el(env); + if (el =3D=3D 2 && !(env->cp15.scr_el3 & SCR_MECEN)) { + return CP_ACCESS_TRAP_EL3; + } + + return CP_ACCESS_OK; +} + +static void mecid_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t valid_mask; + + valid_mask =3D R_MECID_MECID_MASK; + value &=3D valid_mask; + raw_write(env, ri, value); +} + +static uint64_t mecid_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint64_t valid_mask; + + valid_mask =3D R_MECID_MECID_MASK; + return raw_read(env, ri) & valid_mask; +} + +static const ARMCPRegInfo mec_reginfo[] =3D { + { .name =3D "MECIDR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 7, .crn =3D 10, .crm =3D 8, + .resetfn =3D mecidr_reset, + .access =3D PL2_RW, .accessfn =3D mecid_access, .readfn =3D mecidr_r= ead, + .writefn =3D arm_cp_write_ignore, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecidr_el2) }, + { .name =3D "MECID_P0_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 0, .crn =3D 10, .crm =3D 8, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .readfn =3D mecid_read, .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_p0_el2) }, + { .name =3D "MECID_A0_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 1, .crn =3D 10, .crm =3D 8, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .readfn =3D mecid_read, .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_a0_el2) }, + { .name =3D "MECID_P1_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 2, .crn =3D 10, .crm =3D 8, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .readfn =3D mecid_read, .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_p1_el2) }, + { .name =3D "MECID_A1_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 3, .crn =3D 10, .crm =3D 8, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .readfn =3D mecid_read, .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_a1_el2) }, + { .name =3D "MECID_RL_A_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .opc2 =3D 1, .crn =3D 10, .crm =3D 10, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .readfn =3D mecid_read, .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_rl_a_el3) }, + { .name =3D "VMECID_P_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 0, .crn =3D 10, .crm =3D 9, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .readfn =3D mecid_read, .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.vmecid_p_el2) }, + { .name =3D "VMECID_A_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 1, .crn =3D 10, .crm =3D 9, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .readfn =3D mecid_read, .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.vmecid_a_el2) }, +}; + static void define_pmu_regs(ARMCPU *cpu) { /* @@ -9008,6 +9102,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, nmi_reginfo); } =20 + if (cpu_isar_feature(aa64_mec, cpu)) { + define_arm_cp_regs(cpu, mec_reginfo); + } + if (cpu_isar_feature(any_predinv, cpu)) { define_arm_cp_regs(cpu, predinv_reginfo); } --=20 2.34.1