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a="53247146" X-IronPort-AV: E=Sophos;i="6.16,269,1744095600"; d="scan'208";a="53247146" X-CSE-ConnectionGUID: ygSOAq+HS/mOg7y5gPINfA== X-CSE-MsgGUID: 1YPQI+KvS/+bdvb046Yuwg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,269,1744095600"; d="scan'208";a="157084660" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov Cc: Ewan Hai , Xiaoyao Li , Tao Su , Yi Lai , Dapeng Mi , qemu-devel@nongnu.org, Zhao Liu Subject: [PATCH 4/4] i386/cpu: Reorder CPUID leaves in cpu_x86_cpuid() Date: Fri, 27 Jun 2025 11:51:29 +0800 Message-Id: <20250627035129.2755537-5-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250627035129.2755537-1-zhao1.liu@intel.com> References: <20250627035129.2755537-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.17; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750995087596116600 Content-Type: text/plain; charset="utf-8" Sort the CPUID leaves strictly by index to facilitate checking and changing. Signed-off-by: Zhao Liu --- target/i386/cpu.c | 60 +++++++++++++++++++++++------------------------ 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5d5a227d4c8a..18bb0e9cf9f6 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8052,21 +8052,6 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, assert(!(*eax & ~0x1f)); *ebx &=3D 0xffff; /* The count doesn't need to be reliable. */ break; - case 0x1C: - if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_ED= X_ARCH_LBR)) { - x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); - *edx =3D 0; - } - break; - case 0x1F: - /* V2 Extended Topology Enumeration Leaf */ - if (!x86_has_cpuid_0x1f(cpu)) { - *eax =3D *ebx =3D *ecx =3D *edx =3D 0; - break; - } - - encode_topo_cpuid1f(env, count, topo_info, eax, ebx, ecx, edx); - break; case 0xD: { /* Processor Extended State */ *eax =3D 0; @@ -8207,6 +8192,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, } break; } + case 0x1C: + if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_ED= X_ARCH_LBR)) { + x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); + *edx =3D 0; + } + break; case 0x1D: { /* AMX TILE, for now hardcoded for Sapphire Rapids*/ *eax =3D 0; @@ -8244,6 +8235,15 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, } break; } + case 0x1F: + /* V2 Extended Topology Enumeration Leaf */ + if (!x86_has_cpuid_0x1f(cpu)) { + *eax =3D *ebx =3D *ecx =3D *edx =3D 0; + break; + } + + encode_topo_cpuid1f(env, count, topo_info, eax, ebx, ecx, edx); + break; case 0x24: { *eax =3D 0; *ebx =3D 0; @@ -8465,6 +8465,21 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, *edx =3D 0; } break; + case 0x8000001F: + *eax =3D *ebx =3D *ecx =3D *edx =3D 0; + if (sev_enabled()) { + *eax =3D 0x2; + *eax |=3D sev_es_enabled() ? 0x8 : 0; + *eax |=3D sev_snp_enabled() ? 0x10 : 0; + *ebx =3D sev_get_cbit_position() & 0x3f; /* EBX[5:0] */ + *ebx |=3D (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11= :6] */ + } + break; + case 0x80000021: + *eax =3D *ebx =3D *ecx =3D *edx =3D 0; + *eax =3D env->features[FEAT_8000_0021_EAX]; + *ebx =3D env->features[FEAT_8000_0021_EBX]; + break; case 0x80000022: *eax =3D *ebx =3D *ecx =3D *edx =3D 0; /* AMD Extended Performance Monitoring and Debug */ @@ -8497,21 +8512,6 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, *ecx =3D 0; *edx =3D 0; break; - case 0x8000001F: - *eax =3D *ebx =3D *ecx =3D *edx =3D 0; - if (sev_enabled()) { - *eax =3D 0x2; - *eax |=3D sev_es_enabled() ? 0x8 : 0; - *eax |=3D sev_snp_enabled() ? 0x10 : 0; - *ebx =3D sev_get_cbit_position() & 0x3f; /* EBX[5:0] */ - *ebx |=3D (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11= :6] */ - } - break; - case 0x80000021: - *eax =3D *ebx =3D *ecx =3D *edx =3D 0; - *eax =3D env->features[FEAT_8000_0021_EAX]; - *ebx =3D env->features[FEAT_8000_0021_EBX]; - break; default: /* reserved values: zero */ *eax =3D 0; --=20 2.34.1