From nobody Sat Nov 15 16:38:35 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750994747689213.27057054834506; Thu, 26 Jun 2025 20:25:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uUzhj-0005I0-4b; Thu, 26 Jun 2025 23:24:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uUzhg-0005Gp-Vs for qemu-devel@nongnu.org; Thu, 26 Jun 2025 23:24:40 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uUzhY-00066f-1P for qemu-devel@nongnu.org; Thu, 26 Jun 2025 23:24:40 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8AxquDpDl5osQgeAQ--.25938S3; Fri, 27 Jun 2025 11:24:25 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowMBxn8XiDl5oz10sAQ--.3598S9; Fri, 27 Jun 2025 11:24:25 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org, philmd@linaro.org, jiaxun.yang@flygoat.com Subject: [PATCH v3 7/9] hw/loongarch: Implement avec set irq Date: Fri, 27 Jun 2025 11:01:36 +0800 Message-Id: <20250627030138.2482055-8-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250627030138.2482055-1-gaosong@loongson.cn> References: <20250627030138.2482055-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMBxn8XiDl5oz10sAQ--.3598S9 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1750994747895116600 Content-Type: text/plain; charset="utf-8" Implement avec set irq and update CSR_MSIS and CSR_MSGIR. Signed-off-by: Song Gao --- hw/intc/loongarch_avec.c | 44 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 42 insertions(+), 2 deletions(-) diff --git a/hw/intc/loongarch_avec.c b/hw/intc/loongarch_avec.c index c686ac9483..5959d05d13 100644 --- a/hw/intc/loongarch_avec.c +++ b/hw/intc/loongarch_avec.c @@ -16,6 +16,12 @@ #include "migration/vmstate.h" #include "trace.h" #include "hw/qdev-properties.h" +#include "target/loongarch/cpu.h" + +/* msg addr field */ +FIELD(MSG_ADDR, IRQ_NUM, 4, 8) +FIELD(MSG_ADDR, CPU_NUM, 12, 8) +FIELD(MSG_ADDR, FIX, 28, 12) =20 static uint64_t loongarch_avec_mem_read(void *opaque, hwaddr addr, unsigned size) @@ -23,12 +29,46 @@ static uint64_t loongarch_avec_mem_read(void *opaque, return 0; } =20 +static void avec_set_irq(LoongArchAVECState *s, int cpu_num, int irq_num, = int level) +{ + MachineState *machine =3D MACHINE(qdev_get_machine()); + MachineClass *mc =3D MACHINE_GET_CLASS(machine); + const CPUArchIdList *id_list =3D NULL; + CPUState *cpu; + CPULoongArchState *env; + int i; + + assert(mc->possible_cpu_arch_ids(machine)); + id_list =3D mc->possible_cpu_arch_ids(machine); + cpu =3D id_list->cpus[cpu_num].cpu; + env =3D &LOONGARCH_CPU(cpu)->env; + + if (level) { + set_bit(irq_num, &env->CSR_MSGIS[irq_num / 64]); + env->CSR_MSGIR =3D FIELD_DP64(env->CSR_MSGIR, CSR_MSGIR, INTNUM, i= rq_num); + env->CSR_MSGIR =3D FIELD_DP64(env->CSR_MSGIR, CSR_MSGIR, ACTIVE, 0= ); + + for (i =3D 0; i < ARRAY_SIZE(env->CSR_MSGIS); i++) { + if (env->CSR_MSGIS[i]) { + return; + } + } + qemu_set_irq(s->cpu[cpu_num].parent_irq, 0); + } + qemu_set_irq(s->cpu[cpu_num].parent_irq, level); +} + static void loongarch_avec_mem_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { - return; -} + int irq_num, cpu_num =3D 0; + LoongArchAVECState *s =3D LOONGARCH_AVEC(opaque); + uint64_t msg_addr =3D addr + VIRT_AVEC_BASE; =20 + cpu_num =3D FIELD_EX64(msg_addr, MSG_ADDR, CPU_NUM); + irq_num =3D FIELD_EX64(msg_addr, MSG_ADDR, IRQ_NUM); + avec_set_irq(s, cpu_num, irq_num, 1); +} =20 static const MemoryRegionOps loongarch_avec_ops =3D { .read =3D loongarch_avec_mem_read, --=20 2.34.1