From nobody Sat Nov 15 16:37:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1750993068; cv=none; d=zohomail.com; s=zohoarc; b=dccvoFTXJzJPYFBQpmeKBA8FjCw13YOqUevhoUn7fafZkAF+xFvCuuAJyu5e/ym5QUjOlHZkR0LyFiQPr5d2/FmyE/LMr5a3pkplaf/DYh6/p/WOhM1VqTk6dLGI+qpEI2gFW94Wkq3rER4vfbl/VUw3ufd1bGonZIpe2u4gU6Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750993068; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=y20sE+HVPmTGju2eP9tVauCX/Lly8SDo3KfwGZh9Pn8=; b=iRa1ov8TYJg0oag/FPs3RInZ9tet28+m1mQnCuluTIaUkrwfkFQvEWufPMHd+2P4t0oJK0GdMpthZBDyeBbpuMlddQVGhXHhCJXF3yFsAP+T4Yhgs5lLo/IGJ7k2cOJ/G0lXocVRpR8NJFFiDF9WLQnMuClPn1W8nOAJ97PSPv0= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750993068051919.5722288034726; Thu, 26 Jun 2025 19:57:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uUzGI-0007fG-8b; Thu, 26 Jun 2025 22:56:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uUzGF-0007eQ-Cr; Thu, 26 Jun 2025 22:56:19 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uUzGD-0006B6-Qm; Thu, 26 Jun 2025 22:56:19 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Fri, 27 Jun 2025 10:56:07 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Fri, 27 Jun 2025 10:56:07 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v2 1/3] hw/misc/aspeed_otp: Add ASPEED OTP memory device model Date: Fri, 27 Jun 2025 10:56:03 +0800 Message-ID: <20250627025606.631167-2-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250627025606.631167-1-kane_chen@aspeedtech.com> References: <20250627025606.631167-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1750993069613116600 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS Introduce a QEMU device model for ASPEED's One-Time Programmable (OTP) memory. This model simulates a word-addressable OTP region used for secure fuse storage. The OTP memory can operate with an internal memory buffer. The OTP model provides a memory-like interface through a dedicated AddressSpace, allowing other device models (e.g., SBC) to issue transactions as if accessing a memory-mapped region. Signed-off-by: Kane-Chen-AS --- include/hw/nvram/aspeed_otp.h | 30 +++++++++++ hw/nvram/aspeed_otp.c | 94 +++++++++++++++++++++++++++++++++++ hw/nvram/meson.build | 4 ++ 3 files changed, 128 insertions(+) create mode 100644 include/hw/nvram/aspeed_otp.h create mode 100644 hw/nvram/aspeed_otp.c diff --git a/include/hw/nvram/aspeed_otp.h b/include/hw/nvram/aspeed_otp.h new file mode 100644 index 0000000000..aadeb313be --- /dev/null +++ b/include/hw/nvram/aspeed_otp.h @@ -0,0 +1,30 @@ +/* + * ASPEED OTP (One-Time Programmable) memory + * + * Copyright (C) 2025 Aspeed + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef ASPEED_OTP_H +#define ASPEED_OTP_H + +#include "system/memory.h" +#include "system/address-spaces.h" + +#define TYPE_ASPEED_OTP "aspeed.otp" +OBJECT_DECLARE_SIMPLE_TYPE(AspeedOTPState, ASPEED_OTP) + +typedef struct AspeedOTPState { + DeviceState parent_obj; + + uint64_t size; + + AddressSpace as; + + MemoryRegion mmio; + + uint8_t *storage; +} AspeedOTPState; + +#endif /* ASPEED_OTP_H */ diff --git a/hw/nvram/aspeed_otp.c b/hw/nvram/aspeed_otp.c new file mode 100644 index 0000000000..233dc3528b --- /dev/null +++ b/hw/nvram/aspeed_otp.c @@ -0,0 +1,94 @@ +/* + * ASPEED OTP (One-Time Programmable) memory + * + * Copyright (C) 2025 Aspeed + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "hw/qdev-properties.h" +#include "hw/nvram/aspeed_otp.h" + +static uint64_t aspeed_otp_read(void *opaque, hwaddr offset, unsigned size) +{ + AspeedOTPState *s =3D opaque; + uint64_t val =3D 0; + + memcpy(&val, s->storage + offset, size); + + return val; +} + +static void aspeed_otp_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + AspeedOTPState *s =3D opaque; + + memcpy(s->storage + offset, &val, size); +} + +static void aspeed_otp_init_storage(uint8_t *storage, uint64_t size) +{ + uint32_t *p; + int i, num; + + num =3D size / sizeof(uint32_t); + p =3D (uint32_t *)storage; + for (i =3D 0; i < num; i++) { + p[i] =3D (i % 2 =3D=3D 0) ? 0x00000000 : 0xFFFFFFFF; + } +} + +static const MemoryRegionOps aspeed_otp_ops =3D { + .read =3D aspeed_otp_read, + .write =3D aspeed_otp_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 4, +}; + +static void aspeed_otp_realize(DeviceState *dev, Error **errp) +{ + AspeedOTPState *s =3D ASPEED_OTP(dev); + + if (s->size =3D=3D 0) { + error_setg(errp, "aspeed.otp: 'size' property must be set"); + return; + } + + s->storage =3D g_malloc(s->size); + + aspeed_otp_init_storage(s->storage, s->size); + + memory_region_init_io(&s->mmio, OBJECT(dev), &aspeed_otp_ops, + s, "aspeed.otp", s->size); + address_space_init(&s->as, &s->mmio, NULL); +} + +static const Property aspeed_otp_properties[] =3D { + DEFINE_PROP_UINT64("size", AspeedOTPState, size, 0), +}; + +static void aspeed_otp_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + dc->realize =3D aspeed_otp_realize; + device_class_set_props(dc, aspeed_otp_properties); +} + +static const TypeInfo aspeed_otp_info =3D { + .name =3D TYPE_ASPEED_OTP, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(AspeedOTPState), + .class_init =3D aspeed_otp_class_init, +}; + +static void aspeed_otp_register_types(void) +{ + type_register_static(&aspeed_otp_info); +} + +type_init(aspeed_otp_register_types) diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build index 10f3639db6..b66f23605b 100644 --- a/hw/nvram/meson.build +++ b/hw/nvram/meson.build @@ -19,3 +19,7 @@ system_ss.add(when: 'CONFIG_XLNX_BBRAM', if_true: files('= xlnx-bbram.c')) =20 specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c')) specific_ss.add(when: 'CONFIG_ACPI', if_true: files('fw_cfg-acpi.c')) + +system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( + 'aspeed_otp.c', + )) \ No newline at end of file --=20 2.43.0