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a="63902049" X-IronPort-AV: E=Sophos;i="6.16,267,1744095600"; d="scan'208";a="63902049" X-CSE-ConnectionGUID: DnKX6+EeQsS0dJZLp0vcdQ== X-CSE-MsgGUID: qsc3A+fSS2ujMDy6rU72xA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,267,1744095600"; d="scan'208";a="152949754" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost Cc: Ewan Hai , Jason Zeng , Xiaoyao Li , Tao Su , Yi Lai , Dapeng Mi , Tejus GK , Manish Mishra , qemu-devel@nongnu.org, Zhao Liu Subject: [PATCH 1/8] i386/cpu: Introduce cache model for SierraForest Date: Thu, 26 Jun 2025 16:30:58 +0800 Message-Id: <20250626083105.2581859-2-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250626083105.2581859-1-zhao1.liu@intel.com> References: <20250626083105.2581859-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750925448445116600 Add the cache model to SierraForest (v3) to better emulate its environment. The cache model is based on SierraForest-SP (Scalable Performance): --- cache 0 --- cache type =3D data cache (1) cache level =3D 0x1 (1) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x0 (0) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x8 (8) number of sets =3D 0x40 (64) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 64 (size synth) =3D 32768 (32 KB) --- cache 1 --- cache type =3D instruction cache (2) cache level =3D 0x1 (1) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x0 (0) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x8 (8) number of sets =3D 0x80 (128) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 128 (size synth) =3D 65536 (64 KB) --- cache 2 --- cache type =3D unified cache (3) cache level =3D 0x2 (2) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x7 (7) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x10 (16) number of sets =3D 0x1000 (4096) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 4096 (size synth) =3D 4194304 (4 MB) --- cache 3 --- cache type =3D unified cache (3) cache level =3D 0x3 (3) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x1ff (511) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0xc (12) number of sets =3D 0x24000 (147456) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D true number of sets (s) =3D 147456 (size synth) =3D 113246208 (108 MB) --- cache 4 --- cache type =3D no more caches (0) Suggested-by: Tejus GK Suggested-by: Jason Zeng Suggested-by: "Daniel P . Berrang=C3=A9" Signed-off-by: Zhao Liu Reviewed-by: Dapeng Mi Reviewed-by: Tao Su --- target/i386/cpu.c | 96 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 28e5b7859fef..fcaa2625b023 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2883,6 +2883,97 @@ static const CPUCaches epyc_turin_cache_info =3D { .no_invd_sharing =3D true, .complex_indexing =3D false, .share_level =3D CPU_TOPOLOGY_LEVEL_DIE, + } +}; + +static const CPUCaches xeon_srf_cache_info =3D { + .l1d_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x0.EAX */ + .type =3D DATA_CACHE, + .level =3D 1, + .self_init =3D true, + + /* CPUID 0x4.0x0.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 8, + + /* CPUID 0x4.0x0.ECX */ + .sets =3D 64, + + /* CPUID 0x4.0x0.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + .size =3D 32 * KiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l1i_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x1.EAX */ + .type =3D INSTRUCTION_CACHE, + .level =3D 1, + .self_init =3D true, + + /* CPUID 0x4.0x1.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 8, + + /* CPUID 0x4.0x1.ECX */ + .sets =3D 128, + + /* CPUID 0x4.0x1.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + .size =3D 64 * KiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l2_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x2.EAX */ + .type =3D UNIFIED_CACHE, + .level =3D 2, + .self_init =3D true, + + /* CPUID 0x4.0x2.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 16, + + /* CPUID 0x4.0x2.ECX */ + .sets =3D 4096, + + /* CPUID 0x4.0x2.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + .size =3D 4 * MiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_MODULE, + }, + .l3_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x3.EAX */ + .type =3D UNIFIED_CACHE, + .level =3D 3, + .self_init =3D true, + + /* CPUID 0x4.0x3.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 12, + + /* CPUID 0x4.0x3.ECX */ + .sets =3D 147456, + + /* CPUID 0x4.0x3.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D true, + + .size =3D 108 * MiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_SOCKET, }, }; =20 @@ -5008,6 +5099,11 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { { /* end of list */ } } }, + { + .version =3D 3, + .note =3D "with srf-sp cache model", + .cache_info =3D &xeon_srf_cache_info, + }, { /* end of list */ }, }, }, --=20 2.34.1 From nobody Wed Sep 3 04:04:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750925496; cv=none; d=zohomail.com; s=zohoarc; b=b4/knk+BmWY3/Ry8sq56rx8TQJv2ykqi+bLvP3fmmqH8Xh93PcT4YnMfY1/7lMzYkXrMuy4r75jxQnR2QOpbpRyw3yFXqJY3HavsLk6BK4b+R8RW00dgx3ubXG8+Fjk5wWkeWCom5DbnyPPG6Prq21umxJPfHH9sZifoCF11IZ4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750925496; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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X-CSE-ConnectionGUID: DV9MWSVaSUW53NmYZueGXQ== X-CSE-MsgGUID: 4CkCn8KdScOcwbCKG0tH0g== X-IronPort-AV: E=McAfee;i="6800,10657,11475"; a="63902057" X-IronPort-AV: E=Sophos;i="6.16,267,1744095600"; d="scan'208";a="63902057" X-CSE-ConnectionGUID: 6wmsAzQMS0m1xhwy97dlDA== X-CSE-MsgGUID: zXBlVcPKR7W1aEJ2Wlifeg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,267,1744095600"; d="scan'208";a="152949768" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost Cc: Ewan Hai , Jason Zeng , Xiaoyao Li , Tao Su , Yi Lai , Dapeng Mi , Tejus GK , Manish Mishra , qemu-devel@nongnu.org, Zhao Liu Subject: [PATCH 2/8] i386/cpu: Introduce cache model for GraniteRapids Date: Thu, 26 Jun 2025 16:30:59 +0800 Message-Id: <20250626083105.2581859-3-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250626083105.2581859-1-zhao1.liu@intel.com> References: <20250626083105.2581859-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750925496776116600 Add the cache model to GraniteRapids (v3) to better emulate its environment. The cache model is based on GraniteRapids-SP (Scalable Performance): --- cache 0 --- cache type =3D data cache (1) cache level =3D 0x1 (1) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x1 (1) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0xc (12) number of sets =3D 0x40 (64) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 64 (size synth) =3D 49152 (48 KB) --- cache 1 --- cache type =3D instruction cache (2) cache level =3D 0x1 (1) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x1 (1) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x10 (16) number of sets =3D 0x40 (64) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 64 (size synth) =3D 65536 (64 KB) --- cache 2 --- cache type =3D unified cache (3) cache level =3D 0x2 (2) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x1 (1) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x10 (16) number of sets =3D 0x800 (2048) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 2048 (size synth) =3D 2097152 (2 MB) --- cache 3 --- cache type =3D unified cache (3) cache level =3D 0x3 (3) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0xff (255) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x10 (16) number of sets =3D 0x48000 (294912) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D true number of sets (s) =3D 294912 (size synth) =3D 301989888 (288 MB) --- cache 4 --- cache type =3D no more caches (0) Suggested-by: Tejus GK Suggested-by: Jason Zeng Suggested-by: "Daniel P . Berrang=C3=A9" Signed-off-by: Zhao Liu Reviewed-by: Dapeng Mi Reviewed-by: Tao Su --- target/i386/cpu.c | 96 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index fcaa2625b023..b40f1a5b6648 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2886,6 +2886,97 @@ static const CPUCaches epyc_turin_cache_info =3D { } }; =20 +static const CPUCaches xeon_gnr_cache_info =3D { + .l1d_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x0.EAX */ + .type =3D DATA_CACHE, + .level =3D 1, + .self_init =3D true, + + /* CPUID 0x4.0x0.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 12, + + /* CPUID 0x4.0x0.ECX */ + .sets =3D 64, + + /* CPUID 0x4.0x0.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + .size =3D 48 * KiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l1i_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x1.EAX */ + .type =3D INSTRUCTION_CACHE, + .level =3D 1, + .self_init =3D true, + + /* CPUID 0x4.0x1.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 16, + + /* CPUID 0x4.0x1.ECX */ + .sets =3D 64, + + /* CPUID 0x4.0x1.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + .size =3D 64 * KiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l2_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x2.EAX */ + .type =3D UNIFIED_CACHE, + .level =3D 2, + .self_init =3D true, + + /* CPUID 0x4.0x2.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 16, + + /* CPUID 0x4.0x2.ECX */ + .sets =3D 2048, + + /* CPUID 0x4.0x2.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + .size =3D 2 * MiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l3_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x3.EAX */ + .type =3D UNIFIED_CACHE, + .level =3D 3, + .self_init =3D true, + + /* CPUID 0x4.0x3.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 16, + + /* CPUID 0x4.0x3.ECX */ + .sets =3D 294912, + + /* CPUID 0x4.0x3.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D true, + + .size =3D 288 * MiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_SOCKET, + }, +}; + static const CPUCaches xeon_srf_cache_info =3D { .l1d_cache =3D &(CPUCacheInfo) { /* CPUID 0x4.0x0.EAX */ @@ -4954,6 +5045,11 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { { /* end of list */ } } }, + { + .version =3D 3, + .note =3D "with gnr-sp cache model", + .cache_info =3D &xeon_gnr_cache_info, + }, { /* end of list */ }, }, }, --=20 2.34.1 From nobody Wed Sep 3 04:04:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750925511; cv=none; d=zohomail.com; s=zohoarc; b=F0bvDxpugZOq8suedd5R8jRa5eb3xkZezxCGiVm1JuqrW5Mtwpvmyfap8f6gWDgNowmPYyGqIrHOgMhUue3ntIMOh0USfPO1mkrlO0kjlzO1durQNE0zddFK8lJVLQOe9EzBRL45Kv3gTJud5aerszvvSPXzUXr78B3J0MuXReQ= ARC-Message-Signature: i=1; a=rsa-sha256; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750925513119116600 Add the cache model to SapphireRapids (v4) to better emulate its environment. The cache model is based on SapphireRapids-SP (Scalable Performance): --- cache 0 --- cache type =3D data cache (1) cache level =3D 0x1 (1) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x1 (1) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0xc (12) number of sets =3D 0x40 (64) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 64 (size synth) =3D 49152 (48 KB) --- cache 1 --- cache type =3D instruction cache (2) cache level =3D 0x1 (1) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x1 (1) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x8 (8) number of sets =3D 0x40 (64) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 64 (size synth) =3D 32768 (32 KB) --- cache 2 --- cache type =3D unified cache (3) cache level =3D 0x2 (2) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x1 (1) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x10 (16) number of sets =3D 0x800 (2048) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 2048 (size synth) =3D 2097152 (2 MB) --- cache 3 --- cache type =3D unified cache (3) cache level =3D 0x3 (3) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x7f (127) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0xf (15) number of sets =3D 0x10000 (65536) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D true number of sets (s) =3D 65536 (size synth) =3D 62914560 (60 MB) --- cache 4 --- cache type =3D no more caches (0) Suggested-by: Tejus GK Suggested-by: Jason Zeng Suggested-by: "Daniel P . Berrang=C3=A9" Signed-off-by: Zhao Liu Reviewed-by: Dapeng Mi Reviewed-by: Tao Su --- target/i386/cpu.c | 96 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index b40f1a5b6648..a7f2e5dd3fcb 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2886,6 +2886,97 @@ static const CPUCaches epyc_turin_cache_info =3D { } }; =20 +static const CPUCaches xeon_spr_cache_info =3D { + .l1d_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x0.EAX */ + .type =3D DATA_CACHE, + .level =3D 1, + .self_init =3D true, + + /* CPUID 0x4.0x0.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 12, + + /* CPUID 0x4.0x0.ECX */ + .sets =3D 64, + + /* CPUID 0x4.0x0.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + .size =3D 48 * KiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l1i_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x1.EAX */ + .type =3D INSTRUCTION_CACHE, + .level =3D 1, + .self_init =3D true, + + /* CPUID 0x4.0x1.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 8, + + /* CPUID 0x4.0x1.ECX */ + .sets =3D 64, + + /* CPUID 0x4.0x1.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + .size =3D 32 * KiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l2_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x2.EAX */ + .type =3D UNIFIED_CACHE, + .level =3D 2, + .self_init =3D true, + + /* CPUID 0x4.0x2.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 16, + + /* CPUID 0x4.0x2.ECX */ + .sets =3D 2048, + + /* CPUID 0x4.0x2.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + .size =3D 2 * MiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l3_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x3.EAX */ + .type =3D UNIFIED_CACHE, + .level =3D 3, + .self_init =3D true, + + /* CPUID 0x4.0x3.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 15, + + /* CPUID 0x4.0x3.ECX */ + .sets =3D 65536, + + /* CPUID 0x4.0x3.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D true, + + .size =3D 60 * MiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_SOCKET, + }, +}; + static const CPUCaches xeon_gnr_cache_info =3D { .l1d_cache =3D &(CPUCacheInfo) { /* CPUID 0x4.0x0.EAX */ @@ -4892,6 +4983,11 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { { /* end of list */ } } }, + { + .version =3D 4, + .note =3D "with spr-sp cache model", + .cache_info =3D &xeon_spr_cache_info, + }, { /* end of list */ } } }, --=20 2.34.1 From nobody Wed Sep 3 04:04:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750925448; cv=none; d=zohomail.com; s=zohoarc; b=RDSyY3kN7/fze0E1O4nYYo4z78/WwLHlcaL59Zl7y5zbJlJDc0ztwaMULBk6t3mQdEHCA/8kgxLUaUDf1/aae6RxGebxBXIByCATJr1MM8/Ie+IhQ+0LJ3D98J0uMuzU0cM/Aap8sLqnT86VmptsUW56usQ5URjFC2Y3FaHnuzY= ARC-Message-Signature: i=1; a=rsa-sha256; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750925450522116600 Content-Type: text/plain; charset="utf-8" From: Ewan Hai Add the cache model to YongFeng (v3) to better emulate its environment. Note, although YongFeng v2 was added after v10.0, it was also back ported to v10.0.2. Therefore, the new version (v3) is needed to avoid conflict. The cache model is as follows: --- cache 0 --- cache type =3D data cache (1) cache level =3D 0x1 (1) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x0 (0) maximum IDs for cores in pkg =3D 0x0 (0) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x8 (8) number of sets =3D 0x40 (64) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 64 (size synth) =3D 32768 (32 KB) --- cache 1 --- cache type =3D instruction cache (2) cache level =3D 0x1 (1) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x0 (0) maximum IDs for cores in pkg =3D 0x0 (0) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x10 (16) number of sets =3D 0x40 (64) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 64 (size synth) =3D 65536 (64 KB) --- cache 2 --- cache type =3D unified cache (3) cache level =3D 0x2 (2) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x0 (0) maximum IDs for cores in pkg =3D 0x0 (0) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x8 (8) number of sets =3D 0x200 (512) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D true complex cache indexing =3D false number of sets (s) =3D 512 (size synth) =3D 262144 (256 KB) --- cache 3 --- cache type =3D unified cache (3) cache level =3D 0x3 (3) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x0 (0) maximum IDs for cores in pkg =3D 0x0 (0) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x10 (16) number of sets =3D 0x2000 (8192) WBINVD/INVD acts on lower caches =3D true inclusive to lower caches =3D true complex cache indexing =3D false number of sets (s) =3D 8192 (size synth) =3D 8388608 (8 MB) --- cache 4 --- cache type =3D no more caches (0) Signed-off-by: Ewan Hai Signed-off-by: Zhao Liu --- Changes on the original codes: * Rearrange cache model fields to make them easier to check. * And add explanation of why v3 is needed. * Drop lines_per_tag field for L2 & L3. --- target/i386/cpu.c | 104 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index a7f2e5dd3fcb..08c84ba90f52 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -3159,6 +3159,105 @@ static const CPUCaches xeon_srf_cache_info =3D { }, }; =20 +static const CPUCaches yongfeng_cache_info =3D { + .l1d_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x0.EAX */ + .type =3D DATA_CACHE, + .level =3D 1, + .self_init =3D true, + + /* CPUID 0x4.0x0.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 8, + + /* CPUID 0x4.0x0.ECX */ + .sets =3D 64, + + /* CPUID 0x4.0x0.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + /* CPUID 0x80000005.ECX */ + .lines_per_tag =3D 1, + .size =3D 32 * KiB, + + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l1i_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x1.EAX */ + .type =3D INSTRUCTION_CACHE, + .level =3D 1, + .self_init =3D true, + + /* CPUID 0x4.0x1.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 16, + + /* CPUID 0x4.0x1.ECX */ + .sets =3D 64, + + /* CPUID 0x4.0x1.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + /* CPUID 0x80000005.EDX */ + .lines_per_tag =3D 1, + .size =3D 64 * KiB, + + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l2_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x2.EAX */ + .type =3D UNIFIED_CACHE, + .level =3D 2, + .self_init =3D true, + + /* CPUID 0x4.0x2.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 8, + + /* CPUID 0x4.0x2.ECX */ + .sets =3D 512, + + /* CPUID 0x4.0x2.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D true, + .complex_indexing =3D false, + + /* CPUID 0x80000006.ECX */ + .size =3D 256 * KiB, + + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l3_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x3.EAX */ + .type =3D UNIFIED_CACHE, + .level =3D 3, + .self_init =3D true, + + /* CPUID 0x4.0x3.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 16, + + /* CPUID 0x4.0x3.ECX */ + .sets =3D 8192, + + /* CPUID 0x4.0x3.EDX */ + .no_invd_sharing =3D true, + .inclusive =3D true, + .complex_indexing =3D false, + + .size =3D 8 * MiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_DIE, + }, +}; + /* The following VMX features are not supported by KVM and are left out in= the * CPU definitions: * @@ -6438,6 +6537,11 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { { /* end of list */ } } }, + { + .version =3D 3, + .note =3D "with the cache info", + .cache_info =3D &yongfeng_cache_info + }, { /* end of list */ } } }, --=20 2.34.1 From nobody Wed Sep 3 04:04:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750925466; cv=none; d=zohomail.com; s=zohoarc; b=OPhFC5C+arb6g1Mc/ohZMORRZZ0K2mhZ2qrrZR88ERbRGDjntM8T48IoL54npRWYIWKNdkE7nQsyna22+t4WoRhxVRovGgRBh0uNpSPBs8zpQ06Aj6pcCDyb5lCNGR/COaTwzj56hZyRSAe5kP7dJ/jqeoIWIFRBpUT2nQ0Vl+I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750925468483116600 Content-Type: text/plain; charset="utf-8" From: Manish Mishra Add a "x-force-cpuid-0x1f" property so that CPU models can enable it and have 0x1f CPUID leaf natually as the Host CPU. The advantage is that when the CPU model's cache model is already consistent with the Host CPU, for example, SRF defaults to l2 per module & l3 per package, 0x1f can better help users identify the topology in the VM. Adding 0x1f for specific CPU models should not cause any trouble in principle. This property is only enabled for CPU models that already have 0x1f leaf on the Host, so software that originally runs normally on the Host won't encounter issues in the Guest with corresponding CPU model. Conversely, some software that relies on checking 0x1f might have problems in the Guest due to the lack of 0x1f [*]. In summary, adding 0x1f is also intended to further emulate the Host CPU environment. [*]: https://lore.kernel.org/qemu-devel/PH0PR02MB738410511BF51B12DB09BE6CF6= AC2@PH0PR02MB7384.namprd02.prod.outlook.com/ Signed-off-by: Manish Mishra Co-authored-by: Xiaoyao Li Signed-off-by: Xiaoyao Li [Integrated and rebased 2 previous patches (ordered by post time)] Signed-off-by: Zhao Liu Reviewed-by: Dapeng Mi --- Note: This patch integrates the idea from 2 previous posted patches (ordered by post time)[1] [2], following the s-o-b policy of "Re-starting abandoned work" in docs/devel/code-provenance.rst. [1]: From Manish: https://lore.kernel.org/qemu-devel/20240722101859.47408-1= -manish.mishra@nutanix.com/ [2]: From Xiaoyao: https://lore.kernel.org/qemu-devel/20240813033145.279307= -1-xiaoyao.li@intel.com/ --- Changes since RFC: * Rebase and rename the property as "x-force-cpuid-0x1f". (Igor) --- target/i386/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 08c84ba90f52..ee36f7ee2ccc 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -9934,6 +9934,7 @@ static const Property x86_cpu_properties[] =3D { DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, true), DEFINE_PROP_BOOL("x-l1-cache-per-thread", X86CPU, l1_cache_per_core, t= rue), + DEFINE_PROP_BOOL("x-force-cpuid-0x1f", X86CPU, force_cpuid_0x1f, false= ), }; =20 #ifndef CONFIG_USER_ONLY --=20 2.34.1 From nobody Wed Sep 3 04:04:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750925447; cv=none; d=zohomail.com; s=zohoarc; b=MXVTeC8y7Z4sYVUuamEsQZq69WH0E5lDbfuN/hUnjI2DtdVigh1COzn5/m5FABswvFFDsiSk13uMRPaqK49aoTch3ud9PibFrpWzka3TPkoIjaX4CO0zMNiOBL8oSZY4ibmk5MVLGHeFhLEFCLQZyC+JdbjWWzr3AriHS4wBdQ4= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750925448276116600 Content-Type: text/plain; charset="utf-8" Host SierraForest CPU has 0x1f leaf by default, so that enable it for Guest CPU by default as well. Suggested-by: Igor Mammedov Signed-off-by: Zhao Liu Reviewed-by: Dapeng Mi --- Changes since RFC: * Rename the property to "x-force-cpuid-0x1f". (Igor) --- target/i386/cpu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ee36f7ee2ccc..70f8fc37f8e0 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5392,8 +5392,11 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { }, { .version =3D 3, - .note =3D "with srf-sp cache model", + .note =3D "with srf-sp cache model and 0x1f leaf", .cache_info =3D &xeon_srf_cache_info, + .props =3D (PropValue[]) { + { "x-force-cpuid-0x1f", "on" }, + } }, { /* end of list */ }, }, --=20 2.34.1 From nobody Wed Sep 3 04:04:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750925503; cv=none; d=zohomail.com; s=zohoarc; b=iBnEXZihF+VDKXyeP5MNGW/O9pr8xcNJNukbo4DrTL3jiLV/Rp2cM9opnah88J++vanddHkmv6oun0t8yI9Y201y+yhgHSSw5Nqwkgg+f6Ij8KhxY4dJOU5bKhBqE/K+Uu4zd+nnOemuPVFeK+iYok0kUd6c343p4yLdCKklg9E= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750925505014116600 Content-Type: text/plain; charset="utf-8" Host GraniteRapids CPU has 0x1f leaf by default, so that enable it for Guest CPU by default as well. Suggested-by: Igor Mammedov Signed-off-by: Zhao Liu Reviewed-by: Dapeng Mi --- Changes since RFC: * Rename the property to "x-force-cpuid-0x1f". (Igor) --- target/i386/cpu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 70f8fc37f8e0..acf7e0de184d 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5242,8 +5242,11 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { }, { .version =3D 3, - .note =3D "with gnr-sp cache model", + .note =3D "with gnr-sp cache model and 0x1f leaf", .cache_info =3D &xeon_gnr_cache_info, + .props =3D (PropValue[]) { + { "x-force-cpuid-0x1f", "on" }, + } }, { /* end of list */ }, }, --=20 2.34.1 From nobody Wed Sep 3 04:04:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750925481; cv=none; d=zohomail.com; s=zohoarc; b=fALdQbIqhs5hfCO0aPPjtXsUYo7DLb+1DyvklSnhMFIwteZzEf/GcOb2CsTm3gNNbZhvCdNiAMpqxn4L4rSnSHTqT/qj1cMftFZTv1t3/ciwq1G5OimkAxbNV5DqXZ4QFetVoT5/7Z7onMLL6/uNNrkm8i3UR8YQfPB1BCCsjio= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750925484758116600 Content-Type: text/plain; charset="utf-8" Host SapphireRapids CPU has 0x1f leaf by default, so that enable it for Guest CPU by default as well. Suggested-by: Igor Mammedov Signed-off-by: Zhao Liu Reviewed-by: Dapeng Mi --- Changes since RFC: * Rename the property to "x-force-cpuid-0x1f". (Igor) --- target/i386/cpu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index acf7e0de184d..c7f157a0f71c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5084,8 +5084,11 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { }, { .version =3D 4, - .note =3D "with spr-sp cache model", + .note =3D "with spr-sp cache model and 0x1f leaf", .cache_info =3D &xeon_spr_cache_info, + .props =3D (PropValue[]) { + { "x-force-cpuid-0x1f", "on" }, + } }, { /* end of list */ } } --=20 2.34.1