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b=dGXRzD+ABTpKdJZJPrt1WnWFNorEmvWN7lDm4HTpfsoCDSJcpk2jY1vl6gS9znGFFx6Y0mRy6ZfkeT6hl6aUL1DwcBZVgGyGwnqxVFqNl3d/mqHG72GMhrtsQFcxOpYekHcrEQBrsXW01YPTxNLHRx00t0IyjOogH7FSB3+Q537uyGBp17mU2K/ADFB/2vYOBh7I6l0OdMjnrOU+90iDUQWK7jQZAltHdvORw3XtrJ1ZCTS1upbQd2ZI56trkyv6fsXXWPu7F8mzF2LhH/gPhFbxTW87pPTtDsvj0zXt8EXDLxQNIj+M/OGEdZBBXmq2ieL4cizSVcwsayJEcnWJ+g== From: Djordje Todorovic To: "qemu-devel@nongnu.org" CC: "qemu-riscv@nongnu.org" , "cfu@mips.com" , "mst@redhat.com" , "marcel.apfelbaum@gmail.com" , "dbarboza@ventanamicro.com" , Djordje Todorovic Subject: [PATCH v4 04/11] target/riscv: Add MIPS P8700 CSRs Thread-Topic: [PATCH v4 04/11] target/riscv: Add MIPS P8700 CSRs Thread-Index: AQHb5dv/N8i4iNywa0u053s6BoJFKA== Date: Wed, 25 Jun 2025 14:18:18 +0000 Message-ID: <20250625141732.59084-5-djordje.todorovic@htecgroup.com> References: <20250625141732.59084-1-djordje.todorovic@htecgroup.com> In-Reply-To: <20250625141732.59084-1-djordje.todorovic@htecgroup.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a01:111:f403:c201::3; envelope-from=Djordje.Todorovic@htecgroup.com; helo=AS8PR04CU009.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @htecgroup.com) X-ZM-MESSAGEID: 1750861196370116600 Content-Type: text/plain; charset="utf-8" Define MIPS CSRs used for P8700 CPU. Signed-off-by: Chao-ying Fu Signed-off-by: Djordje Todorovic Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 3 + target/riscv/cpu.h | 3 + target/riscv/meson.build | 1 + target/riscv/mips_csr.c | 226 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 233 insertions(+) create mode 100644 target/riscv/mips_csr.c diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 672e30378e..9a11a994c4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -3180,6 +3180,9 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .cfg.ext_zbb =3D true, .cfg.marchid =3D 0x8000000000000201, .cfg.mvendorid =3D MIPS_VENDOR_ID, +#ifndef CONFIG_USER_ONLY + .custom_csrs =3D mips_csr_list, +#endif ), =20 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index fba0b0506b..ed10709a65 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -972,5 +972,8 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32= _bit); /* In th_csr.c */ extern const RISCVCSR th_csr_list[]; =20 +/* Implemented in mips_csr.c */ +extern const RISCVCSR mips_csr_list[]; + const char *priv_spec_to_str(int priv_version); #endif /* RISCV_CPU_H */ diff --git a/target/riscv/meson.build b/target/riscv/meson.build index a4bd61e52a..fbb6c8fb45 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -32,6 +32,7 @@ riscv_system_ss.add(files( 'debug.c', 'monitor.c', 'machine.c', + 'mips_csr.c', 'pmu.c', 'th_csr.c', 'time_helper.c', diff --git a/target/riscv/mips_csr.c b/target/riscv/mips_csr.c new file mode 100644 index 0000000000..759d5e6a67 --- /dev/null +++ b/target/riscv/mips_csr.c @@ -0,0 +1,226 @@ +/* + * MIPS-specific CSRs. + * + * Copyright (c) 2025 MIPS + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "cpu_vendorid.h" + +/* Static MIPS CSR state storage */ +static struct { + uint64_t tvec; + uint64_t config[12]; + uint64_t pmacfg[16]; /* Fixed: was 15, should be 16 */ +} mips_csr_state; + +/* MIPS CSR */ +#define CSR_MIPSTVEC 0x7c0 +#define CSR_MIPSCONFIG0 0x7d0 +#define CSR_MIPSCONFIG1 0x7d1 +#define CSR_MIPSCONFIG2 0x7d2 +#define CSR_MIPSCONFIG3 0x7d3 +#define CSR_MIPSCONFIG4 0x7d4 +#define CSR_MIPSCONFIG5 0x7d5 +#define CSR_MIPSCONFIG6 0x7d6 +#define CSR_MIPSCONFIG7 0x7d7 +#define CSR_MIPSCONFIG8 0x7d8 +#define CSR_MIPSCONFIG9 0x7d9 +#define CSR_MIPSCONFIG10 0x7da +#define CSR_MIPSCONFIG11 0x7db +#define CSR_MIPSPMACFG0 0x7e0 +#define CSR_MIPSPMACFG1 0x7e1 +#define CSR_MIPSPMACFG2 0x7e2 +#define CSR_MIPSPMACFG3 0x7e3 +#define CSR_MIPSPMACFG4 0x7e4 +#define CSR_MIPSPMACFG5 0x7e5 +#define CSR_MIPSPMACFG6 0x7e6 +#define CSR_MIPSPMACFG7 0x7e7 +#define CSR_MIPSPMACFG8 0x7e8 +#define CSR_MIPSPMACFG9 0x7e9 +#define CSR_MIPSPMACFG10 0x7ea +#define CSR_MIPSPMACFG11 0x7eb +#define CSR_MIPSPMACFG12 0x7ec +#define CSR_MIPSPMACFG13 0x7ed +#define CSR_MIPSPMACFG14 0x7ee +#define CSR_MIPSPMACFG15 0x7ef + +static RISCVException any(CPURISCVState *env, int csrno) +{ + return RISCV_EXCP_NONE; +} + +static RISCVException read_mipstvec(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D mips_csr_state.tvec; + return RISCV_EXCP_NONE; +} + +static RISCVException write_mipstvec(CPURISCVState *env, int csrno, + target_ulong val, uintptr_t ra) +{ + mips_csr_state.tvec =3D val; + return RISCV_EXCP_NONE; +} + +static RISCVException read_mipsconfig(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D mips_csr_state.config[csrno - CSR_MIPSCONFIG0]; + return RISCV_EXCP_NONE; +} + +static RISCVException write_mipsconfig(CPURISCVState *env, int csrno, + target_ulong val, uintptr_t ra) +{ + mips_csr_state.config[csrno - CSR_MIPSCONFIG0] =3D val; + return RISCV_EXCP_NONE; +} + +static RISCVException read_mipspmacfg(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D mips_csr_state.pmacfg[csrno - CSR_MIPSPMACFG0]; + return RISCV_EXCP_NONE; +} + +static RISCVException write_mipspmacfg(CPURISCVState *env, int csrno, + target_ulong val, uintptr_t ra) +{ + mips_csr_state.pmacfg[csrno - CSR_MIPSPMACFG0] =3D val; + return RISCV_EXCP_NONE; +} + +const RISCVCSR mips_csr_list[] =3D { + { + .csrno =3D CSR_MIPSTVEC, + .csr_ops =3D { "mipstvec", any, read_mipstvec, write_mipstvec } + }, + { + .csrno =3D CSR_MIPSCONFIG0, + .csr_ops =3D { "mipsconfig0", any, read_mipsconfig, write_mipsconf= ig } + }, + { + .csrno =3D CSR_MIPSCONFIG1, + .csr_ops =3D { "mipsconfig1", any, read_mipsconfig, write_mipsconf= ig } + }, + { + .csrno =3D CSR_MIPSCONFIG2, + .csr_ops =3D { "mipsconfig2", any, read_mipsconfig, write_mipsconf= ig } + }, + { + .csrno =3D CSR_MIPSCONFIG3, + .csr_ops =3D { "mipsconfig3", any, read_mipsconfig, write_mipsconf= ig } + }, + { + .csrno =3D CSR_MIPSCONFIG4, + .csr_ops =3D { "mipsconfig4", any, read_mipsconfig, write_mipsconf= ig } + }, + { + .csrno =3D CSR_MIPSCONFIG5, + .csr_ops =3D { "mipsconfig5", any, read_mipsconfig, write_mipsconf= ig } + }, + { + .csrno =3D CSR_MIPSCONFIG6, + .csr_ops =3D { "mipsconfig6", any, read_mipsconfig, write_mipsconf= ig } + }, + { + .csrno =3D CSR_MIPSCONFIG7, + .csr_ops =3D { "mipsconfig7", any, read_mipsconfig, write_mipsconf= ig } + }, + { + .csrno =3D CSR_MIPSCONFIG8, + .csr_ops =3D { "mipsconfig8", any, read_mipsconfig, write_mipsconf= ig } + }, + { + .csrno =3D CSR_MIPSCONFIG9, + .csr_ops =3D { "mipsconfig9", any, read_mipsconfig, write_mipsconf= ig } + }, + { + .csrno =3D CSR_MIPSCONFIG10, + .csr_ops =3D { "mipsconfig10", any, read_mipsconfig, write_mipscon= fig } + }, + { + .csrno =3D CSR_MIPSCONFIG11, + .csr_ops =3D { "mipsconfig11", any, read_mipsconfig, write_mipscon= fig } + }, + { + .csrno =3D CSR_MIPSPMACFG0, + .csr_ops =3D { "mipspmacfg0", any, read_mipspmacfg, write_mipspmac= fg } + }, + { + .csrno =3D CSR_MIPSPMACFG1, + .csr_ops =3D { "mipspmacfg1", any, read_mipspmacfg, write_mipspmac= fg } + }, + { + .csrno =3D CSR_MIPSPMACFG2, + .csr_ops =3D { "mipspmacfg2", any, read_mipspmacfg, write_mipspmac= fg } + }, + { + .csrno =3D CSR_MIPSPMACFG3, + .csr_ops =3D { "mipspmacfg3", any, read_mipspmacfg, write_mipspmac= fg } + }, + { + .csrno =3D CSR_MIPSPMACFG4, + .csr_ops =3D { "mipspmacfg4", any, read_mipspmacfg, write_mipspmac= fg } + }, + { + .csrno =3D CSR_MIPSPMACFG5, + .csr_ops =3D { "mipspmacfg5", any, read_mipspmacfg, write_mipspmac= fg } + }, + { + .csrno =3D CSR_MIPSPMACFG6, + .csr_ops =3D { "mipspmacfg6", any, read_mipspmacfg, write_mipspmac= fg } + }, + { + .csrno =3D CSR_MIPSPMACFG7, + .csr_ops =3D { "mipspmacfg7", any, read_mipspmacfg, write_mipspmac= fg } + }, + { + .csrno =3D CSR_MIPSPMACFG8, + .csr_ops =3D { "mipspmacfg8", any, read_mipspmacfg, write_mipspmac= fg } + }, + { + .csrno =3D CSR_MIPSPMACFG9, + .csr_ops =3D { "mipspmacfg9", any, read_mipspmacfg, write_mipspmac= fg } + }, + { + .csrno =3D CSR_MIPSPMACFG10, + .csr_ops =3D { "mipspmacfg10", any, read_mipspmacfg, write_mipspma= cfg } + }, + { + .csrno =3D CSR_MIPSPMACFG11, + .csr_ops =3D { "mipspmacfg11", any, read_mipspmacfg, write_mipspma= cfg } + }, + { + .csrno =3D CSR_MIPSPMACFG12, + .csr_ops =3D { "mipspmacfg12", any, read_mipspmacfg, write_mipspma= cfg } + }, + { + .csrno =3D CSR_MIPSPMACFG13, + .csr_ops =3D { "mipspmacfg13", any, read_mipspmacfg, write_mipspma= cfg } + }, + { + .csrno =3D CSR_MIPSPMACFG14, + .csr_ops =3D { "mipspmacfg14", any, read_mipspmacfg, write_mipspma= cfg } + }, + { + .csrno =3D CSR_MIPSPMACFG15, + .csr_ops =3D { "mipspmacfg15", any, read_mipspmacfg, write_mipspma= cfg } + }, + { }, +}; --=20 2.34.1