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([191.255.35.152]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-237d873845esm90847525ad.243.2025.06.23.10.21.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jun 2025 10:21:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1750699293; x=1751304093; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ghnsqsuTP2eOK0pz8lkELt9NeubIcUGu0srdYwhqGo0=; b=e0QnvmOccgoIae82scl+dOWRHpwcsjGnwMk/aJxtpv7xAwwr/7rbv+xs/bw1F3h1sd g84jY50my21g1kO+/aWaDYBRzkKUhRPUcY1exo7qCDEMnGPBxLBbzhssfe4C+7REsiV1 duIkDhzAZaaX8zKZtb2WwBA/8UmR0UhYSfB+MHs5HnwGOMXtaCZ1POxzVUVcjs4UvlR6 UYtcFde33AC3wif9HlgY/MRfZJMHPW9EmpMt3wGbL/CuttnNJO8P8ZtbejYCBnYSHCzR En3TfC7nRk+4FsT5fqiVuftuwCFnWgEQr1dcxAlc6U/ofDGtN++Q8daCNFaGPAnlrT/k MSTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750699293; x=1751304093; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ghnsqsuTP2eOK0pz8lkELt9NeubIcUGu0srdYwhqGo0=; b=qdILnH6QmMFeFV1YMC6ak2LEPo1Ie0uGZiCAD4Nw56MHk2PrSffD5nRbtNl7lRo11p gnol3kJ7ojSoW4xFFV4LHvnbeEIXztohaTd5ZWk8lQyAAfKQGIvowNYSI2dng78jwuUg 4DUF4T54kKM3l/qgu18eJw3tHL3JGnRMHhrtv0zAEMliz46gl+OeA708F3j4mTEO8zmg wfTjEKm9d0/l76etMtvvJ2xaD/eFfLYwbmLAtBa1vM1bV+d3i81Z5PTe/heICP3uzUtV jX0R+PRMdxs5Kg4iDCvAE8kXluTkkscfSnjXsa9YMadz0V/ypW7ME185j1+1XNkQfWJF eUUQ== X-Gm-Message-State: AOJu0YzuGfNfRhx/us6q85HEPYg/X62meolgMn6H6GMRntNA5g8AHDW4 ZHl5NBsyLIyNol+SdMDpnKicY7fL9O0n78wu5IqusKQX3vbDYYrjkEzhXZPETr4CzIrKY2HvzCC ZDkZmKMQ= X-Gm-Gg: ASbGncunMiSQgWIy3UefIrKA5cQ5HFAwBfJCxsEkHwugrlRFeeVVu++fEL/Ts9z3BSz UJl68BW1pK0GcKHWyt2HzoxbT/6o2oLQCstCbHqJk2pUH4qjtqQm+Kj/ZT4K6r8soKP0LP++Vq7 sU57xrjH4gn2zHvsEcntImjdXkJ6wVH0KSPP/7HRT0JqoT979byRmx2tK+lWllnTo5jh9m+jMbT tDggiTraUm6YU012aCeHE8GaMYY4NCCqC0aUjEAY+iA+KfQVE5ptOzS9IULXtFmYkWaQ4lUznjj q8k/jUmOqMDieTLCiaNwxXkkhqpEwhoI58Vrv6jJjLlrNJVA9ZEBI9x+FIHcOcqK4kqSU88tRdw = X-Google-Smtp-Source: AGHT+IFK04sa0p5ov4RETysY0BD2GYY07uznPn5FOVaf/tnK0nmIeC10L9o06hevZcIJGAf0ASkgRw== X-Received: by 2002:a17:902:b417:b0:231:c3c1:babb with SMTP id d9443c01a7336-2380249777emr3446225ad.18.1750699293228; Mon, 23 Jun 2025 10:21:33 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@dabbelt.com, Daniel Henrique Barboza Subject: [PATCH 3/3] target/riscv: print all available CSRs in riscv_cpu_dump_state() Date: Mon, 23 Jun 2025 14:21:19 -0300 Message-ID: <20250623172119.997166-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250623172119.997166-1-dbarboza@ventanamicro.com> References: <20250623172119.997166-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=dbarboza@ventanamicro.com; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1750699341792116600 Content-Type: text/plain; charset="utf-8" At this moment we're printing a small selection of CSRs. There's no particular reason to not print all of them. We're ignoring the note about CSR_SSTATUS being ommited because it can be read via CSR_MSTATUS. There's a huge list of CSRs that would fall in this category and it would be an extra burden to manage them, not mentioning having to document "we're not listing X because it's the same value as Y" to users. Remove 'dump_csrs' and use the existing 'csr_ops' array to print all available CSRs. Create two helpers in csr.c to identify FPU and VPU CSRs and skip them - they'll be printed in the FPU/VPU blocks later. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 55 ++++++++++++++++------------------------------ target/riscv/cpu.h | 2 ++ target/riscv/csr.c | 18 +++++++++++++++ 3 files changed, 39 insertions(+), 36 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 95d0b88937..ed1bf18625 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -544,44 +544,27 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *= f, int flags) #endif qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); #ifndef CONFIG_USER_ONLY - { - static const int dump_csrs[] =3D { - CSR_MHARTID, - CSR_MSTATUS, - CSR_MSTATUSH, - /* - * CSR_SSTATUS is intentionally omitted here as its value - * can be figured out by looking at CSR_MSTATUS - */ - CSR_HSTATUS, - CSR_VSSTATUS, - CSR_MIP, - CSR_MIE, - CSR_MIDELEG, - CSR_HIDELEG, - CSR_MEDELEG, - CSR_HEDELEG, - CSR_MTVEC, - CSR_STVEC, - CSR_VSTVEC, - CSR_MEPC, - CSR_SEPC, - CSR_VSEPC, - CSR_MCAUSE, - CSR_SCAUSE, - CSR_VSCAUSE, - CSR_MTVAL, - CSR_STVAL, - CSR_HTVAL, - CSR_MTVAL2, - CSR_MSCRATCH, - CSR_SSCRATCH, - CSR_SATP, - }; + for (i =3D 0; i < ARRAY_SIZE(csr_ops); i++) { + int csrno =3D i; =20 - for (i =3D 0; i < ARRAY_SIZE(dump_csrs); ++i) { - riscv_dump_csr(env, dump_csrs[i], f); + /* + * Early skip when possible since we're going + * through a lot of NULL entries. + */ + if (csr_ops[csrno].predicate =3D=3D NULL) { + continue; } + + /* + * FPU and VPU CSRs will be printed in the + * CPU_DUMP_FPU/CPU_DUMP_VPU blocks later. + */ + if (riscv_csr_is_fpu(csrno) || + riscv_csr_is_vpu(csrno)) { + continue; + } + + riscv_dump_csr(env, csrno, f); } #endif =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 4a862da615..ecdf709c2d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -967,6 +967,8 @@ bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu); =20 /* CSR function table */ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; +bool riscv_csr_is_fpu(int csrno); +bool riscv_csr_is_vpu(int csrno); =20 extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6296ecd1e1..229257b31b 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -5799,6 +5799,24 @@ static RISCVException write_jvt(CPURISCVState *env, = int csrno, return RISCV_EXCP_NONE; } =20 +bool riscv_csr_is_fpu(int csrno) +{ + if (!csr_ops[csrno].predicate) { + return false; + } + + return csr_ops[csrno].predicate =3D=3D fs; +} + +bool riscv_csr_is_vpu(int csrno) +{ + if (!csr_ops[csrno].predicate) { + return false; + } + + return csr_ops[csrno].predicate =3D=3D vs; +} + /* * Control and Status Register function table * riscv_csr_operations::predicate() must be provided for an implemented C= SR --=20 2.49.0