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Sat, 21 Jun 2025 16:54:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 061/101] target/arm: Implement SME2 ZIP, UZP (four registers) Date: Sat, 21 Jun 2025 16:49:57 -0700 Message-ID: <20250621235037.74091-62-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250621235037.74091-1-richard.henderson@linaro.org> References: <20250621235037.74091-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1750550312945116600 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/tcg/helper-sme.h | 12 ++++++ target/arm/tcg/sme_helper.c | 68 ++++++++++++++++++++++++++++++++++ target/arm/tcg/translate-sme.c | 35 +++++++++++++++++ target/arm/tcg/sme.decode | 11 ++++++ 4 files changed, 126 insertions(+) diff --git a/target/arm/tcg/helper-sme.h b/target/arm/tcg/helper-sme.h index 8d3018fbd9..83277bdcdb 100644 --- a/target/arm/tcg/helper-sme.h +++ b/target/arm/tcg/helper-sme.h @@ -253,3 +253,15 @@ DEF_HELPER_FLAGS_3(sme2_uunpk2_sd, TCG_CALL_NO_RWG, vo= id, ptr, ptr, i32) DEF_HELPER_FLAGS_3(sme2_uunpk4_bh, TCG_CALL_NO_RWG, void, ptr, ptr, i32) DEF_HELPER_FLAGS_3(sme2_uunpk4_hs, TCG_CALL_NO_RWG, void, ptr, ptr, i32) DEF_HELPER_FLAGS_3(sme2_uunpk4_sd, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + +DEF_HELPER_FLAGS_3(sme2_zip4_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sme2_zip4_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sme2_zip4_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sme2_zip4_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sme2_zip4_q, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + +DEF_HELPER_FLAGS_3(sme2_uzp4_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sme2_uzp4_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sme2_uzp4_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sme2_uzp4_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(sme2_uzp4_q, TCG_CALL_NO_RWG, void, ptr, ptr, i32) diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index 12e86de643..f6af876286 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -1754,3 +1754,71 @@ void HELPER(sme2_fcvtl)(void *vd, void *vs, float_st= atus *fpst, uint32_t desc) d1[H4(i)] =3D v1; } } + +#define ZIP4(NAME, TYPE, H) \ +void HELPER(NAME)(void *vd, void *vs, uint32_t desc) \ +{ \ + ARMVectorReg scratch[4]; \ + size_t oprsz =3D simd_oprsz(desc); \ + size_t quads =3D oprsz / (sizeof(TYPE) * 4); \ + TYPE *s0, *s1, *s2, *s3; \ + if (vs =3D=3D vd) { \ + vs =3D memcpy(scratch, vs, sizeof(scratch)); \ + } \ + s0 =3D vs; \ + s1 =3D vs + sizeof(ARMVectorReg); \ + s2 =3D vs + 2 * sizeof(ARMVectorReg); \ + s3 =3D vs + 3 * sizeof(ARMVectorReg); \ + for (size_t r =3D 0; r < 4; ++r) { \ + TYPE *d =3D vd + r * sizeof(ARMVectorReg); \ + size_t base =3D r * quads; \ + for (size_t q =3D 0; q < quads; ++q) { \ + d[H(4 * q + 0)] =3D s0[base + H(q)]; \ + d[H(4 * q + 1)] =3D s1[base + H(q)]; \ + d[H(4 * q + 2)] =3D s2[base + H(q)]; \ + d[H(4 * q + 3)] =3D s3[base + H(q)]; \ + } \ + } \ +} + +ZIP4(sme2_zip4_b, uint8_t, H1) +ZIP4(sme2_zip4_h, uint16_t, H2) +ZIP4(sme2_zip4_s, uint32_t, H4) +ZIP4(sme2_zip4_d, uint64_t, ) +ZIP4(sme2_zip4_q, Int128, ) + +#undef ZIP4 + +#define UZP4(NAME, TYPE, H) \ +void HELPER(NAME)(void *vd, void *vs, uint32_t desc) \ +{ \ + ARMVectorReg scratch[4]; \ + size_t oprsz =3D simd_oprsz(desc); \ + size_t quads =3D oprsz / (sizeof(TYPE) * 4); \ + TYPE *d0, *d1, *d2, *d3; \ + if (vs =3D=3D vd) { \ + vs =3D memcpy(scratch, vs, sizeof(scratch)); \ + } \ + d0 =3D vd; \ + d1 =3D vd + sizeof(ARMVectorReg); \ + d2 =3D vd + 2 * sizeof(ARMVectorReg); \ + d3 =3D vd + 3 * sizeof(ARMVectorReg); \ + for (size_t r =3D 0; r < 4; ++r) { \ + TYPE *s =3D vs + r * sizeof(ARMVectorReg); \ + size_t base =3D r * quads; \ + for (size_t q =3D 0; q < quads; ++q) { \ + d0[base + H(q)] =3D s[H(4 * q + 0)]; \ + d1[base + H(q)] =3D s[H(4 * q + 1)]; \ + d2[base + H(q)] =3D s[H(4 * q + 2)]; \ + d3[base + H(q)] =3D s[H(4 * q + 3)]; \ + } \ + } \ +} + +UZP4(sme2_uzp4_b, uint8_t, H1) +UZP4(sme2_uzp4_h, uint16_t, H2) +UZP4(sme2_uzp4_s, uint32_t, H4) +UZP4(sme2_uzp4_d, uint64_t, ) +UZP4(sme2_uzp4_q, Int128, ) + +#undef UZP4 diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 6e0a1997b4..b118e34849 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -1363,3 +1363,38 @@ TRANS_FEAT(UUNPK_2sd, aa64_sme2, do_zz, a, 0, gen_he= lper_sme2_uunpk2_sd) TRANS_FEAT(UUNPK_4bh, aa64_sme2, do_zz, a, 0, gen_helper_sme2_uunpk4_bh) TRANS_FEAT(UUNPK_4hs, aa64_sme2, do_zz, a, 0, gen_helper_sme2_uunpk4_hs) TRANS_FEAT(UUNPK_4sd, aa64_sme2, do_zz, a, 0, gen_helper_sme2_uunpk4_sd) + +static bool do_zipuzp_4(DisasContext *s, arg_zz_e *a, + gen_helper_gvec_2 * const fn[5]) +{ + int svl =3D streaming_vec_reg_size(s); + + /* Both MO_64 and MO_128 can fail the size test. */ + if (svl < (4 << a->esz)) { + return false; + } + if (sme_sm_enabled_check(s)) { + tcg_gen_gvec_2_ool(vec_full_reg_offset(s, a->zd), + vec_full_reg_offset(s, a->zn), + svl, svl, 0, fn[a->esz]); + } + return true; +} + +static gen_helper_gvec_2 * const zip4_fns[] =3D { + gen_helper_sme2_zip4_b, + gen_helper_sme2_zip4_h, + gen_helper_sme2_zip4_s, + gen_helper_sme2_zip4_d, + gen_helper_sme2_zip4_q, +}; +TRANS_FEAT(ZIP_4, aa64_sme2, do_zipuzp_4, a, zip4_fns) + +static gen_helper_gvec_2 * const uzp4_fns[] =3D { + gen_helper_sme2_uzp4_b, + gen_helper_sme2_uzp4_h, + gen_helper_sme2_uzp4_s, + gen_helper_sme2_uzp4_d, + gen_helper_sme2_uzp4_q, +}; +TRANS_FEAT(UZP_4, aa64_sme2, do_zipuzp_4, a, uzp4_fns) diff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode index 1da64c5258..a43edb625c 100644 --- a/target/arm/tcg/sme.decode +++ b/target/arm/tcg/sme.decode @@ -722,6 +722,7 @@ FMLS_nx_d 11000001 1101 .... 1 .. 00. ...00 10 ..= . @azx_4x1_i1_o3 =20 ### SME2 Multi-vector SVE Constructive Unary =20 +&zz_e zd zn esz &zz_n zd zn n @zz_1x2 ........ ... ..... ...... ..... zd:5 \ &zz_n n=3D1 zn=3D%zn_ax2 @@ -799,3 +800,13 @@ SUNPK_4sd 11000001 111 10101 111000 ....0 ...00 = @zz_4x2_n1 UUNPK_4bh 11000001 011 10101 111000 ....0 ...01 @zz_4x2_n1 UUNPK_4hs 11000001 101 10101 111000 ....0 ...01 @zz_4x2_n1 UUNPK_4sd 11000001 111 10101 111000 ....0 ...01 @zz_4x2_n1 + +ZIP_4 11000001 esz:2 1 10110 111000 ...00 ... 00 \ + &zz_e zd=3D%zd_ax4 zn=3D%zn_ax4 +ZIP_4 11000001 001 10111 111000 ...00 ... 00 \ + &zz_e esz=3D4 zd=3D%zd_ax4 zn=3D%zn_ax4 + +UZP_4 11000001 esz:2 1 10110 111000 ...00 ... 10 \ + &zz_e zd=3D%zd_ax4 zn=3D%zn_ax4 +UZP_4 11000001 001 10111 111000 ...00 ... 10 \ + &zz_e esz=3D4 zd=3D%zd_ax4 zn=3D%zn_ax4 --=20 2.43.0