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Sat, 21 Jun 2025 16:50:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 010/101] linux-user/aarch64: Update hwcap bits from 6.14 Date: Sat, 21 Jun 2025 16:49:06 -0700 Message-ID: <20250621235037.74091-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250621235037.74091-1-richard.henderson@linaro.org> References: <20250621235037.74091-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1750550070803116600 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- linux-user/elfload.c | 75 ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 72 insertions(+), 3 deletions(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 82ebf6a212..2add1665c7 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -751,7 +751,23 @@ enum { ARM_HWCAP_A64_SSBS =3D 1 << 28, ARM_HWCAP_A64_SB =3D 1 << 29, ARM_HWCAP_A64_PACA =3D 1 << 30, - ARM_HWCAP_A64_PACG =3D 1UL << 31, + ARM_HWCAP_A64_PACG =3D 1ULL << 31, + ARM_HWCAP_A64_GCS =3D 1ULL << 32, + ARM_HWCAP_A64_CMPBR =3D 1ULL << 33, + ARM_HWCAP_A64_FPRCVT =3D 1ULL << 34, + ARM_HWCAP_A64_F8MM8 =3D 1ULL << 35, + ARM_HWCAP_A64_F8MM4 =3D 1ULL << 36, + ARM_HWCAP_A64_SVE_F16MM =3D 1ULL << 37, + ARM_HWCAP_A64_SVE_ELTPERM =3D 1ULL << 38, + ARM_HWCAP_A64_SVE_AES2 =3D 1ULL << 39, + ARM_HWCAP_A64_SVE_BFSCALE =3D 1ULL << 40, + ARM_HWCAP_A64_SVE2P2 =3D 1ULL << 41, + ARM_HWCAP_A64_SME2P2 =3D 1ULL << 42, + ARM_HWCAP_A64_SME_SBITPERM =3D 1ULL << 43, + ARM_HWCAP_A64_SME_AES =3D 1ULL << 44, + ARM_HWCAP_A64_SME_SFEXPA =3D 1ULL << 45, + ARM_HWCAP_A64_SME_STMOP =3D 1ULL << 46, + ARM_HWCAP_A64_SME_SMOP4 =3D 1ULL << 47, =20 ARM_HWCAP2_A64_DCPODP =3D 1 << 0, ARM_HWCAP2_A64_SVE2 =3D 1 << 1, @@ -798,6 +814,25 @@ enum { ARM_HWCAP2_A64_SME_F16F16 =3D 1ULL << 42, ARM_HWCAP2_A64_MOPS =3D 1ULL << 43, ARM_HWCAP2_A64_HBC =3D 1ULL << 44, + ARM_HWCAP2_A64_SVE_B16B16 =3D 1ULL << 45, + ARM_HWCAP2_A64_LRCPC3 =3D 1ULL << 46, + ARM_HWCAP2_A64_LSE128 =3D 1ULL << 47, + ARM_HWCAP2_A64_FPMR =3D 1ULL << 48, + ARM_HWCAP2_A64_LUT =3D 1ULL << 49, + ARM_HWCAP2_A64_FAMINMAX =3D 1ULL << 50, + ARM_HWCAP2_A64_F8CVT =3D 1ULL << 51, + ARM_HWCAP2_A64_F8FMA =3D 1ULL << 52, + ARM_HWCAP2_A64_F8DP4 =3D 1ULL << 53, + ARM_HWCAP2_A64_F8DP2 =3D 1ULL << 54, + ARM_HWCAP2_A64_F8E4M3 =3D 1ULL << 55, + ARM_HWCAP2_A64_F8E5M2 =3D 1ULL << 56, + ARM_HWCAP2_A64_SME_LUTV2 =3D 1ULL << 57, + ARM_HWCAP2_A64_SME_F8F16 =3D 1ULL << 58, + ARM_HWCAP2_A64_SME_F8F32 =3D 1ULL << 59, + ARM_HWCAP2_A64_SME_SF8FMA =3D 1ULL << 60, + ARM_HWCAP2_A64_SME_SF8DP4 =3D 1ULL << 61, + ARM_HWCAP2_A64_SME_SF8DP2 =3D 1ULL << 62, + ARM_HWCAP2_A64_POE =3D 1ULL << 63, }; =20 #define ELF_HWCAP get_elf_hwcap() @@ -886,7 +921,7 @@ uint64_t get_elf_hwcap2(void) =20 const char *elf_hwcap_str(uint32_t bit) { - static const char *hwcap_str[] =3D { + static const char * const hwcap_str[] =3D { [__builtin_ctz(ARM_HWCAP_A64_FP )] =3D "fp", [__builtin_ctz(ARM_HWCAP_A64_ASIMD )] =3D "asimd", [__builtin_ctz(ARM_HWCAP_A64_EVTSTRM )] =3D "evtstrm", @@ -919,6 +954,22 @@ const char *elf_hwcap_str(uint32_t bit) [__builtin_ctz(ARM_HWCAP_A64_SB )] =3D "sb", [__builtin_ctz(ARM_HWCAP_A64_PACA )] =3D "paca", [__builtin_ctz(ARM_HWCAP_A64_PACG )] =3D "pacg", + [__builtin_ctzll(ARM_HWCAP_A64_GCS )] =3D "gcs", + [__builtin_ctzll(ARM_HWCAP_A64_CMPBR )] =3D "cmpbr", + [__builtin_ctzll(ARM_HWCAP_A64_FPRCVT)] =3D "fprcvt", + [__builtin_ctzll(ARM_HWCAP_A64_F8MM8 )] =3D "f8mm8", + [__builtin_ctzll(ARM_HWCAP_A64_F8MM4 )] =3D "f8mm4", + [__builtin_ctzll(ARM_HWCAP_A64_SVE_F16MM)] =3D "svef16mm", + [__builtin_ctzll(ARM_HWCAP_A64_SVE_ELTPERM)] =3D "sveeltperm", + [__builtin_ctzll(ARM_HWCAP_A64_SVE_AES2)] =3D "sveaes2", + [__builtin_ctzll(ARM_HWCAP_A64_SVE_BFSCALE)] =3D "svebfscale", + [__builtin_ctzll(ARM_HWCAP_A64_SVE2P2)] =3D "sve2p2", + [__builtin_ctzll(ARM_HWCAP_A64_SME2P2)] =3D "sme2p2", + [__builtin_ctzll(ARM_HWCAP_A64_SME_SBITPERM)] =3D "smesbitperm", + [__builtin_ctzll(ARM_HWCAP_A64_SME_AES)] =3D "smeaes", + [__builtin_ctzll(ARM_HWCAP_A64_SME_SFEXPA)] =3D "smesfexpa", + [__builtin_ctzll(ARM_HWCAP_A64_SME_STMOP)] =3D "smestmop", + [__builtin_ctzll(ARM_HWCAP_A64_SME_SMOP4)] =3D "smesmop4", }; =20 return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL; @@ -926,7 +977,7 @@ const char *elf_hwcap_str(uint32_t bit) =20 const char *elf_hwcap2_str(uint32_t bit) { - static const char *hwcap_str[] =3D { + static const char * const hwcap_str[] =3D { [__builtin_ctz(ARM_HWCAP2_A64_DCPODP )] =3D "dcpodp", [__builtin_ctz(ARM_HWCAP2_A64_SVE2 )] =3D "sve2", [__builtin_ctz(ARM_HWCAP2_A64_SVEAES )] =3D "sveaes", @@ -972,6 +1023,24 @@ const char *elf_hwcap2_str(uint32_t bit) [__builtin_ctzll(ARM_HWCAP2_A64_SME_F16F16 )] =3D "smef16f16", [__builtin_ctzll(ARM_HWCAP2_A64_MOPS )] =3D "mops", [__builtin_ctzll(ARM_HWCAP2_A64_HBC )] =3D "hbc", + [__builtin_ctzll(ARM_HWCAP2_A64_SVE_B16B16 )] =3D "sveb16b16", + [__builtin_ctzll(ARM_HWCAP2_A64_LRCPC3 )] =3D "lrcpc3", + [__builtin_ctzll(ARM_HWCAP2_A64_LSE128 )] =3D "lse128", + [__builtin_ctzll(ARM_HWCAP2_A64_FPMR )] =3D "fpmr", + [__builtin_ctzll(ARM_HWCAP2_A64_LUT )] =3D "lut", + [__builtin_ctzll(ARM_HWCAP2_A64_FAMINMAX )] =3D "faminmax", + [__builtin_ctzll(ARM_HWCAP2_A64_F8CVT )] =3D "f8cvt", + [__builtin_ctzll(ARM_HWCAP2_A64_F8FMA )] =3D "f8fma", + [__builtin_ctzll(ARM_HWCAP2_A64_F8DP4 )] =3D "f8dp4", + [__builtin_ctzll(ARM_HWCAP2_A64_F8DP2 )] =3D "f8dp2", + [__builtin_ctzll(ARM_HWCAP2_A64_F8E4M3 )] =3D "f8e4m3", + [__builtin_ctzll(ARM_HWCAP2_A64_F8E5M2 )] =3D "f8e5m2", + [__builtin_ctzll(ARM_HWCAP2_A64_SME_LUTV2 )] =3D "smelutv2", + [__builtin_ctzll(ARM_HWCAP2_A64_SME_F8F16 )] =3D "smef8f16", + [__builtin_ctzll(ARM_HWCAP2_A64_SME_F8F32 )] =3D "smef8f32", + [__builtin_ctzll(ARM_HWCAP2_A64_SME_SF8DP4 )] =3D "smesf8dp4", + [__builtin_ctzll(ARM_HWCAP2_A64_SME_SF8DP2 )] =3D "smesf8dp2", + [__builtin_ctzll(ARM_HWCAP2_A64_POE )] =3D "poe", }; =20 return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL; --=20 2.43.0