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Fri, 20 Jun 2025 09:41:00 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE3JFuqE+dcd5fdcKUjRpgdDxKTjtijkxVvb+SPO11XtYAxXv/TItUZ6edJWO0hoyAyQlOheA== X-Received: by 2002:a05:6402:34cc:b0:607:35d8:4cf8 with SMTP id 4fb4d7f45d1cf-60a1ccbc846mr3361853a12.11.1750437659917; Fri, 20 Jun 2025 09:40:59 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Peter Maydell Subject: [PULL 02/24] target/i386: fix TB exit logic in gen_movl_seg() when writing to SS Date: Fri, 20 Jun 2025 18:40:30 +0200 Message-ID: <20250620164053.579416-3-pbonzini@redhat.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250620164053.579416-1-pbonzini@redhat.com> References: <20250620164053.579416-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -39 X-Spam_score: -4.0 X-Spam_bar: ---- X-Spam_report: (-4.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1750437806263116600 Content-Type: text/plain; charset="utf-8" From: Mark Cave-Ayland Before commit e54ef98c8a ("target/i386: do not trigger IRQ shadow for LSS")= , any write to SS in gen_movl_seg() would cause a TB exit. The changes introduced= by this commit were intended to restrict the DISAS_EOB_INHIBIT_IRQ exit to the= case where inhibit_irq is true, but missed that a DISAS_EOB_NEXT exit can still = be required when writing to SS and inhibit_irq is false. Comparing the PE(s) && !VM86(s) section with the logic in x86_update_hflags= (), we can see that the DISAS_EOB_NEXT exit is still required for the !CODE32 case= when writing to SS in gen_movl_seg() because any change to the SS flags can affe= ct hflags. Similarly we can see that the existing CODE32 case is still correct= since a change to any of DS, ES and SS can affect hflags. Finally for the gen_op_movl_seg_real() case an explicit TB exit is not needed because the s= egment register selector does not affect hflags. Update the logic in gen_movl_seg() so that a write to SS with inhibit_irq s= et to false where PE(s) && !VM86(s) will generate a DISAS_EOB_NEXT exit along wit= h the inline comment. This has the effect of allowing Win98SE to boot in QEMU once again. Signed-off-by: Mark Cave-Ayland Fixes: e54ef98c8a ("target/i386: do not trigger IRQ shadow for LSS") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2987 Link: https://lore.kernel.org/r/20250611130315.383151-1-mark.cave-ayland@il= ande.co.uk Reviewed-by: Peter Maydell Signed-off-by: Paolo Bonzini --- target/i386/tcg/translate.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 0fcddc2ec08..0cb87d02012 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -2033,8 +2033,11 @@ static void gen_movl_seg(DisasContext *s, X86Seg seg= _reg, TCGv src, bool inhibit tcg_gen_trunc_tl_i32(sel, src); gen_helper_load_seg(tcg_env, tcg_constant_i32(seg_reg), sel); =20 - /* For move to DS/ES/SS, the addseg or ss32 flags may change. */ - if (CODE32(s) && seg_reg < R_FS) { + /* + * For moves to SS, the SS32 flag may change. For CODE32 only, cha= nges + * to SS, DS and ES may change the ADDSEG flags. + */ + if (seg_reg =3D=3D R_SS || (CODE32(s) && seg_reg < R_FS)) { s->base.is_jmp =3D DISAS_EOB_NEXT; } } else { --=20 2.49.0