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Fri, 20 Jun 2025 06:08:19 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Leif Lindholm , Richard Henderson , Radoslaw Biernacki , Alexander Graf , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Phil Dennis-Jordan , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Bernhard Beschow , Cleber Rosa , Peter Maydell , Cameron Esfahani , kvm@vger.kernel.org, qemu-arm@nongnu.org, Eric Auger , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Thomas Huth , Roman Bolshakov , John Snow Subject: [PATCH v2 12/26] target/arm: Restrict system register properties to system binary Date: Fri, 20 Jun 2025 15:06:55 +0200 Message-ID: <20250620130709.31073-13-philmd@linaro.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250620130709.31073-1-philmd@linaro.org> References: <20250620130709.31073-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1750425102467116600 Do not expose the following system-specific properties on user-mode binaries: - psci-conduit - cntfrq (ARM_FEATURE_GENERIC_TIMER) - rvbar (ARM_FEATURE_V8) - has-mpu (ARM_FEATURE_PMSA) - pmsav7-dregion (ARM_FEATURE_PMSA) - reset-cbar (ARM_FEATURE_CBAR) - reset-hivecs (ARM_FEATURE_M) - init-nsvtor (ARM_FEATURE_M) - init-svtor (ARM_FEATURE_M_SECURITY) - idau (ARM_FEATURE_M_SECURITY) Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/cpu.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index eb0639de719..e5b70f5de81 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1500,6 +1500,7 @@ static void arm_cpu_initfn(Object *obj) * 0 means "unset, use the default value". That default might vary dependi= ng * on the CPU type, and is set in the realize fn. */ +#ifndef CONFIG_USER_ONLY static const Property arm_cpu_gt_cntfrq_property =3D DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 0); =20 @@ -1509,7 +1510,6 @@ static const Property arm_cpu_reset_cbar_property =3D static const Property arm_cpu_reset_hivecs_property =3D DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); =20 -#ifndef CONFIG_USER_ONLY static const Property arm_cpu_has_el2_property =3D DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); =20 @@ -1532,6 +1532,7 @@ static const Property arm_cpu_has_neon_property =3D static const Property arm_cpu_has_dsp_property =3D DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); =20 +#ifndef CONFIG_USER_ONLY static const Property arm_cpu_has_mpu_property =3D DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); =20 @@ -1544,6 +1545,7 @@ static const Property arm_cpu_pmsav7_dregion_property= =3D DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, pmsav7_dregion, qdev_prop_uint32, uint32_t); +#endif =20 static bool arm_get_pmu(Object *obj, Error **errp) { @@ -1731,6 +1733,7 @@ static void arm_cpu_post_init(Object *obj) "Set on/off to enable/disable aarc= h64 " "execution state "); } +#ifndef CONFIG_USER_ONLY if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property= ); @@ -1746,7 +1749,6 @@ static void arm_cpu_post_init(Object *obj) OBJ_PROP_FLAG_READWRITE); } =20 -#ifndef CONFIG_USER_ONLY if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { /* Add the has_el3 state CPU property only if EL3 is allowed. Thi= s will * prevent "has_el3" from existing on CPUs which cannot support EL= 3. @@ -1818,6 +1820,7 @@ static void arm_cpu_post_init(Object *obj) qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); } =20 +#ifndef CONFIG_USER_ONLY if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { @@ -1854,8 +1857,6 @@ static void arm_cpu_post_init(Object *obj) &cpu->psci_conduit, OBJ_PROP_FLAG_READWRITE); =20 - qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); - if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); } @@ -1864,7 +1865,6 @@ static void arm_cpu_post_init(Object *obj) kvm_arm_add_vcpu_properties(cpu); } =20 -#ifndef CONFIG_USER_ONLY if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && cpu_isar_feature(aa64_mte, cpu)) { object_property_add_link(obj, "tag-memory", @@ -1882,6 +1882,7 @@ static void arm_cpu_post_init(Object *obj) } } #endif + qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); } =20 static void arm_cpu_finalizefn(Object *obj) --=20 2.49.0