From nobody Sat Nov 15 16:30:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750410442; cv=none; d=zohomail.com; s=zohoarc; b=asrsyyxYzC9Zj3AtgiAHtLq5uk0NNIuXzKgrA6g5DC0qXIqpX4OdMplpVxGVkeg4ZNoVgjPBmg2LxxP5W86eVAJ/u1/yxxpN4rp4w/urr8ksmEaOWWk/KOMk7hU2HQfLfteyB7UbiNUB2aerFXLTWlc7OwdCm3F0mliFNHt4CTc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750410442; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=oJ969jvUOKi3o3wnC9qAp0z7kRiIZSvCNkbiy0lUeKs=; b=Dkg5SqbQaGV1rmpsbnowUHuHHkoliq9OOFthrzGAiF/YOHErLze6ZRfs2gHg3kyzsKQNWnfVTOIFOvBALuWdP6/WV/6guRKoyA8xvFmY8Jibhz4MvZbTx6DeyRmhd5sqYqlWUHnuBPBpGFuQNrXZiC3lpUNBdYye0fQg++gFYuo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750410442981211.19292254815446; Fri, 20 Jun 2025 02:07:22 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uSXi1-000198-Qe; Fri, 20 Jun 2025 05:06:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSXi0-00015R-16 for qemu-devel@nongnu.org; Fri, 20 Jun 2025 05:06:52 -0400 Received: from mgamail.intel.com ([198.175.65.14]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSXhw-0004zi-V6 for qemu-devel@nongnu.org; Fri, 20 Jun 2025 05:06:51 -0400 Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 02:06:48 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by orviesa005.jf.intel.com with ESMTP; 20 Jun 2025 02:06:44 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750410409; x=1781946409; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HrN3V1+xBd1HD2hJfjrsWV527UXP+zi/OnmT0oMwQxE=; b=hn6qLdzzNxzDjtcqnMeWrL3TOfTK4ZJs027bneq97VRepyed7K/cRNDv YKVdLv1VLED65pKv8Y/QZrYwwQjaEfuL92m7jITLqJJCSI9yMORwo4jc9 zkDhWbcsnSJHldW+trNpKL2lqDXJBxpLfv1OnyER42VWhSPHVglYnSl/e RWmOq54RzGRmtoxE7PiKqmNaib9NKchpBgo55DHTMat0SGjI43ssHGO2d ySlIQXRdk35oW6voLbjg/vy2bYQxoIC9dqYHa6hWQ3pOb2L26GGjoEql6 a7v6bn4q8OTs7feTzfIiUmP2S6KVKiFUgIvwXHFk05ljmBwxlWlLvhbkl Q==; X-CSE-ConnectionGUID: bA+ArSz4QQ+j1R7DFUyAZw== X-CSE-MsgGUID: gDuHpLA6Tli8BfpkmZ64pA== X-IronPort-AV: E=McAfee;i="6800,10657,11469"; a="56466649" X-IronPort-AV: E=Sophos;i="6.16,251,1744095600"; d="scan'208";a="56466649" X-CSE-ConnectionGUID: hR7dCHsQSM6ShvN2uk7M5A== X-CSE-MsgGUID: XFSPibD4Qhuuu5QY8k+VvA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,251,1744095600"; d="scan'208";a="156670000" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti , "Michael S . Tsirkin" , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Marcel Apfelbaum , Richard Henderson , Eduardo Habkost Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Babu Moger , Ewan Hai , Pu Wen , Tao Su , Yi Lai , Dapeng Mi , qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu Subject: [PATCH 06/16] i386/cpu: Drop CPUID 0x2 specific cache info in X86CPUState Date: Fri, 20 Jun 2025 17:27:24 +0800 Message-Id: <20250620092734.1576677-7-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620092734.1576677-1-zhao1.liu@intel.com> References: <20250620092734.1576677-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750410443522116600 Content-Type: text/plain; charset="utf-8" With the pre-defined cache model legacy_intel_cpuid2_cache_info, for X86CPUState there's no need to cache special cache information for CPUID 0x2 leaf. Drop the cache_info_cpuid2 field of X86CPUState and use the legacy_intel_cpuid2_cache_info directly. Signed-off-by: Zhao Liu Reviewed-by: Dapeng Mi --- target/i386/cpu.c | 31 +++++++++++-------------------- target/i386/cpu.h | 3 ++- 2 files changed, 13 insertions(+), 21 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index a06aa1d629dc..8f174fb971b6 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -244,19 +244,27 @@ static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *= cache, bool *unmacthed) return CACHE_DESCRIPTOR_UNAVAILABLE; } =20 +static const CPUCaches legacy_intel_cpuid2_cache_info; + /* Encode cache info for CPUID[4] */ static void encode_cache_cpuid2(X86CPU *cpu, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) { CPUX86State *env =3D &cpu->env; - CPUCaches *caches =3D &env->cache_info_cpuid2; + const CPUCaches *caches; int l1d, l1i, l2, l3; bool unmatched =3D false; =20 *eax =3D 1; /* Number of CPUID[EAX=3D2] calls required */ *ebx =3D *ecx =3D *edx =3D 0; =20 + if (env->enable_legacy_cpuid2_cache) { + caches =3D &legacy_intel_cpuid2_cache_info; + } else { + caches =3D &env->cache_info_cpuid4; + } + l1d =3D cpuid2_cache_descriptor(caches->l1d_cache, &unmatched); l1i =3D cpuid2_cache_descriptor(caches->l1i_cache, &unmatched); l2 =3D cpuid2_cache_descriptor(caches->l2_cache, &unmatched); @@ -705,17 +713,6 @@ static CPUCacheInfo legacy_l2_cache =3D { .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }; =20 -/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ -static CPUCacheInfo legacy_l2_cache_cpuid2 =3D { - .type =3D UNIFIED_CACHE, - .level =3D 2, - .size =3D 2 * MiB, - .line_size =3D 64, - .associativity =3D 8, - .share_level =3D CPU_TOPOLOGY_LEVEL_INVALID, -}; - - /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ static CPUCacheInfo legacy_l2_cache_amd =3D { .type =3D UNIFIED_CACHE, @@ -8951,18 +8948,12 @@ static void x86_cpu_realizefn(DeviceState *dev, Err= or **errp) "CPU model '%s' doesn't support legacy-cache=3Doff"= , name); return; } - env->cache_info_cpuid2 =3D env->cache_info_cpuid4 =3D env->cache_i= nfo_amd =3D - *cache_info; + env->cache_info_cpuid4 =3D env->cache_info_amd =3D *cache_info; } else { /* Build legacy cache information */ - env->cache_info_cpuid2.l1d_cache =3D &legacy_l1d_cache; - env->cache_info_cpuid2.l1i_cache =3D &legacy_l1i_cache; if (!cpu->consistent_cache) { - env->cache_info_cpuid2.l2_cache =3D &legacy_l2_cache_cpuid2; - } else { - env->cache_info_cpuid2.l2_cache =3D &legacy_l2_cache; + env->enable_legacy_cpuid2_cache =3D true; } - env->cache_info_cpuid2.l3_cache =3D &legacy_l3_cache; =20 env->cache_info_cpuid4.l1d_cache =3D &legacy_l1d_cache; env->cache_info_cpuid4.l1i_cache =3D &legacy_l1i_cache; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 3c7e59ffb12a..8d3ce8a2b678 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2076,7 +2076,8 @@ typedef struct CPUArchState { * on each CPUID leaf will be different, because we keep compatibility * with old QEMU versions. */ - CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd; + CPUCaches cache_info_cpuid4, cache_info_amd; + bool enable_legacy_cpuid2_cache; =20 /* MTRRs */ uint64_t mtrr_fixed[11]; --=20 2.34.1