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Tsirkin" , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Marcel Apfelbaum , Richard Henderson , Eduardo Habkost Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Babu Moger , Ewan Hai , Pu Wen , Tao Su , Yi Lai , Dapeng Mi , qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu Subject: [PATCH 01/16] i386/cpu: Refine comment of CPUID2CacheDescriptorInfo Date: Fri, 20 Jun 2025 17:27:19 +0800 Message-Id: <20250620092734.1576677-2-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620092734.1576677-1-zhao1.liu@intel.com> References: <20250620092734.1576677-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750410407224116600 Content-Type: text/plain; charset="utf-8" Refer to SDM vol.3 table 1-21, add the notes about the missing descriptor, and fix the typo and comment format. Signed-off-by: Zhao Liu Reviewed-by: Dapeng Mi --- target/i386/cpu.c | 31 ++++++++++++++++++++++--------- 1 file changed, 22 insertions(+), 9 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 40aefb38f6da..e398868a3f8d 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -66,6 +66,7 @@ struct CPUID2CacheDescriptorInfo { =20 /* * Known CPUID 2 cache descriptors. + * TLB, prefetch and sectored cache related descriptors are not included. * From Intel SDM Volume 2A, CPUID instruction */ struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] =3D { @@ -87,18 +88,29 @@ struct CPUID2CacheDescriptorInfo cpuid2_cache_descripto= rs[] =3D { .associativity =3D 2, .line_size =3D 64, }, [0x21] =3D { .level =3D 2, .type =3D UNIFIED_CACHE, .size =3D 256 = * KiB, .associativity =3D 8, .line_size =3D 64, }, - /* lines per sector is not supported cpuid2_cache_descriptor(), - * so descriptors 0x22, 0x23 are not included - */ + /* + * lines per sector is not supported cpuid2_cache_descriptor(), + * so descriptors 0x22, 0x23 are not included + */ [0x24] =3D { .level =3D 2, .type =3D UNIFIED_CACHE, .size =3D 1 = * MiB, .associativity =3D 16, .line_size =3D 64, }, - /* lines per sector is not supported cpuid2_cache_descriptor(), - * so descriptors 0x25, 0x20 are not included - */ + /* + * lines per sector is not supported cpuid2_cache_descriptor(), + * so descriptors 0x25, 0x29 are not included + */ [0x2C] =3D { .level =3D 1, .type =3D DATA_CACHE, .size =3D 32 = * KiB, .associativity =3D 8, .line_size =3D 64, }, [0x30] =3D { .level =3D 1, .type =3D INSTRUCTION_CACHE, .size =3D 32 = * KiB, .associativity =3D 8, .line_size =3D 64, }, + /* + * Newer Intel CPUs (having the cores without L3, e.g., Intel MTL, ARL) + * use CPUID 0x4 leaf to describe cache topology, by encoding CPUID 0x2 + * leaf with 0xFF. For older CPUs (without 0x4 leaf), it's also valid + * to just ignore l3's code if there's no l3. + * + * This already covers all the cases in QEMU, so code 0x40 is not + * included. + */ [0x41] =3D { .level =3D 2, .type =3D UNIFIED_CACHE, .size =3D 128 = * KiB, .associativity =3D 4, .line_size =3D 32, }, [0x42] =3D { .level =3D 2, .type =3D UNIFIED_CACHE, .size =3D 256 = * KiB, @@ -136,9 +148,10 @@ struct CPUID2CacheDescriptorInfo cpuid2_cache_descript= ors[] =3D { .associativity =3D 4, .line_size =3D 64, }, [0x78] =3D { .level =3D 2, .type =3D UNIFIED_CACHE, .size =3D 1 = * MiB, .associativity =3D 4, .line_size =3D 64, }, - /* lines per sector is not supported cpuid2_cache_descriptor(), - * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. - */ + /* + * lines per sector is not supported cpuid2_cache_descriptor(), + * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. + */ [0x7D] =3D { .level =3D 2, .type =3D UNIFIED_CACHE, .size =3D 2 = * MiB, .associativity =3D 8, .line_size =3D 64, }, [0x7F] =3D { .level =3D 2, .type =3D UNIFIED_CACHE, .size =3D 512 = * KiB, --=20 2.34.1