From nobody Sat Nov 15 16:32:35 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750410530; cv=none; d=zohomail.com; s=zohoarc; b=Lj0T0arJMWBhJSKuLrf8LYpEtTW++B72G3/nA928M789D+6+Gn8IEcGOEhV/zDkUrgQmFm0Ib+4ABf5ZFiDJPEcy/lo+9Zlf5sH559/Wr2t8GnHRW5awtfHhewwiJU8ch3B2a4aKUErKx41D9teGCwa3NNstp+JARzG18i2wt2w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750410530; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=uKue2fZ9GRqQvQE9Phi5YL163grW68Jr5KSOnSDtqys=; b=VgBs9rwaL+7tN7uW9ebDsbbLyFrqmWKmS2OPw/WguLoxplpvMoIuZmUvZ4bjy9phLwpbT3NMcLlbxfCWt0EytL8ZG5CJWcj4Y74m3F6NmFJsyk/3vwHLPd623tPZyELR6JEA4AEmmCd2uyBKjJxRYjyTiFgtJ85/aEguu41AL2M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750410530597285.0231718189043; Fri, 20 Jun 2025 02:08:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uSXiP-0001wB-4q; Fri, 20 Jun 2025 05:07:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSXiD-0001TL-JD for qemu-devel@nongnu.org; Fri, 20 Jun 2025 05:07:08 -0400 Received: from mgamail.intel.com ([198.175.65.14]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSXiA-0004zi-L4 for qemu-devel@nongnu.org; Fri, 20 Jun 2025 05:07:05 -0400 Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 02:07:02 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by orviesa005.jf.intel.com with ESMTP; 20 Jun 2025 02:06:58 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750410423; x=1781946423; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=N4GITYpWdJ1HERjdysXD4ZPZutg2U4OiYFYUeFIS6iM=; b=DKcOAMVd1g/pwo1839d2+RUwpMrUiKAIpBF791uAJZFa9PxiGJ4GWEf5 g9yudlHrr14ni8iiMMUTwEbGo/Vk+rhZoD/ktiEax8DtQV2Ko4c4mKJeQ mFiPTAMCQlE3jU65cy+Q/SV7FuhiDof+SiU7ELJzrL7hP/O7Fjmspmki/ +JXbm9/jlr7r/TVkjJt6Phym2j/2XwIN3qmOFe+0dPSOcO+yn1ZqnCFFl xl8D2UWvDy4kN+3h6ztZh6WOucuQ+n0sJJaRNmgjW46lnhR/0I6ebW5me UsNfNbDdMz3x44cw7W/0rGcanJx7dIhSPI0ItIQng9khw/oFsoXtoTrjT w==; X-CSE-ConnectionGUID: RIGGyGVrTfyxyS5mXRxiYg== X-CSE-MsgGUID: +b7fT8tpTtCiuZmaO1qC1g== X-IronPort-AV: E=McAfee;i="6800,10657,11469"; a="56466742" X-IronPort-AV: E=Sophos;i="6.16,251,1744095600"; d="scan'208";a="56466742" X-CSE-ConnectionGUID: T03zHKGqSaSLlO+61lfE1w== X-CSE-MsgGUID: xMTKnt6PSR+jly6fF/X7LQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,251,1744095600"; d="scan'208";a="156670103" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti , "Michael S . Tsirkin" , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Marcel Apfelbaum , Richard Henderson , Eduardo Habkost Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Babu Moger , Ewan Hai , Pu Wen , Tao Su , Yi Lai , Dapeng Mi , qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu Subject: [PATCH 09/16] i386/cpu: Add legacy_intel_cache_info cache model Date: Fri, 20 Jun 2025 17:27:27 +0800 Message-Id: <20250620092734.1576677-10-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620092734.1576677-1-zhao1.liu@intel.com> References: <20250620092734.1576677-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750410532422116600 Content-Type: text/plain; charset="utf-8" Based on legacy_l1d_cache, legacy_l1i_cache, legacy_l2_cache and legacy_l3_cache, build a complete legacy intel cache model, which can clarify the purpose of these trivial legacy cache models, simplify the initialization of cache info in X86CPUState, and make it easier to handle compatibility later. Signed-off-by: Zhao Liu Reviewed-by: Dapeng Mi --- target/i386/cpu.c | 101 +++++++++++++++++++++++++--------------------- 1 file changed, 54 insertions(+), 47 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 0b292aa2e07b..ec229830c532 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -643,21 +643,6 @@ static void encode_topo_cpuid8000001e(X86CPU *cpu, X86= CPUTopoInfo *topo_info, * These are legacy cache values. If there is a need to change any * of these values please use builtin_x86_defs */ - -/* L1 data cache: */ -static CPUCacheInfo legacy_l1d_cache =3D { - .type =3D DATA_CACHE, - .level =3D 1, - .size =3D 32 * KiB, - .self_init =3D 1, - .line_size =3D 64, - .associativity =3D 8, - .sets =3D 64, - .partitions =3D 1, - .no_invd_sharing =3D true, - .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, -}; - static CPUCacheInfo legacy_l1d_cache_amd =3D { .type =3D DATA_CACHE, .level =3D 1, @@ -672,20 +657,6 @@ static CPUCacheInfo legacy_l1d_cache_amd =3D { .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }; =20 -/* L1 instruction cache: */ -static CPUCacheInfo legacy_l1i_cache =3D { - .type =3D INSTRUCTION_CACHE, - .level =3D 1, - .size =3D 32 * KiB, - .self_init =3D 1, - .line_size =3D 64, - .associativity =3D 8, - .sets =3D 64, - .partitions =3D 1, - .no_invd_sharing =3D true, - .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, -}; - static CPUCacheInfo legacy_l1i_cache_amd =3D { .type =3D INSTRUCTION_CACHE, .level =3D 1, @@ -700,20 +671,6 @@ static CPUCacheInfo legacy_l1i_cache_amd =3D { .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }; =20 -/* Level 2 unified cache: */ -static CPUCacheInfo legacy_l2_cache =3D { - .type =3D UNIFIED_CACHE, - .level =3D 2, - .size =3D 4 * MiB, - .self_init =3D 1, - .line_size =3D 64, - .associativity =3D 16, - .sets =3D 4096, - .partitions =3D 1, - .no_invd_sharing =3D true, - .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, -}; - static CPUCacheInfo legacy_l2_cache_amd =3D { .type =3D UNIFIED_CACHE, .level =3D 2, @@ -803,6 +760,59 @@ static const CPUCaches legacy_intel_cpuid2_cache_info = =3D { }, }; =20 +static const CPUCaches legacy_intel_cache_info =3D { + .l1d_cache =3D &(CPUCacheInfo) { + .type =3D DATA_CACHE, + .level =3D 1, + .size =3D 32 * KiB, + .self_init =3D 1, + .line_size =3D 64, + .associativity =3D 8, + .sets =3D 64, + .partitions =3D 1, + .no_invd_sharing =3D true, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l1i_cache =3D &(CPUCacheInfo) { + .type =3D INSTRUCTION_CACHE, + .level =3D 1, + .size =3D 32 * KiB, + .self_init =3D 1, + .line_size =3D 64, + .associativity =3D 8, + .sets =3D 64, + .partitions =3D 1, + .no_invd_sharing =3D true, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l2_cache =3D &(CPUCacheInfo) { + .type =3D UNIFIED_CACHE, + .level =3D 2, + .size =3D 4 * MiB, + .self_init =3D 1, + .line_size =3D 64, + .associativity =3D 16, + .sets =3D 4096, + .partitions =3D 1, + .no_invd_sharing =3D true, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l3_cache =3D &(CPUCacheInfo) { + .type =3D UNIFIED_CACHE, + .level =3D 3, + .size =3D 16 * MiB, + .line_size =3D 64, + .associativity =3D 16, + .sets =3D 16384, + .partitions =3D 1, + .lines_per_tag =3D 1, + .self_init =3D true, + .inclusive =3D true, + .complex_indexing =3D true, + .share_level =3D CPU_TOPOLOGY_LEVEL_DIE, + }, +}; + /* TLB definitions: */ =20 #define L1_DTLB_2M_ASSOC 1 @@ -8971,10 +8981,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Erro= r **errp) env->enable_legacy_cpuid2_cache =3D true; } =20 - env->cache_info_cpuid4.l1d_cache =3D &legacy_l1d_cache; - env->cache_info_cpuid4.l1i_cache =3D &legacy_l1i_cache; - env->cache_info_cpuid4.l2_cache =3D &legacy_l2_cache; - env->cache_info_cpuid4.l3_cache =3D &legacy_l3_cache; + env->cache_info_cpuid4 =3D legacy_intel_cache_info; =20 env->cache_info_amd.l1d_cache =3D &legacy_l1d_cache_amd; env->cache_info_amd.l1i_cache =3D &legacy_l1i_cache_amd; --=20 2.34.1