From nobody Sat Nov 15 14:49:51 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750410405; cv=none; d=zohomail.com; s=zohoarc; b=WuAWp/jjEDtSjQvqSSayQLu37eFK/K5lFgY9davEwwqhoG2VQbGzvsy1ycsSXjESMxd/Rpb7PHTwalI+dpZEE5lAtziVjJg99wyFvNfozE762Efa4RA3HQzefMGDOnDqekXD5Yi9kXR1YeEELjCF6ImbQGVrkxxuNHaGwVZFZYM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750410405; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=DZo9j9uxA+T2ODw5JNaVatIjYoZPo8y2Orf0QqKiUlE=; b=gJyPAuh5VnL7PdyUil+6/aEe8guZMLNYFkitOOzw9N5W5BpAdv//wRcHdFbd6WqPSd+nSbxm7TtlQIGo+ADOIK/o8qxmcNxiyIvHZWv79gqIsVxhIkef1Z20Cz8h9L1gV2u02XyQqhZAw5+kCBA7DfCH5IiXs+hGV9bsi31fdaI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750410405465604.6005290803663; Fri, 20 Jun 2025 02:06:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uSXhk-0000nS-44; Fri, 20 Jun 2025 05:06:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSXhg-0000hW-7v for qemu-devel@nongnu.org; Fri, 20 Jun 2025 05:06:32 -0400 Received: from mgamail.intel.com ([198.175.65.14]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSXhc-0004yv-HY for qemu-devel@nongnu.org; Fri, 20 Jun 2025 05:06:31 -0400 Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 02:06:26 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by orviesa005.jf.intel.com with ESMTP; 20 Jun 2025 02:06:22 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750410389; x=1781946389; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=f7u0fAdjZivukx2yOZWHoGvHXSLSvSk4BLW4LAo7h8s=; b=W0D6cFrekpW+tY40j+GJKFyL5sAE7nGVCGJAyrfDz8SDQ+lMWmDmsY0c AIu1mASLJcmntVVOCf0ifBhMa1DDCTgGj0sBqsHhYcEycfkUpEfqTZ1qw vGdgUX4jQsJhrh9RJ5Zru65PmOg9Ne2p7kF/ypvEFrOSigIv6yAvVWpRy 7pHU7MGhzl2IZUcQTl1Hoozha9u79TgLaQtAlhiIzmG0Dof2T6FjXgvIa blCKOamCIgJ23ZZgrvICU6/hfPlSF+RIp4sFbmKMt7aVQD+Qn19zrzw/F kCM7lMpoqZGu3mNPAHhfcZmKuGpZHjnMo78uyzSY/Mj2X0E5j80kvRui9 w==; X-CSE-ConnectionGUID: XJUG1QUrTYWdFZhw9TvB7w== X-CSE-MsgGUID: WxPdSxv7QymsjQUSZTf/qQ== X-IronPort-AV: E=McAfee;i="6800,10657,11469"; a="56466526" X-IronPort-AV: E=Sophos;i="6.16,251,1744095600"; d="scan'208";a="56466526" X-CSE-ConnectionGUID: 6WY3sepyRWarjz00DPUjdg== X-CSE-MsgGUID: jFb76fb9R0i+7QDm3tLisQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,251,1744095600"; d="scan'208";a="156669805" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti , "Michael S . Tsirkin" , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Marcel Apfelbaum , Richard Henderson , Eduardo Habkost Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Babu Moger , Ewan Hai , Pu Wen , Tao Su , Yi Lai , Dapeng Mi , qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu Subject: [PATCH 01/16] i386/cpu: Refine comment of CPUID2CacheDescriptorInfo Date: Fri, 20 Jun 2025 17:27:19 +0800 Message-Id: <20250620092734.1576677-2-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620092734.1576677-1-zhao1.liu@intel.com> References: <20250620092734.1576677-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750410407224116600 Content-Type: text/plain; charset="utf-8" Refer to SDM vol.3 table 1-21, add the notes about the missing descriptor, and fix the typo and comment format. Signed-off-by: Zhao Liu Reviewed-by: Dapeng Mi --- target/i386/cpu.c | 31 ++++++++++++++++++++++--------- 1 file changed, 22 insertions(+), 9 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 40aefb38f6da..e398868a3f8d 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -66,6 +66,7 @@ struct CPUID2CacheDescriptorInfo { =20 /* * Known CPUID 2 cache descriptors. + * TLB, prefetch and sectored cache related descriptors are not included. * From Intel SDM Volume 2A, CPUID instruction */ struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] =3D { @@ -87,18 +88,29 @@ struct CPUID2CacheDescriptorInfo cpuid2_cache_descripto= rs[] =3D { .associativity =3D 2, .line_size =3D 64, }, [0x21] =3D { .level =3D 2, .type =3D UNIFIED_CACHE, .size =3D 256 = * KiB, .associativity =3D 8, .line_size =3D 64, }, - /* lines per sector is not supported cpuid2_cache_descriptor(), - * so descriptors 0x22, 0x23 are not included - */ + /* + * lines per sector is not supported cpuid2_cache_descriptor(), + * so descriptors 0x22, 0x23 are not included + */ [0x24] =3D { .level =3D 2, .type =3D UNIFIED_CACHE, .size =3D 1 = * MiB, .associativity =3D 16, .line_size =3D 64, }, - /* lines per sector is not supported cpuid2_cache_descriptor(), - * so descriptors 0x25, 0x20 are not included - */ + /* + * lines per sector is not supported cpuid2_cache_descriptor(), + * so descriptors 0x25, 0x29 are not included + */ [0x2C] =3D { .level =3D 1, .type =3D DATA_CACHE, .size =3D 32 = * KiB, .associativity =3D 8, .line_size =3D 64, }, [0x30] =3D { .level =3D 1, .type =3D INSTRUCTION_CACHE, .size =3D 32 = * KiB, .associativity =3D 8, .line_size =3D 64, }, + /* + * Newer Intel CPUs (having the cores without L3, e.g., Intel MTL, ARL) + * use CPUID 0x4 leaf to describe cache topology, by encoding CPUID 0x2 + * leaf with 0xFF. For older CPUs (without 0x4 leaf), it's also valid + * to just ignore l3's code if there's no l3. + * + * This already covers all the cases in QEMU, so code 0x40 is not + * included. + */ [0x41] =3D { .level =3D 2, .type =3D UNIFIED_CACHE, .size =3D 128 = * KiB, .associativity =3D 4, .line_size =3D 32, }, [0x42] =3D { .level =3D 2, .type =3D UNIFIED_CACHE, .size =3D 256 = * KiB, @@ -136,9 +148,10 @@ struct CPUID2CacheDescriptorInfo cpuid2_cache_descript= ors[] =3D { .associativity =3D 4, .line_size =3D 64, }, [0x78] =3D { .level =3D 2, .type =3D UNIFIED_CACHE, .size =3D 1 = * MiB, .associativity =3D 4, .line_size =3D 64, }, - /* lines per sector is not supported cpuid2_cache_descriptor(), - * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. - */ + /* + * lines per sector is not supported cpuid2_cache_descriptor(), + * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. + */ [0x7D] =3D { .level =3D 2, .type =3D UNIFIED_CACHE, .size =3D 2 = * MiB, .associativity =3D 8, .line_size =3D 64, }, [0x7F] =3D { .level =3D 2, .type =3D UNIFIED_CACHE, .size =3D 512 = * KiB, --=20 2.34.1 From nobody Sat Nov 15 14:49:51 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750410413; cv=none; d=zohomail.com; s=zohoarc; b=BFP3idvJyjJsH0CCtLwRQWJ0LMVqvcP/iQ0CIs1Yn0mStlK7qgZyUEmmqbgnw1XsEZHpb8PpEb3hNDzpi9sswtueAGRO4MZyHJCDfJzhU38G0I7JnxNKKYq6KoFLggQurvwAb2ukxvZa7dO+NA+igd7+2r0w6lDVnJn/OH9lDV8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750410413; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=oG20ivn5NbbUEzEDnpzW3Ul7KjXgRCx5vF1xxJIlGJs=; b=XLvIcNHbTbQmVck1PnkcULRd08bVKcfbKsri3dINuYqqrcHVbnV0jgqWdw1ulkwMfgtjH6nLf68z0xOUulHL05t0T/PMokD+eC88Azqv72imprcxIZ0y+mvIihcL7OEH8rI62M9zMJXVW+HARekYXibFv0F3P0/gb4oETQ/EGQM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750410413279824.3189671364472; Fri, 20 Jun 2025 02:06:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uSXhl-0000pT-6k; Fri, 20 Jun 2025 05:06:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSXhj-0000m9-9H for qemu-devel@nongnu.org; Fri, 20 Jun 2025 05:06:35 -0400 Received: from mgamail.intel.com ([198.175.65.14]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSXhg-0004zi-HS for qemu-devel@nongnu.org; Fri, 20 Jun 2025 05:06:34 -0400 Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 02:06:30 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by orviesa005.jf.intel.com with ESMTP; 20 Jun 2025 02:06:26 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750410393; x=1781946393; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rP+3yIcVeLITlIOtxWUE53+6FM+a8wwBuKQISSU42FQ=; b=ahNPlHuPqEpSapTctKR17D+biHHg9iihYHXqujkwhhG22wsMDVMArSyQ UvxapnNP+1CD8qnk3WeS/pkK9BDkH7gmXqID954FLzUcFHWegu2TwrZEQ Oi2oPO4JVvU9Zv52cdJKMdbMwyC2W9jcQ+QG+FszahSRiuHGvoipRxQ/P z/XgF3MD/qTe9aXbU36nDto/egAwHLLMqW8ISzISp3dFe2473YGJXGMAE vkjuhB9FXojtwBcuzvntkPWeUkWLSPmIqC+JCbz16Fpu2I8Fx9/WgpV4K gooz8XyZ0gUIuRmaKXJmA/7wj8M5rGszj8Xb7c/fYPZSu4DYG59QmS35T w==; X-CSE-ConnectionGUID: Z1eHX2jQQEecTL5FfraJSg== X-CSE-MsgGUID: H53/NOqnQyKSS1EoisaVjg== X-IronPort-AV: E=McAfee;i="6800,10657,11469"; a="56466542" X-IronPort-AV: E=Sophos;i="6.16,251,1744095600"; d="scan'208";a="56466542" X-CSE-ConnectionGUID: QlVPWsGrQ9KlMS6Oe37+hQ== X-CSE-MsgGUID: dwkM4O6vRBqtU+YqP+El+Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,251,1744095600"; d="scan'208";a="156669847" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti , "Michael S . Tsirkin" , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Marcel Apfelbaum , Richard Henderson , Eduardo Habkost Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Babu Moger , Ewan Hai , Pu Wen , Tao Su , Yi Lai , Dapeng Mi , qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu Subject: [PATCH 02/16] i386/cpu: Add descriptor 0x49 for CPUID 0x2 encoding Date: Fri, 20 Jun 2025 17:27:20 +0800 Message-Id: <20250620092734.1576677-3-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620092734.1576677-1-zhao1.liu@intel.com> References: <20250620092734.1576677-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750410415269116600 Content-Type: text/plain; charset="utf-8" The legacy_l2_cache (2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size) corresponds to descriptor 0x49, but at present cpuid2_cache_descriptors doesn't support descriptor 0x49 because it has multiple meanings. The 0x49 is necessary when CPUID 0x2 and 0x4 leaves have the consistent cache model, and use legacy_l2_cache as the default l2 cache. Therefore, add descriptor 0x49 to represent general l2 cache. Signed-off-by: Zhao Liu Reviewed-by: Dapeng Mi --- target/i386/cpu.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e398868a3f8d..995766c9d74c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -127,7 +127,18 @@ struct CPUID2CacheDescriptorInfo cpuid2_cache_descript= ors[] =3D { .associativity =3D 8, .line_size =3D 64, }, [0x48] =3D { .level =3D 2, .type =3D UNIFIED_CACHE, .size =3D 3 = * MiB, .associativity =3D 12, .line_size =3D 64, }, - /* Descriptor 0x49 depends on CPU family/model, so it is not included = */ + /* + * Descriptor 0x49 has 2 cases: + * - 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line s= ize. + * - 3rd-level cache: 4MB, 16-way set associative, 64-byte line size + * (Intel Xeon processor MP, Family 0FH, Model 06H). + * + * When it represents l3, then it depends on CPU family/model. Fortuna= tely, + * the legacy cache/CPU models don't have such special l3. So, just ad= d it + * to represent the general l2 case. + */ + [0x49] =3D { .level =3D 2, .type =3D UNIFIED_CACHE, .size =3D 4 = * MiB, + .associativity =3D 16, .line_size =3D 64, }, [0x4A] =3D { .level =3D 3, .type =3D UNIFIED_CACHE, .size =3D 6 = * MiB, .associativity =3D 12, .line_size =3D 64, }, [0x4B] =3D { .level =3D 3, .type =3D UNIFIED_CACHE, .size =3D 8 = * MiB, --=20 2.34.1 From nobody Sat Nov 15 14:49:51 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750410448; cv=none; d=zohomail.com; s=zohoarc; b=UgnKiMNU/tbqgVovUdGaT5ApmRUF0nHJOUhyfL3qLifdzxejpxUwaJIS668VFSVptFfaddZAGEHT/hIUhWXjBhsYD0SXGJRj9fL+tf1r9IMn1FxjsnoQQLqULSCDiXL1Sd9oG7Oy6u4uA75e48ikJJwdlPEzYoL68sZcUbh/ElQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750410448; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=2K7ZILuZryrEfFVGz+xR1fObf4Nt7QuCRBeqF/SK06E=; b=eETi1vXwTd6vb6gZQF51HOGpj4p0DM4gfLmSM4lM+cW8eT4HljOKXF3A/osRmkOVZG+XKu3dLCxckePpcPNUTiJXLjwAJyUDjf9cvV7QqfpeUFdfQp+jQAlTC3UxBwKbFDBlZtlb1KG9QWUGiHfheLYG/JK5f0RvNPY4Yo9ER1E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750410448116455.9946611728644; Fri, 20 Jun 2025 02:07:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uSXhm-0000rV-PW; Fri, 20 Jun 2025 05:06:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSXhl-0000pr-Bn for qemu-devel@nongnu.org; Fri, 20 Jun 2025 05:06:37 -0400 Received: from mgamail.intel.com ([198.175.65.14]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSXhj-0004zi-9H for qemu-devel@nongnu.org; Fri, 20 Jun 2025 05:06:37 -0400 Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 02:06:35 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by orviesa005.jf.intel.com with ESMTP; 20 Jun 2025 02:06:31 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750410396; x=1781946396; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/UaWvm7TqZVE24eodszyVbZ46tgQZ07UFSiLrizRDTM=; b=VNURZ128VzqmCvyvb+TTMzByrCb7EBNSCt6S5X8kSabQ0EMe8tQv5x9N BUYgmZHS2qgAzPt3OurDQRgxwmEftCBOvuKPQ5BE5F8MB2T1x5LIDpCn3 IYD/470d/xTAo7+nNP5VxWOu3wveA6EDufwwHmEKU810ccI4ETQ1UTtDK IzyCGPCpr9f8muk8N1Tgq3LbC6BFNQ60aD5X1RNiYav9hzdOeVmDcPyQc 4hzlrfGD4zFBCRAX9E4eeGQSW0HPGxBBytfDWPUXIuIjaNHt6Z8toPjNp aked/a/aPRNnBl8LRv6Jc19QxSsX27GrP2ouzPddgqGJ3WLmI1uy9pbpy Q==; X-CSE-ConnectionGUID: dTOCzfaJSDqCYPXSPLYkiw== X-CSE-MsgGUID: ujHlwsoWQAel0DIHp9r12w== X-IronPort-AV: E=McAfee;i="6800,10657,11469"; a="56466562" X-IronPort-AV: E=Sophos;i="6.16,251,1744095600"; d="scan'208";a="56466562" X-CSE-ConnectionGUID: V4s4attrReSLiNu1PEuN/w== X-CSE-MsgGUID: He37ufVcT3yAob1jJWhqnA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,251,1744095600"; d="scan'208";a="156669869" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti , "Michael S . Tsirkin" , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Marcel Apfelbaum , Richard Henderson , Eduardo Habkost Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Babu Moger , Ewan Hai , Pu Wen , Tao Su , Yi Lai , Dapeng Mi , qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu Subject: [PATCH 03/16] i386/cpu: Add default cache model for Intel CPUs with level < 4 Date: Fri, 20 Jun 2025 17:27:21 +0800 Message-Id: <20250620092734.1576677-4-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620092734.1576677-1-zhao1.liu@intel.com> References: <20250620092734.1576677-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750410449444116600 Content-Type: text/plain; charset="utf-8" Old Intel CPUs with CPUID level < 4, use CPUID 0x2 leaf (if available) to encode cache information. Introduce a cache model "legacy_intel_cpuid2_cache_info" for the CPUs with CPUID level < 4, based on legacy_l1d_cache, legacy_l1i_cache, legacy_l2_cache_cpuid2 and legacy_l3_cache. But for L2 cache, this cache model completes self_init, sets, partitions, no_invd_sharing and share_level fields, referring legacy_l2_cache, to avoid someone increases CPUID level manually and meets assert() error. But the cache information present in CPUID 0x2 leaf doesn't change. This new cache model makes it possible to remove legacy_l2_cache_cpuid2 in X86CPUState and help to clarify historical cache inconsistency issue. Furthermore, apply this legacy cache model to all Intel CPUs with CPUID level < 4. This includes not only "pentium2" and "pentium3" (which have 0x2 leaf), but also "486" and "pentium" (which only have 0x1 leaf, and cache model won't be presented, just for simplicity). A legacy_intel_cpuid2_cache_info cache model doesn't change the cache information of the above CPUs, because they just depend on 0x2 leaf. Only when someone adjusts the min-level to >=3D4 will the cache information in CPUID leaf 4 differ from before: previously, the L2 cache information in CPUID leaf 0x2 and 0x4 was different, but now with legacy_intel_cpuid2_cache_info, the information they present will be consistent. This case almost never happens, emulating a CPUID that is not supported by the "ancient" hardware is itself meaningless behavior. Therefore, even though there's the above difference (for really rare case) and considering these old CPUs ("486", "pentium", "pentium2" and "pentium3") won't be used for migration, there's no need to add new versioned CPU models Signed-off-by: Zhao Liu --- target/i386/cpu.c | 65 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 995766c9d74c..0a2c32214cc3 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -710,6 +710,67 @@ static CPUCacheInfo legacy_l3_cache =3D { .share_level =3D CPU_TOPOLOGY_LEVEL_DIE, }; =20 +/* + * Only used for the CPU models with CPUID level < 4. + * These CPUs (CPUID level < 4) only use CPUID leaf 2 to present + * cache information. + * + * Note: This cache model is just a default one, and is not + * guaranteed to match real hardwares. + */ +static const CPUCaches legacy_intel_cpuid2_cache_info =3D { + .l1d_cache =3D &(CPUCacheInfo) { + .type =3D DATA_CACHE, + .level =3D 1, + .size =3D 32 * KiB, + .self_init =3D 1, + .line_size =3D 64, + .associativity =3D 8, + .sets =3D 64, + .partitions =3D 1, + .no_invd_sharing =3D true, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l1i_cache =3D &(CPUCacheInfo) { + .type =3D INSTRUCTION_CACHE, + .level =3D 1, + .size =3D 32 * KiB, + .self_init =3D 1, + .line_size =3D 64, + .associativity =3D 8, + .sets =3D 64, + .partitions =3D 1, + .no_invd_sharing =3D true, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l2_cache =3D &(CPUCacheInfo) { + .type =3D UNIFIED_CACHE, + .level =3D 2, + .size =3D 2 * MiB, + .self_init =3D 1, + .line_size =3D 64, + .associativity =3D 8, + .sets =3D 4096, + .partitions =3D 1, + .no_invd_sharing =3D true, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l3_cache =3D &(CPUCacheInfo) { + .type =3D UNIFIED_CACHE, + .level =3D 3, + .size =3D 16 * MiB, + .line_size =3D 64, + .associativity =3D 16, + .sets =3D 16384, + .partitions =3D 1, + .lines_per_tag =3D 1, + .self_init =3D true, + .inclusive =3D true, + .complex_indexing =3D true, + .share_level =3D CPU_TOPOLOGY_LEVEL_DIE, + }, +}; + /* TLB definitions: */ =20 #define L1_DTLB_2M_ASSOC 1 @@ -3043,6 +3104,7 @@ static const X86CPUDefinition builtin_x86_defs[] =3D { I486_FEATURES, .xlevel =3D 0, .model_id =3D "", + .cache_info =3D &legacy_intel_cpuid2_cache_info, }, { .name =3D "pentium", @@ -3055,6 +3117,7 @@ static const X86CPUDefinition builtin_x86_defs[] =3D { PENTIUM_FEATURES, .xlevel =3D 0, .model_id =3D "", + .cache_info =3D &legacy_intel_cpuid2_cache_info, }, { .name =3D "pentium2", @@ -3067,6 +3130,7 @@ static const X86CPUDefinition builtin_x86_defs[] =3D { PENTIUM2_FEATURES, .xlevel =3D 0, .model_id =3D "", + .cache_info =3D &legacy_intel_cpuid2_cache_info, }, { .name =3D "pentium3", @@ -3079,6 +3143,7 @@ static const X86CPUDefinition builtin_x86_defs[] =3D { PENTIUM3_FEATURES, .xlevel =3D 0, .model_id =3D "", + .cache_info =3D &legacy_intel_cpuid2_cache_info, }, { .name =3D "athlon", --=20 2.34.1 From nobody Sat Nov 15 14:49:51 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a="56466582" X-IronPort-AV: E=Sophos;i="6.16,251,1744095600"; d="scan'208";a="56466582" X-CSE-ConnectionGUID: r8fJHho0T6C17B8i5ra8NA== X-CSE-MsgGUID: EOkdRgeMQcu9AI8h9Cym3Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,251,1744095600"; d="scan'208";a="156669904" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti , "Michael S . Tsirkin" , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Marcel Apfelbaum , Richard Henderson , Eduardo Habkost Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Babu Moger , Ewan Hai , Pu Wen , Tao Su , Yi Lai , Dapeng Mi , qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu , Alexander Graf Subject: [PATCH 04/16] i386/cpu: Present same cache model in CPUID 0x2 & 0x4 Date: Fri, 20 Jun 2025 17:27:22 +0800 Message-Id: <20250620092734.1576677-5-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620092734.1576677-1-zhao1.liu@intel.com> References: <20250620092734.1576677-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750410417500116600 Content-Type: text/plain; charset="utf-8" For a long time, the default cache models used in CPUID 0x2 and 0x4 were inconsistent and had a FIXME note from Eduardo at commit 5e891bf8fd50 ("target-i386: Use #defines instead of magic numbers for CPUID cache info"): "/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */". This difference is wrong, in principle, both 0x2 and 0x4 are used for Intel's cache description. 0x2 leaf is used for ancient machines while 0x4 leaf is a subsequent addition, and both should be based on the same cache model. Furthermore, on real hardware, 0x4 leaf should be used in preference to 0x2 when it is available. Revisiting the git history, that difference occurred much earlier. Current legacy_l2_cache_cpuid2 (hardcode: "0x2c307d"), which is used for CPUID 0x2 leaf, is introduced in commit d8134d91d9b7 ("Intel cache info, by Filip Navara."). Its commit message didn't said anything, but its patch [1] mentioned the cache model chosen is "closest to the ones reported in the AMD registers". Now it is not possible to check which AMD generation this cache model is based on (unfortunately, AMD does not use 0x2 leaf), but at least it is close to the Pentium 4. In fact, the patch description of commit d8134d91d9b7 is also a bit wrong, the original cache model in leaf 2 is from Pentium Pro, and its cache descriptor had specified the cache line size ad 32 byte by default, while the updated cache model in commit d8134d91d9b7 has 64 byte line size. But after so many years, such judgments are no longer meaningful. On the other hand, for legacy_l2_cache, which is used in CPUID 0x4 leaf, is based on Intel Core Duo (patch [2]) and Core2 Duo (commit e737b32a3688 ("Core 2 Duo specification (Alexander Graf).") The patches of Core Duo and Core 2 Duo add the cache model for CPUID 0x4, but did not update CPUID 0x2 encoding. This is the reason that Intel Guests use two cache models in 0x2 and 0x4 all the time. Of course, while no Core Duo or Core 2 Duo machines have been found for double checking, this still makes no sense to encode different cache models on a single machine. Referring to the SDM and the real hardware available, 0x2 leaf can be directly encoded 0xFF to instruct software to go to 0x4 leaf to get the cache information, when 0x4 is available. Therefore, it's time to clean up Intel's default cache models. As the first step, add "x-consistent-cache" compat option to allow newer machines (v10.1 and newer) to have the consistent cache model in CPUID 0x2 and 0x4 leaves. This doesn't affect the CPU models with CPUID level < 4 ("486", "pentium", "pentium2" and "pentium3"), because they have already had the special default cache model - legacy_intel_cpuid2_cache_info. [1]: https://lore.kernel.org/qemu-devel/5b31733c0709081227w3e5f1036odbc649e= dfdc8c79b@mail.gmail.com/ [2]: https://lore.kernel.org/qemu-devel/478B65C8.2080602@csgraf.de/ Cc: Alexander Graf Signed-off-by: Zhao Liu --- hw/i386/pc.c | 4 +++- target/i386/cpu.c | 7 ++++++- target/i386/cpu.h | 7 +++++++ 3 files changed, 16 insertions(+), 2 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index b2116335752d..ad2d6495ebde 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -81,7 +81,9 @@ { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }= ,\ { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, =20 -GlobalProperty pc_compat_10_0[] =3D {}; +GlobalProperty pc_compat_10_0[] =3D { + { TYPE_X86_CPU, "x-consistent-cache", "false" }, +}; const size_t pc_compat_10_0_len =3D G_N_ELEMENTS(pc_compat_10_0); =20 GlobalProperty pc_compat_9_2[] =3D {}; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 0a2c32214cc3..2f895bf13523 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8931,7 +8931,11 @@ static void x86_cpu_realizefn(DeviceState *dev, Erro= r **errp) /* Build legacy cache information */ env->cache_info_cpuid2.l1d_cache =3D &legacy_l1d_cache; env->cache_info_cpuid2.l1i_cache =3D &legacy_l1i_cache; - env->cache_info_cpuid2.l2_cache =3D &legacy_l2_cache_cpuid2; + if (!cpu->consistent_cache) { + env->cache_info_cpuid2.l2_cache =3D &legacy_l2_cache_cpuid2; + } else { + env->cache_info_cpuid2.l2_cache =3D &legacy_l2_cache; + } env->cache_info_cpuid2.l3_cache =3D &legacy_l3_cache; =20 env->cache_info_cpuid4.l1d_cache =3D &legacy_l1d_cache; @@ -9457,6 +9461,7 @@ static const Property x86_cpu_properties[] =3D { * own cache information (see x86_cpu_load_def()). */ DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), + DEFINE_PROP_BOOL("x-consistent-cache", X86CPU, consistent_cache, true), DEFINE_PROP_BOOL("legacy-multi-node", X86CPU, legacy_multi_node, false= ), DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false), =20 diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 5910dcf74d42..3c7e59ffb12a 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2259,6 +2259,13 @@ struct ArchCPU { */ bool legacy_cache; =20 + /* + * Compatibility bits for old machine types. + * If true, use the same cache model in CPUID leaf 0x2 + * and 0x4. + */ + bool consistent_cache; + /* Compatibility bits for old machine types. * If true decode the CPUID Function 0x8000001E_ECX to support multiple * nodes per processor --=20 2.34.1 From nobody Sat Nov 15 14:49:51 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750410544; cv=none; d=zohomail.com; s=zohoarc; b=SZvrOOMOiQDwmv1+RdcVAy6kSIBaSPbwRi+60lDuf6Qm/ZwEuVYAzvUPFG3CpmsNd/mFwq3S7TpWEHZQOlCKSLtPXQXkfRF8t0BMQEWnVjoD4UFbYAsN1LwRHMuL7EcuSeYc96uq6cM4vuKHFkoTeBFh8C0k2Wfpho1XdyfBAzQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750410544; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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X-CSE-ConnectionGUID: po/1I9QhR0KWwETB5lKNSQ== X-CSE-MsgGUID: MgpI8uDtT+Kzn1DNK83Ggg== X-IronPort-AV: E=McAfee;i="6800,10657,11469"; a="56466617" X-IronPort-AV: E=Sophos;i="6.16,251,1744095600"; d="scan'208";a="56466617" X-CSE-ConnectionGUID: VYLEjsR1SOGnzxmIf8l0CA== X-CSE-MsgGUID: N3+QkdSwTW2eRz8dwn0pIw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,251,1744095600"; d="scan'208";a="156669950" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti , "Michael S . Tsirkin" , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Marcel Apfelbaum , Richard Henderson , Eduardo Habkost Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Babu Moger , Ewan Hai , Pu Wen , Tao Su , Yi Lai , Dapeng Mi , qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu Subject: [PATCH 05/16] i386/cpu: Consolidate CPUID 0x4 leaf Date: Fri, 20 Jun 2025 17:27:23 +0800 Message-Id: <20250620092734.1576677-6-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620092734.1576677-1-zhao1.liu@intel.com> References: <20250620092734.1576677-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750410546539116600 Content-Type: text/plain; charset="utf-8" Modern Intel CPUs use CPUID 0x4 leaf to describe cache information and leave space in 0x2 for prefetch and TLBs (even TLB has its own leaf CPUID 0x18). And 0x2 leaf provides a descriptor 0xFF to instruct software to check cache information in 0x4 leaf instead. Therefore, follow this behavior to encode 0xFF when Intel CPU has 0x4 leaf with "x-consistent-cache=3Dtrue" for compatibility. In addition, for older CPUs without 0x4 leaf, still enumerate the cache descriptor in 0x2 leaf, except the case that there's no descriptor matching the cache model, then directly encode 0xFF in 0x2 leaf. This makes sense, as in the 0x2 leaf era, all supported caches should have the corresponding descriptor. Signed-off-by: Zhao Liu Reviewed-by: Dapeng Mi --- target/i386/cpu.c | 48 ++++++++++++++++++++++++++++++++++++----------- 1 file changed, 37 insertions(+), 11 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 2f895bf13523..a06aa1d629dc 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -223,7 +223,7 @@ struct CPUID2CacheDescriptorInfo cpuid2_cache_descripto= rs[] =3D { * Return a CPUID 2 cache descriptor for a given cache. * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE */ -static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) +static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache, bool *unmacthe= d) { int i; =20 @@ -240,9 +240,44 @@ static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *c= ache) } } =20 + *unmacthed |=3D true; return CACHE_DESCRIPTOR_UNAVAILABLE; } =20 +/* Encode cache info for CPUID[4] */ +static void encode_cache_cpuid2(X86CPU *cpu, + uint32_t *eax, uint32_t *ebx, + uint32_t *ecx, uint32_t *edx) +{ + CPUX86State *env =3D &cpu->env; + CPUCaches *caches =3D &env->cache_info_cpuid2; + int l1d, l1i, l2, l3; + bool unmatched =3D false; + + *eax =3D 1; /* Number of CPUID[EAX=3D2] calls required */ + *ebx =3D *ecx =3D *edx =3D 0; + + l1d =3D cpuid2_cache_descriptor(caches->l1d_cache, &unmatched); + l1i =3D cpuid2_cache_descriptor(caches->l1i_cache, &unmatched); + l2 =3D cpuid2_cache_descriptor(caches->l2_cache, &unmatched); + l3 =3D cpuid2_cache_descriptor(caches->l3_cache, &unmatched); + + if (!cpu->consistent_cache || + (env->cpuid_min_level < 0x4 && !unmatched)) { + /* + * Though SDM defines code 0x40 for cases with no L2 or L3. It's + * also valid to just ignore l3's code if there's no l2. + */ + if (cpu->enable_l3_cache) { + *ecx =3D l3; + } + *edx =3D (l1d << 16) | (l1i << 8) | l2; + } else { + *ecx =3D 0; + *edx =3D CACHE_DESCRIPTOR_UNAVAILABLE; + } +} + /* CPUID Leaf 4 constants: */ =20 /* EAX: */ @@ -7451,16 +7486,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, *eax =3D *ebx =3D *ecx =3D *edx =3D 0; break; } - *eax =3D 1; /* Number of CPUID[EAX=3D2] calls required */ - *ebx =3D 0; - if (!cpu->enable_l3_cache) { - *ecx =3D 0; - } else { - *ecx =3D cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cac= he); - } - *edx =3D (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache= ) << 16) | - (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) = << 8) | - (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); + encode_cache_cpuid2(cpu, eax, ebx, ecx, edx); break; case 4: /* cache info: needed for Core compatibility */ --=20 2.34.1 From nobody Sat Nov 15 14:49:51 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750410442; cv=none; d=zohomail.com; s=zohoarc; b=asrsyyxYzC9Zj3AtgiAHtLq5uk0NNIuXzKgrA6g5DC0qXIqpX4OdMplpVxGVkeg4ZNoVgjPBmg2LxxP5W86eVAJ/u1/yxxpN4rp4w/urr8ksmEaOWWk/KOMk7hU2HQfLfteyB7UbiNUB2aerFXLTWlc7OwdCm3F0mliFNHt4CTc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750410442; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=oJ969jvUOKi3o3wnC9qAp0z7kRiIZSvCNkbiy0lUeKs=; b=Dkg5SqbQaGV1rmpsbnowUHuHHkoliq9OOFthrzGAiF/YOHErLze6ZRfs2gHg3kyzsKQNWnfVTOIFOvBALuWdP6/WV/6guRKoyA8xvFmY8Jibhz4MvZbTx6DeyRmhd5sqYqlWUHnuBPBpGFuQNrXZiC3lpUNBdYye0fQg++gFYuo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750410442981211.19292254815446; Fri, 20 Jun 2025 02:07:22 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uSXi1-000198-Qe; Fri, 20 Jun 2025 05:06:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSXi0-00015R-16 for qemu-devel@nongnu.org; Fri, 20 Jun 2025 05:06:52 -0400 Received: from mgamail.intel.com ([198.175.65.14]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSXhw-0004zi-V6 for qemu-devel@nongnu.org; Fri, 20 Jun 2025 05:06:51 -0400 Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 02:06:48 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by orviesa005.jf.intel.com with ESMTP; 20 Jun 2025 02:06:44 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750410409; x=1781946409; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HrN3V1+xBd1HD2hJfjrsWV527UXP+zi/OnmT0oMwQxE=; b=hn6qLdzzNxzDjtcqnMeWrL3TOfTK4ZJs027bneq97VRepyed7K/cRNDv YKVdLv1VLED65pKv8Y/QZrYwwQjaEfuL92m7jITLqJJCSI9yMORwo4jc9 zkDhWbcsnSJHldW+trNpKL2lqDXJBxpLfv1OnyER42VWhSPHVglYnSl/e RWmOq54RzGRmtoxE7PiKqmNaib9NKchpBgo55DHTMat0SGjI43ssHGO2d ySlIQXRdk35oW6voLbjg/vy2bYQxoIC9dqYHa6hWQ3pOb2L26GGjoEql6 a7v6bn4q8OTs7feTzfIiUmP2S6KVKiFUgIvwXHFk05ljmBwxlWlLvhbkl Q==; X-CSE-ConnectionGUID: bA+ArSz4QQ+j1R7DFUyAZw== X-CSE-MsgGUID: gDuHpLA6Tli8BfpkmZ64pA== X-IronPort-AV: E=McAfee;i="6800,10657,11469"; a="56466649" X-IronPort-AV: E=Sophos;i="6.16,251,1744095600"; d="scan'208";a="56466649" X-CSE-ConnectionGUID: hR7dCHsQSM6ShvN2uk7M5A== X-CSE-MsgGUID: XFSPibD4Qhuuu5QY8k+VvA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,251,1744095600"; d="scan'208";a="156670000" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti , "Michael S . Tsirkin" , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Marcel Apfelbaum , Richard Henderson , Eduardo Habkost Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Babu Moger , Ewan Hai , Pu Wen , Tao Su , Yi Lai , Dapeng Mi , qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu Subject: [PATCH 06/16] i386/cpu: Drop CPUID 0x2 specific cache info in X86CPUState Date: Fri, 20 Jun 2025 17:27:24 +0800 Message-Id: <20250620092734.1576677-7-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620092734.1576677-1-zhao1.liu@intel.com> References: <20250620092734.1576677-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750410443522116600 Content-Type: text/plain; charset="utf-8" With the pre-defined cache model legacy_intel_cpuid2_cache_info, for X86CPUState there's no need to cache special cache information for CPUID 0x2 leaf. Drop the cache_info_cpuid2 field of X86CPUState and use the legacy_intel_cpuid2_cache_info directly. Signed-off-by: Zhao Liu Reviewed-by: Dapeng Mi --- target/i386/cpu.c | 31 +++++++++++-------------------- target/i386/cpu.h | 3 ++- 2 files changed, 13 insertions(+), 21 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index a06aa1d629dc..8f174fb971b6 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -244,19 +244,27 @@ static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *= cache, bool *unmacthed) return CACHE_DESCRIPTOR_UNAVAILABLE; } =20 +static const CPUCaches legacy_intel_cpuid2_cache_info; + /* Encode cache info for CPUID[4] */ static void encode_cache_cpuid2(X86CPU *cpu, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) { CPUX86State *env =3D &cpu->env; - CPUCaches *caches =3D &env->cache_info_cpuid2; + const CPUCaches *caches; int l1d, l1i, l2, l3; bool unmatched =3D false; =20 *eax =3D 1; /* Number of CPUID[EAX=3D2] calls required */ *ebx =3D *ecx =3D *edx =3D 0; =20 + if (env->enable_legacy_cpuid2_cache) { + caches =3D &legacy_intel_cpuid2_cache_info; + } else { + caches =3D &env->cache_info_cpuid4; + } + l1d =3D cpuid2_cache_descriptor(caches->l1d_cache, &unmatched); l1i =3D cpuid2_cache_descriptor(caches->l1i_cache, &unmatched); l2 =3D cpuid2_cache_descriptor(caches->l2_cache, &unmatched); @@ -705,17 +713,6 @@ static CPUCacheInfo legacy_l2_cache =3D { .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }; =20 -/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ -static CPUCacheInfo legacy_l2_cache_cpuid2 =3D { - .type =3D UNIFIED_CACHE, - .level =3D 2, - .size =3D 2 * MiB, - .line_size =3D 64, - .associativity =3D 8, - .share_level =3D CPU_TOPOLOGY_LEVEL_INVALID, -}; - - /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ static CPUCacheInfo legacy_l2_cache_amd =3D { .type =3D UNIFIED_CACHE, @@ -8951,18 +8948,12 @@ static void x86_cpu_realizefn(DeviceState *dev, Err= or **errp) "CPU model '%s' doesn't support legacy-cache=3Doff"= , name); return; } - env->cache_info_cpuid2 =3D env->cache_info_cpuid4 =3D env->cache_i= nfo_amd =3D - *cache_info; + env->cache_info_cpuid4 =3D env->cache_info_amd =3D *cache_info; } else { /* Build legacy cache information */ - env->cache_info_cpuid2.l1d_cache =3D &legacy_l1d_cache; - env->cache_info_cpuid2.l1i_cache =3D &legacy_l1i_cache; if (!cpu->consistent_cache) { - env->cache_info_cpuid2.l2_cache =3D &legacy_l2_cache_cpuid2; - } else { - env->cache_info_cpuid2.l2_cache =3D &legacy_l2_cache; + env->enable_legacy_cpuid2_cache =3D true; } - env->cache_info_cpuid2.l3_cache =3D &legacy_l3_cache; =20 env->cache_info_cpuid4.l1d_cache =3D &legacy_l1d_cache; env->cache_info_cpuid4.l1i_cache =3D &legacy_l1i_cache; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 3c7e59ffb12a..8d3ce8a2b678 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2076,7 +2076,8 @@ typedef struct CPUArchState { * on each CPUID leaf will be different, because we keep compatibility * with old QEMU versions. */ - CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd; + CPUCaches cache_info_cpuid4, cache_info_amd; + bool enable_legacy_cpuid2_cache; =20 /* MTRRs */ uint64_t mtrr_fixed[11]; --=20 2.34.1 From nobody Sat Nov 15 14:49:51 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750410595; cv=none; d=zohomail.com; s=zohoarc; b=Pk63XPmRlTBfYIKWho5KGAeYTAFVS4YdmPPIW8fG4uJe3pY6AJ/zHMsPYYtHJCWQ1I/Yg9le4ZcsUfl9La8bXikrhpYlk0JwPZJMUfXGaymHWKFlsP/B4Xmo9M0RpBq1F09e4a5mgAxitPfm1E1GbWFI4TBVQul46DxsXTOHAzE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750410595; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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X-CSE-ConnectionGUID: jbZWzAYcQzCscxObrOl6Zw== X-CSE-MsgGUID: 2iFwNNXqQhm7FheT3108OQ== X-IronPort-AV: E=McAfee;i="6800,10657,11469"; a="56466694" X-IronPort-AV: E=Sophos;i="6.16,251,1744095600"; d="scan'208";a="56466694" X-CSE-ConnectionGUID: uXfGFCjTSfSYwqCumqHTDA== X-CSE-MsgGUID: kYjhpG7GQV6+QwHSPwIbtg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,251,1744095600"; d="scan'208";a="156670042" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti , "Michael S . Tsirkin" , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Marcel Apfelbaum , Richard Henderson , Eduardo Habkost Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Babu Moger , Ewan Hai , Pu Wen , Tao Su , Yi Lai , Dapeng Mi , qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu Subject: [PATCH 07/16] i386/cpu: Mark CPUID[0x80000005] as reserved for Intel Date: Fri, 20 Jun 2025 17:27:25 +0800 Message-Id: <20250620092734.1576677-8-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620092734.1576677-1-zhao1.liu@intel.com> References: <20250620092734.1576677-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750410597121116600 Content-Type: text/plain; charset="utf-8" Per SDM, 0x80000005 leaf is reserved for Intel CPU, and its current "assert" check blocks adding new cache model for non-AMD CPUs. And please note, although Zhaoxin mostly follows Intel behavior, this leaf is an exception [1]. So, add a compat property "x-vendor-cpuid-only-v2" (for PC machine v10.0 and older) to keep the original behavior. For the machine since v10.1, check the vendor and encode this leaf as all-0 only for Intel CPU. This fix also resolves 2 FIXMEs of legacy_l1d_cache_amd and legacy_l1i_cache_amd: /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ In addition, per AMD's APM, update the comment of CPUID[0x80000005]. [1]: https://lore.kernel.org/qemu-devel/fa16f7a8-4917-4731-9d9f-7d4c1097716= 8@zhaoxin.com/ Signed-off-by: Zhao Liu --- Changes since RFC: * Only set all-0 for Intel CPU. * Add x-vendor-cpuid-only-v2. --- hw/i386/pc.c | 1 + target/i386/cpu.c | 11 ++++++++--- target/i386/cpu.h | 11 ++++++++++- 3 files changed, 19 insertions(+), 4 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index ad2d6495ebde..9ec3f4db31f3 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -83,6 +83,7 @@ =20 GlobalProperty pc_compat_10_0[] =3D { { TYPE_X86_CPU, "x-consistent-cache", "false" }, + { TYPE_X86_CPU, "x-vendor-cpuid-only-v2", "false" }, }; const size_t pc_compat_10_0_len =3D G_N_ELEMENTS(pc_compat_10_0); =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 8f174fb971b6..df40d1362566 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -655,7 +655,6 @@ static CPUCacheInfo legacy_l1d_cache =3D { .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }; =20 -/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ static CPUCacheInfo legacy_l1d_cache_amd =3D { .type =3D DATA_CACHE, .level =3D 1, @@ -684,7 +683,6 @@ static CPUCacheInfo legacy_l1i_cache =3D { .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }; =20 -/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ static CPUCacheInfo legacy_l1i_cache_amd =3D { .type =3D INSTRUCTION_CACHE, .level =3D 1, @@ -7889,11 +7887,17 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, *edx =3D env->cpuid_model[(index - 0x80000002) * 4 + 3]; break; case 0x80000005: - /* cache info (L1 cache) */ + /* cache info (L1 cache/TLB Associativity Field) */ if (cpu->cache_info_passthrough) { x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); break; } + + if (cpu->vendor_cpuid_only_v2 && IS_INTEL_CPU(env)) { + *eax =3D *ebx =3D *ecx =3D *edx =3D 0; + break; + } + *eax =3D (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); *ebx =3D (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | @@ -9464,6 +9468,7 @@ static const Property x86_cpu_properties[] =3D { DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, tru= e), + DEFINE_PROP_BOOL("x-vendor-cpuid-only-v2", X86CPU, vendor_cpuid_only_v= 2, true), DEFINE_PROP_BOOL("x-amd-topoext-features-only", X86CPU, amd_topoext_fe= atures_only, true), DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 8d3ce8a2b678..02cda176798f 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2282,9 +2282,18 @@ struct ArchCPU { /* Enable auto level-increase for all CPUID leaves */ bool full_cpuid_auto_level; =20 - /* Only advertise CPUID leaves defined by the vendor */ + /* + * Compatibility bits for old machine types (PC machine v6.0 and older= ). + * Only advertise CPUID leaves defined by the vendor. + */ bool vendor_cpuid_only; =20 + /* + * Compatibility bits for old machine types (PC machine v10.0 and olde= r). + * Only advertise CPUID leaves defined by the vendor. + */ + bool vendor_cpuid_only_v2; + /* Only advertise TOPOEXT features that AMD defines */ bool amd_topoext_features_only; =20 --=20 2.34.1 From nobody Sat Nov 15 14:49:51 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750410627; cv=none; d=zohomail.com; s=zohoarc; b=Yl48sqwNxyHhJRMveb1eeXgcxWbepm0v2WBOqaA1ZQwwIPOiHhZbRutcdHnEfscUIQg+cLGEdVR6jmBrQZjeyrzG9KhL84ffx27ZWjO98Q+1rNnu4znTt3gewv+A/0WYVy0a9Lf2HFlx8gqjIqySWX6yuUlV7zJ4zCpOdnaUVX8= ARC-Message-Signature: i=1; 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Tsirkin" , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Marcel Apfelbaum , Richard Henderson , Eduardo Habkost Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Babu Moger , Ewan Hai , Pu Wen , Tao Su , Yi Lai , Dapeng Mi , qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu Subject: [PATCH 08/16] i386/cpu: Fix CPUID[0x80000006] for Intel CPU Date: Fri, 20 Jun 2025 17:27:26 +0800 Message-Id: <20250620092734.1576677-9-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620092734.1576677-1-zhao1.liu@intel.com> References: <20250620092734.1576677-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750410629331116600 Content-Type: text/plain; charset="utf-8" Per SDM, Intel supports CPUID[0x80000006]. But only L2 information is encoded in ECX (note that L2 associativity field encodings rules consistent with AMD are used), all other fields are reserved. Therefore, make the following changes to CPUID[0x80000006]: * Rename AMD_ENC_ASSOC to X86_ENC_ASSOC since Intel also uses the same rules. (While there are some slight differences between the rules in AMD APM v4.07 no.40332 and those in the current QEMU, generally they are consistent.) * Check the vendor in CPUID[0x80000006] and just encode L2 to ECX for Intel. * Assert L2's lines_per_tag is not 0 for AMD, and assert it is 0 for Intel. * Apply the encoding change of Intel for Zhaoxin as well [1]. This fix also resolves the FIXME of legacy_l2_cache_amd: /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ In addition, per AMD's APM, update the comment of CPUID[0x80000006]. [1]: https://lore.kernel.org/qemu-devel/c522ebb5-04d5-49c6-9ad8-d755b899898= 8@zhaoxin.com/ Signed-off-by: Zhao Liu --- Changes since RFC: * Check vendor_cpuid_only_v2 instead of vendor_cpuid_only. * Move lines_per_tag assert check into encode_cache_cpuid80000006(). --- target/i386/cpu.c | 42 +++++++++++++++++++++++++++--------------- 1 file changed, 27 insertions(+), 15 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index df40d1362566..0b292aa2e07b 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -506,8 +506,8 @@ static uint32_t encode_cache_cpuid80000005(CPUCacheInfo= *cache) =20 #define ASSOC_FULL 0xFF =20 -/* AMD associativity encoding used on CPUID Leaf 0x80000006: */ -#define AMD_ENC_ASSOC(a) (a <=3D 1 ? a : \ +/* x86 associativity encoding used on CPUID Leaf 0x80000006: */ +#define X86_ENC_ASSOC(a) (a <=3D 1 ? a : \ a =3D=3D 2 ? 0x2 : \ a =3D=3D 4 ? 0x4 : \ a =3D=3D 8 ? 0x6 : \ @@ -526,23 +526,26 @@ static uint32_t encode_cache_cpuid80000005(CPUCacheIn= fo *cache) */ static void encode_cache_cpuid80000006(CPUCacheInfo *l2, CPUCacheInfo *l3, - uint32_t *ecx, uint32_t *edx) + uint32_t *ecx, uint32_t *edx, + bool lines_per_tag_supported) { assert(l2->size % 1024 =3D=3D 0); assert(l2->associativity > 0); - assert(l2->lines_per_tag > 0); - assert(l2->line_size > 0); + assert(lines_per_tag_supported ? + l2->lines_per_tag > 0 : l2->lines_per_tag =3D=3D 0); *ecx =3D ((l2->size / 1024) << 16) | - (AMD_ENC_ASSOC(l2->associativity) << 12) | + (X86_ENC_ASSOC(l2->associativity) << 12) | (l2->lines_per_tag << 8) | (l2->line_size); =20 + /* For Intel, EDX is reserved. */ if (l3) { assert(l3->size % (512 * 1024) =3D=3D 0); assert(l3->associativity > 0); - assert(l3->lines_per_tag > 0); + assert(lines_per_tag_supported ? + l3->lines_per_tag > 0 : l3->lines_per_tag =3D=3D 0); assert(l3->line_size > 0); *edx =3D ((l3->size / (512 * 1024)) << 18) | - (AMD_ENC_ASSOC(l3->associativity) << 12) | + (X86_ENC_ASSOC(l3->associativity) << 12) | (l3->lines_per_tag << 8) | (l3->line_size); } else { *edx =3D 0; @@ -711,7 +714,6 @@ static CPUCacheInfo legacy_l2_cache =3D { .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }; =20 -/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ static CPUCacheInfo legacy_l2_cache_amd =3D { .type =3D UNIFIED_CACHE, .level =3D 2, @@ -7906,23 +7908,33 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, *edx =3D encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); break; case 0x80000006: - /* cache info (L2 cache) */ + /* cache info (L2 cache/TLB/L3 cache) */ if (cpu->cache_info_passthrough) { x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); break; } - *eax =3D (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | + + if (cpu->vendor_cpuid_only_v2 && + (IS_INTEL_CPU(env) || IS_ZHAOXIN_CPU(env))) { + *eax =3D *ebx =3D 0; + encode_cache_cpuid80000006(env->cache_info_cpuid4.l2_cache, + NULL, ecx, edx, false); + break; + } + + *eax =3D (X86_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | (L2_DTLB_2M_ENTRIES << 16) | - (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | + (X86_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | (L2_ITLB_2M_ENTRIES); - *ebx =3D (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | + *ebx =3D (X86_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | (L2_DTLB_4K_ENTRIES << 16) | - (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | + (X86_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | (L2_ITLB_4K_ENTRIES); + encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, cpu->enable_l3_cache ? env->cache_info_amd.l3_cache : NULL, - ecx, edx); + ecx, edx, true); break; case 0x80000007: *eax =3D 0; --=20 2.34.1 From nobody Sat Nov 15 14:49:51 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750410530; cv=none; d=zohomail.com; s=zohoarc; b=Lj0T0arJMWBhJSKuLrf8LYpEtTW++B72G3/nA928M789D+6+Gn8IEcGOEhV/zDkUrgQmFm0Ib+4ABf5ZFiDJPEcy/lo+9Zlf5sH559/Wr2t8GnHRW5awtfHhewwiJU8ch3B2a4aKUErKx41D9teGCwa3NNstp+JARzG18i2wt2w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750410530; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=uKue2fZ9GRqQvQE9Phi5YL163grW68Jr5KSOnSDtqys=; b=VgBs9rwaL+7tN7uW9ebDsbbLyFrqmWKmS2OPw/WguLoxplpvMoIuZmUvZ4bjy9phLwpbT3NMcLlbxfCWt0EytL8ZG5CJWcj4Y74m3F6NmFJsyk/3vwHLPd623tPZyELR6JEA4AEmmCd2uyBKjJxRYjyTiFgtJ85/aEguu41AL2M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750410530597285.0231718189043; Fri, 20 Jun 2025 02:08:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uSXiP-0001wB-4q; Fri, 20 Jun 2025 05:07:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSXiD-0001TL-JD for qemu-devel@nongnu.org; Fri, 20 Jun 2025 05:07:08 -0400 Received: from mgamail.intel.com ([198.175.65.14]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSXiA-0004zi-L4 for qemu-devel@nongnu.org; Fri, 20 Jun 2025 05:07:05 -0400 Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 02:07:02 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by orviesa005.jf.intel.com with ESMTP; 20 Jun 2025 02:06:58 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750410423; x=1781946423; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=N4GITYpWdJ1HERjdysXD4ZPZutg2U4OiYFYUeFIS6iM=; b=DKcOAMVd1g/pwo1839d2+RUwpMrUiKAIpBF791uAJZFa9PxiGJ4GWEf5 g9yudlHrr14ni8iiMMUTwEbGo/Vk+rhZoD/ktiEax8DtQV2Ko4c4mKJeQ mFiPTAMCQlE3jU65cy+Q/SV7FuhiDof+SiU7ELJzrL7hP/O7Fjmspmki/ +JXbm9/jlr7r/TVkjJt6Phym2j/2XwIN3qmOFe+0dPSOcO+yn1ZqnCFFl xl8D2UWvDy4kN+3h6ztZh6WOucuQ+n0sJJaRNmgjW46lnhR/0I6ebW5me UsNfNbDdMz3x44cw7W/0rGcanJx7dIhSPI0ItIQng9khw/oFsoXtoTrjT w==; X-CSE-ConnectionGUID: RIGGyGVrTfyxyS5mXRxiYg== X-CSE-MsgGUID: +b7fT8tpTtCiuZmaO1qC1g== X-IronPort-AV: E=McAfee;i="6800,10657,11469"; a="56466742" X-IronPort-AV: E=Sophos;i="6.16,251,1744095600"; d="scan'208";a="56466742" X-CSE-ConnectionGUID: T03zHKGqSaSLlO+61lfE1w== X-CSE-MsgGUID: xMTKnt6PSR+jly6fF/X7LQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,251,1744095600"; d="scan'208";a="156670103" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti , "Michael S . Tsirkin" , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Marcel Apfelbaum , Richard Henderson , Eduardo Habkost Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Babu Moger , Ewan Hai , Pu Wen , Tao Su , Yi Lai , Dapeng Mi , qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu Subject: [PATCH 09/16] i386/cpu: Add legacy_intel_cache_info cache model Date: Fri, 20 Jun 2025 17:27:27 +0800 Message-Id: <20250620092734.1576677-10-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620092734.1576677-1-zhao1.liu@intel.com> References: <20250620092734.1576677-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750410532422116600 Content-Type: text/plain; charset="utf-8" Based on legacy_l1d_cache, legacy_l1i_cache, legacy_l2_cache and legacy_l3_cache, build a complete legacy intel cache model, which can clarify the purpose of these trivial legacy cache models, simplify the initialization of cache info in X86CPUState, and make it easier to handle compatibility later. Signed-off-by: Zhao Liu Reviewed-by: Dapeng Mi --- target/i386/cpu.c | 101 +++++++++++++++++++++++++--------------------- 1 file changed, 54 insertions(+), 47 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 0b292aa2e07b..ec229830c532 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -643,21 +643,6 @@ static void encode_topo_cpuid8000001e(X86CPU *cpu, X86= CPUTopoInfo *topo_info, * These are legacy cache values. If there is a need to change any * of these values please use builtin_x86_defs */ - -/* L1 data cache: */ -static CPUCacheInfo legacy_l1d_cache =3D { - .type =3D DATA_CACHE, - .level =3D 1, - .size =3D 32 * KiB, - .self_init =3D 1, - .line_size =3D 64, - .associativity =3D 8, - .sets =3D 64, - .partitions =3D 1, - .no_invd_sharing =3D true, - .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, -}; - static CPUCacheInfo legacy_l1d_cache_amd =3D { .type =3D DATA_CACHE, .level =3D 1, @@ -672,20 +657,6 @@ static CPUCacheInfo legacy_l1d_cache_amd =3D { .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }; =20 -/* L1 instruction cache: */ -static CPUCacheInfo legacy_l1i_cache =3D { - .type =3D INSTRUCTION_CACHE, - .level =3D 1, - .size =3D 32 * KiB, - .self_init =3D 1, - .line_size =3D 64, - .associativity =3D 8, - .sets =3D 64, - .partitions =3D 1, - .no_invd_sharing =3D true, - .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, -}; - static CPUCacheInfo legacy_l1i_cache_amd =3D { .type =3D INSTRUCTION_CACHE, .level =3D 1, @@ -700,20 +671,6 @@ static CPUCacheInfo legacy_l1i_cache_amd =3D { .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }; =20 -/* Level 2 unified cache: */ -static CPUCacheInfo legacy_l2_cache =3D { - .type =3D UNIFIED_CACHE, - .level =3D 2, - .size =3D 4 * MiB, - .self_init =3D 1, - .line_size =3D 64, - .associativity =3D 16, - .sets =3D 4096, - .partitions =3D 1, - .no_invd_sharing =3D true, - .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, -}; - static CPUCacheInfo legacy_l2_cache_amd =3D { .type =3D UNIFIED_CACHE, .level =3D 2, @@ -803,6 +760,59 @@ static const CPUCaches legacy_intel_cpuid2_cache_info = =3D { }, }; =20 +static const CPUCaches legacy_intel_cache_info =3D { + .l1d_cache =3D &(CPUCacheInfo) { + .type =3D DATA_CACHE, + .level =3D 1, + .size =3D 32 * KiB, + .self_init =3D 1, + .line_size =3D 64, + .associativity =3D 8, + .sets =3D 64, + .partitions =3D 1, + .no_invd_sharing =3D true, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l1i_cache =3D &(CPUCacheInfo) { + .type =3D INSTRUCTION_CACHE, + .level =3D 1, + .size =3D 32 * KiB, + .self_init =3D 1, + .line_size =3D 64, + .associativity =3D 8, + .sets =3D 64, + .partitions =3D 1, + .no_invd_sharing =3D true, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l2_cache =3D &(CPUCacheInfo) { + .type =3D UNIFIED_CACHE, + .level =3D 2, + .size =3D 4 * MiB, + .self_init =3D 1, + .line_size =3D 64, + .associativity =3D 16, + .sets =3D 4096, + .partitions =3D 1, + .no_invd_sharing =3D true, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l3_cache =3D &(CPUCacheInfo) { + .type =3D UNIFIED_CACHE, + .level =3D 3, + .size =3D 16 * MiB, + .line_size =3D 64, + .associativity =3D 16, + .sets =3D 16384, + .partitions =3D 1, + .lines_per_tag =3D 1, + .self_init =3D true, + .inclusive =3D true, + .complex_indexing =3D true, + .share_level =3D CPU_TOPOLOGY_LEVEL_DIE, + }, +}; + /* TLB definitions: */ =20 #define L1_DTLB_2M_ASSOC 1 @@ -8971,10 +8981,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Erro= r **errp) env->enable_legacy_cpuid2_cache =3D true; } =20 - env->cache_info_cpuid4.l1d_cache =3D &legacy_l1d_cache; - env->cache_info_cpuid4.l1i_cache =3D &legacy_l1i_cache; - env->cache_info_cpuid4.l2_cache =3D &legacy_l2_cache; - env->cache_info_cpuid4.l3_cache =3D &legacy_l3_cache; + env->cache_info_cpuid4 =3D legacy_intel_cache_info; =20 env->cache_info_amd.l1d_cache =3D &legacy_l1d_cache_amd; env->cache_info_amd.l1i_cache =3D &legacy_l1i_cache_amd; --=20 2.34.1 From nobody Sat Nov 15 14:49:51 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750410535; cv=none; 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Tsirkin" , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Marcel Apfelbaum , Richard Henderson , Eduardo Habkost Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Babu Moger , Ewan Hai , Pu Wen , Tao Su , Yi Lai , Dapeng Mi , qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu Subject: [PATCH 10/16] i386/cpu: Add legacy_amd_cache_info cache model Date: Fri, 20 Jun 2025 17:27:28 +0800 Message-Id: <20250620092734.1576677-11-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620092734.1576677-1-zhao1.liu@intel.com> References: <20250620092734.1576677-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750410536577116600 Content-Type: text/plain; charset="utf-8" Based on legacy_l1d_cachei_amd, legacy_l1i_cache_amd, legacy_l2_cache_amd and legacy_l3_cache, build a complete legacy AMD cache model, which can clarify the purpose of these trivial legacy cache models, simplify the initialization of cache info in X86CPUState, and make it easier to handle compatibility later. Signed-off-by: Zhao Liu Reviewed-by: Dapeng Mi --- target/i386/cpu.c | 112 ++++++++++++++++++++++------------------------ 1 file changed, 53 insertions(+), 59 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ec229830c532..bf8d7a19c88d 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -643,60 +643,58 @@ static void encode_topo_cpuid8000001e(X86CPU *cpu, X8= 6CPUTopoInfo *topo_info, * These are legacy cache values. If there is a need to change any * of these values please use builtin_x86_defs */ -static CPUCacheInfo legacy_l1d_cache_amd =3D { - .type =3D DATA_CACHE, - .level =3D 1, - .size =3D 64 * KiB, - .self_init =3D 1, - .line_size =3D 64, - .associativity =3D 2, - .sets =3D 512, - .partitions =3D 1, - .lines_per_tag =3D 1, - .no_invd_sharing =3D true, - .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, -}; - -static CPUCacheInfo legacy_l1i_cache_amd =3D { - .type =3D INSTRUCTION_CACHE, - .level =3D 1, - .size =3D 64 * KiB, - .self_init =3D 1, - .line_size =3D 64, - .associativity =3D 2, - .sets =3D 512, - .partitions =3D 1, - .lines_per_tag =3D 1, - .no_invd_sharing =3D true, - .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, -}; - -static CPUCacheInfo legacy_l2_cache_amd =3D { - .type =3D UNIFIED_CACHE, - .level =3D 2, - .size =3D 512 * KiB, - .line_size =3D 64, - .lines_per_tag =3D 1, - .associativity =3D 16, - .sets =3D 512, - .partitions =3D 1, - .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, -}; - -/* Level 3 unified cache: */ -static CPUCacheInfo legacy_l3_cache =3D { - .type =3D UNIFIED_CACHE, - .level =3D 3, - .size =3D 16 * MiB, - .line_size =3D 64, - .associativity =3D 16, - .sets =3D 16384, - .partitions =3D 1, - .lines_per_tag =3D 1, - .self_init =3D true, - .inclusive =3D true, - .complex_indexing =3D true, - .share_level =3D CPU_TOPOLOGY_LEVEL_DIE, +static const CPUCaches legacy_amd_cache_info =3D { + .l1d_cache =3D &(CPUCacheInfo) { + .type =3D DATA_CACHE, + .level =3D 1, + .size =3D 64 * KiB, + .self_init =3D 1, + .line_size =3D 64, + .associativity =3D 2, + .sets =3D 512, + .partitions =3D 1, + .lines_per_tag =3D 1, + .no_invd_sharing =3D true, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l1i_cache =3D &(CPUCacheInfo) { + .type =3D INSTRUCTION_CACHE, + .level =3D 1, + .size =3D 64 * KiB, + .self_init =3D 1, + .line_size =3D 64, + .associativity =3D 2, + .sets =3D 512, + .partitions =3D 1, + .lines_per_tag =3D 1, + .no_invd_sharing =3D true, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l2_cache =3D &(CPUCacheInfo) { + .type =3D UNIFIED_CACHE, + .level =3D 2, + .size =3D 512 * KiB, + .line_size =3D 64, + .lines_per_tag =3D 1, + .associativity =3D 16, + .sets =3D 512, + .partitions =3D 1, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l3_cache =3D &(CPUCacheInfo) { + .type =3D UNIFIED_CACHE, + .level =3D 3, + .size =3D 16 * MiB, + .line_size =3D 64, + .associativity =3D 16, + .sets =3D 16384, + .partitions =3D 1, + .lines_per_tag =3D 1, + .self_init =3D true, + .inclusive =3D true, + .complex_indexing =3D true, + .share_level =3D CPU_TOPOLOGY_LEVEL_DIE, + }, }; =20 /* @@ -8982,11 +8980,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Erro= r **errp) } =20 env->cache_info_cpuid4 =3D legacy_intel_cache_info; - - env->cache_info_amd.l1d_cache =3D &legacy_l1d_cache_amd; - env->cache_info_amd.l1i_cache =3D &legacy_l1i_cache_amd; - env->cache_info_amd.l2_cache =3D &legacy_l2_cache_amd; - env->cache_info_amd.l3_cache =3D &legacy_l3_cache; + env->cache_info_amd =3D legacy_amd_cache_info; } =20 #ifndef CONFIG_USER_ONLY --=20 2.34.1 From nobody Sat Nov 15 14:49:51 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750410591; cv=none; d=zohomail.com; s=zohoarc; b=CNpdC3tNS/CaxZOUsN1mVYeJWuH+zxgzs5s+7CagsMP83aSD1oRlIX+P8oNmDqTuk2KT/XLexZrejdXjBJj81hzCQ2Fhcbx+tVOD9ucCsxA7Zet95RYSj3/6/AFElUuK/zdnaCd8GZf5gI86PjF4o2tPmUN9S4NtUw/nq3i6WKs= ARC-Message-Signature: i=1; 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bh=54rHdojaXOof2ZHkdeFHcUlBVP0cmtDTKdkAcczOwns=; b=NbNKImOnJldsXJvESTMLa/VGd63WxCze0n3bCwquYka3x4n+1Dt2jUWE Qq+YwmKsL7CPVHSsT9CwQa5UKmLvm8oFgKyjdZ+VWQQWRX8tJAUV30Gfm aNc+VHlEkvKh5EYX0HAbqPurkR3KN25M4ZyGkJ4MWBECcoOvHcdcftiaz loSR7PqsP3JEgqBV5PNFMx90J/ARItMRh6u1JHXM4vMf/PzqsHPtUbn3B 7n3+v/PFH2StbN2m+6wS/DwfK1LFte2fa7n9othOgjMnMtcQ7EfCvFHft O7CqpWWeRr0Ti9DJhfK9/WQXsK7CJRzGrFVbFeZkzQ/AtgNKB/2IPn1+Z A==; X-CSE-ConnectionGUID: uGvRoi4LT1qNetWm8c0Mbg== X-CSE-MsgGUID: 699/v52MS0aWB98m0Lx8Lg== X-IronPort-AV: E=McAfee;i="6800,10657,11469"; a="56466786" X-IronPort-AV: E=Sophos;i="6.16,251,1744095600"; d="scan'208";a="56466786" X-CSE-ConnectionGUID: kMUigp3XQpe3HkvjEKmjhw== X-CSE-MsgGUID: a44Vy7uqQOaLrZbJXjecJA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,251,1744095600"; d="scan'208";a="156670130" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti , "Michael S . Tsirkin" , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Marcel Apfelbaum , Richard Henderson , Eduardo Habkost Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Babu Moger , Ewan Hai , Pu Wen , Tao Su , Yi Lai , Dapeng Mi , qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu Subject: [PATCH 11/16] i386/cpu: Select legacy cache model based on vendor in CPUID 0x2 Date: Fri, 20 Jun 2025 17:27:29 +0800 Message-Id: <20250620092734.1576677-12-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620092734.1576677-1-zhao1.liu@intel.com> References: <20250620092734.1576677-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750410593065116600 Content-Type: text/plain; charset="utf-8" As preparation for merging cache_info_cpuid4 and cache_info_amd in X86CPUState, set legacy cache model based on vendor in the CPUID 0x2 leaf. For AMD CPU, select legacy AMD cache model (in cache_info_amd) as the default cache model, otherwise, select legacy Intel cache model (in cache_info_cpuid4) as before. To ensure compatibility is not broken, add an enable_legacy_vendor_cache flag based on x-vendor-only-v2 to indicate cases where the legacy cache model should be used regardless of the vendor. For CPUID 0x2 leaf, enable_legacy_vendor_cache flag indicates to pick legacy Intel cache model, which is for compatibility with the behavior of PC machine v10.0 and older. The following explains how current vendor-based default legacy cache model ensures correctness without breaking compatibility. * For the PC machine v6.0 and older, vendor_cpuid_only=3Dfalse, and vendor_cpuid_only_v2=3Dfalse. - If the named CPU model has its own cache model, and doesn't use legacy cache model (legacy_cache=3Dfalse), then cache_info_cpuid4 and cache_info_amd are same, so 0x2 leaf uses its own cache model regardless of the vendor. - For max/host/named CPU (without its own cache model), then the flag enable_legacy_vendor_cache is true, they will use legacy Intel cache model just like their previous behavior. * For the PC machine v10.0 and older (to v6.1), vendor_cpuid_only=3Dtrue, and vendor_cpuid_only_v2=3Dfalse. - If the named CPU model has its own cache model (legacy_cache=3Dfalse), then cache_info_cpuid4 & cache_info_amd both equal to its own cache model, so it uses its own cache model in 0x2 leaf regardless of the vendor. Only AMD CPUs have all-0 leaf due to vendor_cpuid_only=3Dtrue, and this is exactly the behavior of these old machines. - For max/host/named CPU (without its own cache model), then the flag enable_legacy_vendor_cache is true, they will use legacy Intel cache model. Similarly, only AMD CPUs have all-0 leaf, and this is exactly the behavior of these old machines. * For the PC machine v10.1 and newer, vendor_cpuid_only=3Dtrue, and vendor_cpuid_only_v2=3Dtrue. - If the named CPU model has its own cache model (legacy_cache=3Dfalse), then cache_info_cpuid4 & cache_info_amd both equal to its own cache model, so it uses its own cache model in 0x2 leaf regardless of the vendor. And AMD CPUs have all-0 leaf. Nothing will change. - For max/host/named CPU (without its own cache model), then the flag enable_legacy_vendor_cache is false, the legacy cache model is selected based on vendor. For AMD CPU, it will use legacy AMD cache but still get all-0 leaf due to vendor_cpuid_only=3Dtrue. For non-AMD (Intel/Zhaoxin) CPU, it will use legacy Intel cache as expected. Here, selecting the legacy cache model based on the vendor does not change the previous (before the change) behavior. Therefore, the above analysis proves that, with the help of the flag enable_legacy_vendor_cache, it is acceptable to select the default legacy cache model based on the vendor. For the CPUID 0x2 leaf, in X86CPUState, a unified cache_info is enough. It only needs to be initialized and configured with the corresponding legacy cache model based on the vendor. Signed-off-by: Zhao Liu Reviewed-by: Dapeng Mi --- target/i386/cpu.c | 47 +++++++++++++++++++++++++++++++++++++---------- target/i386/cpu.h | 1 + 2 files changed, 38 insertions(+), 10 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index bf8d7a19c88d..524d39de9ace 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -248,23 +248,17 @@ static const CPUCaches legacy_intel_cpuid2_cache_info; =20 /* Encode cache info for CPUID[4] */ static void encode_cache_cpuid2(X86CPU *cpu, + const CPUCaches *caches, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) { CPUX86State *env =3D &cpu->env; - const CPUCaches *caches; int l1d, l1i, l2, l3; bool unmatched =3D false; =20 *eax =3D 1; /* Number of CPUID[EAX=3D2] calls required */ *ebx =3D *ecx =3D *edx =3D 0; =20 - if (env->enable_legacy_cpuid2_cache) { - caches =3D &legacy_intel_cpuid2_cache_info; - } else { - caches =3D &env->cache_info_cpuid4; - } - l1d =3D cpuid2_cache_descriptor(caches->l1d_cache, &unmatched); l1i =3D cpuid2_cache_descriptor(caches->l1i_cache, &unmatched); l2 =3D cpuid2_cache_descriptor(caches->l2_cache, &unmatched); @@ -7482,8 +7476,37 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, *ecx &=3D ~CPUID_EXT_PDCM; } break; - case 2: - /* cache info: needed for Pentium Pro compatibility */ + case 2: { /* cache info: needed for Pentium Pro compatibility */ + const CPUCaches *caches; + + if (env->enable_legacy_cpuid2_cache) { + caches =3D &legacy_intel_cpuid2_cache_info; + } else if (env->enable_legacy_vendor_cache) { + caches =3D &legacy_intel_cache_info; + } else { + /* + * FIXME: Temporarily select cache info model here based on + * vendor, and merge these 2 cache info models later. + * + * This condition covers the following cases (with + * enable_legacy_vendor_cache=3Dfalse): + * - When CPU model has its own cache model and doesn't use l= egacy + * cache model (legacy_model=3Doff). Then cache_info_amd and + * cache_info_cpuid4 are the same. + * + * - For v10.1 and newer machines, when CPU model uses legacy= cache + * model. Non-AMD CPUs use cache_info_cpuid4 like before an= d AMD + * CPU will use cache_info_amd. But this doesn't matter for= AMD + * CPU, because this leaf encodes all-0 for AMD whatever it= s cache + * model is. + */ + if (IS_AMD_CPU(env)) { + caches =3D &env->cache_info_amd; + } else { + caches =3D &env->cache_info_cpuid4; + } + } + if (cpu->cache_info_passthrough) { x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); break; @@ -7491,8 +7514,9 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, *eax =3D *ebx =3D *ecx =3D *edx =3D 0; break; } - encode_cache_cpuid2(cpu, eax, ebx, ecx, edx); + encode_cache_cpuid2(cpu, caches, eax, ebx, ecx, edx); break; + } case 4: /* cache info: needed for Core compatibility */ if (cpu->cache_info_passthrough) { @@ -8979,6 +9003,9 @@ static void x86_cpu_realizefn(DeviceState *dev, Error= **errp) env->enable_legacy_cpuid2_cache =3D true; } =20 + if (!cpu->vendor_cpuid_only_v2) { + env->enable_legacy_vendor_cache =3D true; + } env->cache_info_cpuid4 =3D legacy_intel_cache_info; env->cache_info_amd =3D legacy_amd_cache_info; } diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 02cda176798f..243383efd602 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2078,6 +2078,7 @@ typedef struct CPUArchState { */ CPUCaches cache_info_cpuid4, cache_info_amd; bool enable_legacy_cpuid2_cache; + bool enable_legacy_vendor_cache; =20 /* MTRRs */ uint64_t mtrr_fixed[11]; --=20 2.34.1 From nobody Sat Nov 15 14:49:51 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750410633; cv=none; d=zohomail.com; s=zohoarc; b=MPwbo4nQnPeVd8TM1v9/zIVyHdpG3HCL41batStS84QKpyLCi1iGT8OyV1oJWULeNpYx2Wis2gLod23RyMcPfPspI37/KvNHExYk2pRrm8Q/4p4+2NcNXCH45bGr6qQIanzQcrETpYQM7yRn0Wkw7c6jGGkMV90tI0EdV5KlcA4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750410633; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=9VSjXO+HtpmwJnJDxNLfl89y497CsRdrjy2SqBfVfwE=; b=QD33um6hU6JdUVIIhOCB4Nn2u0895CqypVN9XYMaF2WWNz02JFPcRvTBVXuinz0IdT8sacJ8Za2VE1XpvxissIwr3Xoz8QNXaCSRSoTQuN0Hq8Ms8aP2mDY/3SCJQ76BMpDGjkcbyhsEDeE3oxojK+Exy/eXI0ttV98Nt18q/Tc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750410633316566.4355832524474; Fri, 20 Jun 2025 02:10:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uSXib-0002e8-5g; Fri, 20 Jun 2025 05:07:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSXiX-0002RD-8T for qemu-devel@nongnu.org; Fri, 20 Jun 2025 05:07:26 -0400 Received: from mgamail.intel.com ([198.175.65.14]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSXiP-0004zi-D2 for qemu-devel@nongnu.org; Fri, 20 Jun 2025 05:07:24 -0400 Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 02:07:15 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by orviesa005.jf.intel.com with ESMTP; 20 Jun 2025 02:07:11 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750410438; x=1781946438; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=orVDQ7hhzcZXq/b42GMTa4KUxc/JV9kxqkUb0nElsEc=; b=QZ1uIVb4+ru/bs4v5iNVaglzfQZHhgUhL/FwqK4xLhwv3eY6viWWRv+t RjE9RfuSnMXz2S1u2SoYj8c3MrNgR0fYQFxsqklYFcqGCHBilznYLbJF3 lKty1bMWSHy5T3RziBiBXgYcuxrP3LeiQAGtWht4Ts52l3pv4ylkdB+Ds 6ljTJkL0VCIicb3vXfGlOwyep90MXRvIQhkRTY4P9r8zad9rIFHG9CqSK TaW80BOA6YoGphPZHCliKRJSwT8h26OzcgnwnbFkmAWEy7pzkE8LHk5aS H3Anvl8sv/nMrcFqgOTuamnG7D/5U+AL58SFktH8m4+78u6JfB92UtmD7 g==; X-CSE-ConnectionGUID: CMnOakXTS7Kc/sMQFoeB/A== X-CSE-MsgGUID: TT3wHSS7TIqTPnvbCzSm+A== X-IronPort-AV: E=McAfee;i="6800,10657,11469"; a="56466805" X-IronPort-AV: E=Sophos;i="6.16,251,1744095600"; d="scan'208";a="56466805" X-CSE-ConnectionGUID: I7uco2X+RieTofx7SRwilQ== X-CSE-MsgGUID: 7GeHJErKSVWAGx81ov+g4A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,251,1744095600"; d="scan'208";a="156670146" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti , "Michael S . Tsirkin" , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Marcel Apfelbaum , Richard Henderson , Eduardo Habkost Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Babu Moger , Ewan Hai , Pu Wen , Tao Su , Yi Lai , Dapeng Mi , qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu Subject: [PATCH 12/16] i386/cpu: Select legacy cache model based on vendor in CPUID 0x4 Date: Fri, 20 Jun 2025 17:27:30 +0800 Message-Id: <20250620092734.1576677-13-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620092734.1576677-1-zhao1.liu@intel.com> References: <20250620092734.1576677-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750410635354116600 Content-Type: text/plain; charset="utf-8" As preparation for merging cache_info_cpuid4 and cache_info_amd in X86CPUState, set legacy cache model based on vendor in the CPUID 0x4 leaf. For AMD CPU, select legacy AMD cache model (in cache_info_amd) as the default cache model, otherwise, select legacy Intel cache model (in cache_info_cpuid4) as before. To ensure compatibility is not broken, add an enable_legacy_vendor_cache flag based on x-vendor-only-v2 to indicate cases where the legacy cache model should be used regardless of the vendor. For CPUID 0x4 leaf, enable_legacy_vendor_cache flag indicates to pick legacy Intel cache model, which is for compatibility with the behavior of PC machine v10.0 and older. The following explains how current vendor-based default legacy cache model ensures correctness without breaking compatibility. * For the PC machine v6.0 and older, vendor_cpuid_only=3Dfalse, and vendor_cpuid_only_v2=3Dfalse. - If the named CPU model has its own cache model, and doesn't use legacy cache model (legacy_cache=3Dfalse), then cache_info_cpuid4 and cache_info_amd are same, so 0x4 leaf uses its own cache model regardless of the vendor. - For max/host/named CPU (without its own cache model), then the flag enable_legacy_vendor_cache is true, they will use legacy Intel cache model just like their previous behavior. * For the PC machine v10.0 and older (to v6.1), vendor_cpuid_only=3Dtrue, and vendor_cpuid_only_v2=3Dfalse. - If the named CPU model has its own cache model (legacy_cache=3Dfalse), then cache_info_cpuid4 & cache_info_amd both equal to its own cache model, so it uses its own cache model in 0x4 leaf regardless of the vendor. Only AMD CPUs have all-0 leaf due to vendor_cpuid_only=3Dtrue, and this is exactly the behavior of these old machines. - For max/host/named CPU (without its own cache model), then the flag enable_legacy_vendor_cache is true, they will use legacy Intel cache model. Similarly, only AMD CPUs have all-0 leaf, and this is exactly the behavior of these old machines. * For the PC machine v10.1 and newer, vendor_cpuid_only=3Dtrue, and vendor_cpuid_only_v2=3Dtrue. - If the named CPU model has its own cache model (legacy_cache=3Dfalse), then cache_info_cpuid4 & cache_info_amd both equal to its own cache model, so it uses its own cache model in 0x4 leaf regardless of the vendor. And AMD CPUs have all-0 leaf. Nothing will change. - For max/host/named CPU (without its own cache model), then the flag enable_legacy_vendor_cache is false, the legacy cache model is selected based on vendor. For AMD CPU, it will use legacy AMD cache but still get all-0 leaf due to vendor_cpuid_only=3Dtrue. For non-AMD (Intel/Zhaoxin) CPU, it will use legacy Intel cache as expected. Here, selecting the legacy cache model based on the vendor does not change the previous (before the change) behavior. Therefore, the above analysis proves that, with the help of the flag enable_legacy_vendor_cache, it is acceptable to select the default legacy cache model based on the vendor. For the CPUID 0x4 leaf, in X86CPUState, a unified cache_info is enough. It only needs to be initialized and configured with the corresponding legacy cache model based on the vendor. Signed-off-by: Zhao Liu Reviewed-by: Dapeng Mi --- target/i386/cpu.c | 43 ++++++++++++++++++++++++++++++++++--------- 1 file changed, 34 insertions(+), 9 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 524d39de9ace..afbf11569ab4 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7517,7 +7517,35 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, encode_cache_cpuid2(cpu, caches, eax, ebx, ecx, edx); break; } - case 4: + case 4: { + const CPUCaches *caches; + + if (env->enable_legacy_vendor_cache) { + caches =3D &legacy_intel_cache_info; + } else { + /* + * FIXME: Temporarily select cache info model here based on + * vendor, and merge these 2 cache info models later. + * + * This condition covers the following cases (with + * enable_legacy_vendor_cache=3Dfalse): + * - When CPU model has its own cache model and doesn't use l= egacy + * cache model (legacy_model=3Doff). Then cache_info_amd and + * cache_info_cpuid4 are the same. + * + * - For v10.1 and newer machines, when CPU model uses legacy= cache + * model. Non-AMD CPUs use cache_info_cpuid4 like before an= d AMD + * CPU will use cache_info_amd. But this doesn't matter for= AMD + * CPU, because this leaf encodes all-0 for AMD whatever it= s cache + * model is. + */ + if (IS_AMD_CPU(env)) { + caches =3D &env->cache_info_amd; + } else { + caches =3D &env->cache_info_cpuid4; + } + } + /* cache info: needed for Core compatibility */ if (cpu->cache_info_passthrough) { x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); @@ -7545,30 +7573,26 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, =20 switch (count) { case 0: /* L1 dcache info */ - encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, - topo_info, + encode_cache_cpuid4(caches->l1d_cache, topo_info, eax, ebx, ecx, edx); if (!cpu->l1_cache_per_core) { *eax &=3D ~MAKE_64BIT_MASK(14, 12); } break; case 1: /* L1 icache info */ - encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, - topo_info, + encode_cache_cpuid4(caches->l1i_cache, topo_info, eax, ebx, ecx, edx); if (!cpu->l1_cache_per_core) { *eax &=3D ~MAKE_64BIT_MASK(14, 12); } break; case 2: /* L2 cache info */ - encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, - topo_info, + encode_cache_cpuid4(caches->l2_cache, topo_info, eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ if (cpu->enable_l3_cache) { - encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, - topo_info, + encode_cache_cpuid4(caches->l3_cache, topo_info, eax, ebx, ecx, edx); break; } @@ -7579,6 +7603,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, } } break; + } case 5: /* MONITOR/MWAIT Leaf */ *eax =3D cpu->mwait.eax; /* Smallest monitor-line size in bytes */ --=20 2.34.1 From nobody Sat Nov 15 14:49:51 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750410601; cv=none; d=zohomail.com; s=zohoarc; b=P+lyk1FuQKlKrGEPsyP3txuIB+HtHn0IyTjkLLJlr/VF674H9UhXEpv5pkOkzCLctwAWxjZfnwUMWeQHUOSkLomp6h5xxok9Yj4zZ/QdmP3kM1ZSyeS4nuA33klqRQva0YR2LjiI/qxn+DPcSDUgiaZ41Ec1Az+Rnd45wzznXD0= ARC-Message-Signature: i=1; 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Tsirkin" , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Marcel Apfelbaum , Richard Henderson , Eduardo Habkost Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Babu Moger , Ewan Hai , Pu Wen , Tao Su , Yi Lai , Dapeng Mi , qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu Subject: [PATCH 13/16] i386/cpu: Select legacy cache model based on vendor in CPUID 0x80000005 Date: Fri, 20 Jun 2025 17:27:31 +0800 Message-Id: <20250620092734.1576677-14-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620092734.1576677-1-zhao1.liu@intel.com> References: <20250620092734.1576677-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750410603234116600 Content-Type: text/plain; charset="utf-8" As preparation for merging cache_info_cpuid4 and cache_info_amd in X86CPUState, set legacy cache model based on vendor in the CPUID 0x80000005 leaf. For AMD CPU, select legacy AMD cache model (in cache_info_amd) as the default cache model like before, otherwise, select legacy Intel cache model (in cache_info_cpuid4). To ensure compatibility is not broken, add an enable_legacy_vendor_cache flag based on x-vendor-only-v2 to indicate cases where the legacy cache model should be used regardless of the vendor. For CPUID 0x80000005 leaf, enable_legacy_vendor_cache flag indicates to pick legacy AMD cache model, which is for compatibility with the behavior of PC machine v10.0 and older. The following explains how current vendor-based default legacy cache model ensures correctness without breaking compatibility. * For the PC machine v6.0 and older, vendor_cpuid_only=3Dfalse, and vendor_cpuid_only_v2=3Dfalse. - If the named CPU model has its own cache model, and doesn't use legacy cache model (legacy_cache=3Dfalse), then cache_info_cpuid4 and cache_info_amd are same, so 0x80000005 leaf uses its own cache model regardless of the vendor. - For max/host/named CPU (without its own cache model), then the flag enable_legacy_vendor_cache is true, they will use legacy AMD cache model just like their previous behavior. * For the PC machine v10.0 and older (to v6.1), vendor_cpuid_only=3Dtrue, and vendor_cpuid_only_v2=3Dfalse. - No change, since this leaf doesn't aware vendor_cpuid_only. * For the PC machine v10.1 and newer, vendor_cpuid_only=3Dtrue, and vendor_cpuid_only_v2=3Dtrue. - If the named CPU model has its own cache model (legacy_cache=3Dfalse), then cache_info_cpuid4 & cache_info_amd both equal to its own cache model, so it uses its own cache model in 0x80000005 leaf regardless of the vendor. Only Intel CPUs have all-0 leaf due to vendor_cpuid_only_2=3Dtrue, and this is exactly the expected behavior. - For max/host/named CPU (without its own cache model), then the flag enable_legacy_vendor_cache is false, the legacy cache model is selected based on vendor. For AMD CPU, it will use legacy AMD cache as expected. For Intel CPU, it will use legacy Intel cache but still get all-0 leaf due to vendor_cpuid_only_2=3Dtrue as expected. (Note) And for Zhaoxin CPU, it will use legacy Intel cache model instead of AMD's. This is the difference brought by this change! But it's correct since then Zhaoxin could have the consistent cache info in CPUID 0x2, 0x4 and 0x80000005 leaves. Here, except Zhaoxin, selecting the legacy cache model based on the vendor does not change the previous (before the change) behavior. And the change for Zhaoxin is also a good improvement. Therefore, the above analysis proves that, with the help of the flag enable_legacy_vendor_cache, it is acceptable to select the default legacy cache model based on the vendor. For the CPUID 0x80000005 leaf, in X86CPUState, a unified cache_info is enough. It only needs to be initialized and configured with the corresponding legacy cache model based on the vendor. Cc: EwanHai Signed-off-by: Zhao Liu --- Note, side effect of this patch: fix the inconsistency cache info for Zhaoxin. For more details, see the commit message above. --- target/i386/cpu.c | 36 ++++++++++++++++++++++++++++++++---- 1 file changed, 32 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index afbf11569ab4..16b4ecb76113 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7945,8 +7945,35 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, *ecx =3D env->cpuid_model[(index - 0x80000002) * 4 + 2]; *edx =3D env->cpuid_model[(index - 0x80000002) * 4 + 3]; break; - case 0x80000005: - /* cache info (L1 cache/TLB Associativity Field) */ + case 0x80000005: { /* cache info (L1 cache/TLB Associativity Field) */ + const CPUCaches *caches; + + if (env->enable_legacy_vendor_cache) { + caches =3D &legacy_amd_cache_info; + } else { + /* + * FIXME: Temporarily select cache info model here based on + * vendor, and merge these 2 cache info models later. + * + * This condition covers the following cases (with + * enable_legacy_vendor_cache=3Dfalse): + * - When CPU model has its own cache model and doesn't uses = legacy + * cache model (legacy_model=3Doff). Then cache_info_amd and + * cache_info_cpuid4 are the same. + * + * - For v10.1 and newer machines, when CPU model uses legacy= cache + * model. AMD CPUs use cache_info_amd like before and non-A= MD + * CPU will use cache_info_cpuid4. But this doesn't matter, + * because for Intel CPU, it will get all-0 leaf, and Zhaox= in CPU + * will get correct cache info. Both are expected. + */ + if (IS_AMD_CPU(env)) { + caches =3D &env->cache_info_amd; + } else { + caches =3D &env->cache_info_cpuid4; + } + } + if (cpu->cache_info_passthrough) { x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); break; @@ -7961,9 +7988,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); *ebx =3D (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); - *ecx =3D encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); - *edx =3D encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); + *ecx =3D encode_cache_cpuid80000005(caches->l1d_cache); + *edx =3D encode_cache_cpuid80000005(caches->l1i_cache); break; + } case 0x80000006: /* cache info (L2 cache/TLB/L3 cache) */ if (cpu->cache_info_passthrough) { --=20 2.34.1 From nobody Sat Nov 15 14:49:51 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750410503; cv=none; d=zohomail.com; s=zohoarc; b=Y5tDFruB7KS76rBrHC5dN7npjZAkVXovBBhQ/pvraPRhSMvBFaTTohFl8S2ynlozBYag7ay85k0hEmItDS29wzsmMsbhWAUXfMZCwdrnF3KC3oqHMbmMi59LIfgpFzQU6Txrp+7ny2fgD++K9IcDFZMFzdbdMItOB1rlq2Gre7Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750410503; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=SWjI3He5qg6bljCGhaEOF+JtV5BNLlME4awZSl+fr8k=; b=DaKG/iQjM0An4IQIS/ciOVDQDSemTFUiF20XQJkJ0Gy2SjVzvj1S1PO/9TYx0OymRkjPsQ3mDh7WspJbNX5tKrLhuQG6pp/Aesrcp5zQPGyr2B6OlR6xH/7b8HDK1ORTDlo9yYDEy5lHEOC7p55gXq+WhjF4uhsqhQpZyGhWvnU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750410503552976.5193408038006; Fri, 20 Jun 2025 02:08:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uSXih-000338-NC; Fri, 20 Jun 2025 05:07:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSXib-0002jS-SU for qemu-devel@nongnu.org; Fri, 20 Jun 2025 05:07:31 -0400 Received: from mgamail.intel.com ([198.175.65.14]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSXiY-00055r-G7 for qemu-devel@nongnu.org; Fri, 20 Jun 2025 05:07:29 -0400 Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 02:07:24 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by orviesa005.jf.intel.com with ESMTP; 20 Jun 2025 02:07:20 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750410447; x=1781946447; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=f3bs6AqT/+bwfc6zT2OHpOSRXd2vnkmqjBgAgaEUjTQ=; b=drDspnDKEpsLMwoBLw+AP/INbYaLtK3vhMsVBliOm88Nv5ZbF7jozLCX rfgzfflZ0rWIYuhnX2fxLF5bvikGDHBUOQtsxrwBOnMSuowW+afDOb9Uk j55PLl/RK/+sS0trRs7LD8GbswkMOUUZnK7AbaPq7ib7Mv4LFsWXunVg7 XoLO8UWutlzhoT5TgK0tboKfDhCRNnIj5AXLo7acHV+T0Onauq0xApUz+ xtcSR+E95wkDHA+qUSKEenWzLoVQn6KY0i8aqDDNVYXUt5W26O89ggNbE fLq5POVSgXhFnJ6B1Rn2fbI+t0gShPMvfEVQQL92Onvp1v2EnRD7zFwju A==; X-CSE-ConnectionGUID: rD+RCuBRT1SksEWP8mGjPQ== X-CSE-MsgGUID: y7wi0XORRLK2bBcaCxrvsg== X-IronPort-AV: E=McAfee;i="6800,10657,11469"; a="56466837" X-IronPort-AV: E=Sophos;i="6.16,251,1744095600"; d="scan'208";a="56466837" X-CSE-ConnectionGUID: 3HFMzeHmSiWAq5U13Fc5eg== X-CSE-MsgGUID: QFtiuitrStejMBG7bPu+PQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,251,1744095600"; d="scan'208";a="156670179" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti , "Michael S . Tsirkin" , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Marcel Apfelbaum , Richard Henderson , Eduardo Habkost Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Babu Moger , Ewan Hai , Pu Wen , Tao Su , Yi Lai , Dapeng Mi , qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu Subject: [PATCH 14/16] i386/cpu: Select legacy cache model based on vendor in CPUID 0x80000006 Date: Fri, 20 Jun 2025 17:27:32 +0800 Message-Id: <20250620092734.1576677-15-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620092734.1576677-1-zhao1.liu@intel.com> References: <20250620092734.1576677-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750410506948116600 Content-Type: text/plain; charset="utf-8" As preparation for merging cache_info_cpuid4 and cache_info_amd in X86CPUState, set legacy cache model based on vendor in the CPUID 0x80000006 leaf. For AMD CPU, select legacy AMD cache model (in cache_info_amd) as the default cache model like before, otherwise, select legacy Intel cache model (in cache_info_cpuid4). To ensure compatibility is not broken, add an enable_legacy_vendor_cache flag based on x-vendor-only-v2 to indicate cases where the legacy cache model should be used regardless of the vendor. For CPUID 0x80000006 leaf, enable_legacy_vendor_cache flag indicates to pick legacy Intel cache model, which is for compatibility with the behavior of PC machine v10.0 and older. The following explains how current vendor-based default legacy cache model ensures correctness without breaking compatibility. * For the PC machine v6.0 and older, vendor_cpuid_only=3Dfalse, and vendor_cpuid_only_v2=3Dfalse. - If the named CPU model has its own cache model, and doesn't use legacy cache model (legacy_cache=3Dfalse), then cache_info_cpuid4 and cache_info_amd are same, so 0x80000006 leaf uses its own cache model regardless of the vendor. - For max/host/named CPU (without its own cache model), then the flag enable_legacy_vendor_cache is true, they will use legacy AMD cache model just like their previous behavior. * For the PC machine v10.0 and older (to v6.1), vendor_cpuid_only=3Dtrue, and vendor_cpuid_only_v2=3Dfalse. - No change, since this leaf doesn't aware vendor_cpuid_only. * For the PC machine v10.1 and newer, vendor_cpuid_only=3Dtrue, and vendor_cpuid_only_v2=3Dtrue. - If the named CPU model has its own cache model (legacy_cache=3Dfalse), then cache_info_cpuid4 & cache_info_amd both equal to its own cache model, so it uses its own cache model in 0x80000006 leaf regardless of the vendor. Intel and Zhaoxin CPUs have their special encoding based on SDM, which is the expected behavior and no different from before. - For max/host/named CPU (without its own cache model), then the flag enable_legacy_vendor_cache is false, the legacy cache model is selected based on vendor. For AMD CPU, it will use legacy AMD cache as before. For non-AMD (Intel/Zhaoxin) CPU, it will use legacy Intel cache and be encoded based on SDM as expected. Here, selecting the legacy cache model based on the vendor does not change the previous (before the change) behavior. Therefore, the above analysis proves that, with the help of the flag enable_legacy_vendor_cache, it is acceptable to select the default legacy cache model based on the vendor. For the CPUID 0x80000006 leaf, in X86CPUState, a unified cache_info is enough. It only needs to be initialized and configured with the corresponding legacy cache model based on the vendor. Signed-off-by: Zhao Liu --- target/i386/cpu.c | 36 +++++++++++++++++++++++++++++++----- 1 file changed, 31 insertions(+), 5 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 16b4ecb76113..4fa5907027a0 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7992,8 +7992,33 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, *edx =3D encode_cache_cpuid80000005(caches->l1i_cache); break; } - case 0x80000006: - /* cache info (L2 cache/TLB/L3 cache) */ + case 0x80000006: { /* cache info (L2 cache/TLB/L3 cache) */ + const CPUCaches *caches; + + if (env->enable_legacy_vendor_cache) { + caches =3D &legacy_amd_cache_info; + } else { + /* + * FIXME: Temporarily select cache info model here based on + * vendor, and merge these 2 cache info models later. + * + * This condition covers the following cases (with + * enable_legacy_vendor_cache=3Dfalse): + * - When CPU model has its own cache model and doesn't uses = legacy + * cache model (legacy_model=3Doff). Then cache_info_amd and + * cache_info_cpuid4 are the same. + * + * - For v10.1 and newer machines, when CPU model uses legacy= cache + * model. AMD CPUs use cache_info_amd like before and non-A= MD + * CPU (Intel & Zhaoxin) will use cache_info_cpuid4 as expe= cted. + */ + if (IS_AMD_CPU(env)) { + caches =3D &env->cache_info_amd; + } else { + caches =3D &env->cache_info_cpuid4; + } + } + if (cpu->cache_info_passthrough) { x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); break; @@ -8002,7 +8027,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, if (cpu->vendor_cpuid_only_v2 && (IS_INTEL_CPU(env) || IS_ZHAOXIN_CPU(env))) { *eax =3D *ebx =3D 0; - encode_cache_cpuid80000006(env->cache_info_cpuid4.l2_cache, + encode_cache_cpuid80000006(caches->l2_cache, NULL, ecx, edx, false); break; } @@ -8016,11 +8041,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, (X86_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | (L2_ITLB_4K_ENTRIES); =20 - encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, + encode_cache_cpuid80000006(caches->l2_cache, cpu->enable_l3_cache ? - env->cache_info_amd.l3_cache : NULL, + caches->l3_cache : NULL, ecx, edx, true); break; + } case 0x80000007: *eax =3D 0; *ebx =3D env->features[FEAT_8000_0007_EBX]; --=20 2.34.1 From nobody Sat Nov 15 14:49:51 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750410503; cv=none; d=zohomail.com; s=zohoarc; b=GBzI0alI2NPJz2hvhuRY9aOwa8FKYAr2xCSGzPaNpgkYobV1U0Ka0NEcH1NHWZcL72JMKu6xDetCTPnCUyxQgmVqaRdtOd2C8VN+VpfYoQK7t/TSVZ+aq7g0CEHSfMQrqDUwbnEYayrhldWbMgULWa1IhKtn/T9HepKRAVdxc6A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750410503; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=3I7Iae/8HxfKj7Igc56fubtfZe6BY65Ex1r5t4LCkug=; b=kgp6KttFxUwjQ+AwqUgzrFp8gW+DMBJVnj3v6F4IhQiFOYtVMeVwgcyT5PpM+NqsAVuxf1bO7oIHlRjLaJZ2oM4TbBrvadg5SFC44VZIBbeCaDUJqi8F29fGBjFxDrHBT634VXiqc0+qiVZRz3t4w9Tyq1qdsX6sebC8YXNdHz8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750410503786817.4118501209498; Fri, 20 Jun 2025 02:08:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uSXjC-0003gD-FI; Fri, 20 Jun 2025 05:08:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSXiu-0003El-TI for qemu-devel@nongnu.org; Fri, 20 Jun 2025 05:07:58 -0400 Received: from mgamail.intel.com ([198.175.65.14]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSXid-0004zi-IB for qemu-devel@nongnu.org; Fri, 20 Jun 2025 05:07:37 -0400 Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 02:07:29 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by orviesa005.jf.intel.com with ESMTP; 20 Jun 2025 02:07:25 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750410452; x=1781946452; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lh9RIWNb8fbwwbj3bBbTOmbr82tAR9PK8zJMLq0s76U=; b=aRTyr8srMDcJL0NDmmBOgYIht+VPuq3//h2fCreK+kBozrphnbd6T7z5 2MIxPOE05sQFkPn0ZuLUH+wayd2zj+/nXT7v5GvXNn0qG+vPgDZot+iFx eKhC6ItU9+4brGThQ2vPW+iGkKLmHEidenBH6W+vtzN+yyH35yqj5tvvM n19pUo4jnMd6KuIDo/xU0EVQkLSmTtJpj79EuNdm168pMT8pDc5AFBhtT SWsNhYqmyJ7AfJDSSs1vDa6BfESgm/0ETfmLnM69YMsrH8dfB5hHhOMdo ODuaNxpYe+5B53/Ukj9/L+oymFrh0bzM9WMRmRfsONy16oOtSg19Rkz6Q w==; X-CSE-ConnectionGUID: 0nqncCz7SMSkW1J9wx6n6Q== X-CSE-MsgGUID: EXQ4LDGSTqWQNdHLTolkDA== X-IronPort-AV: E=McAfee;i="6800,10657,11469"; a="56466846" X-IronPort-AV: E=Sophos;i="6.16,251,1744095600"; d="scan'208";a="56466846" X-CSE-ConnectionGUID: poMZEsFRTbOjvohkAsR8OQ== X-CSE-MsgGUID: U8+wHQ3oQb6GMJ50crTdvA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,251,1744095600"; d="scan'208";a="156670194" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti , "Michael S . Tsirkin" , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Marcel Apfelbaum , Richard Henderson , Eduardo Habkost Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Babu Moger , Ewan Hai , Pu Wen , Tao Su , Yi Lai , Dapeng Mi , qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu Subject: [PATCH 15/16] i386/cpu: Select legacy cache model based on vendor in CPUID 0x8000001D Date: Fri, 20 Jun 2025 17:27:33 +0800 Message-Id: <20250620092734.1576677-16-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620092734.1576677-1-zhao1.liu@intel.com> References: <20250620092734.1576677-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750410506889116600 Content-Type: text/plain; charset="utf-8" As preparation for merging cache_info_cpuid4 and cache_info_amd in X86CPUState, set legacy cache model based on vendor in the CPUID 0x8000001D leaf. For AMD CPU, select legacy AMD cache model (in cache_info_amd) as the default cache model like before, otherwise, select legacy Intel cache model (in cache_info_cpuid4). In fact, for Intel (and Zhaoxin) CPU, this change is safe because the extended CPUID level supported by Intel is up to 0x80000008. So Intel Guest doesn't have this 0x8000001D leaf. Although someone could bump "xlevel" up to 0x8000001D for Intel Guest, it's meaningless and this is undefined behavior. This leaf should be considered reserved, but the SDM does not explicitly state this. So, there's no need to specifically use vendor_cpuid_only_v2 to fix anything, as it doesn't even qualify as a fix since nothing is currently broken. Therefore, it is acceptable to select the default legacy cache model based on the vendor. For the CPUID 0x8000001D leaf, in X86CPUState, a unified cache_info is enough. It only needs to be initialized and configured with the corresponding legacy cache model based on the vendor. Signed-off-by: Zhao Liu --- target/i386/cpu.c | 26 +++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 4fa5907027a0..4e9ac37850c0 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8089,7 +8089,22 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, *edx =3D 0; } break; - case 0x8000001D: + case 0x8000001D: { + const CPUCaches *caches; + + /* + * FIXME: Temporarily select cache info model here based on + * vendor, and merge these 2 cache info models later. + * + * Intel doesn't support this leaf so that Intel Guests don't + * have this leaf. This change is harmless to Intel CPUs. + */ + if (IS_AMD_CPU(env)) { + caches =3D &env->cache_info_amd; + } else { + caches =3D &env->cache_info_cpuid4; + } + *eax =3D 0; if (cpu->cache_info_passthrough) { x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); @@ -8097,19 +8112,19 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, } switch (count) { case 0: /* L1 dcache info */ - encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, + encode_cache_cpuid8000001d(caches->l1d_cache, topo_info, eax, ebx, ecx, edx); break; case 1: /* L1 icache info */ - encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, + encode_cache_cpuid8000001d(caches->l1i_cache, topo_info, eax, ebx, ecx, edx); break; case 2: /* L2 cache info */ - encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, + encode_cache_cpuid8000001d(caches->l2_cache, topo_info, eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ - encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, + encode_cache_cpuid8000001d(caches->l3_cache, topo_info, eax, ebx, ecx, edx); break; default: /* end of info */ @@ -8120,6 +8135,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, *edx &=3D CACHE_NO_INVD_SHARING | CACHE_INCLUSIVE; } break; + } case 0x8000001E: if (cpu->core_id <=3D 255) { encode_topo_cpuid8000001e(cpu, topo_info, eax, ebx, ecx, edx); --=20 2.34.1 From nobody Sat Nov 15 14:49:51 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750410556; cv=none; d=zohomail.com; s=zohoarc; b=g1Z6jc6qfxTlTl+kxENu2UfZT3tNqseSExJ/dxaA7yI1LC3rGrzm21ghlgN4WD55tkW1mUyRI2fzuAySEj6IBoh0NljNlFB0qYqY/cfvlWiyOGn1BfYJ6sk5bEArVsHFnVrNCLP1OIHEUE3/LrCUMmrwfa4c34L6fOhvXz6wYww= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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Fri, 20 Jun 2025 05:08:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSXix-0003Ho-Sm for qemu-devel@nongnu.org; Fri, 20 Jun 2025 05:08:00 -0400 Received: from mgamail.intel.com ([198.175.65.14]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSXiq-00055r-MG for qemu-devel@nongnu.org; Fri, 20 Jun 2025 05:07:50 -0400 Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 02:07:34 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by orviesa005.jf.intel.com with ESMTP; 20 Jun 2025 02:07:30 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750410465; x=1781946465; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TObZAbEWJ2CPPP3wgEr0dN5obTobFnYleyBjpYYTALU=; b=JwRILnbgdzf6vR0z5/MksS5y/kfD5KktxQAcMOnxz99tTJxZIpVxP0ym OVaZPbPXcQXg8nCBzWZK9y1SVexXkSPyBKCCRkeiMTowrDlmIVzjLo54I adol5KzKCFMfn9lErcq9pP4LVhVcG3YvlrhKq5HSBmM3/G0BXuk3Vm/mJ Ow+qMLEBlKjOXqssWGJYOLMFZvadaSqdMdCI+F4F6SJ25VSNBYC1QZAA8 dbBpwP4jOX/cq9eju7SM18AoLezfCOH47SneM5z2RzeQZLqUqnwU5QREz rVvtFpbgvoBc9Em1E5S61tdj+2xniH6mX/CTgke2bdcjj20n0Vb6NhHYN A==; X-CSE-ConnectionGUID: 3IZ8j0/CRMiiXacSjuxWnw== X-CSE-MsgGUID: 0P0coZWVSIyyyiHj+edr7w== X-IronPort-AV: E=McAfee;i="6800,10657,11469"; a="56466860" X-IronPort-AV: E=Sophos;i="6.16,251,1744095600"; d="scan'208";a="56466860" X-CSE-ConnectionGUID: wm8HKNloTsWHheErUKlKqg== X-CSE-MsgGUID: wPYRgqVVSm6SMs4Z/8d5ig== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,251,1744095600"; d="scan'208";a="156670210" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti , "Michael S . Tsirkin" , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Marcel Apfelbaum , Richard Henderson , Eduardo Habkost Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Babu Moger , Ewan Hai , Pu Wen , Tao Su , Yi Lai , Dapeng Mi , qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu Subject: [PATCH 16/16] i386/cpu: Use a unified cache_info in X86CPUState Date: Fri, 20 Jun 2025 17:27:34 +0800 Message-Id: <20250620092734.1576677-17-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620092734.1576677-1-zhao1.liu@intel.com> References: <20250620092734.1576677-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750410558653116600 Content-Type: text/plain; charset="utf-8" At present, all cases using the cache model (CPUID 0x2, 0x4, 0x80000005, 0x80000006 and 0x8000001D leaves) have been verified to be able to select either cache_info_intel or cache_info_amd based on the vendor. Therefore, further merge cache_info_intel and cache_info_amd into a unified cache_info in X86CPUState, and during its initialization, set different legacy cache models based on the vendor. Signed-off-by: Zhao Liu Reviewed-by: Dapeng Mi --- target/i386/cpu.c | 150 ++++++++-------------------------------------- target/i386/cpu.h | 5 +- 2 files changed, 27 insertions(+), 128 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 4e9ac37850c0..c1d1289ee9de 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7484,27 +7484,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, } else if (env->enable_legacy_vendor_cache) { caches =3D &legacy_intel_cache_info; } else { - /* - * FIXME: Temporarily select cache info model here based on - * vendor, and merge these 2 cache info models later. - * - * This condition covers the following cases (with - * enable_legacy_vendor_cache=3Dfalse): - * - When CPU model has its own cache model and doesn't use l= egacy - * cache model (legacy_model=3Doff). Then cache_info_amd and - * cache_info_cpuid4 are the same. - * - * - For v10.1 and newer machines, when CPU model uses legacy= cache - * model. Non-AMD CPUs use cache_info_cpuid4 like before an= d AMD - * CPU will use cache_info_amd. But this doesn't matter for= AMD - * CPU, because this leaf encodes all-0 for AMD whatever it= s cache - * model is. - */ - if (IS_AMD_CPU(env)) { - caches =3D &env->cache_info_amd; - } else { - caches =3D &env->cache_info_cpuid4; - } + caches =3D &env->cache_info; } =20 if (cpu->cache_info_passthrough) { @@ -7523,27 +7503,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, if (env->enable_legacy_vendor_cache) { caches =3D &legacy_intel_cache_info; } else { - /* - * FIXME: Temporarily select cache info model here based on - * vendor, and merge these 2 cache info models later. - * - * This condition covers the following cases (with - * enable_legacy_vendor_cache=3Dfalse): - * - When CPU model has its own cache model and doesn't use l= egacy - * cache model (legacy_model=3Doff). Then cache_info_amd and - * cache_info_cpuid4 are the same. - * - * - For v10.1 and newer machines, when CPU model uses legacy= cache - * model. Non-AMD CPUs use cache_info_cpuid4 like before an= d AMD - * CPU will use cache_info_amd. But this doesn't matter for= AMD - * CPU, because this leaf encodes all-0 for AMD whatever it= s cache - * model is. - */ - if (IS_AMD_CPU(env)) { - caches =3D &env->cache_info_amd; - } else { - caches =3D &env->cache_info_cpuid4; - } + caches =3D &env->cache_info; } =20 /* cache info: needed for Core compatibility */ @@ -7951,27 +7911,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, if (env->enable_legacy_vendor_cache) { caches =3D &legacy_amd_cache_info; } else { - /* - * FIXME: Temporarily select cache info model here based on - * vendor, and merge these 2 cache info models later. - * - * This condition covers the following cases (with - * enable_legacy_vendor_cache=3Dfalse): - * - When CPU model has its own cache model and doesn't uses = legacy - * cache model (legacy_model=3Doff). Then cache_info_amd and - * cache_info_cpuid4 are the same. - * - * - For v10.1 and newer machines, when CPU model uses legacy= cache - * model. AMD CPUs use cache_info_amd like before and non-A= MD - * CPU will use cache_info_cpuid4. But this doesn't matter, - * because for Intel CPU, it will get all-0 leaf, and Zhaox= in CPU - * will get correct cache info. Both are expected. - */ - if (IS_AMD_CPU(env)) { - caches =3D &env->cache_info_amd; - } else { - caches =3D &env->cache_info_cpuid4; - } + caches =3D &env->cache_info; } =20 if (cpu->cache_info_passthrough) { @@ -7998,25 +7938,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, if (env->enable_legacy_vendor_cache) { caches =3D &legacy_amd_cache_info; } else { - /* - * FIXME: Temporarily select cache info model here based on - * vendor, and merge these 2 cache info models later. - * - * This condition covers the following cases (with - * enable_legacy_vendor_cache=3Dfalse): - * - When CPU model has its own cache model and doesn't uses = legacy - * cache model (legacy_model=3Doff). Then cache_info_amd and - * cache_info_cpuid4 are the same. - * - * - For v10.1 and newer machines, when CPU model uses legacy= cache - * model. AMD CPUs use cache_info_amd like before and non-A= MD - * CPU (Intel & Zhaoxin) will use cache_info_cpuid4 as expe= cted. - */ - if (IS_AMD_CPU(env)) { - caches =3D &env->cache_info_amd; - } else { - caches =3D &env->cache_info_cpuid4; - } + caches =3D &env->cache_info; } =20 if (cpu->cache_info_passthrough) { @@ -8089,22 +8011,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, *edx =3D 0; } break; - case 0x8000001D: { - const CPUCaches *caches; - - /* - * FIXME: Temporarily select cache info model here based on - * vendor, and merge these 2 cache info models later. - * - * Intel doesn't support this leaf so that Intel Guests don't - * have this leaf. This change is harmless to Intel CPUs. - */ - if (IS_AMD_CPU(env)) { - caches =3D &env->cache_info_amd; - } else { - caches =3D &env->cache_info_cpuid4; - } - + case 0x8000001D: *eax =3D 0; if (cpu->cache_info_passthrough) { x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); @@ -8112,19 +8019,19 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, } switch (count) { case 0: /* L1 dcache info */ - encode_cache_cpuid8000001d(caches->l1d_cache, + encode_cache_cpuid8000001d(env->cache_info.l1d_cache, topo_info, eax, ebx, ecx, edx); break; case 1: /* L1 icache info */ - encode_cache_cpuid8000001d(caches->l1i_cache, + encode_cache_cpuid8000001d(env->cache_info.l1i_cache, topo_info, eax, ebx, ecx, edx); break; case 2: /* L2 cache info */ - encode_cache_cpuid8000001d(caches->l2_cache, + encode_cache_cpuid8000001d(env->cache_info.l2_cache, topo_info, eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ - encode_cache_cpuid8000001d(caches->l3_cache, + encode_cache_cpuid8000001d(env->cache_info.l3_cache, topo_info, eax, ebx, ecx, edx); break; default: /* end of info */ @@ -8135,7 +8042,6 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, *edx &=3D CACHE_NO_INVD_SHARING | CACHE_INCLUSIVE; } break; - } case 0x8000001E: if (cpu->core_id <=3D 255) { encode_topo_cpuid8000001e(cpu, topo_info, eax, ebx, ecx, edx); @@ -8825,46 +8731,34 @@ static bool x86_cpu_update_smp_cache_topo(MachineSt= ate *ms, X86CPU *cpu, =20 level =3D machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D); if (level !=3D CPU_TOPOLOGY_LEVEL_DEFAULT) { - env->cache_info_cpuid4.l1d_cache->share_level =3D level; - env->cache_info_amd.l1d_cache->share_level =3D level; + env->cache_info.l1d_cache->share_level =3D level; } else { machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D, - env->cache_info_cpuid4.l1d_cache->share_level); - machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D, - env->cache_info_amd.l1d_cache->share_level); + env->cache_info.l1d_cache->share_level); } =20 level =3D machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I); if (level !=3D CPU_TOPOLOGY_LEVEL_DEFAULT) { - env->cache_info_cpuid4.l1i_cache->share_level =3D level; - env->cache_info_amd.l1i_cache->share_level =3D level; + env->cache_info.l1i_cache->share_level =3D level; } else { machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I, - env->cache_info_cpuid4.l1i_cache->share_level); - machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I, - env->cache_info_amd.l1i_cache->share_level); + env->cache_info.l1i_cache->share_level); } =20 level =3D machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2); if (level !=3D CPU_TOPOLOGY_LEVEL_DEFAULT) { - env->cache_info_cpuid4.l2_cache->share_level =3D level; - env->cache_info_amd.l2_cache->share_level =3D level; + env->cache_info.l2_cache->share_level =3D level; } else { machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2, - env->cache_info_cpuid4.l2_cache->share_level); - machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2, - env->cache_info_amd.l2_cache->share_level); + env->cache_info.l2_cache->share_level); } =20 level =3D machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3); if (level !=3D CPU_TOPOLOGY_LEVEL_DEFAULT) { - env->cache_info_cpuid4.l3_cache->share_level =3D level; - env->cache_info_amd.l3_cache->share_level =3D level; + env->cache_info.l3_cache->share_level =3D level; } else { machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3, - env->cache_info_cpuid4.l3_cache->share_level); - machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3, - env->cache_info_amd.l3_cache->share_level); + env->cache_info.l3_cache->share_level); } =20 if (!machine_check_smp_cache(ms, errp)) { @@ -9091,7 +8985,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error= **errp) "CPU model '%s' doesn't support legacy-cache=3Doff"= , name); return; } - env->cache_info_cpuid4 =3D env->cache_info_amd =3D *cache_info; + env->cache_info =3D *cache_info; } else { /* Build legacy cache information */ if (!cpu->consistent_cache) { @@ -9101,8 +8995,12 @@ static void x86_cpu_realizefn(DeviceState *dev, Erro= r **errp) if (!cpu->vendor_cpuid_only_v2) { env->enable_legacy_vendor_cache =3D true; } - env->cache_info_cpuid4 =3D legacy_intel_cache_info; - env->cache_info_amd =3D legacy_amd_cache_info; + + if (IS_AMD_CPU(env)) { + env->cache_info =3D legacy_amd_cache_info; + } else { + env->cache_info =3D legacy_intel_cache_info; + } } =20 #ifndef CONFIG_USER_ONLY diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 243383efd602..3f79db679888 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2072,11 +2072,12 @@ typedef struct CPUArchState { /* Features that were explicitly enabled/disabled */ FeatureWordArray user_features; uint32_t cpuid_model[12]; - /* Cache information for CPUID. When legacy-cache=3Don, the cache data + /* + * Cache information for CPUID. When legacy-cache=3Don, the cache data * on each CPUID leaf will be different, because we keep compatibility * with old QEMU versions. */ - CPUCaches cache_info_cpuid4, cache_info_amd; + CPUCaches cache_info; bool enable_legacy_cpuid2_cache; bool enable_legacy_vendor_cache; =20 --=20 2.34.1