From nobody Sat Nov 15 14:49:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750404366; cv=none; d=zohomail.com; s=zohoarc; b=nm+Tg2SEm3wm/8KTStmNqBGcghuj5e4rHJKCo+bQx0+tgWnqDm7N61ayy5UpcLqNvscCi4XGlZuEpvhUtNd2f/2SqV+mmHVrDR/2X/JDQ0PH1UYPiQw/NXmGsoY+uyb6I+K42Gz8f1ia489fPnLgvQABLvTJGRTRlAZjoU4GkJ0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750404366; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=mbOdkfpYyp7kIr42vKkLcOZpOPp23UWAVPD4q33mu90=; b=AbmdYxIcqF+uCo84Xv02UCfd3PJPObwQtQUutvqyg7I7Q/pmhi0JufwW/E66zhbmmRdThv/4GrL2tiMRo9nyOjHQ5lwVFvvmaFchApV3b2hpn02yJ5pz1GrXfFRA5jRYuc6yXov5Rv9R+QmqW8DepVq7945/RXW9p5WMFg+1/ZQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750404366957647.4089198168323; Fri, 20 Jun 2025 00:26:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uSW4s-0004YD-Dy; Fri, 20 Jun 2025 03:22:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW4p-0004Xo-2D for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:22:19 -0400 Received: from mgamail.intel.com ([198.175.65.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW4m-0008Ff-Vn for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:22:18 -0400 Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:22:15 -0700 Received: from spr-s2600bt.bj.intel.com ([10.240.192.127]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:22:10 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750404137; x=1781940137; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5UoRcdKSqNg/li5KK8fdKoy5G7botyobFOpaQrzfZq0=; b=Igc7UUMliO75Yej9WX8jtoX7rslO2Q6vX5vDQdPey9xWjbu6nO0jRWAs Rk9mh/BDAQawOW15rk4NiOWRF77g1mG4xlmUzvgIP7dwJU+q1PGLsI24l ycwm0D3gHmvx6b7S7jlarZOoCvZVtBrLJksi6z64kn/Yyl8xfJy3j7MnE YeiJgpZC33nfPdzXtxlkndx3faPRijhpFvYcW+dcn5mY9Bbt3ngEsN1om dlAxUtmRZMp17p/w3IeHxH0OYnWEWMmtQ1eWQq2r+vYzYamxw0imQ64ld Aao/pO0IImEnFBY+MvjzcfE20fDY6B5mO9pNxR9moQAcjrqOhKX/+UwqO g==; X-CSE-ConnectionGUID: BW6o+M/pRISxVEpLiXJuGQ== X-CSE-MsgGUID: QJuollHNRqyOhQ+0q1Xepw== X-IronPort-AV: E=McAfee;i="6800,10657,11469"; a="52532247" X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="52532247" X-CSE-ConnectionGUID: ER1V5mPBTHeLdJT8aE/yhg== X-CSE-MsgGUID: 4jM9AftOTVarUqId9ctwig== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="181863044" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Subject: [PATCH v2 01/19] intel_iommu: Rename vtd_ce_get_rid2pasid_entry to vtd_ce_get_pasid_entry Date: Fri, 20 Jun 2025 15:17:55 +0800 Message-Id: <20250620071813.55571-2-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620071813.55571-1-zhenzhong.duan@intel.com> References: <20250620071813.55571-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.21; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750404368451116600 In early days vtd_ce_get_rid2pasid_entry() was used to get pasid entry of rid2pasid, then it was extended to get any pasid entry. So a new name vtd_ce_get_pasid_entry is better to match what it actually does. No functional change intended. Signed-off-by: Zhenzhong Duan Reviewed-by: Cl=C3=A9ment Mathieu--Drif Reviewed-by: Yi Liu Reviewed-by: Eric Auger --- hw/i386/intel_iommu.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 69d72ad35c..f0b1f90eff 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -944,7 +944,7 @@ static int vtd_get_pe_from_pasid_table(IntelIOMMUState = *s, return 0; } =20 -static int vtd_ce_get_rid2pasid_entry(IntelIOMMUState *s, +static int vtd_ce_get_pasid_entry(IntelIOMMUState *s, VTDContextEntry *ce, VTDPASIDEntry *pe, uint32_t pasid) @@ -1025,7 +1025,7 @@ static uint32_t vtd_get_iova_level(IntelIOMMUState *s, VTDPASIDEntry pe; =20 if (s->root_scalable) { - vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); + vtd_ce_get_pasid_entry(s, ce, &pe, pasid); if (s->flts) { return VTD_PE_GET_FL_LEVEL(&pe); } else { @@ -1048,7 +1048,7 @@ static uint32_t vtd_get_iova_agaw(IntelIOMMUState *s, VTDPASIDEntry pe; =20 if (s->root_scalable) { - vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); + vtd_ce_get_pasid_entry(s, ce, &pe, pasid); return 30 + ((pe.val[0] >> 2) & VTD_SM_PASID_ENTRY_AW) * 9; } =20 @@ -1116,7 +1116,7 @@ static dma_addr_t vtd_get_iova_pgtbl_base(IntelIOMMUS= tate *s, VTDPASIDEntry pe; =20 if (s->root_scalable) { - vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); + vtd_ce_get_pasid_entry(s, ce, &pe, pasid); if (s->flts) { return pe.val[2] & VTD_SM_PASID_ENTRY_FLPTPTR; } else { @@ -1522,7 +1522,7 @@ static int vtd_ce_rid2pasid_check(IntelIOMMUState *s, * has valid rid2pasid setting, which includes valid * rid2pasid field and corresponding pasid entry setting */ - return vtd_ce_get_rid2pasid_entry(s, ce, &pe, PCI_NO_PASID); + return vtd_ce_get_pasid_entry(s, ce, &pe, PCI_NO_PASID); } =20 /* Map a device to its corresponding domain (context-entry) */ @@ -1611,7 +1611,7 @@ static uint16_t vtd_get_domain_id(IntelIOMMUState *s, VTDPASIDEntry pe; =20 if (s->root_scalable) { - vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); + vtd_ce_get_pasid_entry(s, ce, &pe, pasid); return VTD_SM_PASID_ENTRY_DID(pe.val[1]); } =20 @@ -1687,7 +1687,7 @@ static bool vtd_dev_pt_enabled(IntelIOMMUState *s, VT= DContextEntry *ce, int ret; =20 if (s->root_scalable) { - ret =3D vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); + ret =3D vtd_ce_get_pasid_entry(s, ce, &pe, pasid); if (ret) { /* * This error is guest triggerable. We should assumt PT --=20 2.34.1 From nobody Sat Nov 15 14:49:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750404272; cv=none; d=zohomail.com; s=zohoarc; b=NlZJJ1QfjR62X7r0C8pYt4oDSy9/6s6J6VcADAPe9EykXKDIxpvR1UdvOBcAt75a0i0H25C4O7tpa1COQa8FIRTIdBC6iMS+kNBHeEpfjQi705UzTYxnJqeVMTmu8XfNxwnKPwvTglCfBBbsxqqQiGG/0VxXm4aGwuJfAChR1F0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750404272; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=kTIIYkVUYXHm5Sab4lXOgyTx8/iACGvHLlTVaMvBzAA=; b=hMjZHT/AhRWXwhFTZYfmaz56Hi2NR1LxrM8PDGbazinC/2FiY9BZLln3Wij/ZYZotci3ZWb6so6ZpwA/6ndXVbX3ldAeZSG2pjntyUX46WJiyVB+OeiPg4URAlOX93I4BXTWODpIkYic7kgHURxZWbzwx13GmDvySym4kySJRRU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750404272582308.37132958399843; Fri, 20 Jun 2025 00:24:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uSW4y-0004Z0-3M; Fri, 20 Jun 2025 03:22:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW4v-0004Yj-04 for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:22:25 -0400 Received: from mgamail.intel.com ([198.175.65.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW4p-0008FB-9q for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:22:24 -0400 Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:22:19 -0700 Received: from spr-s2600bt.bj.intel.com ([10.240.192.127]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:22:15 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750404139; x=1781940139; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JL9CLBJX8nnHDI6v27343igxliBeYes2mrdVS1QU33g=; b=UrghDAIts8AphfI8lfjV6Xwb6DWAuSoaygmhzRPIkoZcrJg1YjMgOuvT xwYAaGiyi8Cv/jWfqZAksk4l1LftcpaLmVXg3ch851CCjDcfBk3/oufa1 knXbN4KrivV9VmqMcgeEbo7tMrdMZSOmGHN31wp88HC2dMMJxJsZtreyT RU56UTOVMfeczBSviBhCaUDNKFB/1BCbTsuLlZzydzepe+mvw4uULxLRX 3pJELTTDh7BHn/uKnCg2DAtcF0wFwXVI5B8nTld/Mt6uFw8yXjuBvYdIR MPMChjPe+frW2HmyKtZ3CYDliekvIjZlhzP8QA9uT63uuqFuyIfebmXWq w==; X-CSE-ConnectionGUID: 0UUyiQB9TACbgssqkjGopA== X-CSE-MsgGUID: fWNLUBV3S++PBacU66aRIw== X-IronPort-AV: E=McAfee;i="6800,10657,11469"; a="52532265" X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="52532265" X-CSE-ConnectionGUID: gr8yW0rXQv6A63KToe1nYA== X-CSE-MsgGUID: d1nWaVJRSiqvVG6FmpO2Tg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="181863056" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Marcel Apfelbaum Subject: [PATCH v2 02/19] hw/pci: Introduce pci_device_get_viommu_cap() Date: Fri, 20 Jun 2025 15:17:56 +0800 Message-Id: <20250620071813.55571-3-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620071813.55571-1-zhenzhong.duan@intel.com> References: <20250620071813.55571-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.21; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750404273454116600 Content-Type: text/plain; charset="utf-8" pci_device_get_viommu_cap() call pci_device_get_iommu_bus_devfn() to get iommu_bus->iommu_ops and call get_viommu_cap() callback to get a bitmap with each bit represents a vIOMMU exposed capability. Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan --- include/hw/pci/pci.h | 22 ++++++++++++++++++++++ hw/pci/pci.c | 11 +++++++++++ 2 files changed, 33 insertions(+) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index df3cc7b875..829757b2c2 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -453,6 +453,18 @@ typedef struct PCIIOMMUOps { * @devfn: device and function number of the PCI device. */ void (*unset_iommu_device)(PCIBus *bus, void *opaque, int devfn); + /** + * @get_viommu_cap: get vIOMMU capabilities + * + * Optional callback, if not implemented, then vIOMMU doesn't + * support exposing capabilities to other subsystem, e.g., VFIO. + * vIOMMU can choose which capabilities to expose. + * + * @opaque: the data passed to pci_setup_iommu(). + * + * Returns: 64bit bitmap with each bit represents a capability. + */ + uint64_t (*get_viommu_cap)(void *opaque); /** * @get_iotlb_info: get properties required to initialize a device IOT= LB. * @@ -633,6 +645,16 @@ bool pci_device_set_iommu_device(PCIDevice *dev, HostI= OMMUDevice *hiod, Error **errp); void pci_device_unset_iommu_device(PCIDevice *dev); =20 +/** + * pci_device_get_viommu_cap: get vIOMMU capabilities. + * + * Returns a 64bit bitmap with each bit represents a vIOMMU exposed + * capability, 0 if vIOMMU doesn't support esposing capabilities. + * + * @dev: PCI device pointer. + */ +uint64_t pci_device_get_viommu_cap(PCIDevice *dev); + /** * pci_iommu_get_iotlb_info: get properties required to initialize a * device IOTLB. diff --git a/hw/pci/pci.c b/hw/pci/pci.c index c70b5ceeba..df1fb615a8 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2992,6 +2992,17 @@ void pci_device_unset_iommu_device(PCIDevice *dev) } } =20 +uint64_t pci_device_get_viommu_cap(PCIDevice *dev) +{ + PCIBus *iommu_bus; + + pci_device_get_iommu_bus_devfn(dev, &iommu_bus, NULL, NULL); + if (iommu_bus && iommu_bus->iommu_ops->get_viommu_cap) { + return iommu_bus->iommu_ops->get_viommu_cap(iommu_bus->iommu_opaqu= e); + } + return 0; +} + int pci_pri_request_page(PCIDevice *dev, uint32_t pasid, bool priv_req, bool exec_req, hwaddr addr, bool lpig, uint16_t prgi, bool is_read, bool is_write) --=20 2.34.1 From nobody Sat Nov 15 14:49:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750404199; cv=none; d=zohomail.com; s=zohoarc; b=GmUmnclZwFP0OHJJVDojZlPT3su2dJl2TfWTAqHG73OLV75oorLUwK48e0GfeEp0PyjDnTdcE6h1eZKMFq0xhetihoTnPw1m2VtpghtmDxnFNPWn0aAEjtPyBz+/4drcQZ5NwMEnYwUhHnLHkYSsGEw/mx4SEIQU07Bbq19JNSM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750404199; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=nrEYCg2ne7idrLA0Xpe3lb8CVzEhqdvRidiw7egyKHY=; b=NVmhwdq8/DN7f5xrx4/6DNOOv9YuKyi2a3rrBO1tpqJ5ao3uk1t78Cdg+FJlzuwYo+NRRMcur7dyP1oMFZStuTmKZdECVK6q3ZCiiTVgqbqX/6gjuwlI41qhq8ywHrgoKKFfp5VCjFQg5HC3lb/Q9ZTpitMiBGcf5gmRQlA7CzU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175040419930496.81352032216671; Fri, 20 Jun 2025 00:23:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uSW54-0004Zd-QS; Fri, 20 Jun 2025 03:22:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW4x-0004Z4-4i for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:22:27 -0400 Received: from mgamail.intel.com ([198.175.65.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW4u-0008Ff-Rp for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:22:26 -0400 Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:22:24 -0700 Received: from spr-s2600bt.bj.intel.com ([10.240.192.127]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:22:20 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750404145; x=1781940145; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NrYvyfTwhT5be/BBp7vf0xEivOZkRqhnMvUCZbKJOC0=; b=KjTbOKGJipa95Fm4rXj619kEXVv6bzF1b7a8Hk5aHfj3aSwmWoM98u6p 8jv03V9tAWSgHqBf3ABO4W1J1DESw1qg4yInESoqVQiDkFejQv90rUYLP bbdJmeU3zI512gzwPqcCs1JavCQS1PMHhit7a1PvAeXTTZxv6LvcOO9KU 95vRqR42tN+gHleAQF8shGVw1HOg6JsvpBJJP4BPnq74AKHbCCQeBe8wa FCXR+VxX2dXU8AeDG7SIR5wPTYFUEFpRsrcFE/HFlNDHBAh55CCCCzEFA o4CNHqUWFfvHF+r61iZWLfwCNUGhpO3yZbAjQg4jKDTWjVD2rc0hPBooD Q==; X-CSE-ConnectionGUID: jkAdCPFsRFuNJc94ZmJttQ== X-CSE-MsgGUID: Ap4JXicDTuKn3/v9GT4FKw== X-IronPort-AV: E=McAfee;i="6800,10657,11469"; a="52532287" X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="52532287" X-CSE-ConnectionGUID: Dlwfz0DhT0uw3B9oyA0X1w== X-CSE-MsgGUID: wpdrxUYwTOe3/0hFsgBH3g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="181863067" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Subject: [PATCH v2 03/19] intel_iommu: Implement get_viommu_cap() callback Date: Fri, 20 Jun 2025 15:17:57 +0800 Message-Id: <20250620071813.55571-4-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620071813.55571-1-zhenzhong.duan@intel.com> References: <20250620071813.55571-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.21; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750404200851116600 Content-Type: text/plain; charset="utf-8" Implement get_viommu_cap() callback and expose stage-1 capability for now. VFIO uses it to create nested parent domain which is further used to create nested domain in vIOMMU. All these will be implemented in following patches. Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan --- MAINTAINERS | 1 + include/hw/iommu.h | 14 ++++++++++++++ hw/i386/intel_iommu.c | 12 ++++++++++++ 3 files changed, 27 insertions(+) create mode 100644 include/hw/iommu.h diff --git a/MAINTAINERS b/MAINTAINERS index 94c4076127..27817974a6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2277,6 +2277,7 @@ F: include/system/iommufd.h F: backends/host_iommu_device.c F: include/system/host_iommu_device.h F: include/qemu/chardev_open.h +F: include/hw/iommu.h F: util/chardev_open.c F: docs/devel/vfio-iommufd.rst =20 diff --git a/include/hw/iommu.h b/include/hw/iommu.h new file mode 100644 index 0000000000..3c1c08f05d --- /dev/null +++ b/include/hw/iommu.h @@ -0,0 +1,14 @@ +/* + * General vIOMMU capabilities, flags, etc + * + * Copyright (C) 2025 Intel Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_IOMMU_H +#define HW_IOMMU_H + +#define VIOMMU_CAP_STAGE1 BIT_ULL(0) + +#endif /* HW_IOMMU_H */ diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index f0b1f90eff..702973da5c 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -24,6 +24,7 @@ #include "qemu/main-loop.h" #include "qapi/error.h" #include "hw/sysbus.h" +#include "hw/iommu.h" #include "intel_iommu_internal.h" #include "hw/pci/pci.h" #include "hw/pci/pci_bus.h" @@ -4412,6 +4413,16 @@ static void vtd_dev_unset_iommu_device(PCIBus *bus, = void *opaque, int devfn) vtd_iommu_unlock(s); } =20 +static uint64_t vtd_get_viommu_cap(void *opaque) +{ + IntelIOMMUState *s =3D opaque; + uint64_t caps; + + caps =3D s->flts ? VIOMMU_CAP_STAGE1 : 0; + + return caps; +} + /* Unmap the whole range in the notifier's scope. */ static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n) { @@ -4734,6 +4745,7 @@ static PCIIOMMUOps vtd_iommu_ops =3D { .get_address_space =3D vtd_host_dma_iommu, .set_iommu_device =3D vtd_dev_set_iommu_device, .unset_iommu_device =3D vtd_dev_unset_iommu_device, + .get_viommu_cap =3D vtd_get_viommu_cap, }; =20 static bool vtd_decide_config(IntelIOMMUState *s, Error **errp) --=20 2.34.1 From nobody Sat Nov 15 14:49:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750404190; cv=none; d=zohomail.com; s=zohoarc; b=H24C4mgIsPyNfslVa+OOMTkRuCuK91TOelJK4KLOKvwDRXEs5tCacaOhhmLROnps3SZtX3qs61bQ/YwqbBevSMKlUl7Kj14O6yapAz6DV/1jMiyXT73rgO63iB/eL8pQIBbHEKzBxPD2ySxFVaJrY3Y8ZxGvqND4GVH/rWauSVI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750404190; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=gsrFZshwUFS2bPs4E7oUIC+6u/IUumcqSl6szzwdM40=; b=NDPvNZG+c0Iv89O6da7PNizJBwn1nNS7qusBc5+ofWpbraonY/ubbbkivXPM6wZirIcZl5qmdgt66/uwukZerhpnTdrygW+m5GaTLO0i5xoxCfEJlnphLn9ha0kkN2j4eO905C5piaw1xi1cE4hN/EpZiITCV4+h9J49mrJDHZM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750404190804630.3334377775376; Fri, 20 Jun 2025 00:23:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uSW58-0004b9-K7; Fri, 20 Jun 2025 03:22:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW52-0004a3-Qx for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:22:34 -0400 Received: from mgamail.intel.com ([198.175.65.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW50-0008HF-Lq for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:22:32 -0400 Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:22:28 -0700 Received: from spr-s2600bt.bj.intel.com ([10.240.192.127]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:22:25 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750404151; x=1781940151; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=72XD2+orGphVnlfDHx8HuqM/mIuRt3K0/KSIIUT9oYU=; b=PTjw+eicLVUdZENrvS7akO9/lUcFgerLVDyOR4ZIpGlFPBCSTGmyzpsJ zBKnRcBk/gpEMXtvG1X9gIJhnyeJyxyvwl101F2pC10T9kzzPEPiGjM+s P0zFZY8JJh1IHnj63dxDYNfehgg62JoGl+9kGMaRGacqqKVx05EmGQfYK 1uH4mdGo/u+PKELXOwN72mv4nMzCw73WxS8byuEru+X/bu/KrRAjNEIB8 RCUk1GTJ3JfetJGJ4vL905nzRvB3SNjI2w47128E1svSL/xNS+0Xzscqr g12cVI1cuejqW+lk07ZWtw66Zr6RiiYom+yVUn8MXqGdy99i5dOD/7SeF Q==; X-CSE-ConnectionGUID: toBo3QigSn6AbDoyTJ2aRw== X-CSE-MsgGUID: GmzJsTnZQym3lDL2bdpudw== X-IronPort-AV: E=McAfee;i="6800,10657,11469"; a="52532303" X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="52532303" X-CSE-ConnectionGUID: sIe+/h4vRi+a7QhIV/4j7g== X-CSE-MsgGUID: NJCCrAtHRNqld5JTDVTD4w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="181863079" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v2 04/19] vfio/iommufd: Force creating nested parent domain Date: Fri, 20 Jun 2025 15:17:58 +0800 Message-Id: <20250620071813.55571-5-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620071813.55571-1-zhenzhong.duan@intel.com> References: <20250620071813.55571-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.21; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750404193214116600 Content-Type: text/plain; charset="utf-8" Call pci_device_get_viommu_cap() to get if vIOMMU supports VIOMMU_CAP_STAGE= 1, if yes, create nested parent domain which could be reused by vIOMMU to crea= te nested domain. Suggested-by: Nicolin Chen Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan --- hw/vfio/iommufd.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c index d3efef71af..83a632bdee 100644 --- a/hw/vfio/iommufd.c +++ b/hw/vfio/iommufd.c @@ -20,6 +20,7 @@ #include "trace.h" #include "qapi/error.h" #include "system/iommufd.h" +#include "hw/iommu.h" #include "hw/qdev-core.h" #include "hw/vfio/vfio-cpr.h" #include "system/reset.h" @@ -352,6 +353,19 @@ static bool iommufd_cdev_autodomains_get(VFIODevice *v= basedev, flags =3D IOMMU_HWPT_ALLOC_DIRTY_TRACKING; } =20 + /* + * If vIOMMU supports stage-1 translation, force to create nested pare= nt + * domain which could be reused by vIOMMU to create nested domain. + */ + if (vbasedev->type =3D=3D VFIO_DEVICE_TYPE_PCI) { + VFIOPCIDevice *vdev =3D container_of(vbasedev, VFIOPCIDevice, vbas= edev); + + hw_caps =3D pci_device_get_viommu_cap(&vdev->pdev); + if (hw_caps & VIOMMU_CAP_STAGE1) { + flags |=3D IOMMU_HWPT_ALLOC_NEST_PARENT; + } + } + if (!iommufd_backend_alloc_hwpt(iommufd, vbasedev->devid, container->ioas_id, flags, IOMMU_HWPT_DATA_NONE, 0, NULL, --=20 2.34.1 From nobody Sat Nov 15 14:49:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750404191; cv=none; d=zohomail.com; s=zohoarc; b=f4kzws1q2mL/ewE2UiIgtwD+/z2+ihlg78uzB8MNQqbcN84Cdm8J4JtGwQ323/P/q01HWgsrZsv+G0TBy44Mboc4JFDdRpKgvPq8OFm2BfJEahSofl1enwf6MMeLJpyQo+WUeIiOQ7MhigT6A0RKbhSyqddEW1frzPi6JBVDm1A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750404191; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=CLKAaILttGTwrarcB4fQkY8roeS9WYxyveKi7JUZywA=; b=lVwqFQey2Ji7q+9mbBDKUyGNEs51y+4xGY0ss3c4EPQR3JgD8q0EenyNrLSyxCpL39ff/MHeRjmKLUwxFaFHRQfZb0wawDDDGNFRz0hLLnms/CgnX19k18UoyOeAuR+BiO9jSQePnGBSbUhR77580iEiJ0nxRiR/Dp4Hm3B6U5c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750404191760598.6911130820066; Fri, 20 Jun 2025 00:23:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uSW5D-0004bh-RK; Fri, 20 Jun 2025 03:22:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW55-0004ak-5H for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:22:36 -0400 Received: from mgamail.intel.com ([198.175.65.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW53-0008HF-AY for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:22:34 -0400 Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:22:32 -0700 Received: from spr-s2600bt.bj.intel.com ([10.240.192.127]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:22:29 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750404153; x=1781940153; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gyXkorc2YEb9t/HgYoa8r3CEUGrRW5Har2jZsB4EE1E=; b=IoyPO81I7uEqIT6bdoPbQI1bEnE9jZmQwrdqeW1OlHVr7VwhmN9Ifvju iq9YZWVi9EE9w+V7npk3gV5Xyy8KTYa6OrcquTLWwxpDzm82hSRRkcmYK alJvFtWQsBnlx0IK7n4NarIROvkXm0a/S9JIFhQARBaNFeIIrWjKP9GoQ 1vHsBpuKJL8xdQ556kJsuKva6Z2fB6RyGdlOnkUZAcVHmAuhj1Kx6CZ9y QxsPcfEQmazdgsIUqcFZA+MIatVjqDJdDS/xn3e2nHUaSyo3ZNR0EXD+w vYqJxC5y0RSlv6LKCXKK8hH/NxdmSI5AKCSAhToS/WFJnIDduftXX7fwP Q==; X-CSE-ConnectionGUID: Mcu7iPlBTB2hTzQOixBN9g== X-CSE-MsgGUID: jpkQ/BG9RjaCJoDpY4GO/A== X-IronPort-AV: E=McAfee;i="6800,10657,11469"; a="52532312" X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="52532312" X-CSE-ConnectionGUID: 6lanxiBTQ4qw3lws8WSthQ== X-CSE-MsgGUID: LknnLN3rR8K/3aHTGMgmTA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="181863085" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Marcel Apfelbaum Subject: [PATCH v2 05/19] hw/pci: Export pci_device_get_iommu_bus_devfn() and return bool Date: Fri, 20 Jun 2025 15:17:59 +0800 Message-Id: <20250620071813.55571-6-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620071813.55571-1-zhenzhong.duan@intel.com> References: <20250620071813.55571-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.21; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750404193242116600 Content-Type: text/plain; charset="utf-8" Returns true if PCI device is aliased or false otherwise. This will be used in following patch to determine if a PCI device is under a PCI bridge. Signed-off-by: Zhenzhong Duan --- include/hw/pci/pci.h | 2 ++ hw/pci/pci.c | 12 ++++++++---- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 829757b2c2..3029cdf26f 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -640,6 +640,8 @@ typedef struct PCIIOMMUOps { bool is_write); } PCIIOMMUOps; =20 +bool pci_device_get_iommu_bus_devfn(PCIDevice *dev, PCIBus **piommu_bus, + PCIBus **aliased_bus, int *aliased_dev= fn); AddressSpace *pci_device_iommu_address_space(PCIDevice *dev); bool pci_device_set_iommu_device(PCIDevice *dev, HostIOMMUDevice *hiod, Error **errp); diff --git a/hw/pci/pci.c b/hw/pci/pci.c index df1fb615a8..87f7c942b3 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2857,20 +2857,21 @@ static void pci_device_class_base_init(ObjectClass = *klass, const void *data) * For call sites which don't need aliased BDF, passing NULL to * aliased_[bus|devfn] is allowed. * + * Returns true if PCI device is aliased or false otherwise. + * * @piommu_bus: return root #PCIBus backed by an IOMMU for the PCI device. * * @aliased_bus: return aliased #PCIBus of the PCI device, optional. * * @aliased_devfn: return aliased devfn of the PCI device, optional. */ -static void pci_device_get_iommu_bus_devfn(PCIDevice *dev, - PCIBus **piommu_bus, - PCIBus **aliased_bus, - int *aliased_devfn) +bool pci_device_get_iommu_bus_devfn(PCIDevice *dev, PCIBus **piommu_bus, + PCIBus **aliased_bus, int *aliased_dev= fn) { PCIBus *bus =3D pci_get_bus(dev); PCIBus *iommu_bus =3D bus; int devfn =3D dev->devfn; + bool aliased =3D false; =20 while (iommu_bus && !iommu_bus->iommu_ops && iommu_bus->parent_dev) { PCIBus *parent_bus =3D pci_get_bus(iommu_bus->parent_dev); @@ -2907,6 +2908,7 @@ static void pci_device_get_iommu_bus_devfn(PCIDevice = *dev, devfn =3D parent->devfn; bus =3D parent_bus; } + aliased =3D true; } =20 iommu_bus =3D parent_bus; @@ -2928,6 +2930,8 @@ static void pci_device_get_iommu_bus_devfn(PCIDevice = *dev, if (aliased_devfn) { *aliased_devfn =3D devfn; } + + return aliased; } =20 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev) --=20 2.34.1 From nobody Sat Nov 15 14:49:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750404224; cv=none; d=zohomail.com; s=zohoarc; b=ijqSsJU8PZ/OP9rB1qUdK569IYXIwkt2tBfYfov0GPBRp47C+bsHGbj8/RK4vWVUEus7rvL/T9+xDNRqmLHHoUqqxQqnZxyMjvc1+2EBYWEq2W/gpAVbY4h8OZgUvXVKpvRz66KW+C73Qu92nPZOB8V8K7+BI4vg92GZtYLEu5U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750404224; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=2T8RfJKccvijhtkPHtwR5rzaPFM6kgND2FSO6vCGf0g=; b=YJbsL1wjto7XwpJpTs06H7hkaITkgZXB+uKNTRjUHieAdsI7Q8t7iw2s4LlDSCac/TanKUVDqy66RgnUWho5ePC3yF74TXN/0SfasnUA5dMSSUEsnaXBsNZzmdOxjD3SrkP63VSkuPVnWew+/qDf/TELfsFDVbqMN2W5repoURU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750404224164650.8853892214977; Fri, 20 Jun 2025 00:23:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uSW5J-0004cl-JK; Fri, 20 Jun 2025 03:22:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW5B-0004bc-Bj for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:22:43 -0400 Received: from mgamail.intel.com ([198.175.65.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW59-0008IS-3d for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:22:40 -0400 Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:22:38 -0700 Received: from spr-s2600bt.bj.intel.com ([10.240.192.127]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:22:33 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750404159; x=1781940159; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RZS2p55dxo9IOvEV82x8xQCu503ewsLCel29bMAyhS4=; b=GfTWAA+GDhlVNaO5I0IIjjR01hqHbUo9uHS8B49qUTTZrjiaUM8RF/fu f3tTB+hbzYWVeuWhyWSqqaGpRZpqHCsOWI2A9dhE/Qf0bG9ffOcp6BLHx T19xfNdXjU3ApaGszkvpaMWvp6IsZrXErE7/4YjFFvJCnG1EX/KQdT70D BFcC74CJscxyq9qSJMZ71NynoSMnnMiyhCaTL890sjpfjMz8XHGqKo6pQ Y+mM+uWEqYund315pc+Fxisk5sXUcaqwvabcnRlxP+fQ9/tn/2BJl6W2W GhrUNw8GJjJdWLdRD0u6YJiQvXJ9KqebcpgKzZKI05NcM4y7RMuxJbnYD w==; X-CSE-ConnectionGUID: PQjXw4auQVWgF6L5G9M0PA== X-CSE-MsgGUID: NHhLl9w8Sk283lvOm+ojzA== X-IronPort-AV: E=McAfee;i="6800,10657,11469"; a="52532330" X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="52532330" X-CSE-ConnectionGUID: w1vRtc4MT2GpkeN0Tw5cnA== X-CSE-MsgGUID: Gu5ZxCJPRn2AAGm6ci4ngQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="181863111" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PATCH v2 06/19] intel_iommu: Introduce a new structure VTDHostIOMMUDevice Date: Fri, 20 Jun 2025 15:18:00 +0800 Message-Id: <20250620071813.55571-7-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620071813.55571-1-zhenzhong.duan@intel.com> References: <20250620071813.55571-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.21; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750404225464116600 Content-Type: text/plain; charset="utf-8" Introduce a new structure VTDHostIOMMUDevice which replaces HostIOMMUDevice to be stored in hash table. It includes a reference to HostIOMMUDevice and IntelIOMMUState, also includes BDF information which will be used in future patches. Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger --- hw/i386/intel_iommu_internal.h | 7 +++++++ include/hw/i386/intel_iommu.h | 2 +- hw/i386/intel_iommu.c | 15 +++++++++++++-- 3 files changed, 21 insertions(+), 3 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index e8b211e8b0..7aba259ef8 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -28,6 +28,7 @@ #ifndef HW_I386_INTEL_IOMMU_INTERNAL_H #define HW_I386_INTEL_IOMMU_INTERNAL_H #include "hw/i386/intel_iommu.h" +#include "system/host_iommu_device.h" =20 /* * Intel IOMMU register specification @@ -607,4 +608,10 @@ typedef struct VTDRootEntry VTDRootEntry; /* Bits to decide the offset for each level */ #define VTD_LEVEL_BITS 9 =20 +typedef struct VTDHostIOMMUDevice { + IntelIOMMUState *iommu_state; + PCIBus *bus; + uint8_t devfn; + HostIOMMUDevice *hiod; +} VTDHostIOMMUDevice; #endif diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index e95477e855..50f9b27a45 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -295,7 +295,7 @@ struct IntelIOMMUState { /* list of registered notifiers */ QLIST_HEAD(, VTDAddressSpace) vtd_as_with_notifiers; =20 - GHashTable *vtd_host_iommu_dev; /* HostIOMMUDevice */ + GHashTable *vtd_host_iommu_dev; /* VTDHostIOMMUDevice */ =20 /* interrupt remapping */ bool intr_enabled; /* Whether guest enabled IR */ diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 702973da5c..e90fd2f28f 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -281,7 +281,10 @@ static gboolean vtd_hiod_equal(gconstpointer v1, gcons= tpointer v2) =20 static void vtd_hiod_destroy(gpointer v) { - object_unref(v); + VTDHostIOMMUDevice *vtd_hiod =3D v; + + object_unref(vtd_hiod->hiod); + g_free(vtd_hiod); } =20 static gboolean vtd_hash_remove_by_domain(gpointer key, gpointer value, @@ -4360,6 +4363,7 @@ static bool vtd_dev_set_iommu_device(PCIBus *bus, voi= d *opaque, int devfn, HostIOMMUDevice *hiod, Error **errp) { IntelIOMMUState *s =3D opaque; + VTDHostIOMMUDevice *vtd_hiod; struct vtd_as_key key =3D { .bus =3D bus, .devfn =3D devfn, @@ -4376,7 +4380,14 @@ static bool vtd_dev_set_iommu_device(PCIBus *bus, vo= id *opaque, int devfn, return false; } =20 + vtd_hiod =3D g_malloc0(sizeof(VTDHostIOMMUDevice)); + vtd_hiod->bus =3D bus; + vtd_hiod->devfn =3D (uint8_t)devfn; + vtd_hiod->iommu_state =3D s; + vtd_hiod->hiod =3D hiod; + if (!vtd_check_hiod(s, hiod, errp)) { + g_free(vtd_hiod); vtd_iommu_unlock(s); return false; } @@ -4386,7 +4397,7 @@ static bool vtd_dev_set_iommu_device(PCIBus *bus, voi= d *opaque, int devfn, new_key->devfn =3D devfn; =20 object_ref(hiod); - g_hash_table_insert(s->vtd_host_iommu_dev, new_key, hiod); + g_hash_table_insert(s->vtd_host_iommu_dev, new_key, vtd_hiod); =20 vtd_iommu_unlock(s); =20 --=20 2.34.1 From nobody Sat Nov 15 14:49:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750404348; cv=none; d=zohomail.com; s=zohoarc; b=JgeZ9q+Bw+Ux8dDAFrz0/YWepu/+PtfeUaLQf2A+U+G5B3RkZiw9WC+iH5TacWM3NsbqN32jHbVQtMtNlTjr7FiXimz0SZ90Uk7zLErp38BZSL00zuwfTGgtnyIABMisjHLuMWBD7W7M7icGVQ+2+09DVKjl8V0Bnxy/k1SHocg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750404348; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=EqY6q8berBjupZf4wn4YSh6+isEcj950QYFoP43/A8c=; b=Cpds9XDKi1JCF9BkQFH3O524iD6hggU++5cMuA8xe63pZKuKhgHRVYXJY/CFtGnJbX67sKMitYWDXM5lZTnM5cnBQENkc/bIlUmIAg6iMV5N+TZp162lfNGYOLnc5paRSgjTVhmIy8niHIC+8GHIdrnUFW1Y8GAJ5sZV1Nbp4zU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17504043482621011.9289499260524; Fri, 20 Jun 2025 00:25:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uSW5K-0004d2-Lt; Fri, 20 Jun 2025 03:22:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW5F-0004cH-OO for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:22:47 -0400 Received: from mgamail.intel.com ([198.175.65.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW5D-0008IS-FN for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:22:45 -0400 Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:22:43 -0700 Received: from spr-s2600bt.bj.intel.com ([10.240.192.127]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:22:38 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750404164; x=1781940164; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2Ev68Lz7/J4aSiVBZBDspVfJE1fKcFe0BqnfXTcJRM8=; b=X4mGH3cnLcGvJTtDTUV/V+7Q9SaJfIKw2BgpjEnfweCDLCHbNmHGnqY5 YIDbtzJ0PZbcTGwfQe/H7XGX4XKrqNCSwJGbv9X3mbGtiIvU2gZYQ7dcN BLTlosvfGf9QzsT+pGb/+tJVlcPrLagUnWWDi3oPviMg2QSVHDYLsYAzW BkUSav9WFqxEEGWPbCsE/8Jorru5UDxddZa4F0qtEMWt+TiVIoBYJLg3F OylBAfgyNPyvS9+1xyErvxBocZGdyuf4oapai3kPm6dM3p7iCijqx0wZt IQo+AcEJt3o8fh26jOilHVWHGcnB6WtaucXSpBdbXU7ims8TcTtYm6yH5 w==; X-CSE-ConnectionGUID: 1ItElWT/TzW9EBdzzJNHqg== X-CSE-MsgGUID: KwALiTsAQSWndkS+1DC22A== X-IronPort-AV: E=McAfee;i="6800,10657,11469"; a="52532346" X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="52532346" X-CSE-ConnectionGUID: BcyZWfRgTiKVumOsx3WIiA== X-CSE-MsgGUID: zP0ezj+ESACqY8uZ6JICRQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="181863122" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Subject: [PATCH v2 07/19] intel_iommu: Check for compatibility with IOMMUFD backed device when x-flts=on Date: Fri, 20 Jun 2025 15:18:01 +0800 Message-Id: <20250620071813.55571-8-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620071813.55571-1-zhenzhong.duan@intel.com> References: <20250620071813.55571-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.21; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750404350408116600 Content-Type: text/plain; charset="utf-8" When vIOMMU is configured x-flts=3Don in scalable mode, stage-1 page table is passed to host to construct nested page table. We need to check compatibility of some critical IOMMU capabilities between vIOMMU and host IOMMU to ensure guest stage-1 page table could be used by host. For instance, vIOMMU supports stage-1 1GB huge page mapping, but host does not, then this IOMMUFD backed device should be failed. Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 1 + hw/i386/intel_iommu.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 7aba259ef8..18bc22fc72 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -192,6 +192,7 @@ #define VTD_ECAP_PT (1ULL << 6) #define VTD_ECAP_SC (1ULL << 7) #define VTD_ECAP_MHMV (15ULL << 20) +#define VTD_ECAP_NEST (1ULL << 26) #define VTD_ECAP_SRS (1ULL << 31) #define VTD_ECAP_PASID (1ULL << 40) #define VTD_ECAP_SMTS (1ULL << 43) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index e90fd2f28f..1c79efc1cb 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -40,6 +40,7 @@ #include "kvm/kvm_i386.h" #include "migration/vmstate.h" #include "trace.h" +#include "system/iommufd.h" =20 /* context entry operations */ #define VTD_CE_GET_RID2PASID(ce) \ @@ -4355,6 +4356,33 @@ static bool vtd_check_hiod(IntelIOMMUState *s, HostI= OMMUDevice *hiod, return true; } =20 +#ifdef CONFIG_IOMMUFD + struct HostIOMMUDeviceCaps *caps =3D &hiod->caps; + struct iommu_hw_info_vtd *vtd =3D &caps->vendor_caps.vtd; + + /* Remaining checks are all stage-1 translation specific */ + if (!object_dynamic_cast(OBJECT(hiod), TYPE_HOST_IOMMU_DEVICE_IOMMUFD)= ) { + error_setg(errp, "Need IOMMUFD backend when x-flts=3Don"); + return false; + } + + if (caps->type !=3D IOMMU_HW_INFO_TYPE_INTEL_VTD) { + error_setg(errp, "Incompatible host platform IOMMU type %d", + caps->type); + return false; + } + + if (!(vtd->ecap_reg & VTD_ECAP_NEST)) { + error_setg(errp, "Host IOMMU doesn't support nested translation"); + return false; + } + + if (s->fs1gp && !(vtd->cap_reg & VTD_CAP_FS1GP)) { + error_setg(errp, "Stage-1 1GB huge page is unsupported by host IOM= MU"); + return false; + } +#endif + error_setg(errp, "host device is uncompatible with stage-1 translation= "); return false; } --=20 2.34.1 From nobody Sat Nov 15 14:49:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750404197; cv=none; d=zohomail.com; s=zohoarc; b=FdHd/hSEsgp/0JJq/DmhpvYvvig6HJtKi972MXm5/IydDVlM2BW+oZz3XSdp2rbeVA77lzsX2XvJTPByELHIqhZmin4QdO9JekMaXj7b4dzPbFx9Zp0IXtcaN7jvDsRXp4cAcc3vmTsupro8C8e48KkpVvp1pWyXlIcv8qwCNxQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750404197; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=sl7pxFrmV8fpsaqElOVIy7ICe8FJIx0x2cFyxrnZtOk=; b=ODM3jcqUt0wJBgg2Dp6VTWzAlbT5ymmuSKzk19fN6ovUyo2akgkgihKd/IBzSainljJoPkNXs766CLV3OX6HfqwyGH5yAWYWtG2ff5QUwIwr05iDirSMiT5U7YuqaKfn6/tNDWDf8J1HnuCJ68OKXero0qYW2GlVFd7LdJ2Z5ho= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750404197433105.94783310495654; Fri, 20 Jun 2025 00:23:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uSW5N-0004dx-1x; Fri, 20 Jun 2025 03:22:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW5L-0004dM-9Q for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:22:51 -0400 Received: from mgamail.intel.com ([198.175.65.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW5I-0008IS-9b for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:22:51 -0400 Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:22:48 -0700 Received: from spr-s2600bt.bj.intel.com ([10.240.192.127]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:22:43 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750404168; x=1781940168; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=eXIY1EEbF1RfbgIJIQePt6T9VT6r816CRDXV+6DEzYs=; b=ZF7syC4SfZ2ibu4iRVlVBsATnMiMWPCTgWHOkoiZKStfTycCIvlq4bls aHevGhPqsqy/Yi3mdG41xcQzArMqHH8L7OURKKQpVj/XMLm3yZ+ednz8+ lVR9HGZa7VZfolqnAGWOTs5uCZk7g0VcdJEpDX8j4zi7fToM9QKdy6tHd nqpYsffEaMPN7j5v2v3+Ozi8IHiweoIQxSIJnfweOqIggWsqqUAqVXDWs 7kbfVreZIu9IB2atYcwKPlakZ2o2oKXzwUzc+EU9KTo1bCrGobvEJ9kQe vmHMmJMPXv7BTAcdD6P6WO9ah4JJQPsO7z4Ad4mwayTPAwfXAvwJJzLM5 Q==; X-CSE-ConnectionGUID: t9Jz5NaTQO2UN/BtNp4Rlg== X-CSE-MsgGUID: LSYsXCPcR96zqI+gJJCpQw== X-IronPort-AV: E=McAfee;i="6800,10657,11469"; a="52532366" X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="52532366" X-CSE-ConnectionGUID: BIL3ePNtS0aqS3G74NoEhQ== X-CSE-MsgGUID: CEXQSQkZSzG+Z1nnzxt69g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="181863140" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PATCH v2 08/19] intel_iommu: Fail passthrough device under PCI bridge if x-flts=on Date: Fri, 20 Jun 2025 15:18:02 +0800 Message-Id: <20250620071813.55571-9-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620071813.55571-1-zhenzhong.duan@intel.com> References: <20250620071813.55571-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.21; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750404199001116600 Content-Type: text/plain; charset="utf-8" Currently we don't support nested translation for passthrough device with emulated device under same PCI bridge. Reason is for emulated devices, AS should switch to iommu MR, while for passthrough devices, it needs the AS stick with the system MR hence be able to keep the VFIO container IOAS as a GPA IOAS. To support this, let AS switch to iommu MR and have a separate GPA IOAS is needed, but that brings a new memory listener which duplicates with VFIO memory listener. For trade off, we choose to not support this special scenario because PCIE bridge is more popular than PCI bridge now. Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 1c79efc1cb..9d4adc9458 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -4330,9 +4330,10 @@ VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s,= PCIBus *bus, return vtd_dev_as; } =20 -static bool vtd_check_hiod(IntelIOMMUState *s, HostIOMMUDevice *hiod, +static bool vtd_check_hiod(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hio= d, Error **errp) { + HostIOMMUDevice *hiod =3D vtd_hiod->hiod; HostIOMMUDeviceClass *hiodc =3D HOST_IOMMU_DEVICE_GET_CLASS(hiod); int ret; =20 @@ -4359,6 +4360,8 @@ static bool vtd_check_hiod(IntelIOMMUState *s, HostIO= MMUDevice *hiod, #ifdef CONFIG_IOMMUFD struct HostIOMMUDeviceCaps *caps =3D &hiod->caps; struct iommu_hw_info_vtd *vtd =3D &caps->vendor_caps.vtd; + PCIBus *bus =3D vtd_hiod->bus; + PCIDevice *pdev =3D pci_find_device(bus, pci_bus_num(bus), vtd_hiod->d= evfn); =20 /* Remaining checks are all stage-1 translation specific */ if (!object_dynamic_cast(OBJECT(hiod), TYPE_HOST_IOMMU_DEVICE_IOMMUFD)= ) { @@ -4381,6 +4384,12 @@ static bool vtd_check_hiod(IntelIOMMUState *s, HostI= OMMUDevice *hiod, error_setg(errp, "Stage-1 1GB huge page is unsupported by host IOM= MU"); return false; } + + if (pci_device_get_iommu_bus_devfn(pdev, &bus, NULL, NULL)) { + error_setg(errp, "Host device under PCI bridge is unsupported " + "when x-flts=3Don"); + return false; + } #endif =20 error_setg(errp, "host device is uncompatible with stage-1 translation= "); @@ -4414,7 +4423,7 @@ static bool vtd_dev_set_iommu_device(PCIBus *bus, voi= d *opaque, int devfn, vtd_hiod->iommu_state =3D s; vtd_hiod->hiod =3D hiod; =20 - if (!vtd_check_hiod(s, hiod, errp)) { + if (!vtd_check_hiod(s, vtd_hiod, errp)) { g_free(vtd_hiod); vtd_iommu_unlock(s); return false; --=20 2.34.1 From nobody Sat Nov 15 14:49:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750404344; cv=none; d=zohomail.com; s=zohoarc; b=GpQQqZnaN0b3vd4iZpFJkWpgec8vc8K8b7chgT5dEbqimsBmMxiQPKU+7/BlkPXHtAMOz5/e5rvWUNxEfYfPOk/hn168jPTCiKL4xOlb18eluLR7H5pcY8Mz1aQ9bLE155sNiMwprk1mwDwVnYrJ7kWqI1CZTJ470FQkqjRsLxM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750404344; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=qQewvmgNvSV7lv10sl0mByeNBaPEiD0SN1zF8yrWuls=; b=WUqljMbd7xcAEAfUs801HO9QkjqU3Us0DYibs1z9fPp8oM7YEAm6z4eN2Nnpv8Dfmy92H4SXiKvPbyXJZI2X1ABkVlFQmAp5wczaDSZe0nn4qMkf4mGcqwW+halDXUzTLsdvpFMAqqpL8ycN1gms2NVZBZjg5dHxsJratCXesuM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750404344725607.1041663301097; Fri, 20 Jun 2025 00:25:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uSW5R-0004eW-6R; Fri, 20 Jun 2025 03:22:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW5Q-0004e0-3W for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:22:56 -0400 Received: from mgamail.intel.com ([198.175.65.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW5N-0008IS-AH for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:22:54 -0400 Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:22:53 -0700 Received: from spr-s2600bt.bj.intel.com ([10.240.192.127]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:22:49 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750404173; x=1781940173; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RB91QrmOkLHCzDB+MgutIgWrn+rC2ExcQB12PfsYJik=; b=D7NXbJEHrdonUFIuhWWk/VFZz/4ZzDKbWUNQjDi1HvAyAr1buazD3w0w BaGIg6YBrb91tPj7IZyI2CGCiqL8td1SIVn5zIzTL0cXZUgFRwKYxWkLQ 9cH5Euf+gRsBxT+7viPig575bdXtXOg7jYE77yPUh6ZzMU+4j3h4qBks9 NTqgjxhGn9Qg5zDxH6096UnHr9oZKo8BrXOGNwP7foXidHztyBQw0BXbs n3CTSrWDOYJWd5sJcXQDpNYY6vFzkmnUn/tfrYAmrzoFUF3b+KnSNq6GI n6sI/eZqnWf/vxiNgBH8U1yb5d3faJvFH+ijocod3XLh7NlkoADY1yl5q w==; X-CSE-ConnectionGUID: Wu1mixtmR5uChyRXfZdHIw== X-CSE-MsgGUID: gw9yZSYJQIi18ldISxxR8Q== X-IronPort-AV: E=McAfee;i="6800,10657,11469"; a="52532380" X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="52532380" X-CSE-ConnectionGUID: +tOrIRHPTd+IlV2wikXDYQ== X-CSE-MsgGUID: Wj3NAwm/Q16T7fkLjriI5w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="181863146" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Subject: [PATCH v2 09/19] intel_iommu: Introduce two helpers vtd_as_from/to_iommu_pasid_locked Date: Fri, 20 Jun 2025 15:18:03 +0800 Message-Id: <20250620071813.55571-10-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620071813.55571-1-zhenzhong.duan@intel.com> References: <20250620071813.55571-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.21; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750404346318116600 Content-Type: text/plain; charset="utf-8" PCI device supports two request types, Requests-without-PASID and Requests-with-PASID. Requests-without-PASID doesn't include a PASID TLP prefix, IOMMU fetches rid_pasid from context entry and use it as IOMMU's pasid to index pasid table. So we need to translate between PCI's pasid and IOMMU's pasid specially for Requests-without-PASID, e.g., PCI_NO_PASID(-1) <-> rid_pasid. For Requests-with-PASID, PCI's pasid and IOMMU's pasid are same value. vtd_as_from_iommu_pasid_locked() translates from BDF+iommu_pasid to vtd_as which contains PCI's pasid vtd_as->pasid. vtd_as_to_iommu_pasid_locked() translates from BDF+vtd_as->pasid to iommu_p= asid. Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 58 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 9d4adc9458..8948b8370f 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -1602,6 +1602,64 @@ static int vtd_dev_to_context_entry(IntelIOMMUState = *s, uint8_t bus_num, return 0; } =20 +static inline int vtd_as_to_iommu_pasid_locked(VTDAddressSpace *vtd_as, + uint32_t *pasid) +{ + VTDContextCacheEntry *cc_entry =3D &vtd_as->context_cache_entry; + IntelIOMMUState *s =3D vtd_as->iommu_state; + uint8_t bus_num =3D pci_bus_num(vtd_as->bus); + uint8_t devfn =3D vtd_as->devfn; + VTDContextEntry ce; + int ret; + + if (cc_entry->context_cache_gen =3D=3D s->context_cache_gen) { + ce =3D cc_entry->context_entry; + } else { + ret =3D vtd_dev_to_context_entry(s, bus_num, devfn, &ce); + if (ret) { + return ret; + } + } + + /* Translate to iommu pasid if PCI_NO_PASID */ + if (vtd_as->pasid =3D=3D PCI_NO_PASID) { + *pasid =3D VTD_CE_GET_RID2PASID(&ce); + } else { + *pasid =3D vtd_as->pasid; + } + + return 0; +} + +static gboolean vtd_find_as_by_sid_and_iommu_pasid(gpointer key, gpointer = value, + gpointer user_data) +{ + VTDAddressSpace *vtd_as =3D (VTDAddressSpace *)value; + struct vtd_as_raw_key *target =3D (struct vtd_as_raw_key *)user_data; + uint16_t sid =3D PCI_BUILD_BDF(pci_bus_num(vtd_as->bus), vtd_as->devfn= ); + uint32_t pasid; + + if (vtd_as_to_iommu_pasid_locked(vtd_as, &pasid)) { + return false; + } + + return (pasid =3D=3D target->pasid) && (sid =3D=3D target->sid); +} + +/* Translate iommu pasid to vtd_as */ +static inline +VTDAddressSpace *vtd_as_from_iommu_pasid_locked(IntelIOMMUState *s, + uint16_t sid, uint32_t pas= id) +{ + struct vtd_as_raw_key key =3D { + .sid =3D sid, + .pasid =3D pasid + }; + + return g_hash_table_find(s->vtd_address_spaces, + vtd_find_as_by_sid_and_iommu_pasid, &key); +} + static int vtd_sync_shadow_page_hook(const IOMMUTLBEvent *event, void *private) { --=20 2.34.1 From nobody Sat Nov 15 14:49:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750404294; cv=none; d=zohomail.com; s=zohoarc; b=BjjP2EnIEmQ3aRGd9xdoqUFn1+5F/9/ALgkLL9tkzJmlCTiwJlD8IR7eZw7tGaTP6UAxdnRF+CskmBKz5CPRMJM+qT+Mouv6CWxxUtA+fORvSMdQBmt1w1NLeJYwe2Ih/kSbtEMVRtB3ERtM7ciS7TvBpUykrC47F/ofEs1eJ14= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750404294; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=pMeTkgWJ3ZtI1AG6Mn5NVghXM5KoYO7mDAVd1RR3ZiA=; b=oMFKzg7UdbhCUtAcEsSoOc8/6Nlgd/MEq96ysPoBQ7MgsWuueF0/eRBF7h3XuAiV3/yDRuv9AvlVJio7/aExBdlxlJyk9C350DEVkqx2f/0vjq4UHwOixHBSxMZ3r51TyY0Cait29xUdCEffXGOoYIuzR/tCK3KrhnCDMcPiBXI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750404294493708.3593326804444; Fri, 20 Jun 2025 00:24:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uSW5W-0004fP-Rw; Fri, 20 Jun 2025 03:23:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW5V-0004fB-NH for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:23:01 -0400 Received: from mgamail.intel.com ([198.175.65.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW5S-0008IS-W0 for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:23:01 -0400 Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:22:58 -0700 Received: from spr-s2600bt.bj.intel.com ([10.240.192.127]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:22:54 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750404179; x=1781940179; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fM8vpJl9hZIM27w/9IgNjuh0cmwQShO0EoXVYcKlQfg=; b=GhCouaJhgSnQwTbubpUKrL3csWY+uk2ml6jzRu6w2ng84Et+7wnXtGHI VONhjWgEyRj1IQGaNKTuKIFt6j/HyMInXcWt8DR6sP93M8kF89QHdRLYf UwzfJ9wnC+MyJxF4PWLI/pplBQBYLcHfeqvlc1xA+VEJoAcyLgg6AoGGK 5zkwmieW6t7VNROtJL9WdVvFHdtrlnVa7k1HLGFKCtIWtz/nd/TEpKjQm UpNsf2yeWg64GOvqKB5tILXVGJtkcY1R9NFtOdwuYjT9ARc+UxtHRYyeU QduZHHmpWengMeRk31nUVInc86+2MtRJw3pjZHTSlEuUtNG5LHfSL1J77 g==; X-CSE-ConnectionGUID: VySAIbX8Ri20xi+IFqCfcw== X-CSE-MsgGUID: PqjN+6bPRIywSaVes4oDNw== X-IronPort-AV: E=McAfee;i="6800,10657,11469"; a="52532406" X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="52532406" X-CSE-ConnectionGUID: ibd0fMxvSpuh1pddYRgTRQ== X-CSE-MsgGUID: FPOBzrp8SgiQIrQZRoXNUQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="181863164" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Yi Sun , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Subject: [PATCH v2 10/19] intel_iommu: Handle PASID entry removing and updating Date: Fri, 20 Jun 2025 15:18:04 +0800 Message-Id: <20250620071813.55571-11-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620071813.55571-1-zhenzhong.duan@intel.com> References: <20250620071813.55571-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.21; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750404296050116600 Content-Type: text/plain; charset="utf-8" This adds an new entry VTDPASIDCacheEntry in VTDAddressSpace to cache the pasid entry and track PASID usage and future PASID tagged DMA address translation support in vIOMMU. VTDAddressSpace of PCI_NO_PASID is allocated when device is plugged and never freed. For other pasid, VTDAddressSpace instance is created/destroyed per the guest pasid entry set up/destroy for passthrough devices. While for emulated devices, VTDAddressSpace instance is created in the PASID tagged D= MA translation and be destroyed per guest PASID cache invalidation. This focus= es on the PASID cache management for passthrough devices as there is no PASID capable emulated devices yet. When guest modifies a PASID entry, QEMU will capture the guest pasid select= ive pasid cache invalidation, allocate or remove a VTDAddressSpace instance per= the invalidation reasons: a) a present pasid entry moved to non-present b) a present pasid entry to be a present entry c) a non-present pasid entry moved to present This handles a) and b), following patch will handle c). vIOMMU emulator could figure out the reason by fetching latest guest pasid = entry and compare it with the PASID cache. Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 27 ++++ include/hw/i386/intel_iommu.h | 6 + hw/i386/intel_iommu.c | 265 +++++++++++++++++++++++++++++++-- hw/i386/trace-events | 3 + 4 files changed, 291 insertions(+), 10 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 18bc22fc72..01c881ed4d 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -315,6 +315,7 @@ typedef enum VTDFaultReason { * request while disabled */ VTD_FR_IR_SID_ERR =3D 0x26, /* Invalid Source-ID */ =20 + VTD_FR_RTADDR_INV_TTM =3D 0x31, /* Invalid TTM in RTADDR */ /* PASID directory entry access failure */ VTD_FR_PASID_DIR_ACCESS_ERR =3D 0x50, /* The Present(P) field of pasid directory entry is 0 */ @@ -492,6 +493,15 @@ typedef union VTDInvDesc VTDInvDesc; #define VTD_INV_DESC_PIOTLB_RSVD_VAL0 0xfff000000000f1c0ULL #define VTD_INV_DESC_PIOTLB_RSVD_VAL1 0xf80ULL =20 +#define VTD_INV_DESC_PASIDC_G (3ULL << 4) +#define VTD_INV_DESC_PASIDC_PASID(val) (((val) >> 32) & 0xfffffULL) +#define VTD_INV_DESC_PASIDC_DID(val) (((val) >> 16) & VTD_DOMAIN_ID_MASK) +#define VTD_INV_DESC_PASIDC_RSVD_VAL0 0xfff000000000f1c0ULL + +#define VTD_INV_DESC_PASIDC_DSI (0ULL << 4) +#define VTD_INV_DESC_PASIDC_PASID_SI (1ULL << 4) +#define VTD_INV_DESC_PASIDC_GLOBAL (3ULL << 4) + /* Information about page-selective IOTLB invalidate */ struct VTDIOTLBPageInvInfo { uint16_t domain_id; @@ -552,6 +562,22 @@ typedef struct VTDRootEntry VTDRootEntry; #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL0(aw) (0x1e0ULL | ~VTD_HAW_MASK(aw)) #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 0xffffffffffe00000ULL =20 +typedef enum VTDPCInvType { + /* pasid cache invalidation rely on guest PASID entry */ + VTD_PASID_CACHE_GLOBAL_INV, /* pasid cache global invalidation */ + VTD_PASID_CACHE_DOMSI, /* pasid cache domain selective invalidati= on */ + VTD_PASID_CACHE_PASIDSI, /* pasid cache pasid selective invalidatio= n */ +} VTDPCInvType; + +typedef struct VTDPASIDCacheInfo { + VTDPCInvType type; + uint16_t domain_id; + uint32_t pasid; + PCIBus *bus; + uint16_t devfn; + bool error_happened; +} VTDPASIDCacheInfo; + /* PASID Table Related Definitions */ #define VTD_PASID_DIR_BASE_ADDR_MASK (~0xfffULL) #define VTD_PASID_TABLE_BASE_ADDR_MASK (~0xfffULL) @@ -563,6 +589,7 @@ typedef struct VTDRootEntry VTDRootEntry; #define VTD_PASID_TABLE_BITS_MASK (0x3fULL) #define VTD_PASID_TABLE_INDEX(pasid) ((pasid) & VTD_PASID_TABLE_BITS_MASK) #define VTD_PASID_ENTRY_FPD (1ULL << 1) /* Fault Processing Disa= ble */ +#define VTD_PASID_TBL_ENTRY_NUM (1ULL << 6) =20 /* PASID Granular Translation Type Mask */ #define VTD_PASID_ENTRY_P 1ULL diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 50f9b27a45..fbc9da903a 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -95,6 +95,11 @@ struct VTDPASIDEntry { uint64_t val[8]; }; =20 +typedef struct VTDPASIDCacheEntry { + struct VTDPASIDEntry pasid_entry; + bool cache_filled; +} VTDPASIDCacheEntry; + struct VTDAddressSpace { PCIBus *bus; uint8_t devfn; @@ -107,6 +112,7 @@ struct VTDAddressSpace { MemoryRegion iommu_ir_fault; /* Interrupt region for catching fault */ IntelIOMMUState *iommu_state; VTDContextCacheEntry context_cache_entry; + VTDPASIDCacheEntry pasid_cache_entry; QLIST_ENTRY(VTDAddressSpace) next; /* Superset of notifier flags that this address space has */ IOMMUNotifierFlag notifier_flags; diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 8948b8370f..1db581d14a 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -826,11 +826,24 @@ static inline bool vtd_pe_type_check(IntelIOMMUState = *s, VTDPASIDEntry *pe) } } =20 +static inline uint16_t vtd_pe_get_did(VTDPASIDEntry *pe) +{ + return VTD_SM_PASID_ENTRY_DID((pe)->val[1]); +} + static inline bool vtd_pdire_present(VTDPASIDDirEntry *pdire) { return pdire->val & 1; } =20 +static inline void pasid_cache_info_set_error(VTDPASIDCacheInfo *pc_info) +{ + if (pc_info->error_happened) { + return; + } + pc_info->error_happened =3D true; +} + /** * Caller of this function should check present bit if wants * to use pdir entry for further usage except for fpd bit check. @@ -3103,6 +3116,241 @@ static bool vtd_process_piotlb_desc(IntelIOMMUState= *s, return true; } =20 +static inline int vtd_dev_get_pe_from_pasid(VTDAddressSpace *vtd_as, + uint32_t pasid, VTDPASIDEntry = *pe) +{ + IntelIOMMUState *s =3D vtd_as->iommu_state; + VTDContextEntry ce; + int ret; + + if (!s->root_scalable) { + return -VTD_FR_RTADDR_INV_TTM; + } + + ret =3D vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus), vtd_as->= devfn, + &ce); + if (ret) { + return ret; + } + + return vtd_ce_get_pasid_entry(s, &ce, pe, pasid); +} + +static bool vtd_pasid_entry_compare(VTDPASIDEntry *p1, VTDPASIDEntry *p2) +{ + return !memcmp(p1, p2, sizeof(*p1)); +} + +/* + * This function fills in the pasid entry in &vtd_as. Caller + * of this function should hold iommu_lock. + */ +static int vtd_fill_pe_in_cache(IntelIOMMUState *s, VTDAddressSpace *vtd_a= s, + VTDPASIDEntry *pe) +{ + VTDPASIDCacheEntry *pc_entry =3D &vtd_as->pasid_cache_entry; + + if (vtd_pasid_entry_compare(pe, &pc_entry->pasid_entry)) { + /* No need to go further as cached pasid entry is latest */ + return 0; + } + + pc_entry->pasid_entry =3D *pe; + pc_entry->cache_filled =3D true; + + /* + * TODO: send pasid bind to host for passthru devices + */ + + return 0; +} + +/* + * This function is used to update or clear cached pasid entry in vtd_as + * instances. Caller of this function should hold iommu_lock. + */ +static gboolean vtd_flush_pasid(gpointer key, gpointer value, + gpointer user_data) +{ + VTDPASIDCacheInfo *pc_info =3D user_data; + VTDAddressSpace *vtd_as =3D value; + IntelIOMMUState *s =3D vtd_as->iommu_state; + VTDPASIDCacheEntry *pc_entry =3D &vtd_as->pasid_cache_entry; + VTDPASIDEntry pe; + uint16_t did; + uint32_t pasid; + int ret; + + if (!pc_entry->cache_filled) { + return false; + } + did =3D vtd_pe_get_did(&pc_entry->pasid_entry); + + if (vtd_as_to_iommu_pasid_locked(vtd_as, &pasid)) { + goto remove; + } + + switch (pc_info->type) { + case VTD_PASID_CACHE_PASIDSI: + if (pc_info->pasid !=3D pasid) { + return false; + } + /* Fall through */ + case VTD_PASID_CACHE_DOMSI: + if (pc_info->domain_id !=3D did) { + return false; + } + /* Fall through */ + case VTD_PASID_CACHE_GLOBAL_INV: + break; + default: + error_report("invalid pc_info->type"); + abort(); + } + + /* + * pasid cache invalidation may indicate a present pasid + * entry to present pasid entry modification. To cover such + * case, vIOMMU emulator needs to fetch latest guest pasid + * entry and check cached pasid entry, then update pasid + * cache and send pasid bind/unbind to host properly. + */ + ret =3D vtd_dev_get_pe_from_pasid(vtd_as, pasid, &pe); + if (ret) { + /* + * No valid pasid entry in guest memory. e.g. pasid entry + * was modified to be either all-zero or non-present. Either + * case means existing pasid cache should be removed. + */ + goto remove; + } + + if (vtd_fill_pe_in_cache(s, vtd_as, &pe)) { + pasid_cache_info_set_error(pc_info); + } + return false; + +remove: + /* + * TODO: send pasid unbind to host for passthru devices + */ + pc_entry->cache_filled =3D false; + + /* + * Don't remove address space of PCI_NO_PASID which is created by PCI + * sub-system. + */ + if (vtd_as->pasid =3D=3D PCI_NO_PASID) { + return false; + } + return true; +} + +/* + * This function syncs the pasid bindings between guest and host. + * It includes updating the pasid cache in vIOMMU and updating the + * pasid bindings per guest's latest pasid entry presence. + */ +static void vtd_pasid_cache_sync(IntelIOMMUState *s, + VTDPASIDCacheInfo *pc_info) +{ + if (!s->flts || !s->root_scalable || !s->dmar_enabled) { + return; + } + + /* + * Regards to a pasid cache invalidation, e.g. a PSI. + * it could be either cases of below: + * a) a present pasid entry moved to non-present + * b) a present pasid entry to be a present entry + * c) a non-present pasid entry moved to present + * + * Different invalidation granularity may affect different device + * scope and pasid scope. But for each invalidation granularity, + * it needs to do two steps to sync host and guest pasid binding. + * + * Here is the handling of a PSI: + * 1) loop all the existing vtd_as instances to update them + * according to the latest guest pasid entry in pasid table. + * this will make sure affected existing vtd_as instances + * cached the latest pasid entries. Also, during the loop, the + * host should be notified if needed. e.g. pasid unbind or pasid + * update. Should be able to cover case a) and case b). + * + * 2) loop all devices to cover case c) + * - For devices which are backed by HostIOMMUDeviceIOMMUFD instanc= es, + * we loop them and check if guest pasid entry exists. If yes, + * it is case c), we update the pasid cache and also notify + * host. + * - For devices which are not backed by HostIOMMUDeviceIOMMUFD, + * it is not necessary to create pasid cache at this phase since + * it could be created when vIOMMU does DMA address translation. + * This is not yet implemented since there is no emulated + * pasid-capable devices today. If we have such devices in + * future, the pasid cache shall be created there. + * Other granularity follow the same steps, just with different scope + * + */ + + vtd_iommu_lock(s); + /* + * Step 1: loop all the existing vtd_as instances for pasid unbind and + * update. + */ + g_hash_table_foreach_remove(s->vtd_address_spaces, vtd_flush_pasid, + pc_info); + vtd_iommu_unlock(s); + + /* TODO: Step 2: loop all the existing vtd_hiod instances for pasid bi= nd. */ +} + +static bool vtd_process_pasid_desc(IntelIOMMUState *s, + VTDInvDesc *inv_desc) +{ + uint16_t domain_id; + uint32_t pasid; + VTDPASIDCacheInfo pc_info =3D {}; + uint64_t mask[4] =3D {VTD_INV_DESC_PASIDC_RSVD_VAL0, VTD_INV_DESC_ALL_= ONE, + VTD_INV_DESC_ALL_ONE, VTD_INV_DESC_ALL_ONE}; + + if (!vtd_inv_desc_reserved_check(s, inv_desc, mask, true, + __func__, "pasid cache inv")) { + return false; + } + + domain_id =3D VTD_INV_DESC_PASIDC_DID(inv_desc->val[0]); + pasid =3D VTD_INV_DESC_PASIDC_PASID(inv_desc->val[0]); + + switch (inv_desc->val[0] & VTD_INV_DESC_PASIDC_G) { + case VTD_INV_DESC_PASIDC_DSI: + trace_vtd_pasid_cache_dsi(domain_id); + pc_info.type =3D VTD_PASID_CACHE_DOMSI; + pc_info.domain_id =3D domain_id; + break; + + case VTD_INV_DESC_PASIDC_PASID_SI: + /* PASID selective implies a DID selective */ + trace_vtd_pasid_cache_psi(domain_id, pasid); + pc_info.type =3D VTD_PASID_CACHE_PASIDSI; + pc_info.domain_id =3D domain_id; + pc_info.pasid =3D pasid; + break; + + case VTD_INV_DESC_PASIDC_GLOBAL: + trace_vtd_pasid_cache_gsi(); + pc_info.type =3D VTD_PASID_CACHE_GLOBAL_INV; + break; + + default: + error_report_once("invalid-inv-granu-in-pc_inv_desc hi: 0x%" PRIx64 + " lo: 0x%" PRIx64, inv_desc->val[1], inv_desc->val[0]); + return false; + } + + vtd_pasid_cache_sync(s, &pc_info); + return !pc_info.error_happened ? true : false; +} + static bool vtd_process_inv_iec_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc) { @@ -3264,6 +3512,13 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s) } break; =20 + case VTD_INV_DESC_PC: + trace_vtd_inv_desc("pasid-cache", inv_desc.val[1], inv_desc.val[0]= ); + if (!vtd_process_pasid_desc(s, &inv_desc)) { + return false; + } + break; + case VTD_INV_DESC_PIOTLB: trace_vtd_inv_desc("p-iotlb", inv_desc.val[1], inv_desc.val[0]); if (!vtd_process_piotlb_desc(s, &inv_desc)) { @@ -3299,16 +3554,6 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s) } break; =20 - /* - * TODO: the entity of below two cases will be implemented in future s= eries. - * To make guest (which integrates scalable mode support patch set in - * iommu driver) work, just return true is enough so far. - */ - case VTD_INV_DESC_PC: - if (s->scalable_mode) { - break; - } - /* fallthrough */ default: error_report_once("%s: invalid inv desc: hi=3D%"PRIx64", lo=3D%"PR= Ix64 " (unknown type)", __func__, inv_desc.hi, diff --git a/hw/i386/trace-events b/hw/i386/trace-events index ac9e1a10aa..ae5bbfcdc0 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -24,6 +24,9 @@ vtd_inv_qi_head(uint16_t head) "read head %d" vtd_inv_qi_tail(uint16_t head) "write tail %d" vtd_inv_qi_fetch(void) "" vtd_context_cache_reset(void) "" +vtd_pasid_cache_gsi(void) "" +vtd_pasid_cache_dsi(uint16_t domain) "Domain selective PC invalidation dom= ain 0x%"PRIx16 +vtd_pasid_cache_psi(uint16_t domain, uint32_t pasid) "PASID selective PC i= nvalidation domain 0x%"PRIx16" pasid 0x%"PRIx32 vtd_re_not_present(uint8_t bus) "Root entry bus %"PRIu8" not present" vtd_ce_not_present(uint8_t bus, uint8_t devfn) "Context entry bus %"PRIu8"= devfn %"PRIu8" not present" vtd_iotlb_page_hit(uint16_t sid, uint64_t addr, uint64_t slpte, uint16_t d= omain) "IOTLB page hit sid 0x%"PRIx16" iova 0x%"PRIx64" slpte 0x%"PRIx64" d= omain 0x%"PRIx16 --=20 2.34.1 From nobody Sat Nov 15 14:49:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750404261; cv=none; d=zohomail.com; s=zohoarc; b=ilhVBlgc0mrm46irE9wWlE2KkapS1h5W3D323cQJSL9SR9/J30CzDBYZ3xw+F4SrS/gCwzlo8AeIDkZf8Va5Jd5bh2lkEax+Xmy8mIm+fGNyQpqisIa2vqUzReboBLZK1qHPZuT1thJlQwRoR329t7FzF5KKuYzEgJqLRGN5jWQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750404261; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=klimH42lhp3H4BN7AH3mRSPyheF7bSoZAGlPLkYDQzw=; b=Vz1gREm9nwxDmO4g1E9pAhnuH2eS09mfvf8MItuycJ6jfA5K+O1HYCWBrUg8oOobt9sRigIl15tUUY+VrlYg9BtaiCehYpCjEoeazEYOXMiDJG5WzB/fCaOMwyfLnxFf/DwoHXhguyX/9SVP5ersvD4ZHW5piuP0U4+ll0TLyJo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750404261159597.3224903167759; Fri, 20 Jun 2025 00:24:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uSW5e-0004me-9I; Fri, 20 Jun 2025 03:23:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW5b-0004gU-SD for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:23:07 -0400 Received: from mgamail.intel.com ([198.175.65.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW5Y-0008IS-3p for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:23:07 -0400 Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:23:03 -0700 Received: from spr-s2600bt.bj.intel.com ([10.240.192.127]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:22:59 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750404184; x=1781940184; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=B4cEMgSjmU068gRuPx5HIPdkt0+5w/rB4JeXu6eo3pQ=; b=eE3hBV17chtyl6G3wmH81p/0yvb5ZtFasEe6yEhsv/EgXqcPz9iKrE/9 /dW1H5itt8O0Ox7BrXlC36O1kHPltGmRfR8yu+ZJKi1S5iIXFdAruwG/v zj2SnnpXgkOUay3KqrMc2MqzQr5aFdzwtyfdhp6JJ4MM85fHML8Tzeeqt aEqhwrGqYLC3oKbaUfS/S6BTr9DDBNX4l9Dcp5G9Q84cFa4QEWSTRkbNd e20gVnQhhAuizlrg5t41DJKMq2Cyh3gLr2lhSIx3R2+DS37rgr8036Pmq Er4wEbSZTDBAUIBKIWc9M8vrOrzDVW6C2Hn6uQr86e8DOrx6xln6fj1b5 Q==; X-CSE-ConnectionGUID: 4XmFrKphT/ujm615ODxnZA== X-CSE-MsgGUID: ikCIQ77WT42dnHxH3oyuNA== X-IronPort-AV: E=McAfee;i="6800,10657,11469"; a="52532420" X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="52532420" X-CSE-ConnectionGUID: fXo9SXzCTBCDHM3OoVTfpQ== X-CSE-MsgGUID: lgOrHunRS9Kscjcm8A/OrA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="181863222" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Yi Sun , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Subject: [PATCH v2 11/19] intel_iommu: Handle PASID entry adding Date: Fri, 20 Jun 2025 15:18:05 +0800 Message-Id: <20250620071813.55571-12-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620071813.55571-1-zhenzhong.duan@intel.com> References: <20250620071813.55571-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.21; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750404261693116600 Content-Type: text/plain; charset="utf-8" When guest modifies a PASID entry, QEMU will capture the guest pasid select= ive pasid cache invalidation, allocate or remove a VTDAddressSpace instance per= the invalidation reasons: a) a present pasid entry moved to non-present b) a present pasid entry to be a present entry c) a non-present pasid entry moved to present This handles c). Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 1 + hw/i386/intel_iommu.c | 169 ++++++++++++++++++++++++++++++++- 2 files changed, 169 insertions(+), 1 deletion(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 01c881ed4d..025787b3b9 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -558,6 +558,7 @@ typedef struct VTDRootEntry VTDRootEntry; #define VTD_CTX_ENTRY_LEGACY_SIZE 16 #define VTD_CTX_ENTRY_SCALABLE_SIZE 32 =20 +#define VTD_SM_CONTEXT_ENTRY_PDTS(val) (((val) >> 9) & 0x7) #define VTD_SM_CONTEXT_ENTRY_RID2PASID_MASK 0xfffff #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL0(aw) (0x1e0ULL | ~VTD_HAW_MASK(aw)) #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 0xffffffffffe00000ULL diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 1db581d14a..f4273dc640 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -826,6 +826,11 @@ static inline bool vtd_pe_type_check(IntelIOMMUState *= s, VTDPASIDEntry *pe) } } =20 +static inline uint32_t vtd_sm_ce_get_pdt_entry_num(VTDContextEntry *ce) +{ + return 1U << (VTD_SM_CONTEXT_ENTRY_PDTS(ce->val[0]) + 7); +} + static inline uint16_t vtd_pe_get_did(VTDPASIDEntry *pe) { return VTD_SM_PASID_ENTRY_DID((pe)->val[1]); @@ -3246,6 +3251,159 @@ remove: return true; } =20 +static void vtd_sm_pasid_table_walk_one(IntelIOMMUState *s, + dma_addr_t pt_base, + int start, + int end, + VTDPASIDCacheInfo *info) +{ + VTDPASIDEntry pe; + int pasid =3D start; + int pasid_next; + + while (pasid < end) { + pasid_next =3D pasid + 1; + + if (!vtd_get_pe_in_pasid_leaf_table(s, pasid, pt_base, &pe) + && vtd_pe_present(&pe)) { + int bus_n =3D pci_bus_num(info->bus), devfn =3D info->devfn; + uint16_t sid =3D PCI_BUILD_BDF(bus_n, devfn); + VTDAddressSpace *vtd_as; + + vtd_iommu_lock(s); + /* + * When indexed by rid2pasid, vtd_as should have been created, + * e.g., by PCI subsystem. For other iommu pasid, we need to + * create vtd_as dynamically. The other iommu pasid is same as + * PCI's pasid, so it's used as input of vtd_find_add_as(). + */ + vtd_as =3D vtd_as_from_iommu_pasid_locked(s, sid, pasid); + vtd_iommu_unlock(s); + if (!vtd_as) { + vtd_as =3D vtd_find_add_as(s, info->bus, devfn, pasid); + } + + if ((info->type =3D=3D VTD_PASID_CACHE_DOMSI || + info->type =3D=3D VTD_PASID_CACHE_PASIDSI) && + !(info->domain_id =3D=3D vtd_pe_get_did(&pe))) { + /* + * VTD_PASID_CACHE_DOMSI and VTD_PASID_CACHE_PASIDSI + * requires domain ID check. If domain Id check fail, + * go to next pasid. + */ + pasid =3D pasid_next; + continue; + } + if (vtd_fill_pe_in_cache(s, vtd_as, &pe)) { + pasid_cache_info_set_error(info); + } + } + pasid =3D pasid_next; + } +} + +/* + * Currently, VT-d scalable mode pasid table is a two level table, + * this function aims to loop a range of PASIDs in a given pasid + * table to identify the pasid config in guest. + */ +static void vtd_sm_pasid_table_walk(IntelIOMMUState *s, + dma_addr_t pdt_base, + int start, + int end, + VTDPASIDCacheInfo *info) +{ + VTDPASIDDirEntry pdire; + int pasid =3D start; + int pasid_next; + dma_addr_t pt_base; + + while (pasid < end) { + pasid_next =3D ((end - pasid) > VTD_PASID_TBL_ENTRY_NUM) ? + (pasid + VTD_PASID_TBL_ENTRY_NUM) : end; + if (!vtd_get_pdire_from_pdir_table(pdt_base, pasid, &pdire) + && vtd_pdire_present(&pdire)) { + pt_base =3D pdire.val & VTD_PASID_TABLE_BASE_ADDR_MASK; + vtd_sm_pasid_table_walk_one(s, pt_base, pasid, pasid_next, inf= o); + } + pasid =3D pasid_next; + } +} + +static void vtd_replay_pasid_bind_for_dev(IntelIOMMUState *s, + int start, int end, + VTDPASIDCacheInfo *info) +{ + VTDContextEntry ce; + + if (!vtd_dev_to_context_entry(s, pci_bus_num(info->bus), info->devfn, + &ce)) { + uint32_t max_pasid; + + max_pasid =3D vtd_sm_ce_get_pdt_entry_num(&ce) * VTD_PASID_TBL_ENT= RY_NUM; + if (end > max_pasid) { + end =3D max_pasid; + } + vtd_sm_pasid_table_walk(s, + VTD_CE_GET_PASID_DIR_TABLE(&ce), + start, + end, + info); + } +} + +/* + * This function replay the guest pasid bindings to hosts by + * walking the guest PASID table. This ensures host will have + * latest guest pasid bindings. + */ +static void vtd_replay_guest_pasid_bindings(IntelIOMMUState *s, + VTDPASIDCacheInfo *pc_info) +{ + VTDHostIOMMUDevice *vtd_hiod; + int start =3D 0, end =3D 1; /* only rid2pasid is supported */ + VTDPASIDCacheInfo walk_info; + GHashTableIter as_it; + + switch (pc_info->type) { + case VTD_PASID_CACHE_PASIDSI: + start =3D pc_info->pasid; + end =3D pc_info->pasid + 1; + /* + * PASID selective invalidation is within domain, + * thus fall through. + */ + case VTD_PASID_CACHE_DOMSI: + case VTD_PASID_CACHE_GLOBAL_INV: + /* loop all assigned devices */ + break; + default: + error_report("invalid pc_info->type for replay"); + abort(); + } + + /* + * In this replay, only needs to care about the devices which + * are backed by host IOMMU. For such devices, their vtd_hiod + * instances are in the s->vtd_host_iommu_dev. For devices which + * are not backed by host IOMMU, it is not necessary to replay + * the bindings since their cache could be re-created in the future + * DMA address translation. Access to vtd_host_iommu_dev is already + * protected by BQL, so no iommu lock needed here. + */ + walk_info =3D *pc_info; + g_hash_table_iter_init(&as_it, s->vtd_host_iommu_dev); + while (g_hash_table_iter_next(&as_it, NULL, (void **)&vtd_hiod)) { + /* bus|devfn fields are not identical with pc_info */ + walk_info.bus =3D vtd_hiod->bus; + walk_info.devfn =3D vtd_hiod->devfn; + vtd_replay_pasid_bind_for_dev(s, start, end, &walk_info); + } + if (walk_info.error_happened) { + pasid_cache_info_set_error(pc_info); + } +} + /* * This function syncs the pasid bindings between guest and host. * It includes updating the pasid cache in vIOMMU and updating the @@ -3301,7 +3459,16 @@ static void vtd_pasid_cache_sync(IntelIOMMUState *s, pc_info); vtd_iommu_unlock(s); =20 - /* TODO: Step 2: loop all the existing vtd_hiod instances for pasid bi= nd. */ + /* + * Step 2: loop all the existing vtd_hiod instances for pasid bind. + * Ideally, needs to loop all devices to find if there is any new + * PASID binding regards to the PASID cache invalidation request. + * But it is enough to loop the devices which are backed by host + * IOMMU. For devices backed by vIOMMU (a.k.a emulated devices), + * if new PASID happened on them, their vtd_as instance could + * be created during future vIOMMU DMA translation. + */ + vtd_replay_guest_pasid_bindings(s, pc_info); } =20 static bool vtd_process_pasid_desc(IntelIOMMUState *s, --=20 2.34.1 From nobody Sat Nov 15 14:49:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750404273; cv=none; d=zohomail.com; s=zohoarc; b=dpHnRXqvCCh9h4qSxONBHPIdOtScUaYQibiFAq0FCcqUvLKzXGE41BqScGGkSeT1avz3RZCSueE7++S1nokNx2ntNSv9X5BvsAaapGN35qrdPo9pi5SvU7jIcQ6qDKOfLCK4NBiDhVpBDp9HrAGCLMWCzgrxaOUjpqxMIC/dcos= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750404273; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=09+c07bM9gptqIzYzQq9TosXoaRssiv25ReoP+oCqqs=; b=Jf1b6S0maTG9+lVumwmHd/yX8zndQymF+6Adtm6jn+Y+LedJq/s+TeIBW8Jbou8I66vZytrWMw7ktovVznFyY/P7k5b61WUH9p5AavO+TsVnnNZK2RulZKBvik+yuPtQZmPTB31jELuO5gXOmComOI8q2n9e6lB5KeJmti8B+SM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175040427343858.69326768881831; Fri, 20 Jun 2025 00:24:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uSW5j-0005Mv-VQ; Fri, 20 Jun 2025 03:23:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW5h-00057B-4R for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:23:13 -0400 Received: from mgamail.intel.com ([198.175.65.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW5d-0008IS-Ba for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:23:12 -0400 Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:23:09 -0700 Received: from spr-s2600bt.bj.intel.com ([10.240.192.127]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:23:04 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750404189; x=1781940189; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=veUHEbH419QoJuqP5XFkbi7AiOBwRCAapAno4Cqhj6c=; b=eY7lx3YMg8DeDLtFf3ZwB2qQHx5EcHfjuC9OsVW9MWyrnHzM3jzmu2Zs +V8EDRDJrRtB7meyUMJKjfvxU2gHGF55hiXFR8ZaQHubBEoZGhjUqtDy2 m8rw/INfA31D6X0eqkYiLvpr8i5ISq4Cbja/SEqmQr2YGVYuC9yyl1in2 2YFDVkK/TZqbpClP+LFWFMhdav3EMz4PzNMf2o5py7r+50B4ehlfen5fl Mv7/6cgoYpiU/hdlxiXP6nbFmUujYUrhFsUpAei0s25mMXypu6cCnygUR /627oywI6FNk/RvRsA2Udt1PwXq7ckowrredxGfoCg9SN80Y8w3N9gx1z g==; X-CSE-ConnectionGUID: 3ZArQOqgRla5iT0JK8WfMQ== X-CSE-MsgGUID: baVRf5pkRt6Fxm/OKDqk3w== X-IronPort-AV: E=McAfee;i="6800,10657,11469"; a="52532435" X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="52532435" X-CSE-ConnectionGUID: mVR8t1HhSCyijgJ5Eax2ng== X-CSE-MsgGUID: ocLXBFZ1R/2elSHweRnD0w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="181863234" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Yi Sun , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Subject: [PATCH v2 12/19] intel_iommu: Introduce a new pasid cache invalidation type FORCE_RESET Date: Fri, 20 Jun 2025 15:18:06 +0800 Message-Id: <20250620071813.55571-13-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620071813.55571-1-zhenzhong.duan@intel.com> References: <20250620071813.55571-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.21; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750404275645116600 Content-Type: text/plain; charset="utf-8" FORCE_RESET is different from GLOBAL_INV which updates pasid cache if underlying pasid entry is still valid, it drops all the pasid caches. FORCE_RESET isn't a VTD spec defined invalidation type for pasid cache, only used internally in system level reset. Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 2 ++ hw/i386/intel_iommu.c | 28 ++++++++++++++++++++++++++++ hw/i386/trace-events | 1 + 3 files changed, 31 insertions(+) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 025787b3b9..5ed76864be 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -564,6 +564,8 @@ typedef struct VTDRootEntry VTDRootEntry; #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 0xffffffffffe00000ULL =20 typedef enum VTDPCInvType { + /* Force reset all */ + VTD_PASID_CACHE_FORCE_RESET =3D 0, /* pasid cache invalidation rely on guest PASID entry */ VTD_PASID_CACHE_GLOBAL_INV, /* pasid cache global invalidation */ VTD_PASID_CACHE_DOMSI, /* pasid cache domain selective invalidati= on */ diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index f4273dc640..ed71bb8ec7 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -87,6 +87,8 @@ struct vtd_iotlb_key { static void vtd_address_space_refresh_all(IntelIOMMUState *s); static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n); =20 +static void vtd_pasid_cache_reset_locked(IntelIOMMUState *s); + static void vtd_panic_require_caching_mode(void) { error_report("We need to set caching-mode=3Don for intel-iommu to enab= le " @@ -391,6 +393,7 @@ static void vtd_reset_caches(IntelIOMMUState *s) vtd_iommu_lock(s); vtd_reset_iotlb_locked(s); vtd_reset_context_cache_locked(s); + vtd_pasid_cache_reset_locked(s); vtd_iommu_unlock(s); } =20 @@ -3196,6 +3199,8 @@ static gboolean vtd_flush_pasid(gpointer key, gpointe= r value, } =20 switch (pc_info->type) { + case VTD_PASID_CACHE_FORCE_RESET: + goto remove; case VTD_PASID_CACHE_PASIDSI: if (pc_info->pasid !=3D pasid) { return false; @@ -3251,6 +3256,26 @@ remove: return true; } =20 +/* Caller of this function should hold iommu_lock */ +static void vtd_pasid_cache_reset_locked(IntelIOMMUState *s) +{ + VTDPASIDCacheInfo pc_info =3D {}; + + trace_vtd_pasid_cache_reset(); + + pc_info.type =3D VTD_PASID_CACHE_FORCE_RESET; + + /* + * Reset pasid cache is a big hammer, so use g_hash_table_foreach_remo= ve + * which will free the vtd_as instances. Also, as a big hammer, use + * VTD_PASID_CACHE_FORCE_RESET to ensure all the vtd_as instances are + * dropped, meanwhile the change will be passed to host if + * HostIOMMUDeviceIOMMUFD is available. + */ + g_hash_table_foreach_remove(s->vtd_address_spaces, + vtd_flush_pasid, &pc_info); +} + static void vtd_sm_pasid_table_walk_one(IntelIOMMUState *s, dma_addr_t pt_base, int start, @@ -3377,6 +3402,9 @@ static void vtd_replay_guest_pasid_bindings(IntelIOMM= UState *s, case VTD_PASID_CACHE_GLOBAL_INV: /* loop all assigned devices */ break; + case VTD_PASID_CACHE_FORCE_RESET: + /* For force reset, no need to go further replay */ + return; default: error_report("invalid pc_info->type for replay"); abort(); diff --git a/hw/i386/trace-events b/hw/i386/trace-events index ae5bbfcdc0..c8a936eb46 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -24,6 +24,7 @@ vtd_inv_qi_head(uint16_t head) "read head %d" vtd_inv_qi_tail(uint16_t head) "write tail %d" vtd_inv_qi_fetch(void) "" vtd_context_cache_reset(void) "" +vtd_pasid_cache_reset(void) "" vtd_pasid_cache_gsi(void) "" vtd_pasid_cache_dsi(uint16_t domain) "Domain selective PC invalidation dom= ain 0x%"PRIx16 vtd_pasid_cache_psi(uint16_t domain, uint32_t pasid) "PASID selective PC i= nvalidation domain 0x%"PRIx16" pasid 0x%"PRIx32 --=20 2.34.1 From nobody Sat Nov 15 14:49:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750404293; cv=none; d=zohomail.com; s=zohoarc; b=hlSwUchlFVXv4+zThT39aV/p2j985nIBAMCPSGlL7/wXgUVOqQIFPo0s+uWCKV2pw4liNNoUVwH/RRHAHSS6+gyvKXcpfAFd0rRZpdBRJHHRqbsNl3okNt6Blw3sU8ut1c1O09ng+12QCIJad2Y/VSTGgbBrJHhnz69LhpcZCKg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750404293; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=jn41/X22WbqyT0qxWBrV83S+aCvzh8q8iIlFTnHHo9o=; b=HL/vZAY7PlI/UKO4D1DYfUI2Ol1eZ6+BgIi+irkiDaslxNBl1I3ReE9Dui6gbCtssnPnoOPVzQVKmIos2IvQanIXMKmxevkACmai7TQ12fHEG8JU7o+Sgd1bC0jFU2igQS55KI1tTxO44uV2AdMxbhLh7HWm0akGACPB/JERTv4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750404293028890.8996429756421; Fri, 20 Jun 2025 00:24:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uSW5m-0005ZW-I2; Fri, 20 Jun 2025 03:23:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW5l-0005UD-DW for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:23:17 -0400 Received: from mgamail.intel.com ([198.175.65.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW5j-0008IS-Bq for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:23:17 -0400 Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:23:14 -0700 Received: from spr-s2600bt.bj.intel.com ([10.240.192.127]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:23:10 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750404195; x=1781940195; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hNjzVaKFCwVRuZP8JnfjtysWXGQfahRUN8nIqfws418=; b=B+oW3iPCvWipmzi5fHLGjoZgAKd2gY7YDCIyfJ4r98V92EJ9GPwOHGXJ +7+2Lo6mRAYby2d6bLWESGaJ288krM1tt1nhiqZLvejSN/hWhVk2hBle2 kKnZliNNl4mrRwrnL0lkljgIJjLFo2uPsNQobat3Bv0yrQi9trayN+0ym QW6u8/M1dM2ZhJ71WB7vVovHQJNwOYioIy5eSxn9JUQas7AhR4n9KHznl +3YDZYDSJe2QvfWZlv2SR1ZwXJgGf8IgE333t3FFI97iYdjfNmGHWp/FT wRGhh2p0++nxT2cirFQY6yfTzuzZ4tcIA4Ewmm88qtaWyV6hy3Tq/Td8b g==; X-CSE-ConnectionGUID: g0l/CgSXS4C5vYrBmxkGTQ== X-CSE-MsgGUID: DfCVYx3BQ1aSItcb1iwt2g== X-IronPort-AV: E=McAfee;i="6800,10657,11469"; a="52532461" X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="52532461" X-CSE-ConnectionGUID: XOVQaZ//S92lWRLy7pib5g== X-CSE-MsgGUID: HDUdy+GqS66P8xtUvp1o9Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="181863251" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Subject: [PATCH v2 13/19] intel_iommu: Stick to system MR for IOMMUFD backed host device when x-fls=on Date: Fri, 20 Jun 2025 15:18:07 +0800 Message-Id: <20250620071813.55571-14-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620071813.55571-1-zhenzhong.duan@intel.com> References: <20250620071813.55571-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.21; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750404293809116600 Content-Type: text/plain; charset="utf-8" When guest in scalable mode and x-flts=3Don, we stick to system MR for IOMM= UFD backed host device. Then its default hwpt contains GPA->HPA mappings which = is used directly if PGTT=3DPT and used as nested parent if PGTT=3DFLT. Otherwi= se fallback to original processing. Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index ed71bb8ec7..be01f8885f 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -1779,6 +1779,7 @@ static bool vtd_dev_pt_enabled(IntelIOMMUState *s, VT= DContextEntry *ce, */ return false; } + return (VTD_PE_GET_TYPE(&pe) =3D=3D VTD_SM_PASID_ENTRY_PT); } =20 @@ -1790,10 +1791,33 @@ static bool vtd_as_pt_enabled(VTDAddressSpace *as) { IntelIOMMUState *s; VTDContextEntry ce; + struct vtd_as_key key =3D { + .bus =3D as->bus, + .devfn =3D as->devfn, + }; =20 assert(as); =20 s =3D as->iommu_state; + + /* + * When guest in scalable mode and x-flts=3Don, we stick to system MR + * for IOMMUFD backed host device. Then its default hwpt contains + * GPA->HPA mappings which is used directly if PGTT=3DPT and used as + * nested parent if PGTT=3DFLT. Otherwise fallback to original + * processing. + */ + if (s->root_scalable && s->flts) { + VTDHostIOMMUDevice *vtd_hiod; + + vtd_hiod =3D g_hash_table_lookup(s->vtd_host_iommu_dev, &key); + if (vtd_hiod && vtd_hiod->hiod && + object_dynamic_cast(OBJECT(vtd_hiod->hiod), + TYPE_HOST_IOMMU_DEVICE_IOMMUFD)) { + return true; + } + } + if (vtd_dev_to_context_entry(s, pci_bus_num(as->bus), as->devfn, &ce)) { /* --=20 2.34.1 From nobody Sat Nov 15 14:49:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750404239; cv=none; d=zohomail.com; s=zohoarc; b=cKfEKCwgV2PH7PrsZbk7+zyqHa2yax12/t3SbIqePrcJZifjiinos5E7ewLhaZuL7eNgjkq2T02xX/jFRLQodcCtVtJ4yPSMlLiGLHOME+9QT2eMapdDjKplOU6evDIhFMWannx0ElHvq+QsfaTKlJR65Gtuvrf/ChQFoTKgeAU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750404239; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=BlgtFE5n/IGAfY8E+N+qBh/+tjYDDSb0Wn/YfF/ksnQ=; b=Edo+ZZyhE6m9Q+Zk1Ru62cbICXSu57RP6zZXclcEdAkfYRBbvrY5gXWY6ufBHSR9O0tQ4wecn59dVQSN3sAD+fPFmMfaGfPbQzHAdveteXjQOMQ42Y4AMcHeHo7CFOqPOME0zaZopsq9i9cWtCToHY9qoxWDpupm14IXPKzXTfQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175040423924129.56884518305992; Fri, 20 Jun 2025 00:23:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uSW5r-0005uE-Pf; Fri, 20 Jun 2025 03:23:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW5q-0005pv-GZ for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:23:22 -0400 Received: from mgamail.intel.com ([198.175.65.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW5n-0008IS-O8 for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:23:22 -0400 Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:23:19 -0700 Received: from spr-s2600bt.bj.intel.com ([10.240.192.127]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:23:15 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750404200; x=1781940200; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lsVWpiXaJ141hti9PvpnrW7Otyc28/GLwcTz3BUtzHA=; b=miExXOE2Il8rZKBMwPTNMZZ3mO/+vi2A/aLxf7O3U9WzJDfdOTctMD1l Z76a/kKaTXiGrtnBDuFjaAxB9IVRWzn+mhM3+xcfBsG26Re4Emo+sekH+ pUhAd2/NAWly8rcBjlguyJw1RksThSeLalAHkM5r1yM1/6F538vbYY06d ZvWNLCQ8mUm3yIrrspXWQkfYJ+XJQjQTMS9YOjQxlbFjNq+RIcsCHFC3A nJwlk5gZZ2/d56ExvN6miJLqKj7b4pUPi4zgDAuV5ciSVUI2eEKjoB+Xs D/yBPvfml4gLLHHVnffu09vLpFyG70MV3/eABxHVQniTCd5JCHyQQpFDh g==; X-CSE-ConnectionGUID: hzA0Hn43TOiBhkrY9MOuKw== X-CSE-MsgGUID: kfOSD24gT6arbQiJ/A07Zw== X-IronPort-AV: E=McAfee;i="6800,10657,11469"; a="52532471" X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="52532471" X-CSE-ConnectionGUID: BDOTkgCnT5Gyl4ke7QfsFw== X-CSE-MsgGUID: pIlCF0RIQlehZdTXmvWaUA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="181863257" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Yi Sun , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PATCH v2 14/19] intel_iommu: Bind/unbind guest page table to host Date: Fri, 20 Jun 2025 15:18:08 +0800 Message-Id: <20250620071813.55571-15-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620071813.55571-1-zhenzhong.duan@intel.com> References: <20250620071813.55571-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.21; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750404241514116600 Content-Type: text/plain; charset="utf-8" This captures the guest PASID table entry modifications and propagates the changes to host to attach a hwpt with type determined per guest IOMMU mdoe and PGTT configuration. When PGTT is Pass-through(100b), the hwpt on host side is a stage-2 page table(GPA->HPA). When PGTT is First-stage Translation only(001b), vIOMMU reuse hwpt(GPA->HPA) provided by VFIO as nested parent to construct nested page table. When guest decides to use legacy mode then vIOMMU switches the MRs of the device's AS, hence the IOAS created by VFIO container would be switched to using the IOMMU_NOTIFIER_IOTLB_EVENTS since the MR is switched to IOMMU MR. So it is able to support shadowing the guest IO page table. Co-Authored-by: Yi Liu Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 11 ++ hw/i386/intel_iommu.c | 244 +++++++++++++++++++++++++++++++-- hw/i386/trace-events | 3 + 3 files changed, 243 insertions(+), 15 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 5ed76864be..92a533db54 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -563,6 +563,13 @@ typedef struct VTDRootEntry VTDRootEntry; #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL0(aw) (0x1e0ULL | ~VTD_HAW_MASK(aw)) #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 0xffffffffffe00000ULL =20 +typedef enum VTDPASIDOp { + VTD_PASID_BIND, + VTD_PASID_UPDATE, + VTD_PASID_UNBIND, + VTD_OP_NUM +} VTDPASIDOp; + typedef enum VTDPCInvType { /* Force reset all */ VTD_PASID_CACHE_FORCE_RESET =3D 0, @@ -607,6 +614,9 @@ typedef struct VTDPASIDCacheInfo { =20 #define VTD_SM_PASID_ENTRY_FLPM 3ULL #define VTD_SM_PASID_ENTRY_FLPTPTR (~0xfffULL) +#define VTD_SM_PASID_ENTRY_SRE_BIT(val) (!!((val) & 1ULL)) +#define VTD_SM_PASID_ENTRY_WPE_BIT(val) (!!(((val) >> 4) & 1ULL)) +#define VTD_SM_PASID_ENTRY_EAFE_BIT(val) (!!(((val) >> 7) & 1ULL)) =20 /* First Level Paging Structure */ /* Masks for First Level Paging Entry */ @@ -644,5 +654,6 @@ typedef struct VTDHostIOMMUDevice { PCIBus *bus; uint8_t devfn; HostIOMMUDevice *hiod; + uint32_t s1_hwpt; } VTDHostIOMMUDevice; #endif diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index be01f8885f..1c94a0033c 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -20,6 +20,7 @@ */ =20 #include "qemu/osdep.h" +#include CONFIG_DEVICES /* CONFIG_IOMMUFD */ #include "qemu/error-report.h" #include "qemu/main-loop.h" #include "qapi/error.h" @@ -41,6 +42,9 @@ #include "migration/vmstate.h" #include "trace.h" #include "system/iommufd.h" +#ifdef CONFIG_IOMMUFD +#include +#endif =20 /* context entry operations */ #define VTD_CE_GET_RID2PASID(ce) \ @@ -839,6 +843,27 @@ static inline uint16_t vtd_pe_get_did(VTDPASIDEntry *p= e) return VTD_SM_PASID_ENTRY_DID((pe)->val[1]); } =20 +static inline dma_addr_t vtd_pe_get_flpt_base(VTDPASIDEntry *pe) +{ + return pe->val[2] & VTD_SM_PASID_ENTRY_FLPTPTR; +} + +static inline uint32_t vtd_pe_get_fl_aw(VTDPASIDEntry *pe) +{ + return 48 + ((pe->val[2] >> 2) & VTD_SM_PASID_ENTRY_FLPM) * 9; +} + +static inline bool vtd_pe_pgtt_is_pt(VTDPASIDEntry *pe) +{ + return (VTD_PE_GET_TYPE(pe) =3D=3D VTD_SM_PASID_ENTRY_PT); +} + +/* check if pgtt is first stage translation */ +static inline bool vtd_pe_pgtt_is_flt(VTDPASIDEntry *pe) +{ + return (VTD_PE_GET_TYPE(pe) =3D=3D VTD_SM_PASID_ENTRY_FLT); +} + static inline bool vtd_pdire_present(VTDPASIDDirEntry *pdire) { return pdire->val & 1; @@ -2431,6 +2456,188 @@ static void vtd_context_global_invalidate(IntelIOMM= UState *s) vtd_iommu_replay_all(s); } =20 +#ifdef CONFIG_IOMMUFD +static void vtd_init_s1_hwpt_data(struct iommu_hwpt_vtd_s1 *vtd, + VTDPASIDEntry *pe) +{ + memset(vtd, 0, sizeof(*vtd)); + + vtd->flags =3D (VTD_SM_PASID_ENTRY_SRE_BIT(pe->val[2]) ? + IOMMU_VTD_S1_SRE : 0) | + (VTD_SM_PASID_ENTRY_WPE_BIT(pe->val[2]) ? + IOMMU_VTD_S1_WPE : 0) | + (VTD_SM_PASID_ENTRY_EAFE_BIT(pe->val[2]) ? + IOMMU_VTD_S1_EAFE : 0); + vtd->addr_width =3D vtd_pe_get_fl_aw(pe); + vtd->pgtbl_addr =3D (uint64_t)vtd_pe_get_flpt_base(pe); +} + +static int vtd_create_s1_hwpt(VTDHostIOMMUDevice *vtd_hiod, + VTDPASIDEntry *pe, Error **errp) +{ + HostIOMMUDeviceIOMMUFD *idev =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->h= iod); + struct iommu_hwpt_vtd_s1 vtd; + uint32_t s1_hwpt; + + vtd_init_s1_hwpt_data(&vtd, pe); + + if (!iommufd_backend_alloc_hwpt(idev->iommufd, idev->devid, + idev->hwpt_id, 0, IOMMU_HWPT_DATA_VTD_= S1, + sizeof(vtd), &vtd, &s1_hwpt, errp)) { + return -EINVAL; + } + + vtd_hiod->s1_hwpt =3D s1_hwpt; + + return 0; +} + +static void vtd_destroy_s1_hwpt(VTDHostIOMMUDevice *vtd_hiod) +{ + HostIOMMUDeviceIOMMUFD *idev =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->h= iod); + + iommufd_backend_free_id(idev->iommufd, vtd_hiod->s1_hwpt); + vtd_hiod->s1_hwpt =3D 0; +} + +static int vtd_device_attach_iommufd(VTDHostIOMMUDevice *vtd_hiod, + uint32_t pasid, VTDPASIDEntry *pe, + Error **errp) +{ + HostIOMMUDeviceIOMMUFD *idev =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->h= iod); + uint32_t hwpt_id; + int ret; + + if (vtd_pe_pgtt_is_flt(pe)) { + ret =3D vtd_create_s1_hwpt(vtd_hiod, pe, errp); + if (ret) { + return ret; + } + hwpt_id =3D vtd_hiod->s1_hwpt; + } else { + hwpt_id =3D idev->hwpt_id; + } + + ret =3D !host_iommu_device_iommufd_attach_hwpt(idev, hwpt_id, errp); + trace_vtd_device_attach_hwpt(idev->devid, pasid, hwpt_id, ret); + if (ret && vtd_pe_pgtt_is_flt(pe)) { + vtd_destroy_s1_hwpt(vtd_hiod); + } + + return ret; +} + +static int vtd_device_detach_iommufd(VTDHostIOMMUDevice *vtd_hiod, + uint32_t pasid, VTDPASIDEntry *pe, + Error **errp) +{ + HostIOMMUDeviceIOMMUFD *idev =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->h= iod); + int ret; + + if (vtd_hiod->iommu_state->dmar_enabled) { + ret =3D !host_iommu_device_iommufd_detach_hwpt(idev, errp); + trace_vtd_device_detach_hwpt(idev->devid, pasid, ret); + } else { + ret =3D !host_iommu_device_iommufd_attach_hwpt(idev, idev->hwpt_id= , errp); + trace_vtd_device_reattach_def_hwpt(idev->devid, pasid, idev->hwpt_= id, + ret); + } + + if (vtd_pe_pgtt_is_flt(pe)) { + vtd_destroy_s1_hwpt(vtd_hiod); + } + + return ret; +} + +static int vtd_device_attach_pgtbl(VTDHostIOMMUDevice *vtd_hiod, + VTDAddressSpace *vtd_as, VTDPASIDEntry = *pe) +{ + /* + * If pe->gptt =3D=3D FLT, should be go ahead to do bind as host only + * accepts guest FLT under nesting. If pe->pgtt=3D=3DPT, should setup + * the pasid with GPA page table. Otherwise should return failure. + */ + if (!vtd_pe_pgtt_is_flt(pe) && !vtd_pe_pgtt_is_pt(pe)) { + return -EINVAL; + } + + /* Should fail if the FLPT base is 0 */ + if (vtd_pe_pgtt_is_flt(pe) && !vtd_pe_get_flpt_base(pe)) { + return -EINVAL; + } + + return vtd_device_attach_iommufd(vtd_hiod, vtd_as->pasid, pe, &error_a= bort); +} + +static int vtd_device_detach_pgtbl(VTDHostIOMMUDevice *vtd_hiod, + VTDAddressSpace *vtd_as) +{ + VTDPASIDEntry *cached_pe =3D vtd_as->pasid_cache_entry.cache_filled ? + &vtd_as->pasid_cache_entry.pasid_entry : NULL; + + if (!cached_pe || + (!vtd_pe_pgtt_is_flt(cached_pe) && !vtd_pe_pgtt_is_pt(cached_pe)))= { + return 0; + } + + return vtd_device_detach_iommufd(vtd_hiod, vtd_as->pasid, cached_pe, + &error_abort); +} + +/** + * Caller should hold iommu_lock. + */ +static int vtd_bind_guest_pasid(VTDAddressSpace *vtd_as, + VTDPASIDEntry *pe, VTDPASIDOp op) +{ + IntelIOMMUState *s =3D vtd_as->iommu_state; + VTDHostIOMMUDevice *vtd_hiod; + int devfn =3D vtd_as->devfn; + int ret =3D -EINVAL; + struct vtd_as_key key =3D { + .bus =3D vtd_as->bus, + .devfn =3D devfn, + }; + + vtd_hiod =3D g_hash_table_lookup(s->vtd_host_iommu_dev, &key); + if (!vtd_hiod || !vtd_hiod->hiod) { + /* means no need to go further, e.g. for emulated devices */ + return 0; + } + + if (vtd_as->pasid !=3D PCI_NO_PASID) { + error_report("Non-rid_pasid %d not supported yet", vtd_as->pasid); + return ret; + } + + switch (op) { + case VTD_PASID_UPDATE: + case VTD_PASID_BIND: + { + ret =3D vtd_device_attach_pgtbl(vtd_hiod, vtd_as, pe); + break; + } + case VTD_PASID_UNBIND: + { + ret =3D vtd_device_detach_pgtbl(vtd_hiod, vtd_as); + break; + } + default: + error_report_once("Unknown VTDPASIDOp!!!\n"); + break; + } + + return ret; +} +#else +static int vtd_bind_guest_pasid(VTDAddressSpace *vtd_as, + VTDPASIDEntry *pe, VTDPASIDOp op) +{ + return 0; +} +#endif + /* Do a context-cache device-selective invalidation. * @func_mask: FM field after shifting */ @@ -3181,20 +3388,23 @@ static int vtd_fill_pe_in_cache(IntelIOMMUState *s,= VTDAddressSpace *vtd_as, VTDPASIDEntry *pe) { VTDPASIDCacheEntry *pc_entry =3D &vtd_as->pasid_cache_entry; + int ret; =20 - if (vtd_pasid_entry_compare(pe, &pc_entry->pasid_entry)) { - /* No need to go further as cached pasid entry is latest */ - return 0; + if (pc_entry->cache_filled) { + if (vtd_pasid_entry_compare(pe, &pc_entry->pasid_entry)) { + /* No need to go further as cached pasid entry is latest */ + return 0; + } + ret =3D vtd_bind_guest_pasid(vtd_as, pe, VTD_PASID_UPDATE); + } else { + ret =3D vtd_bind_guest_pasid(vtd_as, pe, VTD_PASID_BIND); } =20 - pc_entry->pasid_entry =3D *pe; - pc_entry->cache_filled =3D true; - - /* - * TODO: send pasid bind to host for passthru devices - */ - - return 0; + if (!ret) { + pc_entry->pasid_entry =3D *pe; + pc_entry->cache_filled =3D true; + } + return ret; } =20 /* @@ -3265,10 +3475,14 @@ static gboolean vtd_flush_pasid(gpointer key, gpoin= ter value, return false; =20 remove: - /* - * TODO: send pasid unbind to host for passthru devices - */ - pc_entry->cache_filled =3D false; + if (pc_entry->cache_filled) { + if (vtd_bind_guest_pasid(vtd_as, NULL, VTD_PASID_UNBIND)) { + pasid_cache_info_set_error(pc_info); + return false; + } else { + pc_entry->cache_filled =3D false; + } + } =20 /* * Don't remove address space of PCI_NO_PASID which is created by PCI diff --git a/hw/i386/trace-events b/hw/i386/trace-events index c8a936eb46..1c31b9a873 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -73,6 +73,9 @@ vtd_warn_invalid_qi_tail(uint16_t tail) "tail 0x%"PRIx16 vtd_warn_ir_vector(uint16_t sid, int index, int vec, int target) "sid 0x%"= PRIx16" index %d vec %d (should be: %d)" vtd_warn_ir_trigger(uint16_t sid, int index, int trig, int target) "sid 0x= %"PRIx16" index %d trigger %d (should be: %d)" vtd_reset_exit(void) "" +vtd_device_attach_hwpt(uint32_t dev_id, uint32_t pasid, uint32_t hwpt_id, = int ret) "dev_id %d pasid %d hwpt_id %d, ret: %d" +vtd_device_detach_hwpt(uint32_t dev_id, uint32_t pasid, int ret) "dev_id %= d pasid %d ret: %d" +vtd_device_reattach_def_hwpt(uint32_t dev_id, uint32_t pasid, uint32_t hwp= t_id, int ret) "dev_id %d pasid %d hwpt_id %d, ret: %d" =20 # amd_iommu.c amdvi_evntlog_fail(uint64_t addr, uint32_t head) "error: fail to write at = addr 0x%"PRIx64" + offset 0x%"PRIx32 --=20 2.34.1 From nobody Sat Nov 15 14:49:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750404288; cv=none; d=zohomail.com; s=zohoarc; b=RWcAC8p5oM8qgaIkqmlCaesMkTgqmjkkksZHxddyc2WrP5IRo+96LhIURZEC6U8GOGrlSRWO2sq01xstZ9Q5r1NtJxURT8xKDI2SQoYkn6i2VvaEPx+iBlBunPqMoxtak3JWWOEFRE24OP+wAXiFl9uFfqDwLq9+qSrsVAOe6ow= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750404288; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Qj/u7FEbLyXMTlTQZLHUTd0RLj80NG0gpE202rKXeUw=; b=fCel6ILdlDr5UBd7Yz/JlclSuWjNw204cI4Xuw8XM1NKOSbVaDJfbVmU36Rd+7sWidctYR2OuoXsM8ZJ3JI5hXaF1QQSt8IGIzN1zu8NcfS76x5w2JQ87NX1htU2bvfec5ghomD4D3hU//9Hmn5ZEU+ymON4LsQG+a2qYUO4Vck= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750404288160587.3633664406818; Fri, 20 Jun 2025 00:24:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uSW61-00067X-0P; Fri, 20 Jun 2025 03:23:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW5z-00064k-I1 for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:23:31 -0400 Received: from mgamail.intel.com ([198.175.65.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW5t-0008IS-4L for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:23:30 -0400 Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:23:24 -0700 Received: from spr-s2600bt.bj.intel.com ([10.240.192.127]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:23:20 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750404205; x=1781940205; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=a+4DL6Kt9UrDBXTU7mc6IQmiznf4ZHMvJYuhZ/TpLLU=; b=BV6N3WA2p989KMFHLMv5/lJ6pHs88TEw+Nrd72toXDfJTg9T3INNvedh kQVSATPh+gRGYhVAC31jmms8NWQb3umMgcvlKYXbWf3baknSmCh/PrDpJ NsoP18PftQ+l15CaikSbJttj95OTOrSz8SsfgsaWFZhS4YW+GIe17aCxb g07hwEd8iPpOT9EFyYw4/ULyl3nd5wYSLRtbMmbprRwQSZHenm0sU/Kgh UX9m3RQdBbjuu++OTkhBcR3a+rpmiekv4RC06ll6LwTCln2viQHBxapi2 5eF1hNiydjuCrfPStEpeP8Oz3PihKCtEFFv5NDIE+na9z9J5lov5ZtqbT w==; X-CSE-ConnectionGUID: 8zaCfZhCSn+87WLicilW3Q== X-CSE-MsgGUID: atFdRzimTn2XRt56ZRoFEQ== X-IronPort-AV: E=McAfee;i="6800,10657,11469"; a="52532496" X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="52532496" X-CSE-ConnectionGUID: L6m/dZzCTUKWErHxeN4mYA== X-CSE-MsgGUID: JsOj/RiPT+SGs4MD4DHwFQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="181863262" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Yi Sun , Zhenzhong Duan , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Subject: [PATCH v2 15/19] intel_iommu: Replay pasid binds after context cache invalidation Date: Fri, 20 Jun 2025 15:18:09 +0800 Message-Id: <20250620071813.55571-16-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620071813.55571-1-zhenzhong.duan@intel.com> References: <20250620071813.55571-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.21; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750404289974116600 Content-Type: text/plain; charset="utf-8" From: Yi Liu This replays guest pasid attachments after context cache invalidation. This is a behavior to ensure safety. Actually, programmer should issue pasid cache invalidation with proper granularity after issuing a context cache invalidation. Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 1 + hw/i386/intel_iommu.c | 51 ++++++++++++++++++++++++++++++++-- hw/i386/trace-events | 1 + 3 files changed, 51 insertions(+), 2 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 92a533db54..b3e4aa23f1 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -575,6 +575,7 @@ typedef enum VTDPCInvType { VTD_PASID_CACHE_FORCE_RESET =3D 0, /* pasid cache invalidation rely on guest PASID entry */ VTD_PASID_CACHE_GLOBAL_INV, /* pasid cache global invalidation */ + VTD_PASID_CACHE_DEVSI, /* pasid cache device selective invalidati= on */ VTD_PASID_CACHE_DOMSI, /* pasid cache domain selective invalidati= on */ VTD_PASID_CACHE_PASIDSI, /* pasid cache pasid selective invalidatio= n */ } VTDPCInvType; diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 1c94a0033c..621b07aa02 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -92,6 +92,10 @@ static void vtd_address_space_refresh_all(IntelIOMMUStat= e *s); static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n); =20 static void vtd_pasid_cache_reset_locked(IntelIOMMUState *s); +static void vtd_pasid_cache_sync(IntelIOMMUState *s, + VTDPASIDCacheInfo *pc_info); +static void vtd_pasid_cache_devsi(IntelIOMMUState *s, + PCIBus *bus, uint16_t devfn); =20 static void vtd_panic_require_caching_mode(void) { @@ -2437,6 +2441,8 @@ static void vtd_iommu_replay_all(IntelIOMMUState *s) =20 static void vtd_context_global_invalidate(IntelIOMMUState *s) { + VTDPASIDCacheInfo pc_info =3D { .error_happened =3D false, }; + trace_vtd_inv_desc_cc_global(); /* Protects context cache */ vtd_iommu_lock(s); @@ -2454,6 +2460,9 @@ static void vtd_context_global_invalidate(IntelIOMMUS= tate *s) * VT-d emulation codes. */ vtd_iommu_replay_all(s); + + pc_info.type =3D VTD_PASID_CACHE_GLOBAL_INV; + vtd_pasid_cache_sync(s, &pc_info); } =20 #ifdef CONFIG_IOMMUFD @@ -2696,6 +2705,21 @@ static void vtd_context_device_invalidate(IntelIOMMU= State *s, * happened. */ vtd_address_space_sync(vtd_as); + /* + * Per spec, context flush should also followed with PASID + * cache and iotlb flush. Regards to a device selective + * context cache invalidation: + * if (emaulted_device) + * invalidate pasid cache and pasid-based iotlb + * else if (assigned_device) + * check if the device has been bound to any pasid + * invoke pasid_unbind regards to each bound pasid + * Here, we have vtd_pasid_cache_devsi() to invalidate pasid + * caches, while for piotlb in QEMU, we don't have it yet, so + * no handling. For assigned device, host iommu driver would + * flush piotlb when a pasid unbind is pass down to it. + */ + vtd_pasid_cache_devsi(s, vtd_as->bus, devfn); } } } @@ -3447,6 +3471,11 @@ static gboolean vtd_flush_pasid(gpointer key, gpoint= er value, /* Fall through */ case VTD_PASID_CACHE_GLOBAL_INV: break; + case VTD_PASID_CACHE_DEVSI: + if (pc_info->bus !=3D vtd_as->bus || pc_info->devfn !=3D vtd_as->d= evfn) { + return false; + } + break; default: error_report("invalid pc_info->type"); abort(); @@ -3640,6 +3669,11 @@ static void vtd_replay_guest_pasid_bindings(IntelIOM= MUState *s, case VTD_PASID_CACHE_GLOBAL_INV: /* loop all assigned devices */ break; + case VTD_PASID_CACHE_DEVSI: + walk_info.bus =3D pc_info->bus; + walk_info.devfn =3D pc_info->devfn; + vtd_replay_pasid_bind_for_dev(s, start, end, &walk_info); + return; case VTD_PASID_CACHE_FORCE_RESET: /* For force reset, no need to go further replay */ return; @@ -3675,8 +3709,7 @@ static void vtd_replay_guest_pasid_bindings(IntelIOMM= UState *s, * It includes updating the pasid cache in vIOMMU and updating the * pasid bindings per guest's latest pasid entry presence. */ -static void vtd_pasid_cache_sync(IntelIOMMUState *s, - VTDPASIDCacheInfo *pc_info) +static void vtd_pasid_cache_sync(IntelIOMMUState *s, VTDPASIDCacheInfo *pc= _info) { if (!s->flts || !s->root_scalable || !s->dmar_enabled) { return; @@ -3737,6 +3770,20 @@ static void vtd_pasid_cache_sync(IntelIOMMUState *s, vtd_replay_guest_pasid_bindings(s, pc_info); } =20 +static void vtd_pasid_cache_devsi(IntelIOMMUState *s, + PCIBus *bus, uint16_t devfn) +{ + VTDPASIDCacheInfo pc_info =3D { .error_happened =3D false, }; + + trace_vtd_pasid_cache_devsi(devfn); + + pc_info.type =3D VTD_PASID_CACHE_DEVSI; + pc_info.bus =3D bus; + pc_info.devfn =3D devfn; + + vtd_pasid_cache_sync(s, &pc_info); +} + static bool vtd_process_pasid_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc) { diff --git a/hw/i386/trace-events b/hw/i386/trace-events index 1c31b9a873..830b11f68b 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -28,6 +28,7 @@ vtd_pasid_cache_reset(void) "" vtd_pasid_cache_gsi(void) "" vtd_pasid_cache_dsi(uint16_t domain) "Domain selective PC invalidation dom= ain 0x%"PRIx16 vtd_pasid_cache_psi(uint16_t domain, uint32_t pasid) "PASID selective PC i= nvalidation domain 0x%"PRIx16" pasid 0x%"PRIx32 +vtd_pasid_cache_devsi(uint16_t devfn) "Dev selective PC invalidation dev: = 0x%"PRIx16 vtd_re_not_present(uint8_t bus) "Root entry bus %"PRIu8" not present" vtd_ce_not_present(uint8_t bus, uint8_t devfn) "Context entry bus %"PRIu8"= devfn %"PRIu8" not present" vtd_iotlb_page_hit(uint16_t sid, uint64_t addr, uint64_t slpte, uint16_t d= omain) "IOTLB page hit sid 0x%"PRIx16" iova 0x%"PRIx64" slpte 0x%"PRIx64" d= omain 0x%"PRIx16 --=20 2.34.1 From nobody Sat Nov 15 14:49:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750404338; cv=none; d=zohomail.com; s=zohoarc; b=ZrDCfVQCgvvPYkZ3KbURbYOMpm1l51k08CFZ/q7HiQszk4eqtithWd1dXRXaG7A4nwF42MTt3gH7M+3Z3DoE9whIY2ToXv1YhxvdagmjeHN+j/CtxjYTMin8Q+iRQnrXe5ehddOtAKYTfWybZB2nS+2lEZFydjj/4KHphMpRzFk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750404338; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=WKlbX8c6GDWuoRO1zsBGOTuCmgltdDs6Ye603QLmAjo=; b=DxZt4GUtOF1vTma7a3UDEexx2mXX3NQZ8If78gEtWAKZORg47YCzwxybSeCyZGwxnfJQQCnImQzcTI+8McuAt3GD2TuUZDwyW4uQjzcMHsAwE8klJW7lI2ZxQH98uG7a6NLmZXIeJ/Xb9qaK1a1BShx9O8x/GNGFtpRVBTKQpv0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750404338556744.2981036925646; Fri, 20 Jun 2025 00:25:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uSW63-0006CK-45; Fri, 20 Jun 2025 03:23:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW61-00067Z-0g for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:23:33 -0400 Received: from mgamail.intel.com ([198.175.65.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW5y-0008OF-Vp for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:23:32 -0400 Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:23:29 -0700 Received: from spr-s2600bt.bj.intel.com ([10.240.192.127]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:23:25 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750404211; x=1781940211; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nnvG2xtnaKIFcWQTmrzVrU+8r3z7FiJUhlrx+0+GXLc=; b=FZomA7fCFyn+hlTbzTZJ8bh/PSCQCgFV4mL9PAhBd69pOofuJgjq5VFG KdhQ0LyvruRxzyxtsnQRU5w9Sd6TIYYl5w7ysch7dQabKJ/STEYN2KlDD t/pF+MQ4ZYg8yOocKmRhbixXMLWXThsE9UUOEUXkQnx4Dl7LWJQfaCIHg JgxKswiFAfbcyZXHD84Yw3Fn6jH+KTzrgGNAtGhV9URJ3YpJ3RxX9A+ZZ Vn0DuIr2arUpnjamG8+WgLlxAQNRpesMkzuqFvF4jqDVmfonZ7XKvR47K F6+nLfdKcO0I6xjxX6z9YceHi1jGOxNTzJ3jTdff7E/cgEmSC5Hiji7DR Q==; X-CSE-ConnectionGUID: pPusw6J7TR6yKoJ7ZjZtjQ== X-CSE-MsgGUID: vY0cCvcnSVibTAxUI9CvSw== X-IronPort-AV: E=McAfee;i="6800,10657,11469"; a="52532513" X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="52532513" X-CSE-ConnectionGUID: n6HAxrRLQzOGyBjWIYbVtg== X-CSE-MsgGUID: n5B5d+pKT7SGSvsDlqWw4g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="181863267" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Yi Sun , Zhenzhong Duan , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Subject: [PATCH v2 16/19] intel_iommu: Propagate PASID-based iotlb invalidation to host Date: Fri, 20 Jun 2025 15:18:10 +0800 Message-Id: <20250620071813.55571-17-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620071813.55571-1-zhenzhong.duan@intel.com> References: <20250620071813.55571-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.21; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750404340516116600 Content-Type: text/plain; charset="utf-8" From: Yi Liu This traps the guest PASID-based iotlb invalidation request and propagate it to host. Intel VT-d 3.0 supports nested translation in PASID granular. Guest SVA sup= port could be implemented by configuring nested translation on specific PASID. T= his is also known as dual stage DMA translation. Under such configuration, guest owns the GVA->GPA translation which is configured as stage-1 page table in host side for a specific pasid, and host owns GPA->HPA translation. As guest owns stage-1 translation table, piotlb invalidation should be propagated to host since host IOMMU will cache first level page table related mappings during DMA address translation. Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 6 ++ hw/i386/intel_iommu.c | 113 ++++++++++++++++++++++++++++++++- 2 files changed, 117 insertions(+), 2 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index b3e4aa23f1..07bfb97499 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -589,6 +589,12 @@ typedef struct VTDPASIDCacheInfo { bool error_happened; } VTDPASIDCacheInfo; =20 +typedef struct VTDPIOTLBInvInfo { + uint16_t domain_id; + uint32_t pasid; + struct iommu_hwpt_vtd_s1_invalidate *inv_data; +} VTDPIOTLBInvInfo; + /* PASID Table Related Definitions */ #define VTD_PASID_DIR_BASE_ADDR_MASK (~0xfffULL) #define VTD_PASID_TABLE_BASE_ADDR_MASK (~0xfffULL) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 621b07aa02..d1fa395274 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2639,12 +2639,105 @@ static int vtd_bind_guest_pasid(VTDAddressSpace *v= td_as, =20 return ret; } + +/* + * Caller of this function should hold iommu_lock. + */ +static void vtd_invalidate_piotlb(VTDAddressSpace *vtd_as, + struct iommu_hwpt_vtd_s1_invalidate *cac= he) +{ + VTDHostIOMMUDevice *vtd_hiod; + HostIOMMUDeviceIOMMUFD *idev; + int devfn =3D vtd_as->devfn; + struct vtd_as_key key =3D { + .bus =3D vtd_as->bus, + .devfn =3D devfn, + }; + IntelIOMMUState *s =3D vtd_as->iommu_state; + uint32_t entry_num =3D 1; /* Only implement one request for simplicity= */ + Error *err; + + vtd_hiod =3D g_hash_table_lookup(s->vtd_host_iommu_dev, &key); + if (!vtd_hiod || !vtd_hiod->hiod) { + return; + } + idev =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->hiod); + + if (!iommufd_backend_invalidate_cache(idev->iommufd, vtd_hiod->s1_hwpt, + IOMMU_HWPT_INVALIDATE_DATA_VTD_S= 1, + sizeof(*cache), &entry_num, cach= e, + &err)) { + error_report_err(err); + } +} + +/* + * This function is a loop function for the s->vtd_address_spaces + * list with VTDPIOTLBInvInfo as execution filter. It propagates + * the piotlb invalidation to host. Caller of this function + * should hold iommu_lock. + */ +static void vtd_flush_pasid_iotlb(gpointer key, gpointer value, + gpointer user_data) +{ + VTDPIOTLBInvInfo *piotlb_info =3D user_data; + VTDAddressSpace *vtd_as =3D value; + VTDPASIDCacheEntry *pc_entry =3D &vtd_as->pasid_cache_entry; + uint32_t pasid; + uint16_t did; + + /* Replay only fill pasid entry cache for passthrough device */ + if (!pc_entry->cache_filled || + !vtd_pe_pgtt_is_flt(&pc_entry->pasid_entry)) { + return; + } + + if (vtd_as_to_iommu_pasid_locked(vtd_as, &pasid)) { + return; + } + + did =3D vtd_pe_get_did(&pc_entry->pasid_entry); + + if (piotlb_info->domain_id =3D=3D did && piotlb_info->pasid =3D=3D pas= id) { + vtd_invalidate_piotlb(vtd_as, piotlb_info->inv_data); + } +} + +static void vtd_flush_pasid_iotlb_all(IntelIOMMUState *s, + uint16_t domain_id, uint32_t pasid, + hwaddr addr, uint64_t npages, bool i= h) +{ + struct iommu_hwpt_vtd_s1_invalidate cache_info =3D { 0 }; + VTDPIOTLBInvInfo piotlb_info; + + cache_info.addr =3D addr; + cache_info.npages =3D npages; + cache_info.flags =3D ih ? IOMMU_VTD_INV_FLAGS_LEAF : 0; + + piotlb_info.domain_id =3D domain_id; + piotlb_info.pasid =3D pasid; + piotlb_info.inv_data =3D &cache_info; + + /* + * Here loops all the vtd_as instances in s->vtd_address_spaces + * to find out the affected devices since piotlb invalidation + * should check pasid cache per architecture point of view. + */ + g_hash_table_foreach(s->vtd_address_spaces, + vtd_flush_pasid_iotlb, &piotlb_info); +} #else static int vtd_bind_guest_pasid(VTDAddressSpace *vtd_as, VTDPASIDEntry *pe, VTDPASIDOp op) { return 0; } + +static void vtd_flush_pasid_iotlb_all(IntelIOMMUState *s, + uint16_t domain_id, uint32_t pasid, + hwaddr addr, uint64_t npages, bool i= h) +{ +} #endif =20 /* Do a context-cache device-selective invalidation. @@ -3300,6 +3393,13 @@ static void vtd_piotlb_pasid_invalidate(IntelIOMMUSt= ate *s, info.pasid =3D pasid; =20 vtd_iommu_lock(s); + /* + * Here loops all the vtd_as instances in s->vtd_as + * to find out the affected devices since piotlb invalidation + * should check pasid cache per architecture point of view. + */ + vtd_flush_pasid_iotlb_all(s, domain_id, pasid, 0, (uint64_t)-1, 0); + g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_pasid, &info); vtd_iommu_unlock(s); @@ -3323,7 +3423,8 @@ static void vtd_piotlb_pasid_invalidate(IntelIOMMUSta= te *s, } =20 static void vtd_piotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain= _id, - uint32_t pasid, hwaddr addr, uint8_= t am) + uint32_t pasid, hwaddr addr, uint8_= t am, + bool ih) { VTDIOTLBPageInvInfo info; =20 @@ -3333,6 +3434,13 @@ static void vtd_piotlb_page_invalidate(IntelIOMMUSta= te *s, uint16_t domain_id, info.mask =3D ~((1 << am) - 1); =20 vtd_iommu_lock(s); + /* + * Here loops all the vtd_as instances in s->vtd_as + * to find out the affected devices since piotlb invalidation + * should check pasid cache per architecture point of view. + */ + vtd_flush_pasid_iotlb_all(s, domain_id, pasid, addr, 1 << am, ih); + g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_page_piotlb, &info); vtd_iommu_unlock(s); @@ -3366,7 +3474,8 @@ static bool vtd_process_piotlb_desc(IntelIOMMUState *= s, case VTD_INV_DESC_PIOTLB_PSI_IN_PASID: am =3D VTD_INV_DESC_PIOTLB_AM(inv_desc->val[1]); addr =3D (hwaddr) VTD_INV_DESC_PIOTLB_ADDR(inv_desc->val[1]); - vtd_piotlb_page_invalidate(s, domain_id, pasid, addr, am); + vtd_piotlb_page_invalidate(s, domain_id, pasid, addr, am, + VTD_INV_DESC_PIOTLB_IH(inv_desc->val[1]= )); break; =20 default: --=20 2.34.1 From nobody Sat Nov 15 14:49:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750404286; cv=none; d=zohomail.com; s=zohoarc; b=QmD+W3u00vhHHwmcevyCWYU+6zjv3jO7xEpp2P6E3QNHR7npsKbsnvCVgGa27F8SRG89XhzTIA3TkiUy6fSpwQ3BTTUZLsBf6wAnRrsaYBo2FX9Wz+M3tJigriEWDdGV9iCk1el2vTyjkaYMAfiRkSlB+9aiO73KJ6WZ7C5cqJ4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750404286; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=lBDzvCpkkSX3bgBpsIEANbkcf/NF4hJaPX+pPCzIdy0=; b=dbNxyWO8PLyEyf9GRFAPJWaUxef/aEgaZv8IgVJ0jifEXMFC4gyocR05DWkv5jTySfB53yPuYNlWbzBIBIhfaemH+oexYlqyC35N0RCoRwxqsWCCY6PKWrdcTKquyEqSlXmS7BYhZPCiIJ8ORrnK0cfMTMLau4Xy4ceBlPLXimI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750404286643147.8547042664328; Fri, 20 Jun 2025 00:24:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uSW6E-00078p-6n; Fri, 20 Jun 2025 03:23:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW6D-00074M-GE for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:23:45 -0400 Received: from mgamail.intel.com ([198.175.65.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW66-0008Oh-94 for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:23:45 -0400 Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:23:34 -0700 Received: from spr-s2600bt.bj.intel.com ([10.240.192.127]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:23:30 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750404218; x=1781940218; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PmPNXq5DluNt2rvRLdyAOdZc/jwKfcS+19fXNWUCNQ0=; b=Hnf0AmdAMkPFo4LYe7+AEDCeiSftuCemQimuENswSv8bXxwZY7P2dvAN QoieUSi9VQ5G89loVfMo6JQLffdofVzKbNi7b0uuxu7fhF7UMKqOoV+QQ mV0K6GalwSj46ciQq7prLaY3Z3WTznycNR0VcXyc9Yw4ddvdJqzWXQPjf uJ3WDl6ySuBn83q3q3ISS328hUOQHgNb3Zsis8r5wJW/wvvCpxJRbs3i7 mzZj/6cYRpmOA0FGwpf/hquiFtf5z+S9slr1Xg55oolRrWnyhtxqAheFD gU06f0bFrp/yZHox4IyJluwZUewKsmdbXvzzvHW9E0ORbbWiHqBZ6D1ds Q==; X-CSE-ConnectionGUID: 4eBPnCSjR6uCIHol/ON3Rg== X-CSE-MsgGUID: PWtdMmMuQv26dNzp71kRaQ== X-IronPort-AV: E=McAfee;i="6800,10657,11469"; a="52532524" X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="52532524" X-CSE-ConnectionGUID: ux31/NHXQLq2qZl+0SIUbg== X-CSE-MsgGUID: jfi8noxtTn2AHRXiBxDgkg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="181863273" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Subject: [PATCH v2 17/19] intel_iommu: Refresh pasid bind when either SRTP or TE bit is changed Date: Fri, 20 Jun 2025 15:18:11 +0800 Message-Id: <20250620071813.55571-18-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620071813.55571-1-zhenzhong.duan@intel.com> References: <20250620071813.55571-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.21; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750404287769116600 Content-Type: text/plain; charset="utf-8" From: Yi Liu When either 'Set Root Table Pointer' or 'Translation Enable' bit is changed, the pasid bindings on host side become stale and need to be updated. Introduce a helper function vtd_refresh_pasid_bind() for that purpose. Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index d1fa395274..0b322078cc 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -90,6 +90,7 @@ struct vtd_iotlb_key { =20 static void vtd_address_space_refresh_all(IntelIOMMUState *s); static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n); +static void vtd_refresh_pasid_bind(IntelIOMMUState *s); =20 static void vtd_pasid_cache_reset_locked(IntelIOMMUState *s); static void vtd_pasid_cache_sync(IntelIOMMUState *s, @@ -3066,6 +3067,7 @@ static void vtd_handle_gcmd_srtp(IntelIOMMUState *s) vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_RTPS); vtd_reset_caches(s); vtd_address_space_refresh_all(s); + vtd_refresh_pasid_bind(s); } =20 /* Set Interrupt Remap Table Pointer */ @@ -3100,6 +3102,7 @@ static void vtd_handle_gcmd_te(IntelIOMMUState *s, bo= ol en) =20 vtd_reset_caches(s); vtd_address_space_refresh_all(s); + vtd_refresh_pasid_bind(s); } =20 /* Handle Interrupt Remap Enable/Disable */ @@ -3813,6 +3816,26 @@ static void vtd_replay_guest_pasid_bindings(IntelIOM= MUState *s, } } =20 +static void vtd_refresh_pasid_bind(IntelIOMMUState *s) +{ + VTDPASIDCacheInfo pc_info =3D { .error_happened =3D false, + .type =3D VTD_PASID_CACHE_GLOBAL_INV }; + + /* + * Only when dmar is enabled, should pasid bindings replayed, + * otherwise no need to replay. + */ + if (!s->dmar_enabled) { + return; + } + + if (!s->flts || !s->root_scalable) { + return; + } + + vtd_replay_guest_pasid_bindings(s, &pc_info); +} + /* * This function syncs the pasid bindings between guest and host. * It includes updating the pasid cache in vIOMMU and updating the --=20 2.34.1 From nobody Sat Nov 15 14:49:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750404267; cv=none; d=zohomail.com; s=zohoarc; b=aOmgzdEQ/U6oPaZwKJkIB1F61ejkTij77df4JXsJnw54GZuaSlUgqzo6ayfwhGkSwulsKt3A2mP8bW2fqILvKXgnR9OlYHVex9rx2gbJ0Nzb6XtDp5BOtanLCUdUcLJKfTDr1sila70VfQCIJZZxrl0VuG5immTrCTyabtUe1+0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750404267; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=H8BilzuUDd2/IqtPbzPtZjxBx1jHK/JMPOa16MrQ+0w=; b=HmsPxegNUfvpS1zZB4IIk5xgOHkM2agVlUFfRVTuF5f7KmW6GIcmGFyC30uY3B/4637DVvdE3ZsbO70OJvfDshK9Fhh0j0HVyBZo9dsioT+R+X0iefSySqeMci9eIHigTDAjrWCzlL8RcwmlsC6lrgnNl308Ip/J/caLe4WKOlE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750404267176149.1713304241041; Fri, 20 Jun 2025 00:24:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uSW6E-0007CN-Ta; Fri, 20 Jun 2025 03:23:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW6C-000708-Pz for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:23:45 -0400 Received: from mgamail.intel.com ([198.175.65.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW68-0008Ot-Bg for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:23:44 -0400 Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:23:39 -0700 Received: from spr-s2600bt.bj.intel.com ([10.240.192.127]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:23:35 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750404220; x=1781940220; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VzUt0kb/wH2GYgYNrDND9uyye5VJquaKBiwKH23wriM=; b=d0Srf7vY7NkV311DWsbqx1X+XWzchwEkQSb8gfxfGsWqzmyZndkANZr/ tXjJ3JhLo5ZTWw3i4w8rlN0muRkegU5PXyw4BOY/wcTMvNVg/+30Uh0Ml qc4HojIwWtDCSPoVac/H0d8ZByvAq/J5yWDcOkyWY3Z1kKRsUJglGjIpk poRuQXeACXfe01bd+NHf8VNbZGJpRsxBCQQ6hDbnpvP+/nwgesIrw4Nr5 rypSMOmSdIFTUDBJa8s9zTvQws9/wrG9/4Y3ZOagVrMtY0XnqrQK+uoWu qW52/IemqCTw4GrKSIXQEePdKvwi+xucYw8+D0yuFoFmWkoCnW9jY5MI+ A==; X-CSE-ConnectionGUID: mprVRM0NTDioHqo4SpUN3w== X-CSE-MsgGUID: f8IIv6/iR9iWgkBa1KSHPw== X-IronPort-AV: E=McAfee;i="6800,10657,11469"; a="52532550" X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="52532550" X-CSE-ConnectionGUID: IWNMB03hQsO0t2+mjKmWCg== X-CSE-MsgGUID: JMfLiqzcSEScfErqv577Ww== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="181863284" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v2 18/19] Workaround for ERRATA_772415_SPR17 Date: Fri, 20 Jun 2025 15:18:12 +0800 Message-Id: <20250620071813.55571-19-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620071813.55571-1-zhenzhong.duan@intel.com> References: <20250620071813.55571-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.21; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750404267655116600 Content-Type: text/plain; charset="utf-8" On a system influenced by ERRATA_772415, IOMMU_HW_INFO_VTD_ERRATA_772415_SP= R17 is repored by IOMMU_DEVICE_GET_HW_INFO. Due to this errata, even the readon= ly range mapped on stage-2 page table could still be written. Reference from 4th Gen Intel Xeon Processor Scalable Family Specification Update, Errata Details, SPR17. https://www.intel.com/content/www/us/en/content-details/772415/content-deta= ils.html Signed-off-by: Zhenzhong Duan --- include/hw/vfio/vfio-container-base.h | 1 + hw/vfio/iommufd.c | 8 +++++++- hw/vfio/listener.c | 13 +++++++++---- 3 files changed, 17 insertions(+), 5 deletions(-) diff --git a/include/hw/vfio/vfio-container-base.h b/include/hw/vfio/vfio-c= ontainer-base.h index f0232654ee..e5c51a51ac 100644 --- a/include/hw/vfio/vfio-container-base.h +++ b/include/hw/vfio/vfio-container-base.h @@ -51,6 +51,7 @@ typedef struct VFIOContainerBase { QLIST_HEAD(, VFIODevice) device_list; GList *iova_ranges; NotifierWithReturn cpr_reboot_notifier; + bool bypass_ro; } VFIOContainerBase; =20 typedef struct VFIOGuestIOMMU { diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c index 83a632bdee..23839a511a 100644 --- a/hw/vfio/iommufd.c +++ b/hw/vfio/iommufd.c @@ -306,6 +306,7 @@ static bool iommufd_cdev_autodomains_get(VFIODevice *vb= asedev, { ERRP_GUARD(); IOMMUFDBackend *iommufd =3D vbasedev->iommufd; + struct iommu_hw_info_vtd vtd; uint32_t type, flags =3D 0; uint64_t hw_caps; VFIOIOASHwpt *hwpt; @@ -345,10 +346,15 @@ static bool iommufd_cdev_autodomains_get(VFIODevice *= vbasedev, * instead. */ if (!iommufd_backend_get_device_info(vbasedev->iommufd, vbasedev->devi= d, - &type, NULL, 0, &hw_caps, errp)) { + &type, &vtd, sizeof(vtd), &hw_cap= s, + errp)) { return false; } =20 + if (vtd.flags & IOMMU_HW_INFO_VTD_ERRATA_772415_SPR17) { + container->bcontainer.bypass_ro =3D true; + } + if (hw_caps & IOMMU_HW_CAP_DIRTY_TRACKING) { flags =3D IOMMU_HWPT_ALLOC_DIRTY_TRACKING; } diff --git a/hw/vfio/listener.c b/hw/vfio/listener.c index f498e23a93..c64aa4539e 100644 --- a/hw/vfio/listener.c +++ b/hw/vfio/listener.c @@ -364,7 +364,8 @@ static bool vfio_known_safe_misalignment(MemoryRegionSe= ction *section) return true; } =20 -static bool vfio_listener_valid_section(MemoryRegionSection *section, +static bool vfio_listener_valid_section(VFIOContainerBase *bcontainer, + MemoryRegionSection *section, const char *name) { if (vfio_listener_skipped_section(section)) { @@ -375,6 +376,10 @@ static bool vfio_listener_valid_section(MemoryRegionSe= ction *section, return false; } =20 + if (bcontainer && bcontainer->bypass_ro && section->readonly) { + return false; + } + if (unlikely((section->offset_within_address_space & ~qemu_real_host_page_mask()) !=3D (section->offset_within_region & ~qemu_real_host_page_mas= k()))) { @@ -494,7 +499,7 @@ void vfio_container_region_add(VFIOContainerBase *bcont= ainer, int ret; Error *err =3D NULL; =20 - if (!vfio_listener_valid_section(section, "region_add")) { + if (!vfio_listener_valid_section(bcontainer, section, "region_add")) { return; } =20 @@ -655,7 +660,7 @@ static void vfio_listener_region_del(MemoryListener *li= stener, int ret; bool try_unmap =3D true; =20 - if (!vfio_listener_valid_section(section, "region_del")) { + if (!vfio_listener_valid_section(bcontainer, section, "region_del")) { return; } =20 @@ -812,7 +817,7 @@ static void vfio_dirty_tracking_update(MemoryListener *= listener, container_of(listener, VFIODirtyRangesListener, listener); hwaddr iova, end; =20 - if (!vfio_listener_valid_section(section, "tracking_update") || + if (!vfio_listener_valid_section(NULL, section, "tracking_update") || !vfio_get_section_iova_range(dirty->bcontainer, section, &iova, &end, NULL)) { return; --=20 2.34.1 From nobody Sat Nov 15 14:49:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1750404281; cv=none; d=zohomail.com; s=zohoarc; b=X5cEGNJqLp1VisVAVOzLiI2ySEEsteU6sA3fTmKsvsx7DngVBkrSdJ9kt3hyK4t8/t9d6FYX6i8br1IEpxAy8ot9XeWv1jPeFZt8PU8bs4cZjCqd5sMAUfdIj/IW+z5P2v1+FYPxqGlERtVpGk71aV6To9WId3NHD2SQ6RaPvnw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750404281; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=vcFd9687KFdC0Ems80BRioU8D/8nt3djH7tQk/aAvsE=; b=M3PwCLftZ0m5E8FyOj/4gsuyMHcGkRyE6Ux4jzGgT+tdqXLL/xiYVEdrZoS4UEWqVy45Zf/LP0KlPYSwHCsMmF9VexsNpB7ps73nxT9zrU8dzhznSnm6ff0E6eV/5bmABS70WutFS/R0LSVXWABwu2AyYKbE2LhzMfvuThc4Hr4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175040428175418.23326049719026; Fri, 20 Jun 2025 00:24:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uSW6L-0007fJ-7T; Fri, 20 Jun 2025 03:23:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW6J-0007UW-43 for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:23:51 -0400 Received: from mgamail.intel.com ([198.175.65.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSW6D-0008Ot-Pp for qemu-devel@nongnu.org; Fri, 20 Jun 2025 03:23:50 -0400 Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:23:44 -0700 Received: from spr-s2600bt.bj.intel.com ([10.240.192.127]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2025 00:23:40 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1750404226; x=1781940226; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=D+dc7LHOrfFxCsSPxmn1Invm9HS5geBOVM4r4eW7FRQ=; b=MtQ8Qjg7OXmTHqHCVSSffGr/TFDSD9PJMepPs46Bc2hwgNhON2A2aX1F d1W/kBlzVWFfaRDf4dtvMQ7WHbtZAQtjxx0GM02GswVuvQ66+q1oGIZZx eWR3l4WMxBRA9U7mYq4ic+xHcgzaF8VkrVOul4w5OOJ25gfFnHYUmpcqR PA+b+6F8Y5DaOEchrv63/R8YVdREGpdXtkIYiNdO1ouKIJylGqUNdMyRd rfW7wlsFok95wH6QjFs+o+fY22MXpmlYiJFf6XM9WHjsSO9BP983xaHDb 9+15O9SQ3sAp3Mv1wE4v7vdgEbl/29fpd77M+p2M3svWXjH6PHeaYhelu Q==; X-CSE-ConnectionGUID: QI2sqmoeTaOkmf51vJ6Hzg== X-CSE-MsgGUID: ENB2rFWuTh+jvLg+UpUo9g== X-IronPort-AV: E=McAfee;i="6800,10657,11469"; a="52532576" X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="52532576" X-CSE-ConnectionGUID: 2YECpPkhRgiAZmHz/gOYkQ== X-CSE-MsgGUID: vJdbcjvaRB6EuQqodVWYKg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,250,1744095600"; d="scan'208";a="181863295" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Subject: [PATCH v2 19/19] intel_iommu: Enable host device when x-flts=on in scalable mode Date: Fri, 20 Jun 2025 15:18:13 +0800 Message-Id: <20250620071813.55571-20-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250620071813.55571-1-zhenzhong.duan@intel.com> References: <20250620071813.55571-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.21; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -62 X-Spam_score: -6.3 X-Spam_bar: ------ X-Spam_report: (-6.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.897, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1750404283737116600 Content-Type: text/plain; charset="utf-8" Now that all infrastructures of supporting passthrough device running with stage-1 translation are there, enable it now. Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 0b322078cc..88ccce1f94 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -5305,6 +5305,8 @@ static bool vtd_check_hiod(IntelIOMMUState *s, VTDHos= tIOMMUDevice *vtd_hiod, "when x-flts=3Don"); return false; } + + return true; #endif =20 error_setg(errp, "host device is uncompatible with stage-1 translation= "); --=20 2.34.1