From nobody Sat Nov 15 16:38:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1750346340; cv=none; d=zohomail.com; s=zohoarc; b=FUbPmq6DYaShQYK0GKAPbCQWVkDneybUSDyX1jhK64YxhT5DxPleuPqczKHqb/U3Sn7QemqCCRKAugvFfJ2zHrLJzrj8oJa7EV28olENkfl/8hD0hbxIcebF/Vg5DZU5Vu215ImxTP3VBKaOXb26ElEQ9lc3u2EDYeDuwlrAPIM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750346340; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=ui3l+Z3soDW8KTgeMjlK1sx7sQ87hdUq73fKnvojlbE=; b=NJWLdgtWlBYymKRXa6muVxMFpbI3ksfLhn7CzzPfrrN1gIqDpF48m0GXcbGsIcfstFGZ/wLH1A4QIPvmPZbTnd6Av2EAh9wjQ05TwSlERZCDrT5Z41287+5PBc0M55QmlFFR5j8YylnCBvmKa3y6OBCq6DOBI6gzAYyniwH99oc= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750346340483951.9011926795599; Thu, 19 Jun 2025 08:19:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uSH18-0003Ex-Hj; Thu, 19 Jun 2025 11:17:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSH0e-0002s4-RO for qemu-devel@nongnu.org; Thu, 19 Jun 2025 11:17:01 -0400 Received: from [185.176.79.56] (helo=frasgout.his.huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uSH0b-00021O-Hd for qemu-devel@nongnu.org; Thu, 19 Jun 2025 11:17:00 -0400 Received: from mail.maildlp.com (unknown [172.18.186.31]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4bNPKH1Xttz6L5sP; Thu, 19 Jun 2025 23:14:27 +0800 (CST) Received: from frapeml500007.china.huawei.com (unknown [7.182.85.172]) by mail.maildlp.com (Postfix) with ESMTPS id 4462F1400D9; Thu, 19 Jun 2025 23:16:43 +0800 (CST) Received: from P_UKIT01-A7bmah.china.huawei.com (10.195.246.81) by frapeml500007.china.huawei.com (7.182.85.172) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Thu, 19 Jun 2025 17:16:42 +0200 To: , , CC: , , , Subject: [PATCH v2 3/7] hw/cxl/events: Updates for rev3.2 DRAM event record Date: Thu, 19 Jun 2025 16:16:15 +0100 Message-ID: <20250619151619.1695-4-shiju.jose@huawei.com> X-Mailer: git-send-email 2.43.0.windows.1 In-Reply-To: <20250619151619.1695-1-shiju.jose@huawei.com> References: <20250619151619.1695-1-shiju.jose@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.195.246.81] X-ClientProxiedBy: lhrpeml500006.china.huawei.com (7.191.161.198) To frapeml500007.china.huawei.com (7.182.85.172) X-Host-Lookup-Failed: Reverse DNS lookup failed for 185.176.79.56 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shiju.jose@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: From: shiju.jose--- via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1750346342823116600 Content-Type: text/plain; charset="utf-8" From: Shiju Jose CXL spec rev3.2 section 8.2.10.2.1.2 Table 8-58, DRAM event record has updated with following new fields. 1. Component Identifier 2. Sub-channel of the memory event location 3. Advanced Programmable Corrected Memory Error Threshold Event Flags 4. Corrected Volatile Memory Error Count at Event 5. Memory Event Sub-Type Add updates for the above spec changes in the CXL DRAM event reporting and QMP command to inject DRAM event. Signed-off-by: Shiju Jose --- hw/mem/cxl_type3.c | 24 ++++++++++++++++++++++++ hw/mem/cxl_type3_stubs.c | 5 +++++ include/hw/cxl/cxl_events.h | 9 +++++++-- qapi/cxl.json | 22 +++++++++++++++++++++- 4 files changed, 57 insertions(+), 3 deletions(-) diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index 410ff445d0..b99a100fe0 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -1924,6 +1924,9 @@ void qmp_cxl_inject_general_media_event(const char *p= ath, CxlEventLog log, #define CXL_DRAM_VALID_ROW BIT(5) #define CXL_DRAM_VALID_COLUMN BIT(6) #define CXL_DRAM_VALID_CORRECTION_MASK BIT(7) +#define CXL_DRAM_VALID_COMPONENT BIT(8) +#define CXL_DRAM_VALID_COMPONENT_ID_FORMAT BIT(9) +#define CXL_DRAM_VALID_SUB_CHANNEL BIT(10) =20 void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log, uint32_t= flags, uint8_t class, uint8_t subclass, @@ -1939,6 +1942,11 @@ void qmp_cxl_inject_dram_event(const char *path, Cxl= EventLog log, uint32_t flags bool has_column, uint16_t column, bool has_correction_mask, uint64List *correction_mask, + const char *component_id, + bool has_sub_channel, uint8_t sub_channel, + uint8_t cme_ev_flags, + uint32_t cvme_count, + uint8_t sub_type, Error **errp) { Object *obj =3D object_resolve_path(path, NULL); @@ -2023,6 +2031,22 @@ void qmp_cxl_inject_dram_event(const char *path, Cxl= EventLog log, uint32_t flags valid_flags |=3D CXL_DRAM_VALID_CORRECTION_MASK; } =20 + if (component_id) { + strncpy((char *)dram.component_id, component_id, + sizeof(dram.component_id) - 1); + valid_flags |=3D CXL_DRAM_VALID_COMPONENT; + valid_flags |=3D CXL_DRAM_VALID_COMPONENT_ID_FORMAT; + } + + if (has_sub_channel) { + dram.sub_channel =3D sub_channel; + valid_flags |=3D CXL_DRAM_VALID_SUB_CHANNEL; + } + + dram.cme_ev_flags =3D cme_ev_flags; + st24_le_p(dram.cvme_count, cvme_count); + dram.sub_type =3D sub_type; + stw_le_p(&dram.validity_flags, valid_flags); =20 if (cxl_event_insert(cxlds, enc_log, (CXLEventRecordRaw *)&dram)) { diff --git a/hw/mem/cxl_type3_stubs.c b/hw/mem/cxl_type3_stubs.c index b2a11bded8..26161c086a 100644 --- a/hw/mem/cxl_type3_stubs.c +++ b/hw/mem/cxl_type3_stubs.c @@ -42,6 +42,11 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEven= tLog log, uint32_t flags bool has_column, uint16_t column, bool has_correction_mask, uint64List *correction_mask, + const char *component_id, + bool has_sub_channel, uint8_t sub_channel, + uint8_t cme_ev_flags, + uint32_t cvme_count, + uint8_t sub_type, Error **errp) {} =20 void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log, diff --git a/include/hw/cxl/cxl_events.h b/include/hw/cxl/cxl_events.h index 352f9891bd..a3c5f2ec20 100644 --- a/include/hw/cxl/cxl_events.h +++ b/include/hw/cxl/cxl_events.h @@ -138,7 +138,7 @@ typedef struct CXLEventGenMedia { =20 /* * DRAM Event Record - * CXL r3.1 Section 8.2.9.2.1.2: Table 8-46 + * CXL r3.2 Section 8.2.10.2.1.2: Table 8-58 * All fields little endian. */ typedef struct CXLEventDram { @@ -156,7 +156,12 @@ typedef struct CXLEventDram { uint8_t row[3]; uint16_t column; uint64_t correction_mask[4]; - uint8_t reserved[0x17]; + uint8_t component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE]; + uint8_t sub_channel; + uint8_t cme_ev_flags; + uint8_t cvme_count[3]; + uint8_t sub_type; + uint8_t reserved; } QEMU_PACKED CXLEventDram; =20 /* diff --git a/qapi/cxl.json b/qapi/cxl.json index dd01d50c25..0ba3a8e0f3 100644 --- a/qapi/cxl.json +++ b/qapi/cxl.json @@ -167,6 +167,23 @@ # @correction-mask: Bits within each nibble. Used in order of bits # set in the nibble-mask. Up to 4 nibbles may be covered. # +# @component-id: Device specific component identifier for the event. +# May describe a field replaceable sub-component of the device. +# See CXL r3.2 Table 8-58 DRAM Event Record. +# +# @sub-channel: The sub-channel of the memory event location. +# See CXL r3.2 Table 8-58 DRAM Event Record. +# +# @cme-ev-flags: Advanced programmable corrected memory error +# threshold event flags. +# See CXL r3.2 Table 8-58 DRAM Event Record. +# +# @cvme-count: Corrected volatile memory error count at event. +# See CXL r3.2 Table 8-58 DRAM Event Record. +# +# @sub-type: Memory event sub-type. +# See CXL r3.2 Table 8-58 DRAM Event Record. +# # Since: 8.1 ## { 'command': 'cxl-inject-dram-event', @@ -177,7 +194,10 @@ 'type': 'uint8', 'transaction-type': 'uint8', '*channel': 'uint8', '*rank': 'uint8', '*nibble-mask': 'uint32= ', '*bank-group': 'uint8', '*bank': 'uint8', '*row': 'uint32', - '*column': 'uint16', '*correction-mask': [ 'uint64' ] + '*column': 'uint16', '*correction-mask': [ 'uint64' ], + '*component-id': 'str', '*sub-channel':'uint8', + 'cme-ev-flags':'uint8', 'cvme-count':'uint32', + 'sub-type':'uint8' }} =20 ## --=20 2.43.0