From nobody Sat Nov 15 14:53:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1750315385; cv=none; d=zohomail.com; s=zohoarc; b=cwr/mrzZMBVlBY8OXVfQhEbb0q/Lb0L4l46AQdgDQnoSNdnwUK1C0tfrpp83eP5Ybdubtanq7AoH8xG9fr5kI76qsjjtAcDub6JiMW6QZxUYp5rm+ttc1trf9IQjhA+SYRqrpCX9pB0NuN9KDT3Vto4u9iYrSzNbjEa7SXjekUU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750315385; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=QGkzt2OXyvvXTV/gAiilby18HQC1XzfXzh41je8QjG8=; b=CE1e9UyXkLpUIWhui9oh/21EnJ+DckHvmzKrqgrm/2DZSW3ZYxBNMPm6Jnpnivbas3ztV8wPv/1URs16Mg06HsFpfbdIe8qgD5cojfj6QmeXl2G5qTq49leZgpESsXh68Plwf4C3owXBUslqKxNpwzXw4SnEAcFSIpRGnvLWC6s= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750315385762984.1544798995551; Wed, 18 Jun 2025 23:43:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uS8xp-0002Ue-QB; Thu, 19 Jun 2025 02:41:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uS8xn-0002Tv-QI; Thu, 19 Jun 2025 02:41:31 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uS8xl-0001s1-Q5; Thu, 19 Jun 2025 02:41:31 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 19 Jun 2025 14:41:16 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 19 Jun 2025 14:41:16 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [RFC v5 1/4] hw/misc/aspeed_otp: Add ASPEED OTP memory device model Date: Thu, 19 Jun 2025 14:41:10 +0800 Message-ID: <20250619064115.4182202-2-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250619064115.4182202-1-kane_chen@aspeedtech.com> References: <20250619064115.4182202-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1750315388071116600 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS Introduce a QEMU device model for ASPEED's One-Time Programmable (OTP) memory. This model simulates a word-addressable OTP region used for secure fuse storage or boot-time configuration. The OTP memory can operate with either: - a file-backed backend via the 'drive' property, which allows persistent emulation of burned fuse states using -blockdev, or - an internal fallback buffer The OTP model provides a memory-like interface through a dedicated AddressSpace, allowing other device models (e.g., SBC) to issue transactions as if accessing a memory-mapped region. Actual data is maintained in a file-backed or internal buffer. Logging is included to assist with debugging and to indicate fallback behavior when no backend is provided. Signed-off-by: Kane-Chen-AS --- hw/misc/aspeed_otpmem.c | 117 ++++++++++++++++++++++++++++++++ hw/misc/meson.build | 1 + include/hw/misc/aspeed_otpmem.h | 35 ++++++++++ 3 files changed, 153 insertions(+) create mode 100644 hw/misc/aspeed_otpmem.c create mode 100644 include/hw/misc/aspeed_otpmem.h diff --git a/hw/misc/aspeed_otpmem.c b/hw/misc/aspeed_otpmem.c new file mode 100644 index 0000000000..c5a67621c9 --- /dev/null +++ b/hw/misc/aspeed_otpmem.c @@ -0,0 +1,117 @@ +/* + * ASPEED OTP (One-Time Programmable) memory + * + * Copyright (C) 2025 Aspeed + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "trace.h" +#include "system/block-backend-global-state.h" +#include "system/block-backend-io.h" +#include "hw/misc/aspeed_otpmem.h" + +static uint64_t aspeed_otpmem_read(void *opaque, hwaddr offset, unsigned s= ize) +{ + AspeedOTPMemState *s =3D opaque; + uint64_t val =3D 0; + + memcpy(&val, s->storage + offset, size); + + return val; +} + +static void aspeed_otpmem_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + int ret; + AspeedOTPMemState *s =3D opaque; + + memcpy(s->storage + offset, &val, size); + if (s->blk) { + ret =3D blk_pwrite(s->blk, offset, size, &val, BDRV_REQ_FUA); + if (ret < 0) { + qemu_log_mask(LOG_GUEST_ERROR, + "blk_pwrite failed offset 0x%" HWADDR_PRIx + ", ret =3D %d\n", + offset, ret); + } + } +} + +static const MemoryRegionOps aspeed_otpmem_ops =3D { + .read =3D aspeed_otpmem_read, + .write =3D aspeed_otpmem_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 4, +}; + +static void aspeed_otpmem_realize(DeviceState *dev, Error **errp) +{ + AspeedOTPMemState *s =3D ASPEED_OTPMEM(dev); + const size_t size =3D OTPMEM_SIZE; + int i, num; + uint32_t *p; + + s->storage =3D blk_blockalign(s->blk, size); + if (!s->storage) { + error_setg(errp, "Failed to allocate OTP memory storage buffer"); + return; + } + + if (s->blk) { + uint64_t perm =3D BLK_PERM_CONSISTENT_READ | + (blk_supports_write_perm(s->blk) ? BLK_PERM_WRITE = : 0); + if (blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp) < 0) { + error_setg(errp, "Failed to set permission"); + return; + } + + if (blk_pread(s->blk, 0, s->size, s->storage, 0) < 0) { + error_setg(errp, "Failed to read the initial flash content"); + return; + } + } else { + num =3D size / sizeof(uint32_t); + p =3D (uint32_t *)s->storage; + for (i =3D 0; i < num; i++) { + p[i] =3D (i % 2 =3D=3D 0) ? 0x00000000 : 0xFFFFFFFF; + } + qemu_log_mask(LOG_GUEST_ERROR, + "OTP image is not presented, use local buffer\n"); + } + + memory_region_init_io(&s->mmio, OBJECT(dev), &aspeed_otpmem_ops, + s, "aspeed.otpmem", size); + address_space_init(&s->as, &s->mmio, NULL); +} + +static const Property aspeed_otpmem_properties[] =3D { + DEFINE_PROP_UINT64("size", AspeedOTPMemState, size, OTPMEM_SIZE), + DEFINE_PROP_DRIVE("drive", AspeedOTPMemState, blk), +}; + +static void aspeed_otpmem_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + dc->realize =3D aspeed_otpmem_realize; + device_class_set_props(dc, aspeed_otpmem_properties); +} + +static const TypeInfo aspeed_otpmem_info =3D { + .name =3D TYPE_ASPEED_OTPMEM, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(AspeedOTPMemState), + .class_init =3D aspeed_otpmem_class_init, +}; + +static void aspeed_otpmem_register_types(void) +{ + type_register_static(&aspeed_otpmem_info); +} + +type_init(aspeed_otpmem_register_types) diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 6d47de482c..ed1eaaa2ad 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -136,6 +136,7 @@ system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed_sbc.c', 'aspeed_sdmc.c', 'aspeed_xdma.c', + 'aspeed_otpmem.c', 'aspeed_peci.c', 'aspeed_sli.c')) =20 diff --git a/include/hw/misc/aspeed_otpmem.h b/include/hw/misc/aspeed_otpme= m.h new file mode 100644 index 0000000000..7f469d9fd7 --- /dev/null +++ b/include/hw/misc/aspeed_otpmem.h @@ -0,0 +1,35 @@ +/* + * ASPEED OTP (One-Time Programmable) memory + * + * Copyright (C) 2025 Aspeed + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef ASPEED_OTPMMEM_H +#define ASPEED_OTPMMEM_H + +#include "system/memory.h" +#include "hw/block/block.h" +#include "system/memory.h" +#include "system/address-spaces.h" + +#define OTPMEM_SIZE 0x4000 +#define TYPE_ASPEED_OTPMEM "aspeed.otpmem" +OBJECT_DECLARE_SIMPLE_TYPE(AspeedOTPMemState, ASPEED_OTPMEM) + +typedef struct AspeedOTPMemState { + DeviceState parent_obj; + + BlockBackend *blk; + + uint64_t size; + + AddressSpace as; + + MemoryRegion mmio; + + uint8_t *storage; +} AspeedOTPMemState; + +#endif /* ASPEED_OTPMMEM_H */ --=20 2.43.0 From nobody Sat Nov 15 14:53:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1750315370; cv=none; d=zohomail.com; s=zohoarc; b=fRRXV4WMBcZCVF+dFrK+V17Gs5hKMXXPiH7VOXXa355UGqVMdd3TSC9nrBUu+LyNymmduGfz688MjpEA9JuUSwR5ukeAj1VKmJVmF044fMSQtOGTf5NmS0FgDerRXRiw8hHuOR1KqHr2ax0vv8lalbZ1WSIE4oMPltTDjRYhUFY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750315370; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Thu, 19 Jun 2025 02:41:34 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 19 Jun 2025 14:41:16 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 19 Jun 2025 14:41:16 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [RFC v5 2/4] hw/misc/aspeed_sbc: Connect ASPEED OTP memory device to SBC Date: Thu, 19 Jun 2025 14:41:11 +0800 Message-ID: <20250619064115.4182202-3-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250619064115.4182202-1-kane_chen@aspeedtech.com> References: <20250619064115.4182202-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1750315374197116600 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS This patch connects the aspeed.otpmem device to the ASPEED Secure Boot Controller (SBC) model. It implements OTP memory access via the SBC's command interface and enables emulation of secure fuse programming flows. The following OTP commands are supported: - READ: reads a 32-bit word from OTP memory into internal registers - PROG: programs a 32-bit word value to the specified OTP address The integration supports both externally provided OTP devices (via -M otpmem=3DXYZ and -device aspeed.otpmem) and fallback to an internal OTP instance if no drive is specified. A dedicated AddressSpace is used to issue memory transactions from SBC to the OTP backend. Trace events are added to observe read/program operations and command handling flow. Signed-off-by: Kane-Chen-AS --- hw/misc/aspeed_sbc.c | 161 +++++++++++++++++++++++++++++++++++ hw/misc/trace-events | 7 ++ include/hw/misc/aspeed_sbc.h | 7 ++ 3 files changed, 175 insertions(+) diff --git a/hw/misc/aspeed_sbc.c b/hw/misc/aspeed_sbc.c index a7d101ba71..8e192e9496 100644 --- a/hw/misc/aspeed_sbc.c +++ b/hw/misc/aspeed_sbc.c @@ -12,12 +12,19 @@ #include "qemu/log.h" #include "qemu/error-report.h" #include "hw/qdev-properties.h" +#include "system/system.h" +#include "qemu/notify.h" #include "hw/misc/aspeed_sbc.h" #include "qapi/error.h" #include "migration/vmstate.h" +#include "trace.h" =20 #define R_PROT (0x000 / 4) +#define R_CMD (0x004 / 4) +#define R_ADDR (0x010 / 4) #define R_STATUS (0x014 / 4) +#define R_CAMP1 (0x020 / 4) +#define R_CAMP2 (0x024 / 4) #define R_QSR (0x040 / 4) =20 /* R_STATUS */ @@ -41,6 +48,14 @@ #define QSR_RSA_MASK (0x3 << 12) #define QSR_HASH_MASK (0x3 << 10) =20 +typedef enum { + SBC_OTP_CMD_READ =3D 0x23b1e361, + SBC_OTP_CMD_PROG =3D 0x23b1e364, +} SBC_OTP_Command; + +#define OTP_DATA_DWORD_COUNT (0x800) +#define OTP_TOTAL_DWORD_COUNT (0x1000) + static uint64_t aspeed_sbc_read(void *opaque, hwaddr addr, unsigned int si= ze) { AspeedSBCState *s =3D ASPEED_SBC(opaque); @@ -57,6 +72,82 @@ static uint64_t aspeed_sbc_read(void *opaque, hwaddr add= r, unsigned int size) return s->regs[addr]; } =20 +static bool aspeed_sbc_otpmem_read(AspeedSBCState *s, + uint32_t otp_addr, Error **errp) +{ + MemTxResult ret; + AspeedSBCClass *sc =3D ASPEED_SBC_GET_CLASS(s); + AspeedOTPMemState *otp =3D ASPEED_OTPMEM(s->otpmem); + uint32_t value; + + if (sc->has_otpmem =3D=3D false) { + trace_aspeed_sbc_otpmem_state("disabled"); + return true; + } + ret =3D address_space_read(&otp->as, otp_addr, MEMTXATTRS_UNSPECIFIED, + &value, sizeof(value)); + if (ret !=3D 0) { + qemu_log_mask(LOG_GUEST_ERROR, "Failed to read OTP memory\n"); + return false; + } + s->regs[R_CAMP1] =3D value; + trace_aspeed_sbc_otp_read(otp_addr, value); + + return true; +} + +static bool aspeed_sbc_otpmem_prog(AspeedSBCState *s, + uint32_t otp_addr, Error **errp) +{ + AspeedSBCClass *sc =3D ASPEED_SBC_GET_CLASS(s); + AspeedOTPMemState *otp =3D ASPEED_OTPMEM(s->otpmem); + uint32_t value =3D 0x12345678; + + if (sc->has_otpmem =3D=3D false) { + trace_aspeed_sbc_otpmem_state("disabled"); + return true; + } + address_space_write(&otp->as, otp_addr, MEMTXATTRS_UNSPECIFIED, + &value, sizeof(value)); + trace_aspeed_sbc_otp_prog(otp_addr, value); + + return true; +} + +static void aspeed_sbc_handle_command(void *opaque, uint32_t cmd) +{ + AspeedSBCState *s =3D ASPEED_SBC(opaque); + Error *local_err =3D NULL; + bool ret =3D false; + uint32_t otp_addr; + + s->regs[R_STATUS] &=3D ~(OTP_MEM_IDLE | OTP_IDLE); + otp_addr =3D s->regs[R_ADDR]; + + switch (cmd) { + case SBC_OTP_CMD_READ: + ret =3D aspeed_sbc_otpmem_read(s, otp_addr, &local_err); + break; + case SBC_OTP_CMD_PROG: + ret =3D aspeed_sbc_otpmem_prog(s, otp_addr, &local_err); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Unknown command 0x%x\n", + __func__, cmd); + break; + } + + trace_aspeed_sbc_handle_cmd(cmd, otp_addr, ret); + if (ret =3D=3D false && local_err) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: %s\n", + __func__, error_get_pretty(local_err)); + error_free(local_err); + } + s->regs[R_STATUS] |=3D (OTP_MEM_IDLE | OTP_IDLE); +} + static void aspeed_sbc_write(void *opaque, hwaddr addr, uint64_t data, unsigned int size) { @@ -78,6 +169,9 @@ static void aspeed_sbc_write(void *opaque, hwaddr addr, = uint64_t data, "%s: write to read only register 0x%" HWADDR_PRIx "\= n", __func__, addr << 2); return; + case R_CMD: + aspeed_sbc_handle_command(opaque, data); + return; default: break; } @@ -115,15 +209,82 @@ static void aspeed_sbc_reset(DeviceState *dev) s->regs[R_QSR] =3D s->signing_settings; } =20 +static void aspeed_otp_machine_init_done_notify(Notifier *n, void *opaque) +{ + AspeedSBCState *s =3D container_of(n, AspeedSBCState, machine_done); + Object *machine =3D qdev_get_machine(); + Object *sbc =3D object_resolve_path("/machine/soc/sbc", NULL); + char *otpmem_drive =3D NULL; + Object *otp_dev =3D NULL; + Error *local_err =3D NULL; + char otp_path[128]; + + if (!sbc || !machine) { + error_report("Failed to resolve QOM paths"); + return; + } + + otpmem_drive =3D object_property_get_str(machine, "otpmem", &local_err= ); + if (local_err) { + qemu_log_mask(LOG_GUEST_ERROR, + "Failed to get otpmem property, %s\n", + error_get_pretty(local_err)); + error_free(local_err); + return; + } + if (strlen(otpmem_drive)) { + snprintf(otp_path, sizeof(otp_path), + "/machine/peripheral/%s", otpmem_drive); + otp_dev =3D object_resolve_path(otp_path, NULL); + if (otp_dev) { + object_property_add_alias(sbc, "otpmem", otp_dev, "drive"); + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "Failed to get otpmem object\n"); + } + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "otpmem-drive is not presented\n"); + error_free(local_err); + } + g_free(otpmem_drive); + + if (!otp_dev) { + s->otpmem =3D ASPEED_OTPMEM(object_new(TYPE_ASPEED_OTPMEM)); + object_initialize_child(OBJECT(s), "otp", s->otpmem, + TYPE_ASPEED_OTPMEM); + qdev_realize(DEVICE(s->otpmem), NULL, &local_err); + + if (local_err) { + qemu_log_mask(LOG_GUEST_ERROR, + "OTP memory realize is failed, err =3D %s\n", + error_get_pretty(local_err)); + error_free(local_err); + } + } else { + s->otpmem =3D ASPEED_OTPMEM(otp_dev); + } +} + static void aspeed_sbc_realize(DeviceState *dev, Error **errp) { AspeedSBCState *s =3D ASPEED_SBC(dev); SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + AspeedSBCClass *sc =3D ASPEED_SBC_GET_CLASS(s); =20 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sbc_ops, s, TYPE_ASPEED_SBC, 0x1000); =20 sysbus_init_mmio(sbd, &s->iomem); + + /* + * Blockdev backend is created later than realize stage, + * to associate SBC and OTP in a later stage. + */ + if (sc->has_otpmem) { + s->machine_done.notify =3D aspeed_otp_machine_init_done_notify; + qemu_add_machine_init_done_notifier(&s->machine_done); + } } =20 static const VMStateDescription vmstate_aspeed_sbc =3D { diff --git a/hw/misc/trace-events b/hw/misc/trace-events index e3f64c0ff6..0f6e2038cf 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -90,6 +90,13 @@ slavio_sysctrl_mem_readl(uint32_t ret) "Read system cont= rol 0x%08x" slavio_led_mem_writew(uint32_t val) "Write diagnostic LED 0x%04x" slavio_led_mem_readw(uint32_t ret) "Read diagnostic LED 0x%04x" =20 +# aspped_sbc.c +aspeed_sbc_otpmem_state(const char *enabled) "OTP Memory is %s" +aspeed_sbc_ignore_cmd(uint32_t cmd) "Ignoring command 0x%" PRIx32 +aspeed_sbc_handle_cmd(uint32_t cmd, uint32_t addr, bool ret) "Handling com= mand 0x%" PRIx32 " for OTP addr 0x%" PRIx32 " Result: %d" +aspeed_sbc_otp_read(uint32_t addr, uint32_t value) "OTP Memory read: addr = 0x%" PRIx32 " value 0x%" PRIx32 +aspeed_sbc_otp_prog(uint32_t addr, uint32_t value) "OTP Memory write: addr= 0x%" PRIx32 " value 0x%" PRIx32 + # aspeed_scu.c aspeed_scu_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" P= RIx64 " of size %u: 0x%" PRIx32 aspeed_scu_read(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PR= Ix64 " of size %u: 0x%" PRIx32 diff --git a/include/hw/misc/aspeed_sbc.h b/include/hw/misc/aspeed_sbc.h index 405e6782b9..858e82861b 100644 --- a/include/hw/misc/aspeed_sbc.h +++ b/include/hw/misc/aspeed_sbc.h @@ -10,6 +10,7 @@ #define ASPEED_SBC_H =20 #include "hw/sysbus.h" +#include "hw/misc/aspeed_otpmem.h" =20 #define TYPE_ASPEED_SBC "aspeed.sbc" #define TYPE_ASPEED_AST2600_SBC TYPE_ASPEED_SBC "-ast2600" @@ -30,16 +31,22 @@ OBJECT_DECLARE_TYPE(AspeedSBCState, AspeedSBCClass, ASP= EED_SBC) struct AspeedSBCState { SysBusDevice parent; =20 + Notifier machine_done; + bool emmc_abr; uint32_t signing_settings; =20 MemoryRegion iomem; =20 uint32_t regs[ASPEED_SBC_NR_REGS]; + + AspeedOTPMemState *otpmem; }; =20 struct AspeedSBCClass { SysBusDeviceClass parent_class; + + bool has_otpmem; }; =20 #endif /* ASPEED_SBC_H */ --=20 2.43.0 From nobody Sat Nov 15 14:53:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1750315331; cv=none; d=zohomail.com; s=zohoarc; b=bPjm6iSAfMiTAMvXfoWAHz1YoKUUr7riiAzHV6GBvQAA4E3947wh13hoDY5G9evpGT0aX46Ta0Fu0Q/Rb3PlJP5JolSg2nLCSJIgi8GrsU5HP5RK622jkG5AiL4Nbv3vXR0MaNHcUcX4MO9+nsREzQDtF+njeAp3qtg5/qDlfug= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750315331; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Thu, 19 Jun 2025 02:41:38 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 19 Jun 2025 14:41:16 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 19 Jun 2025 14:41:16 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [RFC v5 3/4] hw/arm: Integrate ASPEED OTP memory support into AST10x0 and AST2600 SoCs Date: Thu, 19 Jun 2025 14:41:12 +0800 Message-ID: <20250619064115.4182202-4-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250619064115.4182202-1-kane_chen@aspeedtech.com> References: <20250619064115.4182202-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1750315332501116600 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS This patch exposes a new "otpmem" machine parameter to allow users to attach an OTP memory device to AST1030 and AST2600-based platforms. The value of this parameter is passed as a QOM alias to the Secure Boot Controller (SBC), enabling binding to an aspeed.otpmem device created via -device. This allows emulation of secure boot flows that rely on fuse-based configuration stored in OTP memory. The has_otpmem attribute is enabled in the SBC subclasses for AST10x0 and AST2600 to control the presence of OTP support per SoC type. Users can preload a custom OTP memory image for boot-time behavior. For example: ```bash for i in $(seq 1 2048); do printf '\x00\x00\x00\x00\xff\xff\xff\xff' done > otpmem.img ``` Users can test OTP memory integration using the following command, which loads a file-backed OTP image into the emulated SoC: ```bash qemu-system-arm -machine ast2600-evb,otpmem=3Dotpmem-drive \ -blockdev driver=3Dfile,filename=3Dotpmem.img,node-name=3Dotpmem \ -device aspeed.otpmem,drive=3Dotpmem,id=3Dotpmem-drive \ ... ``` Signed-off-by: Kane-Chen-AS --- hw/arm/aspeed.c | 20 ++++++++++++++++++++ hw/arm/aspeed_ast10x0.c | 2 +- hw/arm/aspeed_ast2600.c | 2 +- hw/misc/aspeed_sbc.c | 18 ++++++++++++++++++ include/hw/misc/aspeed_sbc.h | 1 + 5 files changed, 41 insertions(+), 2 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index d0b333646e..734416c217 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -47,6 +47,7 @@ struct AspeedMachineState { uint32_t uart_chosen; char *fmc_model; char *spi_model; + char *otpmem; uint32_t hw_strap1; }; =20 @@ -1199,6 +1200,21 @@ static void aspeed_set_bmc_console(Object *obj, cons= t char *value, Error **errp) bmc->uart_chosen =3D val + ASPEED_DEV_UART0; } =20 +static char *aspeed_get_otpmem(Object *obj, Error **errp) +{ + AspeedMachineState *bmc =3D ASPEED_MACHINE(obj); + + return g_strdup(bmc->otpmem); +} + +static void aspeed_set_otpmem(Object *obj, const char *value, Error **errp) +{ + AspeedMachineState *bmc =3D ASPEED_MACHINE(obj); + + g_free(bmc->otpmem); + bmc->otpmem =3D g_strdup(value); +} + static void aspeed_machine_class_props_init(ObjectClass *oc) { object_class_property_add_bool(oc, "execute-in-place", @@ -1220,6 +1236,10 @@ static void aspeed_machine_class_props_init(ObjectCl= ass *oc) aspeed_set_spi_model); object_class_property_set_description(oc, "spi-model", "Change the SPI Flash model"); + object_class_property_add_str(oc, "otpmem", aspeed_get_otpmem, + aspeed_set_otpmem); + object_class_property_set_description(oc, "otpmem", + "Set OTP Memory Drive"); } =20 static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc) diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index e6e1ee63c1..c446e70b24 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -154,7 +154,7 @@ static void aspeed_soc_ast1030_init(Object *obj) =20 object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); =20 - object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC); + object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_AST10X0_SBC); =20 for (i =3D 0; i < sc->wdts_num; i++) { snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index d12707f0ab..59ffd41a4a 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -261,7 +261,7 @@ static void aspeed_soc_ast2600_init(Object *obj) =20 object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C); =20 - object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC); + object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_AST2600_SBC); =20 object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DE= VICE); object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DE= VICE); diff --git a/hw/misc/aspeed_sbc.c b/hw/misc/aspeed_sbc.c index 8e192e9496..38f6d2745e 100644 --- a/hw/misc/aspeed_sbc.c +++ b/hw/misc/aspeed_sbc.c @@ -323,8 +323,10 @@ static const TypeInfo aspeed_sbc_info =3D { static void aspeed_ast2600_sbc_class_init(ObjectClass *klass, const void *= data) { DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedSBCClass *sc =3D ASPEED_SBC_CLASS(klass); =20 dc->desc =3D "AST2600 Secure Boot Controller"; + sc->has_otpmem =3D true; } =20 static const TypeInfo aspeed_ast2600_sbc_info =3D { @@ -333,9 +335,25 @@ static const TypeInfo aspeed_ast2600_sbc_info =3D { .class_init =3D aspeed_ast2600_sbc_class_init, }; =20 +static void aspeed_ast10x0_sbc_class_init(ObjectClass *klass, const void *= data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedSBCClass *sc =3D ASPEED_SBC_CLASS(klass); + + dc->desc =3D "AST10X0 Secure Boot Controller"; + sc->has_otpmem =3D true; +} + +static const TypeInfo aspeed_ast10x0_sbc_info =3D { + .name =3D TYPE_ASPEED_AST10X0_SBC, + .parent =3D TYPE_ASPEED_SBC, + .class_init =3D aspeed_ast10x0_sbc_class_init, +}; + static void aspeed_sbc_register_types(void) { type_register_static(&aspeed_ast2600_sbc_info); + type_register_static(&aspeed_ast10x0_sbc_info); type_register_static(&aspeed_sbc_info); } =20 diff --git a/include/hw/misc/aspeed_sbc.h b/include/hw/misc/aspeed_sbc.h index 858e82861b..34ee949fad 100644 --- a/include/hw/misc/aspeed_sbc.h +++ b/include/hw/misc/aspeed_sbc.h @@ -14,6 +14,7 @@ =20 #define TYPE_ASPEED_SBC "aspeed.sbc" #define TYPE_ASPEED_AST2600_SBC TYPE_ASPEED_SBC "-ast2600" +#define TYPE_ASPEED_AST10X0_SBC TYPE_ASPEED_SBC "-ast10X0" OBJECT_DECLARE_TYPE(AspeedSBCState, AspeedSBCClass, ASPEED_SBC) =20 #define ASPEED_SBC_NR_REGS (0x93c >> 2) --=20 2.43.0 From nobody Sat Nov 15 14:53:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 19 Jun 2025 14:41:17 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 19 Jun 2025 14:41:17 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [RFC v5 4/4] tests/functional: Add integration tests for ASPEED OTP memory model Date: Thu, 19 Jun 2025 14:41:13 +0800 Message-ID: <20250619064115.4182202-5-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250619064115.4182202-1-kane_chen@aspeedtech.com> References: <20250619064115.4182202-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1750315402473116600 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS Introduce a functional test suite to validate the ASPEED OTP memory device integration under different machine configurations. The following cases are covered: - AST2600 with blockdev + device + machine parameter (full binding) - AST2600 fallback with no machine parameter - AST2600 with only blockdev + device (no machine param) - AST2600 with only machine parameter (no backend/device) - AST1030 fallback test with Zephyr-based image The tests ensure that the OTP model behaves correctly across boot-time binding variations and fallback paths, and that firmware boot is successful under each condition. Signed-off-by: Kane-Chen-AS --- tests/functional/meson.build | 1 + tests/functional/test_aspeed_otpmem.py | 82 ++++++++++++++++++++++++++ 2 files changed, 83 insertions(+) create mode 100644 tests/functional/test_aspeed_otpmem.py diff --git a/tests/functional/meson.build b/tests/functional/meson.build index e9f19d54a2..ce999eeab1 100644 --- a/tests/functional/meson.build +++ b/tests/functional/meson.build @@ -41,6 +41,7 @@ test_timeouts =3D { 'arm_replay' : 240, 'arm_tuxrun' : 240, 'arm_sx1' : 360, + 'aspeed_otpmem': 1200, 'intel_iommu': 300, 'mips_malta' : 480, 'mipsel_malta' : 420, diff --git a/tests/functional/test_aspeed_otpmem.py b/tests/functional/test= _aspeed_otpmem.py new file mode 100644 index 0000000000..67d2a7ecf6 --- /dev/null +++ b/tests/functional/test_aspeed_otpmem.py @@ -0,0 +1,82 @@ + +import os +import time +import tempfile +import subprocess + +from qemu_test import LinuxKernelTest, Asset +from aspeed import AspeedTest +from qemu_test import exec_command_and_wait_for_pattern, skipIfMissingComm= ands + +class AspeedOtpMemoryTest(AspeedTest): + # AST2600 SDK image + ASSET_SDK_V906_AST2600 =3D Asset( + 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.0= 6/ast2600-default-obmc.tar.gz', + '768d76e247896ad78c154b9cff4f766da2ce65f217d620b286a4a03a8a4f68f5') + + # AST1030 Zephyr image + ASSET_ZEPHYR_3_00 =3D Asset( + ('https://github.com/AspeedTech-BMC' + '/zephyr/releases/download/v00.03.00/ast1030-evb-demo.zip'), + '37fe3ecd4a1b9d620971a15b96492a81093435396eeac69b6f3e384262ff555f') + def generate_otpmem_image(self): + path =3D self.scratch_file("otpmem.img") + pattern =3D b'\x00\x00\x00\x00\xff\xff\xff\xff' * (16 * 1024 // 8) + with open(path, "wb") as f: + f.write(pattern) + return path + + def test_ast2600_otp_fallback(self): + image_path =3D self.archive_extract(self.ASSET_SDK_V906_AST2600) + bmc_image =3D self.scratch_file("ast2600-default", "image-bmc") + self.vm.set_machine("ast2600-evb") + self.vm.set_console() + self.do_test_arm_aspeed_sdk_start( + self.scratch_file("ast2600-default", "image-bmc")) + self.wait_for_console_pattern('ast2600-default login:') + + def test_ast2600_otp_blockdev_device(self): + image_path =3D self.archive_extract(self.ASSET_SDK_V906_AST2600) + otp_img =3D self.generate_otpmem_image() + self.vm.set_console() + self.vm.add_args( + "-blockdev", f"node-name=3Dotpmem,driver=3Dfile,filename=3D{ot= p_img}", + "-device", "aspeed.otpmem,drive=3Dotpmem,id=3Dotpmem-drive", + "-machine", "ast2600-evb,otpmem=3Dotpmem-drive" + ) + self.do_test_arm_aspeed_sdk_start(self.scratch_file("ast2600-defau= lt", "image-bmc")) + self.wait_for_console_pattern("ast2600-default login:") + + def test_ast2600_otp_only_blockdev(self): + image_path =3D self.archive_extract(self.ASSET_SDK_V906_AST2600) + otp_img =3D self.generate_otpmem_image() + self.vm.set_machine("ast2600-evb") + self.vm.set_console() + self.vm.add_args( + "-blockdev", f"node-name=3Dotpmem,driver=3Dfile,filename=3D{ot= p_img}", + "-device", "aspeed.otpmem,drive=3Dotpmem,id=3Dotpmem-drive", + ) + self.do_test_arm_aspeed_sdk_start(self.scratch_file("ast2600-defau= lt", "image-bmc")) + self.wait_for_console_pattern("ast2600-default login:") + + def test_ast2600_otp_only_machine_param(self): + image_path =3D self.archive_extract(self.ASSET_SDK_V906_AST2600) + self.vm.set_console() + self.vm.add_args( + "-machine", "ast2600-evb,otpmem=3Dotpmem-drive" + ) + self.do_test_arm_aspeed_sdk_start(self.scratch_file("ast2600-defau= lt", "image-bmc")) + self.wait_for_console_pattern("ast2600-default login:") + + def test_ast1030_otp_fallback(self): + kernel_name =3D "ast1030-evb-demo/zephyr.elf" + kernel_file =3D self.archive_extract(self.ASSET_ZEPHYR_3_00, membe= r=3Dkernel_name) + + self.vm.set_machine("ast1030-evb") + self.vm.set_console() + self.vm.add_args("-kernel", kernel_file) + self.vm.launch() + self.wait_for_console_pattern("Booting Zephyr OS") + +if __name__ =3D=3D '__main__': + AspeedTest.main() \ No newline at end of file --=20 2.43.0