From nobody Sat Nov 15 14:52:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1750310634; cv=none; d=zohomail.com; s=zohoarc; b=MpTrERT48T6OlO6I2rcRrL89gtl1iqvyGbwNC/sgrJMsqmqy1mBPaNUutXoDm9Oy8ZN4ZmHlXG2rel7KGPpPUP8gMt7UpGe4CBU757RZACi6g97X9PktjpnHtONLlJh7BbVLiXl5KLuFb15TbpvrpEOuS2nAg/mcdYvkNUUR/J4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750310634; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=YoWgkZAM1/K4+mucpLsdn7PsOAaPfqrp2PmMNTBms14=; b=Esp0BuqqE3O6EQrY5keXSZouEv+wQ88Xskd+GjWYbLsCLTdrL3qsMCFE3MCBJKo3RIm3Tyw4zTXCKc2rXoZ0AvgHax5WQtwiS8vSVcxlez7sQD/7rRgE0D2Mf5TlxVe/HrdnQ3qrytFai4+CHoojkBZ4N3w+9d5TkFZwdOBIbzA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750310634396377.31903892491243; Wed, 18 Jun 2025 22:23:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uS7il-0003J5-5g; Thu, 19 Jun 2025 01:21:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uS1qu-0006pH-SQ for qemu-devel@nongnu.org; Wed, 18 Jun 2025 19:05:56 -0400 Received: from mail-io1-xd2a.google.com ([2607:f8b0:4864:20::d2a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uS1qr-00063n-MZ for qemu-devel@nongnu.org; Wed, 18 Jun 2025 19:05:56 -0400 Received: by mail-io1-xd2a.google.com with SMTP id ca18e2360f4ac-875f28fde67so12312739f.1 for ; Wed, 18 Jun 2025 16:05:53 -0700 (PDT) Received: from user-jcksn.hsd1.mi.comcast.net ([2601:401:101:1070:b57:773f:14d7:807b]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-50149b9df11sm3036915173.54.2025.06.18.16.05.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jun 2025 16:05:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1750287952; x=1750892752; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YoWgkZAM1/K4+mucpLsdn7PsOAaPfqrp2PmMNTBms14=; b=bqHr9lxfkcz/22K8yh6ecdU2hmXzxlfhuj6BnbKbAP7gaIJWcXIoAUw90Nijxs0mTk bLrMgS2qyEvSXqAXZ10DuGSvtCSU+UWeor0t3e0pEsnn9UWRqkPeFl3OW+pj0n43J+rb ArNqlTl0xz09/cwN93HJH7I0PzW59/lwvc/6kFhvjPIIRQxQtXizO5mF4ZtFdpJuSvIP IQHT1uMfJqQTPFFSpQMqwfP0lyyEh4gMn4C8V45LSOZZ40zrEfYh/7M5v7AZCeTuEjSN NBd38i9xF+FfPfOLflRi81sP6DOfFZiBoJC+1JunYwNkIw5p9s54rvYQAa4dYeTqDivf rjwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750287952; x=1750892752; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YoWgkZAM1/K4+mucpLsdn7PsOAaPfqrp2PmMNTBms14=; b=QZtU1BJMcmMixJVJywUOgtP3iQMNYtAhctXUwzKpQxofkk29NOiayWuLupfGYC8fCX qHfDVwI8yOtgTwXO8ENdGmLKkfgqP5sko2moQt7P2rNZ/+JZo47EaD2vicX6H5acoEl4 b3CBsSnI4q9bLTonvz2jBQ0qgVJz34cvMdPZNVLZUE1qa58xKWxDzethQRo11UQWvqTq IxyQcx5/EaF3mbXDiAAHxGFf6vz2G+a8wrrOHn9yn7OaEll5LzoKtGH5pqlIJ5YEkLdc 702eLiT46clbP8O5gCiVr87NdCFYYyE+8T3YwXTGu2PqU5Yv8NN9eNhJbdSULSg38bmo ie3w== X-Gm-Message-State: AOJu0Yz9eVIi8u3AtPj9JtueryEvuv9OpMkbdC4mggtYArjNzPZ4n+WL EMfKj+VHEHG5an+Q1j8ElkPqnkaTGL8X1hf0Rl0MLxSnApXgA7+YS3d13iharBL6vfk= X-Gm-Gg: ASbGncvIl0rDsCPcEhWXRxFaKelvzbWewanbck6vk+xQ/X/8TSQEp4br6wXUZiFcrGS oL516vg/y6AwvB38JCUKonhdGhxHlwZimH1sK/IMXQQV/QUO3eX+E53r/kaa6s6ynAg3W8U1tKZ S4nlypz+TNVQQA6aGC25rHJovae9Set8jLbhGrWtDoru4HE6sYXLKMNJ2VUh9EwriDGb/tp28Yw zITke8T+P9dJ/zAv/A2rf/W+oNviklsZLTlpAIJ86lSSoMM60Qqe9jrRJWnuMLY/d+uDIrTiIK8 zxvfJz9iVsIiCxHS/UvU5jL4DTGlmoQpfl14RM60BfVyq60WJfNCA+GB9wAMcRzIRu+A/KFiP6b NElYP5mxBxW6v25k= X-Google-Smtp-Source: AGHT+IFfzX7tTnCmRsiCX7F/hPrtAuSOPcEX/dGog8Mq1PV2mmJdGGStAWNfXxCZpQivZrn+2CxmQg== X-Received: by 2002:a05:6602:148e:b0:86c:ec82:c7d7 with SMTP id ca18e2360f4ac-875ded369aemr2372184039f.1.1750287951683; Wed, 18 Jun 2025 16:05:51 -0700 (PDT) From: Jackson Donaldson X-Google-Original-From: Jackson Donaldson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH v2 01/11] MAX78000: Add MAX78000FTHR Machine Date: Wed, 18 Jun 2025 19:05:39 -0400 Message-Id: <20250618230549.3351152-2-jcksn@duck.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250618230549.3351152-1-jcksn@duck.com> References: <20250618230549.3351152-1-jcksn@duck.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::d2a; envelope-from=jackson88044@gmail.com; helo=mail-io1-xd2a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 19 Jun 2025 01:21:41 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1750310636840116600 Content-Type: text/plain; charset="utf-8" This patch adds support for the MAX78000FTHR machine. The MAX78000FTHR contains a MAX78000 and a RISC-V core. This patch implements only the MAX78000, which is Cortex-M4 based. Details can be found at: https://www.analog.com/media/en/technical-documentation/user-guides/max7800= 0-user-guide.pdf Signed-off-by: Jackson Donaldson Reviewed-by: Peter Maydell --- hw/arm/Kconfig | 10 ++ hw/arm/max78000_soc.c | 172 ++++++++++++++++++++++++++++++++++ hw/arm/max78000fthr.c | 50 ++++++++++ hw/arm/meson.build | 2 + include/hw/arm/max78000_soc.h | 35 +++++++ 5 files changed, 269 insertions(+) create mode 100644 hw/arm/max78000_soc.c create mode 100644 hw/arm/max78000fthr.c create mode 100644 include/hw/arm/max78000_soc.h diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index f543d944c3..ddaafa8faa 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -95,6 +95,12 @@ config INTEGRATOR select PL181 # display select SMC91C111 =20 +config MAX78000FTHR + bool + default y + depends on TCG && ARM + select MAX78000_SOC + config MPS3R bool default y @@ -357,6 +363,10 @@ config ALLWINNER_R40 select USB_EHCI_SYSBUS select SD =20 +config MAX78000_SOC + bool + select ARM_V7M + config RASPI bool default y diff --git a/hw/arm/max78000_soc.c b/hw/arm/max78000_soc.c new file mode 100644 index 0000000000..9676ada6a2 --- /dev/null +++ b/hw/arm/max78000_soc.c @@ -0,0 +1,172 @@ +/* + * MAX78000 SOC + * + * Copyright (c) 2025 Jackson Donaldson + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * Implementation based on stm32f205 and Max78000 user guide at + * https://www.analog.com/media/en/technical-documentation/user-guides/max= 78000-user-guide.pdf + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "system/address-spaces.h" +#include "system/system.h" +#include "hw/arm/max78000_soc.h" +#include "hw/qdev-clock.h" +#include "hw/misc/unimp.h" + +static void max78000_soc_initfn(Object *obj) +{ + MAX78000State *s =3D MAX78000_SOC(obj); + + object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); + + s->sysclk =3D qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); +} + +static void max78000_soc_realize(DeviceState *dev_soc, Error **errp) +{ + MAX78000State *s =3D MAX78000_SOC(dev_soc); + MemoryRegion *system_memory =3D get_system_memory(); + DeviceState *armv7m; + Error *err =3D NULL; + + if (!clock_has_source(s->sysclk)) { + error_setg(errp, "sysclk clock must be wired up by the board code"= ); + return; + } + + memory_region_init_rom(&s->flash, OBJECT(dev_soc), "MAX78000.flash", + FLASH_SIZE, &err); + if (err !=3D NULL) { + error_propagate(errp, err); + return; + } + + memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->fla= sh); + + memory_region_init_ram(&s->sram, NULL, "MAX78000.sram", SRAM_SIZE, + &err); + if (err !=3D NULL) { + error_propagate(errp, err); + return; + } + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram= ); + + armv7m =3D DEVICE(&s->armv7m); + + /* + * The MAX78000 user guide's Interrupt Vector Table section + * suggests that there are 120 IRQs in the text, while only listing + * 104 in table 5-1. Implement the more generous of the two. + * This has not been tested in hardware. + */ + qdev_prop_set_uint32(armv7m, "num-irq", 120); + qdev_prop_set_uint8(armv7m, "num-prio-bits", 3); + qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"= )); + qdev_prop_set_bit(armv7m, "enable-bitband", true); + qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); + object_property_set_link(OBJECT(&s->armv7m), "memory", + OBJECT(system_memory), &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) { + return; + } + + create_unimplemented_device("globalControl", 0x40000000, 0x400); + create_unimplemented_device("systemInterface", 0x40000400, 0x400); + create_unimplemented_device("functionControl", 0x40000800, 0x400); + create_unimplemented_device("watchdogTimer0", 0x40003000, 0x400); + create_unimplemented_device("dynamicVoltScale", 0x40003c00, 0x40); + create_unimplemented_device("SIMO", 0x40004400, 0x400); + create_unimplemented_device("trimSystemInit", 0x40005400, 0x400); + create_unimplemented_device("generalCtrlFunc", 0x40005800, 0x400); + create_unimplemented_device("wakeupTimer", 0x40006400, 0x400); + create_unimplemented_device("powerSequencer", 0x40006800, 0x400); + create_unimplemented_device("miscControl", 0x40006c00, 0x400); + + create_unimplemented_device("aes", 0x40007400, 0x400); + create_unimplemented_device("aesKey", 0x40007800, 0x400); + + create_unimplemented_device("gpio0", 0x40008000, 0x1000= ); + create_unimplemented_device("gpio1", 0x40009000, 0x1000= ); + + create_unimplemented_device("parallelCamInterface", 0x4000e000, 0x1000= ); + create_unimplemented_device("CRC", 0x4000f000, 0x1000= ); + + create_unimplemented_device("timer0", 0x40010000, 0x1000= ); + create_unimplemented_device("timer1", 0x40011000, 0x1000= ); + create_unimplemented_device("timer2", 0x40012000, 0x1000= ); + create_unimplemented_device("timer3", 0x40013000, 0x1000= ); + + create_unimplemented_device("i2c0", 0x4001d000, 0x1000= ); + create_unimplemented_device("i2c1", 0x4001e000, 0x1000= ); + create_unimplemented_device("i2c2", 0x4001f000, 0x1000= ); + + create_unimplemented_device("standardDMA", 0x40028000, 0x1000= ); + create_unimplemented_device("flashController0", 0x40029000, 0x400); + + create_unimplemented_device("icc0", 0x4002a000, 0x800); + create_unimplemented_device("icc1", 0x4002a800, 0x800); + + create_unimplemented_device("adc", 0x40034000, 0x1000= ); + create_unimplemented_device("pulseTrainEngine", 0x4003c000, 0xa0); + create_unimplemented_device("oneWireMaster", 0x4003d000, 0x1000= ); + create_unimplemented_device("semaphore", 0x4003e000, 0x1000= ); + + create_unimplemented_device("uart0", 0x40042000, 0x1000= ); + create_unimplemented_device("uart1", 0x40043000, 0x1000= ); + create_unimplemented_device("uart2", 0x40044000, 0x1000= ); + + create_unimplemented_device("spi1", 0x40046000, 0x2000= ); + create_unimplemented_device("trng", 0x4004d000, 0x1000= ); + create_unimplemented_device("i2s", 0x40060000, 0x1000= ); + create_unimplemented_device("lowPowerControl", 0x40080000, 0x400); + create_unimplemented_device("gpio2", 0x40080400, 0x200); + create_unimplemented_device("lowPowerWatchdogTimer", 0x40080800, 0x= 400); + create_unimplemented_device("lowPowerTimer4", 0x40080c00, 0x400); + + create_unimplemented_device("lowPowerTimer5", 0x40081000, 0x400); + create_unimplemented_device("lowPowerUART0", 0x40081400, 0x400); + create_unimplemented_device("lowPowerComparator", 0x40088000, 0x400); + + create_unimplemented_device("spi0", 0x400be000, 0x400); + + /* + * The MAX78000 user guide's base address map lists the CNN TX FIFO as + * beginning at 0x400c0400 and ending at 0x400c0400. Given that CNN_FI= FO + * is listed as having data accessible up to offset 0x1000, the user + * guide is likely incorrect. + */ + create_unimplemented_device("cnnTxFIFO", 0x400c0400, 0x2000= ); + + create_unimplemented_device("cnnGlobalControl", 0x50000000, 0x1000= 0); + create_unimplemented_device("cnnx16quad0", 0x50100000, 0x4000= 0); + create_unimplemented_device("cnnx16quad1", 0x50500000, 0x4000= 0); + create_unimplemented_device("cnnx16quad2", 0x50900000, 0x4000= 0); + create_unimplemented_device("cnnx16quad3", 0x50d00000, 0x4000= 0); + +} + +static void max78000_soc_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D max78000_soc_realize; +} + +static const TypeInfo max78000_soc_info =3D { + .name =3D TYPE_MAX78000_SOC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(MAX78000State), + .instance_init =3D max78000_soc_initfn, + .class_init =3D max78000_soc_class_init, +}; + +static void max78000_soc_types(void) +{ + type_register_static(&max78000_soc_info); +} + +type_init(max78000_soc_types) diff --git a/hw/arm/max78000fthr.c b/hw/arm/max78000fthr.c new file mode 100644 index 0000000000..c4f6b5b1b0 --- /dev/null +++ b/hw/arm/max78000fthr.c @@ -0,0 +1,50 @@ +/* + * MAX78000FTHR Evaluation Board + * + * Copyright (c) 2025 Jackson Donaldson + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/boards.h" +#include "hw/qdev-properties.h" +#include "hw/qdev-clock.h" +#include "qemu/error-report.h" +#include "hw/arm/max78000_soc.h" +#include "hw/arm/boot.h" + +/* 60MHz is the default, but other clocks can be selected. */ +#define SYSCLK_FRQ 60000000ULL +static void max78000_init(MachineState *machine) +{ + DeviceState *dev; + Clock *sysclk; + + sysclk =3D clock_new(OBJECT(machine), "SYSCLK"); + clock_set_hz(sysclk, SYSCLK_FRQ); + + dev =3D qdev_new(TYPE_MAX78000_SOC); + object_property_add_child(OBJECT(machine), "soc", OBJECT(dev)); + qdev_connect_clock_in(dev, "sysclk", sysclk); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + + armv7m_load_kernel(ARM_CPU(first_cpu), + machine->kernel_filename, + 0x00000000, FLASH_SIZE); +} + +static void max78000_machine_init(MachineClass *mc) +{ + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-m4"), + NULL + }; + + mc->desc =3D "MAX78000FTHR Board (Cortex-M4 / (Unimplemented) RISC-V)"; + mc->init =3D max78000_init; + mc->valid_cpu_types =3D valid_cpu_types; +} + +DEFINE_MACHINE("max78000fthr", max78000_machine_init) diff --git a/hw/arm/meson.build b/hw/arm/meson.build index d90be8f4c9..dc68391305 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -27,6 +27,7 @@ arm_common_ss.add(when: 'CONFIG_OMAP', if_true: files('om= ap1.c')) arm_common_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-= a10.c', 'cubieboard.c')) arm_common_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h= 3.c', 'orangepi.c')) arm_common_ss.add(when: 'CONFIG_ALLWINNER_R40', if_true: files('allwinner-= r40.c', 'bananapi_m2u.c')) +arm_common_ss.add(when: 'CONFIG_MAX78000_SOC', if_true: files('max78000_so= c.c')) arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2836.c', 'raspi.c')) arm_common_ss.add(when: ['CONFIG_RASPI', 'TARGET_AARCH64'], if_true: files= ('bcm2838.c', 'raspi4b.c')) arm_common_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_= soc.c')) @@ -71,6 +72,7 @@ arm_ss.add(when: 'CONFIG_XEN', if_true: files( arm_common_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmu-common.c= ')) arm_common_ss.add(when: 'CONFIG_COLLIE', if_true: files('collie.c')) arm_common_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4_boards.c= ')) +arm_common_ss.add(when: 'CONFIG_MAX78000FTHR', if_true: files('max78000fth= r.c')) arm_common_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c')) arm_common_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripheral= s.c')) arm_common_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2838_peripheral= s.c')) diff --git a/include/hw/arm/max78000_soc.h b/include/hw/arm/max78000_soc.h new file mode 100644 index 0000000000..97bf4099c9 --- /dev/null +++ b/include/hw/arm/max78000_soc.h @@ -0,0 +1,35 @@ +/* + * MAX78000 SOC + * + * Copyright (c) 2025 Jackson Donaldson + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_ARM_MAX78000_SOC_H +#define HW_ARM_MAX78000_SOC_H + +#include "hw/or-irq.h" +#include "hw/arm/armv7m.h" +#include "qom/object.h" + +#define TYPE_MAX78000_SOC "max78000-soc" +OBJECT_DECLARE_SIMPLE_TYPE(MAX78000State, MAX78000_SOC) + +#define FLASH_BASE_ADDRESS 0x10000000 +#define FLASH_SIZE (512 * 1024) +#define SRAM_BASE_ADDRESS 0x20000000 +#define SRAM_SIZE (128 * 1024) + +struct MAX78000State { + SysBusDevice parent_obj; + + ARMv7MState armv7m; + + MemoryRegion sram; + MemoryRegion flash; + + Clock *sysclk; +}; + +#endif --=20 2.34.1 From nobody Sat Nov 15 14:52:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1750310537; cv=none; d=zohomail.com; s=zohoarc; b=TsbGck+nwqVHCkaYtEV53y9K1XSH62ifYyp+rGuP8PcUFKrf0Kv08d0eZQdg9mURqiOfD7Tz2nQmT2SQ8Dxd6Q1Ooukp+4AlVxWKqgayrZqGr1CTEPhdldGGpSvkqMT3ylY2SSa9uVZD1LCCUc6oNibfQbRqaE/f9+Fy+XrlZzE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750310537; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=T4cdcAxYkzBW0Nm+D7J/VR1WzZ/Z2l4FEYQJF9yL5r4=; b=h8ok5a02n2MfEl2tC6tgd6L7KCjXJJg95Rro7DpwTn4g6vMknyFdzI5wUAgCp1E4ytaKz8+eIPhd4edBSt/0YO/ygDAQmwykNeM9MmnAU4EBo3yf7mWj6v4OuslDIoQghDbtZo+0JTFyiOEW0i8w4/54m7pWPKIvOkHwiX5BNns= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750310537320403.16363858802345; Wed, 18 Jun 2025 22:22:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uS7ib-0003HK-3v; Thu, 19 Jun 2025 01:21:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uS1qu-0006oz-Aj for qemu-devel@nongnu.org; Wed, 18 Jun 2025 19:05:56 -0400 Received: from mail-il1-x12d.google.com ([2607:f8b0:4864:20::12d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uS1qs-00063u-De for qemu-devel@nongnu.org; Wed, 18 Jun 2025 19:05:56 -0400 Received: by mail-il1-x12d.google.com with SMTP id e9e14a558f8ab-3de18fdeab0so2052565ab.3 for ; Wed, 18 Jun 2025 16:05:53 -0700 (PDT) Received: from user-jcksn.hsd1.mi.comcast.net ([2601:401:101:1070:b57:773f:14d7:807b]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-50149b9df11sm3036915173.54.2025.06.18.16.05.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jun 2025 16:05:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1750287953; x=1750892753; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=T4cdcAxYkzBW0Nm+D7J/VR1WzZ/Z2l4FEYQJF9yL5r4=; b=FZli17xAsWgoH+770Fy3+XB2mDMW/JjpqmF0WddzsvWSKYRGsKVD1TepW2Lrf+v9NE Z4rZsWNRaprtHqlmqFsDUxLg2RWQFbJ0f46aoUNtC4vKze4pGBFHpSxaRmNo7yR6dzgv QklWzXYKFB2/KIaRZDyerZ4LqcOBFqwOXCu1orW2/ekWe8qfmWqlzDiSY3ndjsYNSJi0 aRty1zo+cGcMt4pvcpw7gxetpATL9ICzlS7ZqY0OM9eELDGaEYQkvlfOJyC7IBrzw0/b 4i9haN6eHqMagR495w/bYiSySTzv8vYkD7Pkj/eJUZ6+nyVjFUPuUBXRfTwSU7rHCv5n 8fIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750287953; x=1750892753; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=T4cdcAxYkzBW0Nm+D7J/VR1WzZ/Z2l4FEYQJF9yL5r4=; b=SEtY9VQcUXjtfQTF+xObPRMJXhonR6jQiYey/Qb8Bd1DMVdbSCDIaow5Og1YSNunP3 nCZOuEhKMRCJGBZq6x50qJL7eVZQXqzmkakKFfeyGayKVSNS+7rWX7YqUhj3YRbeKRdk Z65cZskgnC7VPSbap9Fp87Oy1wVZ/H0uqNOtS3LvO2x++blzHecnwm2p3lFIlywOUJc7 osHQWJAIlkBhmnD8bGsy+T/WqLGp2r/m8EtpT96jDRuQTwyxrqXp4smAEubGajDUH5La eFmjx9kwHMTWv7iNLEhG212R72zRAndi9OdMImdqG5cBhIBkZJWBDXtOCErIbhos6PcU GhRA== X-Gm-Message-State: AOJu0Yw5KL+p6LFs5J9Y7X2ZBTFt+1Na9JkBPh1T4iGtRn6xgiYnI562 Q1kHPYHA/Go7/7vdG9GCjLW91YVBYjH9JjKqDMy3ajIrXRpg9i8HupGygL2SCOxiUBs= X-Gm-Gg: ASbGncsY+9nYu3VZt77FFfkQrxbApvtx/jwNRgSbWAvgRJ9gzPCzQpNINXip20JyQRq 7rIClUfl0uBPY0V6bCfu0tZK++j1Sg+2uOjHkfiQuJoq41x12FCgh82pBOf/gZERNO2YLp3zW8s sn0WYfyQUPG0UmBdm82BCzDAMVUeHef8modehpY+nQZlBH8Y3D0p/L0sDKOCrsmOS3b+TaiP7gS 5ou3qItPUKMrnE2K7A+JGsR7HrkLeRXxnMDaDHpzG4BJHsRxQs2KWvtNZ4qwllJelUmkd/GfBr3 Q4Yk0OMPhCItHpAUy9RCehxraOMaqWbOmRNcOAn8vfz0dc7SHG63l+xcTYeDNjbkVIOsoLrd1Rw 2E39M X-Google-Smtp-Source: AGHT+IEE4L6upZ7X3X7yYH8WirhfCgSJg/kyCMEXX/OfIHVrRAVKbafxHOpp1b+zq/FwuXGCp/s8Ww== X-Received: by 2002:a92:ca4e:0:b0:3dd:b762:ed1d with SMTP id e9e14a558f8ab-3de07cb669amr200955375ab.14.1750287952697; Wed, 18 Jun 2025 16:05:52 -0700 (PDT) From: Jackson Donaldson X-Google-Original-From: Jackson Donaldson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH v2 02/11] MAX78000: ICC Implementation Date: Wed, 18 Jun 2025 19:05:40 -0400 Message-Id: <20250618230549.3351152-3-jcksn@duck.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250618230549.3351152-1-jcksn@duck.com> References: <20250618230549.3351152-1-jcksn@duck.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::12d; envelope-from=jackson88044@gmail.com; helo=mail-il1-x12d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 19 Jun 2025 01:21:38 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1750310539755116600 Content-Type: text/plain; charset="utf-8" This commit implements the Instruction Cache Controller for the MAX78000 Signed-off-by: Jackson Donaldson Reviewed-by: Peter Maydell --- hw/arm/Kconfig | 1 + hw/misc/Kconfig | 3 + hw/misc/max78000_icc.c | 120 +++++++++++++++++++++++++++++++++ hw/misc/meson.build | 1 + include/hw/misc/max78000_icc.h | 33 +++++++++ 5 files changed, 158 insertions(+) create mode 100644 hw/misc/max78000_icc.c create mode 100644 include/hw/misc/max78000_icc.h diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index ddaafa8faa..e3b419b468 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -366,6 +366,7 @@ config ALLWINNER_R40 config MAX78000_SOC bool select ARM_V7M + select MAX78000_ICC =20 config RASPI bool diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index ec0fa5aa9f..781bcf74cc 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -47,6 +47,9 @@ config A9SCU config ARM11SCU bool =20 +config MAX78000_ICC + bool + config MOS6522 bool =20 diff --git a/hw/misc/max78000_icc.c b/hw/misc/max78000_icc.c new file mode 100644 index 0000000000..6f7d2b20bf --- /dev/null +++ b/hw/misc/max78000_icc.c @@ -0,0 +1,120 @@ +/* + * MAX78000 Instruction Cache + * + * Copyright (c) 2025 Jackson Donaldson + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "trace.h" +#include "hw/irq.h" +#include "migration/vmstate.h" +#include "hw/misc/max78000_icc.h" + + +static uint64_t max78000_icc_read(void *opaque, hwaddr addr, + unsigned int size) +{ + Max78000IccState *s =3D opaque; + switch (addr) { + case ICC_INFO: + return s->info; + + case ICC_SZ: + return s->sz; + + case ICC_CTRL: + return s->ctrl; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%" HWADDR_PRIx "\n", + __func__, addr); + return 0; + + } +} + +static void max78000_icc_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + Max78000IccState *s =3D opaque; + + switch (addr) { + case ICC_CTRL: + s->ctrl =3D 0x10000 | (val64 & 1); + break; + + case ICC_INVALIDATE: + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%" HWADDR_PRIx "\n", + __func__, addr); + break; + } +} + +static const MemoryRegionOps max78000_icc_ops =3D { + .read =3D max78000_icc_read, + .write =3D max78000_icc_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, +}; + +static const VMStateDescription max78000_icc_vmstate =3D { + .name =3D TYPE_MAX78000_ICC, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT32(info, Max78000IccState), + VMSTATE_UINT32(sz, Max78000IccState), + VMSTATE_UINT32(ctrl, Max78000IccState), + VMSTATE_END_OF_LIST() + } +}; + +static void max78000_icc_reset_hold(Object *obj, ResetType type) +{ + Max78000IccState *s =3D MAX78000_ICC(obj); + s->info =3D 0; + s->sz =3D 0x10000010; + s->ctrl =3D 0x10000; +} + +static void max78000_icc_init(Object *obj) +{ + Max78000IccState *s =3D MAX78000_ICC(obj); + + memory_region_init_io(&s->mmio, obj, &max78000_icc_ops, s, + TYPE_MAX78000_ICC, 0x800); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); +} + +static void max78000_icc_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + rc->phases.hold =3D max78000_icc_reset_hold; + dc->vmsd =3D &max78000_icc_vmstate; +} + +static const TypeInfo max78000_icc_info =3D { + .name =3D TYPE_MAX78000_ICC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(Max78000IccState), + .instance_init =3D max78000_icc_init, + .class_init =3D max78000_icc_class_init, +}; + +static void max78000_icc_register_types(void) +{ + type_register_static(&max78000_icc_info); +} + +type_init(max78000_icc_register_types) diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 6d47de482c..a21a994ff8 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -70,6 +70,7 @@ system_ss.add(when: 'CONFIG_IMX', if_true: files( 'imx_ccm.c', 'imx_rngc.c', )) +system_ss.add(when: 'CONFIG_MAX78000_ICC', if_true: files('max78000_icc.c'= )) system_ss.add(when: 'CONFIG_NPCM7XX', if_true: files( 'npcm_clk.c', 'npcm_gcr.c', diff --git a/include/hw/misc/max78000_icc.h b/include/hw/misc/max78000_icc.h new file mode 100644 index 0000000000..6fe2bb7a15 --- /dev/null +++ b/include/hw/misc/max78000_icc.h @@ -0,0 +1,33 @@ +/* + * MAX78000 Instruction Cache + * + * Copyright (c) 2025 Jackson Donaldson + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_MAX78000_ICC_H +#define HW_MAX78000_ICC_H + +#include "hw/sysbus.h" +#include "qom/object.h" + +#define TYPE_MAX78000_ICC "max78000-icc" +OBJECT_DECLARE_SIMPLE_TYPE(Max78000IccState, MAX78000_ICC) + +#define ICC_INFO 0x0 +#define ICC_SZ 0x4 +#define ICC_CTRL 0x100 +#define ICC_INVALIDATE 0x700 + +struct Max78000IccState { + SysBusDevice parent_obj; + + MemoryRegion mmio; + + uint32_t info; + uint32_t sz; + uint32_t ctrl; +}; + +#endif --=20 2.34.1 From nobody Sat Nov 15 14:52:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1750310558; cv=none; d=zohomail.com; s=zohoarc; b=SBE7utSgs7WMJbmLrPXhv2/ENlm3IOA3P+M14UoCDP7kkNxcQD8sG8t5Ve2AdoibLvQ7a/NZ1FZDMWq8dJTX+yFlChpjgweIwHjUJhFVECx6UNX1Sgl0f7c6LueAeDK0DFfmYHBFDf7v1bdiXlHQsMbr8d2kTsWBiILVKagw2dk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750310558; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=w5uB+PMcq729M/d0Xq5PyNGVe7AuOqs5CggiPdWCmOo=; b=mElpBRZjShFD1yTGUcYrDCkjCePMls3BmTgYMRI1cebA/J0fSM3J0/eMT1IFq4hxAcaJAslswAhugv6WDlajkyJM5HFRzSWKPMdL08+0fI9eOKTfnePlH7OqTNt0XceFBbBRhcMSk2J2Dd7VxTatZwd1EtKNz2U0Ba2vtKeFkas= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750310558291551.8711932030301; Wed, 18 Jun 2025 22:22:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uS7ib-0003HL-CX; Thu, 19 Jun 2025 01:21:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uS1r2-0006r4-58 for qemu-devel@nongnu.org; Wed, 18 Jun 2025 19:06:04 -0400 Received: from mail-io1-xd31.google.com ([2607:f8b0:4864:20::d31]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uS1r0-00065C-AR for qemu-devel@nongnu.org; Wed, 18 Jun 2025 19:06:03 -0400 Received: by mail-io1-xd31.google.com with SMTP id ca18e2360f4ac-86d0bd7ebb5so4819839f.0 for ; Wed, 18 Jun 2025 16:06:01 -0700 (PDT) Received: from user-jcksn.hsd1.mi.comcast.net ([2601:401:101:1070:b57:773f:14d7:807b]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-50149b9df11sm3036915173.54.2025.06.18.16.05.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jun 2025 16:06:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1750287961; x=1750892761; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=w5uB+PMcq729M/d0Xq5PyNGVe7AuOqs5CggiPdWCmOo=; b=TWmT5wx07LoeBLABKoNU7PyyZWUIUFRtGcH7oo5C7PRrcHCSMlrBkf0L/GNn/RpJ4r CnZLV6WNgg0PS1i7edyeU8MV0EetWxkARCEmOv+QQzOn1fXlhqhcu8s5TCKkkkP0MX6/ a81QIZTRMCehbNgSa2TGCOnrt6vjeQ7MqsetdorCmma7NRpbZpuQrfgM/vgyTvKlI34X Mk853M70mwYCELN7DvgHk3/mi5w6hDI3mxwqcIdta4T9JEc5xlqJ1+0QK0HawrsE9U5s as8rg+TDgPMbOJmpyHsblOjkG2+2xB+L4fZliwafbKMu+kIXllDZPCCxLWUCI6WJgAMh SV6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750287961; x=1750892761; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=w5uB+PMcq729M/d0Xq5PyNGVe7AuOqs5CggiPdWCmOo=; b=NP1MJtMg694M/EYJ0jpU5qpIZRzoC1IWij/eyw2X1M60KbFOhGjnaroCNejhIFYRki EP2FyGC38Vx44K/UBIkAmT6k7j0dFmntH4s2hBq+QzWmOC3U6VQQR+bvCaz4DEMBKAvv lUmKa7ah8tAEQTJVcbUSSrJMB7mdV7V81VeS45lfhVo3kzGQyJiG4/z5yucpnWRHLVuh FPydSYuL2qqW0004gAEvQopWKnlnc7dfhV5nImtbHCJw+Tc6RVbBrk35rvnNyYnTfXRM EPNwgWoigio0DF7Xz4Y7mcUaablJIFz4L1DFTT9XTQcoR8rtMXAi6K9c8pLZG3Q30W46 pSGA== X-Gm-Message-State: AOJu0Yx0mkJZy2TZPW4dh+3/rZsxxzaJakkTQ8+RAdQ5gYLZZN/+Xc3m 7PeSBSbH+6QwCfp7g/TCq2m/U70DEy3fDhO5QHT07I1DwNIiBGyl5k3c02e2+bXs30g= X-Gm-Gg: ASbGncsUKTT6pb4koZO//lxzxDvYIqfC0PRBk0dqHPAhWSlaB9IpbiAyTmafXpMY4Bi F34gVXwvlmcl5q1oHxsaOVItGxDMLMY2p56/rzjI81Qt4jYgx7kFqcH6Gx2MS6yeENQzk2fn9xV o9yynuffztWJx+qlHixUjS4MiRdozEXAzrcGLnx785FB9xgUP/NbDjF9zqQUpGJHA5HeKL49lkq v8LyKG54Ip+yJwitejREshUe6hygs3iodWiG+1yhJBnBODtyMwv95ymnQ/xmYmTRxOcMjuQGhW9 cIMS+pG0+0jihDmI71kwlIr+mVk2AAtTCVOkWOXJV7ZeevrCgEWrWziqHc9893V/9l7hLa5DYzi Rs8+7BclYxNHfhpA= X-Google-Smtp-Source: AGHT+IG6FlNhDwbItk3VBcAthiP4/CXxMSSzvIfk2cnA53I4npHwtNmhBOx55OH5i2dEZPES5nFbxQ== X-Received: by 2002:a05:6602:487:b0:86d:9ec4:effe with SMTP id ca18e2360f4ac-875ded5d898mr2242492539f.8.1750287960848; Wed, 18 Jun 2025 16:06:00 -0700 (PDT) From: Jackson Donaldson X-Google-Original-From: Jackson Donaldson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH v2 03/11] MAX78000: Add ICC to SOC Date: Wed, 18 Jun 2025 19:05:41 -0400 Message-Id: <20250618230549.3351152-4-jcksn@duck.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250618230549.3351152-1-jcksn@duck.com> References: <20250618230549.3351152-1-jcksn@duck.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::d31; envelope-from=jackson88044@gmail.com; helo=mail-io1-xd31.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 19 Jun 2025 01:21:41 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1750310559763116600 Content-Type: text/plain; charset="utf-8" This commit adds the instruction cache controller to max78000_soc Signed-off-by: Jackson Donaldson --- hw/arm/max78000_soc.c | 19 +++++++++++++++---- include/hw/arm/max78000_soc.h | 6 ++++++ 2 files changed, 21 insertions(+), 4 deletions(-) diff --git a/hw/arm/max78000_soc.c b/hw/arm/max78000_soc.c index 9676ada6a2..8d8d2dce61 100644 --- a/hw/arm/max78000_soc.c +++ b/hw/arm/max78000_soc.c @@ -17,12 +17,19 @@ #include "hw/qdev-clock.h" #include "hw/misc/unimp.h" =20 +static const uint32_t max78000_icc_addr[] =3D {0x4002a000, 0x4002a800}; + static void max78000_soc_initfn(Object *obj) { MAX78000State *s =3D MAX78000_SOC(obj); + int i; =20 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); =20 + for (i =3D 0; i < MAX78000_NUM_ICC; i++) { + object_initialize_child(obj, "icc[*]", &s->icc[i], TYPE_MAX78000_I= CC); + } + s->sysclk =3D qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); } =20 @@ -30,8 +37,9 @@ static void max78000_soc_realize(DeviceState *dev_soc, Er= ror **errp) { MAX78000State *s =3D MAX78000_SOC(dev_soc); MemoryRegion *system_memory =3D get_system_memory(); - DeviceState *armv7m; + DeviceState *dev, *armv7m; Error *err =3D NULL; + int i; =20 if (!clock_has_source(s->sysclk)) { error_setg(errp, "sysclk clock must be wired up by the board code"= ); @@ -74,6 +82,12 @@ static void max78000_soc_realize(DeviceState *dev_soc, E= rror **errp) return; } =20 + for (i =3D 0; i < MAX78000_NUM_ICC; i++) { + dev =3D DEVICE(&(s->icc[i])); + sysbus_realize(SYS_BUS_DEVICE(dev), errp); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, max78000_icc_addr[i]); + } + create_unimplemented_device("globalControl", 0x40000000, 0x400); create_unimplemented_device("systemInterface", 0x40000400, 0x400); create_unimplemented_device("functionControl", 0x40000800, 0x400); @@ -107,9 +121,6 @@ static void max78000_soc_realize(DeviceState *dev_soc, = Error **errp) create_unimplemented_device("standardDMA", 0x40028000, 0x1000= ); create_unimplemented_device("flashController0", 0x40029000, 0x400); =20 - create_unimplemented_device("icc0", 0x4002a000, 0x800); - create_unimplemented_device("icc1", 0x4002a800, 0x800); - create_unimplemented_device("adc", 0x40034000, 0x1000= ); create_unimplemented_device("pulseTrainEngine", 0x4003c000, 0xa0); create_unimplemented_device("oneWireMaster", 0x4003d000, 0x1000= ); diff --git a/include/hw/arm/max78000_soc.h b/include/hw/arm/max78000_soc.h index 97bf4099c9..27b506d6ee 100644 --- a/include/hw/arm/max78000_soc.h +++ b/include/hw/arm/max78000_soc.h @@ -11,6 +11,7 @@ =20 #include "hw/or-irq.h" #include "hw/arm/armv7m.h" +#include "hw/misc/max78000_icc.h" #include "qom/object.h" =20 #define TYPE_MAX78000_SOC "max78000-soc" @@ -21,6 +22,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(MAX78000State, MAX78000_SOC) #define SRAM_BASE_ADDRESS 0x20000000 #define SRAM_SIZE (128 * 1024) =20 +/* The MAX78k has 2 instruction caches; only icc0 matters, icc1 is for RIS= C */ +#define MAX78000_NUM_ICC 2 + struct MAX78000State { SysBusDevice parent_obj; =20 @@ -29,6 +33,8 @@ struct MAX78000State { MemoryRegion sram; MemoryRegion flash; =20 + Max78000IccState icc[MAX78000_NUM_ICC]; + Clock *sysclk; }; =20 --=20 2.34.1 From nobody Sat Nov 15 14:52:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1750310613; cv=none; d=zohomail.com; s=zohoarc; b=Qi156SkFK/UlsrkaMuUVBclrShBH8rKGZzI7gT744NCoVokdWsuvhSt8JpMUkCL6P0T99gC3qTXCbI/MTYfhdvLoEUyDFhnHOPzvhSv2PDca+2kk9ZuBamDCljwxxnKrI9zKVGYgLTRuogL3f4ow60UtsN1wuMc7Y4GOo/Uumyk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750310613; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=TdU8xJ6sM7vIFHzPgj/5e8/XfKTBvO05KBQRZeSchyE=; b=Sif5yQMGvCjSJ7SzmGZaP7CG9cJ9bsS47jFqLLBBJfzSbH/n+/scXkrK6oY0yIu2jUBWnm5JdgInwTSkcfje74hBSdjNfX0jZ6iOyDVf4m3ORXappk86TppIarPDB/TYg50Oy5DlQYjKFqMiELfX8ca0DaJ6Bri2E8A0ca++p+M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750310613018642.5622584938792; Wed, 18 Jun 2025 22:23:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uS7io-0003KV-DU; Thu, 19 Jun 2025 01:21:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uS1r3-0006rF-DU for qemu-devel@nongnu.org; Wed, 18 Jun 2025 19:06:05 -0400 Received: from mail-il1-x131.google.com ([2607:f8b0:4864:20::131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uS1r1-00065U-As for qemu-devel@nongnu.org; Wed, 18 Jun 2025 19:06:05 -0400 Received: by mail-il1-x131.google.com with SMTP id e9e14a558f8ab-3ddda8e419bso641955ab.0 for ; Wed, 18 Jun 2025 16:06:02 -0700 (PDT) Received: from user-jcksn.hsd1.mi.comcast.net ([2601:401:101:1070:b57:773f:14d7:807b]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-50149b9df11sm3036915173.54.2025.06.18.16.06.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jun 2025 16:06:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1750287962; x=1750892762; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TdU8xJ6sM7vIFHzPgj/5e8/XfKTBvO05KBQRZeSchyE=; b=EQ53pNC11YvuNskq4Lk9ZaDUT3cxnkg3B4K464CBCsd/pyKRxxs7mGsMI4cyHdfYEK 4toUPj1Jmn4IjcIBC/hjKOGxSaPObfbrWL9/0Ra++vcYzftWAF4PMsHkM/pCtsY1opZT lVclyoNXKixeJoaA2+PHP92LMOvYPKsd0y92deDB7ZLRVDn8eDMCuRps8Eq+kpAMkeg2 DAlLStyXSE/Isa+h+z1pKJIIh11tSaglir1kktfPA6PSvnxj2VQmqSVjwPJAEWupQ031 rA9y5yCX/g3lk2eqByr0LRurIJ/nAodcBHmw/l7nsiAtG4kcifG4QXTTM+Z4ASxBGKdR 6QlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750287962; x=1750892762; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TdU8xJ6sM7vIFHzPgj/5e8/XfKTBvO05KBQRZeSchyE=; b=spsKn7l5EhxCE7h4mauzwO9oAgSr/0xnr2wENNRPakts+mw3glvCpaTRxuSaLmMwpF WjoZP9OPp8ZQdPiRkowMsQOARKlFIf7ptOUOcKW/xGhIBWApXiEKBZF9uIJgLPW7OGtw lBTs9bDGnOq3DduvLXdlafsYVSEQ9JQsAnMS8rgIogF+TI3Om33Y9IoRYLdnsnrbBjRP qmNPgpQRiaRYiB48ZpFYDbFlMGMiUzF9WAEMAC0O4BtOr/55zT9dYjpfuCC9KQtzxVrq Xg1xnqOKoC8EdpPKftQSGg8mF4L6qSicIy/1Yfbr0HEMFmeKuB4plVspqrXpLLZfqzIO 6dNA== X-Gm-Message-State: AOJu0YyO1TeSscxgt6hnzFpVwLVuEXWqg3lZPatqO3zHvNZuCe8VzHkv uzDcZoqvzvIqN+6HyjtQ24E8mBhXeo3ZxVFX2bXYPwBPx25TJs7QYXTN04XYcEspTdg= X-Gm-Gg: ASbGnctnoVWU0pqWdtKQYS9GzKOsGIghi9RqkLP4V/I91ikkbGur6omtSWl4ujyTP/O ulnjyYt2YkD9QC79wS8B9vIdrwXgJi9gOJtntxo7fzk6tpDsfvpspQqAgp2ipPSaRqsRUtUcp7D cnP6cciQ2juPAVHqJBal06HfSXnmeS0M4U3fjk+wsCCTsUUqCv3HEocuBOucS9SoVBLnHv4tcgi nVoBzed2vgQpt/IYSdH3dWvO5tEGoZdFIpcGhhyet3wBu4BzVd3nKDYOxizPIqJKr+vhRBgJB8w lsK3zFulrfMU/feFUC5c5x0S0XUrz80T3lDU8IqsfIszVLHMevz6/UI2Rx5lqIrnvDiLFMB0rZa j9LWb X-Google-Smtp-Source: AGHT+IG02FmdiY0vDUdf1baX1j9ZgfUNdQhk99L7zqMX5XEjnLFP/o3DBHUB0ML4w8xCfdhqOkSayQ== X-Received: by 2002:a05:6e02:b:b0:3dd:bf91:23f7 with SMTP id e9e14a558f8ab-3de302baef3mr15550505ab.7.1750287961761; Wed, 18 Jun 2025 16:06:01 -0700 (PDT) From: Jackson Donaldson X-Google-Original-From: Jackson Donaldson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH v2 04/11] MAX78000: UART Implementation Date: Wed, 18 Jun 2025 19:05:42 -0400 Message-Id: <20250618230549.3351152-5-jcksn@duck.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250618230549.3351152-1-jcksn@duck.com> References: <20250618230549.3351152-1-jcksn@duck.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::131; envelope-from=jackson88044@gmail.com; helo=mail-il1-x131.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 19 Jun 2025 01:21:41 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1750310614621116600 Content-Type: text/plain; charset="utf-8" This commit implements UART support for the MAX78000 Signed-off-by: Jackson Donaldson Reviewed-by: Peter Maydell --- hw/arm/Kconfig | 1 + hw/char/Kconfig | 3 + hw/char/max78000_uart.c | 285 ++++++++++++++++++++++++++++++++ hw/char/meson.build | 1 + include/hw/char/max78000_uart.h | 78 +++++++++ 5 files changed, 368 insertions(+) create mode 100644 hw/char/max78000_uart.c create mode 100644 include/hw/char/max78000_uart.h diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index e3b419b468..031e0bf59e 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -367,6 +367,7 @@ config MAX78000_SOC bool select ARM_V7M select MAX78000_ICC + select MAX78000_UART =20 config RASPI bool diff --git a/hw/char/Kconfig b/hw/char/Kconfig index 9d517f3e28..020c0a84bb 100644 --- a/hw/char/Kconfig +++ b/hw/char/Kconfig @@ -48,6 +48,9 @@ config VIRTIO_SERIAL default y depends on VIRTIO =20 +config MAX78000_UART + bool + config STM32F2XX_USART bool =20 diff --git a/hw/char/max78000_uart.c b/hw/char/max78000_uart.c new file mode 100644 index 0000000000..19506d52ef --- /dev/null +++ b/hw/char/max78000_uart.c @@ -0,0 +1,285 @@ +/* + * MAX78000 UART + * + * Copyright (c) 2025 Jackson Donaldson + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/char/max78000_uart.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "hw/qdev-properties-system.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "migration/vmstate.h" +#include "trace.h" + + +static int max78000_uart_can_receive(void *opaque) +{ + Max78000UartState *s =3D opaque; + if (!(s->ctrl & UART_BCLKEN)) { + return 0; + } + return fifo8_num_free(&s->rx_fifo); +} + +static void max78000_update_irq(Max78000UartState *s) +{ + int interrupt_level; + + interrupt_level =3D s->int_fl & s->int_en; + qemu_set_irq(s->irq, interrupt_level); +} + +static void max78000_uart_receive(void *opaque, const uint8_t *buf, int si= ze) +{ + Max78000UartState *s =3D opaque; + + assert(size <=3D fifo8_num_free(&s->rx_fifo)); + + fifo8_push_all(&s->rx_fifo, buf, size); + + uint32_t rx_threshold =3D s->ctrl & 0xf; + + if (fifo8_num_used(&s->rx_fifo) >=3D rx_threshold) { + s->int_fl |=3D UART_RX_THD; + } + + max78000_update_irq(s); +} + +static void max78000_uart_reset_hold(Object *obj, ResetType type) +{ + Max78000UartState *s =3D MAX78000_UART(obj); + + s->ctrl =3D 0; + s->status =3D UART_TX_EM | UART_RX_EM; + s->int_en =3D 0; + s->int_fl =3D 0; + s->osr =3D 0; + s->txpeek =3D 0; + s->pnr =3D UART_RTS; + s->fifo =3D 0; + s->dma =3D 0; + s->wken =3D 0; + s->wkfl =3D 0; + fifo8_reset(&s->rx_fifo); +} + +static uint64_t max78000_uart_read(void *opaque, hwaddr addr, + unsigned int size) +{ + Max78000UartState *s =3D opaque; + uint64_t retvalue =3D 0; + switch (addr) { + case UART_CTRL: + retvalue =3D s->ctrl; + break; + case UART_STATUS: + retvalue =3D (fifo8_num_used(&s->rx_fifo) << UART_RX_LVL) | + UART_TX_EM | + (fifo8_is_empty(&s->rx_fifo) ? UART_RX_EM : 0); + break; + case UART_INT_EN: + retvalue =3D s->int_en; + break; + case UART_INT_FL: + retvalue =3D s->int_fl; + break; + case UART_CLKDIV: + retvalue =3D s->clkdiv; + break; + case UART_OSR: + retvalue =3D s->osr; + break; + case UART_TXPEEK: + if (!fifo8_is_empty(&s->rx_fifo)) { + retvalue =3D fifo8_peek(&s->rx_fifo); + } + break; + case UART_PNR: + retvalue =3D s->pnr; + break; + case UART_FIFO: + if (!fifo8_is_empty(&s->rx_fifo)) { + retvalue =3D fifo8_pop(&s->rx_fifo); + max78000_update_irq(s); + } + break; + case UART_DMA: + /* DMA not implemented */ + retvalue =3D s->dma; + break; + case UART_WKEN: + retvalue =3D s->wken; + break; + case UART_WKFL: + retvalue =3D s->wkfl; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); + break; + } + + return retvalue; +} + +static void max78000_uart_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + Max78000UartState *s =3D opaque; + + uint32_t value =3D val64; + uint8_t data; + + switch (addr) { + case UART_CTRL: + if (value & UART_FLUSH_RX) { + fifo8_reset(&s->rx_fifo); + } + if (value & UART_BCLKEN) { + value =3D value | UART_BCLKRDY; + } + s->ctrl =3D value & ~(UART_FLUSH_RX | UART_FLUSH_TX); + + /* + * Software can manage UART flow control manually by setting hfc_en + * in UART_CTRL. This would require emulating uart at a lower leve= l, + * and is currently unimplemented. + */ + + return; + case UART_STATUS: + /* UART_STATUS is read only */ + return; + case UART_INT_EN: + s->int_en =3D value; + return; + case UART_INT_FL: + s->int_fl =3D s->int_fl & ~(value); + max78000_update_irq(s); + return; + case UART_CLKDIV: + s->clkdiv =3D value; + return; + case UART_OSR: + s->osr =3D value; + return; + case UART_PNR: + s->pnr =3D value; + return; + case UART_FIFO: + data =3D value & 0xff; + /* + * XXX this blocks entire thread. Rewrite to use + * qemu_chr_fe_write and background I/O callbacks + */ + qemu_chr_fe_write_all(&s->chr, &data, 1); + + /* TX is always empty */ + s->int_fl |=3D UART_TX_HE; + max78000_update_irq(s); + + return; + case UART_DMA: + /* DMA not implemented */ + s->dma =3D value; + return; + case UART_WKEN: + s->wken =3D value; + return; + case UART_WKFL: + s->wkfl =3D value; + return; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" + HWADDR_PRIx "\n", __func__, addr); + } +} + +static const MemoryRegionOps max78000_uart_ops =3D { + .read =3D max78000_uart_read, + .write =3D max78000_uart_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, +}; + +static const Property max78000_uart_properties[] =3D { + DEFINE_PROP_CHR("chardev", Max78000UartState, chr), +}; + +static const VMStateDescription max78000_uart_vmstate =3D { + .name =3D TYPE_MAX78000_UART, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(ctrl, Max78000UartState), + VMSTATE_UINT32(status, Max78000UartState), + VMSTATE_UINT32(int_en, Max78000UartState), + VMSTATE_UINT32(int_fl, Max78000UartState), + VMSTATE_UINT32(clkdiv, Max78000UartState), + VMSTATE_UINT32(osr, Max78000UartState), + VMSTATE_UINT32(txpeek, Max78000UartState), + VMSTATE_UINT32(pnr, Max78000UartState), + VMSTATE_UINT32(fifo, Max78000UartState), + VMSTATE_UINT32(dma, Max78000UartState), + VMSTATE_UINT32(wken, Max78000UartState), + VMSTATE_UINT32(wkfl, Max78000UartState), + VMSTATE_FIFO8(rx_fifo, Max78000UartState), + VMSTATE_END_OF_LIST() + } +}; + +static void max78000_uart_init(Object *obj) +{ + Max78000UartState *s =3D MAX78000_UART(obj); + fifo8_create(&s->rx_fifo, 8); + + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); + + memory_region_init_io(&s->mmio, obj, &max78000_uart_ops, s, + TYPE_MAX78000_UART, 0x400); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); +} + +static void max78000_uart_realize(DeviceState *dev, Error **errp) +{ + Max78000UartState *s =3D MAX78000_UART(dev); + + qemu_chr_fe_set_handlers(&s->chr, max78000_uart_can_receive, + max78000_uart_receive, NULL, NULL, + s, NULL, true); +} + +static void max78000_uart_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + rc->phases.hold =3D max78000_uart_reset_hold; + + device_class_set_props(dc, max78000_uart_properties); + dc->realize =3D max78000_uart_realize; + + dc->vmsd =3D &max78000_uart_vmstate; +} + +static const TypeInfo max78000_uart_info =3D { + .name =3D TYPE_MAX78000_UART, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(Max78000UartState), + .instance_init =3D max78000_uart_init, + .class_init =3D max78000_uart_class_init, +}; + +static void max78000_uart_register_types(void) +{ + type_register_static(&max78000_uart_info); +} + +type_init(max78000_uart_register_types) diff --git a/hw/char/meson.build b/hw/char/meson.build index 4e439da8b9..a9e1dc26c0 100644 --- a/hw/char/meson.build +++ b/hw/char/meson.build @@ -26,6 +26,7 @@ system_ss.add(when: 'CONFIG_AVR_USART', if_true: files('a= vr_usart.c')) system_ss.add(when: 'CONFIG_COLDFIRE', if_true: files('mcf_uart.c')) system_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic-uart.c')) system_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_uart.c')) +system_ss.add(when: 'CONFIG_MAX78000_UART', if_true: files('max78000_uart.= c')) system_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_uart.c')) system_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_aux.c')) system_ss.add(when: 'CONFIG_RENESAS_SCI', if_true: files('renesas_sci.c')) diff --git a/include/hw/char/max78000_uart.h b/include/hw/char/max78000_uar= t.h new file mode 100644 index 0000000000..cf90d51dbf --- /dev/null +++ b/include/hw/char/max78000_uart.h @@ -0,0 +1,78 @@ +/* + * MAX78000 UART + * + * Copyright (c) 2025 Jackson Donaldson + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_MAX78000_UART_H +#define HW_MAX78000_UART_H + +#include "hw/sysbus.h" +#include "chardev/char-fe.h" +#include "qemu/fifo8.h" +#include "qom/object.h" + +#define UART_CTRL 0x0 +#define UART_STATUS 0x4 +#define UART_INT_EN 0x8 +#define UART_INT_FL 0xc +#define UART_CLKDIV 0x10 +#define UART_OSR 0x14 +#define UART_TXPEEK 0x18 +#define UART_PNR 0x1c +#define UART_FIFO 0x20 +#define UART_DMA 0x30 +#define UART_WKEN 0x34 +#define UART_WKFL 0x38 + +/* CTRL */ +#define UART_CTF_DIS (1 << 7) +#define UART_FLUSH_TX (1 << 8) +#define UART_FLUSH_RX (1 << 9) +#define UART_BCLKEN (1 << 15) +#define UART_BCLKRDY (1 << 19) + +/* STATUS */ +#define UART_RX_LVL 8 +#define UART_TX_EM (1 << 6) +#define UART_RX_FULL (1 << 5) +#define UART_RX_EM (1 << 4) + +/* PNR (Pin Control Register) */ +#define UART_CTS 1 +#define UART_RTS (1 << 1) + +/* INT_EN / INT_FL */ +#define UART_RX_THD (1 << 4) +#define UART_TX_HE (1 << 6) + +#define UART_RXBUFLEN 0x100 +#define TYPE_MAX78000_UART "max78000-uart" +OBJECT_DECLARE_SIMPLE_TYPE(Max78000UartState, MAX78000_UART) + +struct Max78000UartState { + SysBusDevice parent_obj; + + MemoryRegion mmio; + + uint32_t ctrl; + uint32_t status; + uint32_t int_en; + uint32_t int_fl; + uint32_t clkdiv; + uint32_t osr; + uint32_t txpeek; + uint32_t pnr; + uint32_t fifo; + uint32_t dma; + uint32_t wken; + uint32_t wkfl; + + Fifo8 rx_fifo; + + CharBackend chr; + qemu_irq irq; +}; +#endif /* HW_STM32F2XX_USART_H */ --=20 2.34.1 From nobody Sat Nov 15 14:52:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1750310616; cv=none; d=zohomail.com; s=zohoarc; b=H1D5JwR0iS/LmMcFnWu6FIVHa+Q1VDCedMQUWDyef7K320Dtdwh4pYgKgRB0yD/D8PRsVaOcyScLcn/EcG2k6okM7724dFRymhApb1Ivu98RBmtjWHU5m3/JxLfchWCboyVFcbUT/kHlCmG8KPEt/Z4OA3sljCj+UMdTnVpc8Ws= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750310616; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=KRYj8rEaeYKV08YM0H0JNx6pDU9r7YO11slIfaj7nMI=; b=eBP1wdk+kn4WJppoH6wo2E4urpHy0icis5Ljr36jveIDLRTSrLIoupLuc4/ek4BrN1X5y4s1NrM5BbHuftVU4gHoq5YePKuRtzvoJP0sbyPrsjvPMCEiX58IBqaicU/z5MZaDm8v/DOsZj+yxHrqXH4vzBG/LGQ2mef4+B7uXng= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17503106168141020.3834166766763; Wed, 18 Jun 2025 22:23:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uS7ic-0003HM-9z; Thu, 19 Jun 2025 01:21:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uS1r4-0006rn-Tu for qemu-devel@nongnu.org; Wed, 18 Jun 2025 19:06:06 -0400 Received: from mail-il1-x132.google.com ([2607:f8b0:4864:20::132]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uS1r2-00065c-Au for qemu-devel@nongnu.org; Wed, 18 Jun 2025 19:06:06 -0400 Received: by mail-il1-x132.google.com with SMTP id e9e14a558f8ab-3dc9e7d10bdso680875ab.2 for ; Wed, 18 Jun 2025 16:06:03 -0700 (PDT) Received: from user-jcksn.hsd1.mi.comcast.net ([2601:401:101:1070:b57:773f:14d7:807b]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-50149b9df11sm3036915173.54.2025.06.18.16.06.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jun 2025 16:06:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1750287963; x=1750892763; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KRYj8rEaeYKV08YM0H0JNx6pDU9r7YO11slIfaj7nMI=; b=cqEVyH8qKmwppuVd+B5oDjLTGE7CoRrd21XSl+4h6GZov41BWubAhsF1TxuQPz72Gz KtUTxtOwc0yrimVaNS0x04VdbmPGKgwDlkA9pqGz/NjgvJLHmjH8xIt+kdhYF15yV4z3 EzIAkVzFUbzovjOQxZIbNn3hOqrraiKXbf9iMOIm3S5ms+5WGW/5wQvnk9z80kAhS9dl 8jI+BFOHwwvjFVQHCo/b4okettPieuDm0bMmd+pd76/LBPjx51axUart3qu3lO0aJS8d sP0LoW6xREkT3r3rx4AnSMIwo++l0PwVCmrlDVlnhjo9wziKAImotxfihDlnU/BQSh3t ThBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750287963; x=1750892763; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KRYj8rEaeYKV08YM0H0JNx6pDU9r7YO11slIfaj7nMI=; b=gtlmbYtvivNtzT7ba6qpImNOVDNnq8iwmhSYK6VOsKwhHoI3bWwkRSTSJkQgzBsEeu Yqsk4zVUGQZX5fK1Wk26bMNykJMZFl+hToWnQGltMjRntK/VcLS8IzPep9p62kt7vsTI QnGgxV7LfBV2AjeYlYacylZJ4B9qFKZha/yG65+BX82G/87p1vqCPllg4BhRV6zWO370 txw3/3pyKlZA3lLLYq2Q/uWFlMDV5lVosxcqAOeGrnfu+oL213zI2Ldjo3nkLb8em5Fu J4ScJjwNVto7XHFXCcHTRQMnu5BXanE2bXqnOJHIHX+/OOe7Zey272rpCvLD6wPG6CvE I5BA== X-Gm-Message-State: AOJu0YxM8d/wH1yEyNOaR6yi87ZJcjSOnqd+UFwAirA7J4ybyZeM9atn Om+IhX/13S6hg5kI/IeX6gsy0aDAHM1ePLDb6v+7gp8HqUAAy8zmaastVNUMJgBVPzo= X-Gm-Gg: ASbGncuTicNpKuRWpuyR55Szj+xkzzZFeS2otLY3JmEFAMj9SwFgz12DdgJQwQ+IyjX k1jSFoSeuQU9lodBY8lIZIojrNNEwCB8oLw1o+dVJX09sKl8ghYmwRrgyo8gKXKOUHQ93h3zq4n oglODeCU808Fdinzz6RuJxuBXh2deZMLcx1T9vuInPVV9kV6hEHWgn8C/kY57ThHChEPY4Ab5wn 8qjZid7NJNarVu2N4EDy07eIfvQrGx11/rPPNhGaNzw41n/UaLGBpUKaRk9EsuuDra/fBxwt1zr WApYYj2RKXzdbHeKqNRZXguYRsCu/dM8lwm+d87KAmmjXzLSjS5eoRqj5GbZjYATFskWkn2neMX e+2yx X-Google-Smtp-Source: AGHT+IHQMtBFcP21kZa2FsfI1u30sOvP77aUymTqKw5FS8m1tvyLzEKOla+SpM28JrFHq2dSyr5a6w== X-Received: by 2002:a05:6e02:184a:b0:3db:7c22:303c with SMTP id e9e14a558f8ab-3de07cfe991mr200312265ab.8.1750287962740; Wed, 18 Jun 2025 16:06:02 -0700 (PDT) From: Jackson Donaldson X-Google-Original-From: Jackson Donaldson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH v2 05/11] MAX78000: Add UART to SOC Date: Wed, 18 Jun 2025 19:05:43 -0400 Message-Id: <20250618230549.3351152-6-jcksn@duck.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250618230549.3351152-1-jcksn@duck.com> References: <20250618230549.3351152-1-jcksn@duck.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::132; envelope-from=jackson88044@gmail.com; helo=mail-il1-x132.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 19 Jun 2025 01:21:41 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1750310618569116600 Content-Type: text/plain; charset="utf-8" This commit adds UART to max78000_soc Signed-off-by: Jackson Donaldson --- hw/arm/max78000_soc.c | 28 ++++++++++++++++++++++++---- include/hw/arm/max78000_soc.h | 3 +++ 2 files changed, 27 insertions(+), 4 deletions(-) diff --git a/hw/arm/max78000_soc.c b/hw/arm/max78000_soc.c index 8d8d2dce61..7217924191 100644 --- a/hw/arm/max78000_soc.c +++ b/hw/arm/max78000_soc.c @@ -18,6 +18,10 @@ #include "hw/misc/unimp.h" =20 static const uint32_t max78000_icc_addr[] =3D {0x4002a000, 0x4002a800}; +static const uint32_t max78000_uart_addr[] =3D {0x40042000, 0x40043000, + 0x40044000}; + +static const int max78000_uart_irq[] =3D {14, 15, 34}; =20 static void max78000_soc_initfn(Object *obj) { @@ -30,6 +34,11 @@ static void max78000_soc_initfn(Object *obj) object_initialize_child(obj, "icc[*]", &s->icc[i], TYPE_MAX78000_I= CC); } =20 + for (i =3D 0; i < MAX78000_NUM_UART; i++) { + object_initialize_child(obj, "uart[*]", &s->uart[i], + TYPE_MAX78000_UART); + } + s->sysclk =3D qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); } =20 @@ -38,6 +47,7 @@ static void max78000_soc_realize(DeviceState *dev_soc, Er= ror **errp) MAX78000State *s =3D MAX78000_SOC(dev_soc); MemoryRegion *system_memory =3D get_system_memory(); DeviceState *dev, *armv7m; + SysBusDevice *busdev; Error *err =3D NULL; int i; =20 @@ -88,6 +98,20 @@ static void max78000_soc_realize(DeviceState *dev_soc, E= rror **errp) sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, max78000_icc_addr[i]); } =20 + for (i =3D 0; i < MAX78000_NUM_UART; i++) { + dev =3D DEVICE(&(s->uart[i])); + qdev_prop_set_chr(dev, "chardev", serial_hd(i)); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) { + return; + } + dev->id =3D g_strdup_printf("uart%d", i); + + busdev =3D SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, max78000_uart_addr[i]); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, + max78000_uart_irq[i= ])); + } + create_unimplemented_device("globalControl", 0x40000000, 0x400); create_unimplemented_device("systemInterface", 0x40000400, 0x400); create_unimplemented_device("functionControl", 0x40000800, 0x400); @@ -126,10 +150,6 @@ static void max78000_soc_realize(DeviceState *dev_soc,= Error **errp) create_unimplemented_device("oneWireMaster", 0x4003d000, 0x1000= ); create_unimplemented_device("semaphore", 0x4003e000, 0x1000= ); =20 - create_unimplemented_device("uart0", 0x40042000, 0x1000= ); - create_unimplemented_device("uart1", 0x40043000, 0x1000= ); - create_unimplemented_device("uart2", 0x40044000, 0x1000= ); - create_unimplemented_device("spi1", 0x40046000, 0x2000= ); create_unimplemented_device("trng", 0x4004d000, 0x1000= ); create_unimplemented_device("i2s", 0x40060000, 0x1000= ); diff --git a/include/hw/arm/max78000_soc.h b/include/hw/arm/max78000_soc.h index 27b506d6ee..57894f0035 100644 --- a/include/hw/arm/max78000_soc.h +++ b/include/hw/arm/max78000_soc.h @@ -12,6 +12,7 @@ #include "hw/or-irq.h" #include "hw/arm/armv7m.h" #include "hw/misc/max78000_icc.h" +#include "hw/char/max78000_uart.h" #include "qom/object.h" =20 #define TYPE_MAX78000_SOC "max78000-soc" @@ -24,6 +25,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(MAX78000State, MAX78000_SOC) =20 /* The MAX78k has 2 instruction caches; only icc0 matters, icc1 is for RIS= C */ #define MAX78000_NUM_ICC 2 +#define MAX78000_NUM_UART 3 =20 struct MAX78000State { SysBusDevice parent_obj; @@ -34,6 +36,7 @@ struct MAX78000State { MemoryRegion flash; =20 Max78000IccState icc[MAX78000_NUM_ICC]; + Max78000UartState uart[MAX78000_NUM_UART]; =20 Clock *sysclk; }; --=20 2.34.1 From nobody Sat Nov 15 14:52:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1750310658; cv=none; d=zohomail.com; s=zohoarc; b=cQv1kHPQmjoaEFcI8j0YtEpOSAUQR9LPX8ogn2ymA241UrCERBf6bFeKpSkg6nYHGIwsymQ90l3eL26WXsUMf+h1wMlBOHt/blp2MA2gmd6lJ6w7v1i7niP/XTz1mJ7fDgTwMrT+LD0hchTHDkhMnAhY/Ws5SdfXElwOxuL45eQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750310658; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=fUtpX1lj2MzzMMT1nFHPGsST6WDworu4g6zqNUbOPHQ=; b=gfLRDbryjr25LQWveack7u+1OYAVDfxV8ggEEx0u7tfzF1lNZv5j3A+MZL78F33vxofwBrOqO+hVZbcZdlb+WzpaVuZAIuVd8tr7x/k5WqWS4Ko1OmqlZqex+w0biqt/7Sx+uggYvWx0ovxJuH0TeUGy2gRC8W7u7kJYTv2Mclk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750310658774880.4880923552965; Wed, 18 Jun 2025 22:24:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uS7im-0003JA-4D; Thu, 19 Jun 2025 01:21:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uS1r5-0006s6-NX for qemu-devel@nongnu.org; Wed, 18 Jun 2025 19:06:07 -0400 Received: from mail-ot1-x32d.google.com ([2607:f8b0:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uS1r3-00065o-GD for qemu-devel@nongnu.org; Wed, 18 Jun 2025 19:06:07 -0400 Received: by mail-ot1-x32d.google.com with SMTP id 46e09a7af769-72c14138668so57904a34.2 for ; Wed, 18 Jun 2025 16:06:05 -0700 (PDT) Received: from user-jcksn.hsd1.mi.comcast.net ([2601:401:101:1070:b57:773f:14d7:807b]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-50149b9df11sm3036915173.54.2025.06.18.16.06.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jun 2025 16:06:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1750287964; x=1750892764; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fUtpX1lj2MzzMMT1nFHPGsST6WDworu4g6zqNUbOPHQ=; b=kCYsOnB2i75k2UQ2wTG2287y5PMjh2DD0f91vkB3WEvW44FblfY6u1hMjwpwP3QHww lCeejC94QQAVvXzpi/4+UnQ/Xf2Wv9vuy/L4RbMrc3gQO/mKkBdSEV0inZmKQtgx3v56 cNMxcAmXxoeKT70WB+v5ilUMFF4WT5RnU4DLVBCm8460Q7EO+KJ2gnb4Aga/Ei/GvwX7 mISTAYkp30JoqqkSBCcX2HmQ5Ncq6NT+HiiTinqe5GN3kE9CB1fAiQnp0BugDFmdoKuf 2g5LT/OsusGWIFNz0RnuCuuxlWwnyFHKPnKqt7JS4Np2jN9338teGbB6Q7C3j4WZ0oDi iIbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750287964; x=1750892764; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fUtpX1lj2MzzMMT1nFHPGsST6WDworu4g6zqNUbOPHQ=; b=N5HSl6dY124o9I5lcNxir9jIYmqmt/DCuiC+XhRytlt/g8QYG8cF3MBiXpRqH39Kg1 Wr8Ee3XpM1i6Wzb7OCzeOcefNG+KdqFtS/tyO9CIRy6/UvvFCCVvT7cq038tmiGACVjb r5i8nt9vYfQp/7oJk4/PJLifLSUKK2CRS4KlSufgnU6VmEbt0aqgknBDtKvvUVsSrgig KIUxuUbFiGGHyHIRY+GDQj5imS1VHbxyMGUqqaKIqmEM19sQcXTu+b+cy6iGsCgim2Q+ FrF6WHLIII0EhkNFHZQNpSYCF0bQTCatG11jbcpUW6nGs4iNLVGOtUYOLVCwBnSYJR4P YMfA== X-Gm-Message-State: AOJu0Yzt1yjrcTkfXwx39mwYaRn599cX5faStY4WdPZXaDX9GZNIAGxm trUw+mhGEse/fOE5D4oygiV6z87jgZjNxQV5UEXq8tJhb4ki2LJBL8GGtJzrSoSHhZM= X-Gm-Gg: ASbGncvhF4dwRWZwxC0aiEsQDOshXWXFadiW4A24txpp22vZedjCoQkJsaV6NQwIdLk qCQ3oXD8iOnEqJ2ibSzXZAH7AWyeFKsR6YksdwX0h08BI5NbW+nSlG8t+V7hvjnGyGBz0dR0Bk6 2eEtO4Bp8XgGDgTb5g3hWKuzmcPG4qGyQLygnmycsUc2qpDKYkUtLcVmu/jWvq+8WWLI87bmeV0 uXz3vC6gu2RChrXFTvwh0dSwpfYQmBuTgX9KzZnpO+aYGecjpjq+G7F5gfJ0plwvYL4a4pMMbKw TjTPks+YnyhEiXQxr3JpG+7vRNapxcqBJdfiLrHjDX5wtiHrIJyl79D34AZwJXw0Xy7Z7rBcoFD txPZ9 X-Google-Smtp-Source: AGHT+IEkCCx2WGQdOpzxCJdn5adByKRFfqe2IhIhJPoYoqndlfwu4lvwHBTCYUaZ4vrxk3HmFM0Ciw== X-Received: by 2002:a9d:7cd6:0:b0:73a:6eb4:e8e6 with SMTP id 46e09a7af769-73a6eb4f7c9mr2611523a34.4.1750287963821; Wed, 18 Jun 2025 16:06:03 -0700 (PDT) From: Jackson Donaldson X-Google-Original-From: Jackson Donaldson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH v2 06/11] MAX78000: GCR Implementation Date: Wed, 18 Jun 2025 19:05:44 -0400 Message-Id: <20250618230549.3351152-7-jcksn@duck.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250618230549.3351152-1-jcksn@duck.com> References: <20250618230549.3351152-1-jcksn@duck.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32d; envelope-from=jackson88044@gmail.com; helo=mail-ot1-x32d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 19 Jun 2025 01:21:41 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1750310660933116600 Content-Type: text/plain; charset="utf-8" This commit implements the Global Control Register for the MAX78000 Signed-off-by: Jackson Donaldson Reviewed-by: Peter Maydell --- hw/arm/Kconfig | 1 + hw/misc/Kconfig | 3 + hw/misc/max78000_gcr.c | 339 +++++++++++++++++++++++++++++++++ hw/misc/meson.build | 1 + include/hw/misc/max78000_gcr.h | 129 +++++++++++++ 5 files changed, 473 insertions(+) create mode 100644 hw/misc/max78000_gcr.c create mode 100644 include/hw/misc/max78000_gcr.h diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 031e0bf59e..41bb64458f 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -368,6 +368,7 @@ config MAX78000_SOC select ARM_V7M select MAX78000_ICC select MAX78000_UART + select MAX78000_GCR =20 config RASPI bool diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index 781bcf74cc..fde2266b8f 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -47,6 +47,9 @@ config A9SCU config ARM11SCU bool =20 +config MAX78000_GCR + bool + config MAX78000_ICC bool =20 diff --git a/hw/misc/max78000_gcr.c b/hw/misc/max78000_gcr.c new file mode 100644 index 0000000000..8c282f3916 --- /dev/null +++ b/hw/misc/max78000_gcr.c @@ -0,0 +1,339 @@ +/* + * MAX78000 Global Control Registers + * + * Copyright (c) 2025 Jackson Donaldson + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "trace.h" +#include "hw/irq.h" +#include "system/runstate.h" +#include "migration/vmstate.h" +#include "hw/qdev-properties.h" +#include "hw/char/max78000_uart.h" +#include "hw/misc/max78000_gcr.h" + + +static void max78000_gcr_reset_hold(Object *obj, ResetType type) +{ + DeviceState *dev =3D DEVICE(obj); + Max78000GcrState *s =3D MAX78000_GCR(dev); + s->sysctrl =3D 0x21002; + s->rst0 =3D 0; + /* All clocks are always ready */ + s->clkctrl =3D 0x3e140008; + s->pm =3D 0x3f000; + s->pclkdiv =3D 0; + s->pclkdis0 =3D 0xffffffff; + s->memctrl =3D 0x5; + s->memz =3D 0; + s->sysst =3D 0; + s->rst1 =3D 0; + s->pckdis1 =3D 0xffffffff; + s->eventen =3D 0; + s->revision =3D 0xa1; + s->sysie =3D 0; + s->eccerr =3D 0; + s->ecced =3D 0; + s->eccie =3D 0; + s->eccaddr =3D 0; +} + +static uint64_t max78000_gcr_read(void *opaque, hwaddr addr, + unsigned int size) +{ + Max78000GcrState *s =3D opaque; + + switch (addr) { + case SYSCTRL: + return s->sysctrl; + + case RST0: + return s->rst0; + + case CLKCTRL: + return s->clkctrl; + + case PM: + return s->pm; + + case PCLKDIV: + return s->pclkdiv; + + case PCLKDIS0: + return s->pclkdis0; + + case MEMCTRL: + return s->memctrl; + + case MEMZ: + return s->memz; + + case SYSST: + return s->sysst; + + case RST1: + return s->rst1; + + case PCKDIS1: + return s->pckdis1; + + case EVENTEN: + return s->eventen; + + case REVISION: + return s->revision; + + case SYSIE: + return s->sysie; + + case ECCERR: + return s->eccerr; + + case ECCED: + return s->ecced; + + case ECCIE: + return s->eccie; + + case ECCADDR: + return s->eccaddr; + + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" + HWADDR_PRIx "\n", __func__, addr); + return 0; + + } +} + +static void max78000_gcr_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + Max78000GcrState *s =3D opaque; + uint32_t val =3D val64; + uint8_t zero[0xc000] =3D {0}; + switch (addr) { + case SYSCTRL: + /* Checksum calculations always pass immediately */ + s->sysctrl =3D (val & 0x30000) | 0x1002; + break; + + case RST0: + if (val & SYSTEM_RESET) { + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + } + if (val & PERIPHERAL_RESET) { + /* + * Peripheral reset resets all peripherals. The CPU + * retains its state. The GPIO, watchdog timers, AoD, + * RAM retention, and general control registers (GCR), + * including the clock configuration, are unaffected. + */ + val =3D UART2_RESET | UART1_RESET | UART0_RESET | + ADC_RESET | CNN_RESET | TRNG_RESET | + RTC_RESET | I2C0_RESET | SPI1_RESET | + TMR3_RESET | TMR2_RESET | TMR1_RESET | + TMR0_RESET | WDT0_RESET | DMA_RESET; + } + if (val & SOFT_RESET) { + /* Soft reset also resets GPIO */ + val =3D UART2_RESET | UART1_RESET | UART0_RESET | + ADC_RESET | CNN_RESET | TRNG_RESET | + RTC_RESET | I2C0_RESET | SPI1_RESET | + TMR3_RESET | TMR2_RESET | TMR1_RESET | + TMR0_RESET | GPIO1_RESET | GPIO0_RESET | + DMA_RESET; + } + if (val & UART2_RESET) { + device_cold_reset(s->uart2); + } + if (val & UART1_RESET) { + device_cold_reset(s->uart1); + } + if (val & UART0_RESET) { + device_cold_reset(s->uart0); + } + /* TODO: As other devices are implemented, add them here */ + break; + + case CLKCTRL: + s->clkctrl =3D val | SYSCLK_RDY; + break; + + case PM: + s->pm =3D val; + break; + + case PCLKDIV: + s->pclkdiv =3D val; + break; + + case PCLKDIS0: + s->pclkdis0 =3D val; + break; + + case MEMCTRL: + s->memctrl =3D val; + break; + + case MEMZ: + if (val & ram0) { + address_space_write(&s->sram_as, SYSRAM0_START, + MEMTXATTRS_UNSPECIFIED, zero, 0x8000); + } + if (val & ram1) { + address_space_write(&s->sram_as, SYSRAM1_START, + MEMTXATTRS_UNSPECIFIED, zero, 0x8000); + } + if (val & ram2) { + address_space_write(&s->sram_as, SYSRAM2_START, + MEMTXATTRS_UNSPECIFIED, zero, 0xC000); + } + if (val & ram3) { + address_space_write(&s->sram_as, SYSRAM3_START, + MEMTXATTRS_UNSPECIFIED, zero, 0x4000); + } + break; + + case SYSST: + s->sysst =3D val; + break; + + case RST1: + /* TODO: As other devices are implemented, add them here */ + s->rst1 =3D val; + break; + + case PCKDIS1: + s->pckdis1 =3D val; + break; + + case EVENTEN: + s->eventen =3D val; + break; + + case REVISION: + s->revision =3D val; + break; + + case SYSIE: + s->sysie =3D val; + break; + + case ECCERR: + s->eccerr =3D val; + break; + + case ECCED: + s->ecced =3D val; + break; + + case ECCIE: + s->eccie =3D val; + break; + + case ECCADDR: + s->eccaddr =3D val; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\= n", + __func__, addr); + break; + + } +} + +static const Property max78000_gcr_properties[] =3D { + DEFINE_PROP_LINK("sram", Max78000GcrState, sram, + TYPE_MEMORY_REGION, MemoryRegion*), + DEFINE_PROP_LINK("uart0", Max78000GcrState, uart0, + TYPE_MAX78000_UART, DeviceState*), + DEFINE_PROP_LINK("uart1", Max78000GcrState, uart1, + TYPE_MAX78000_UART, DeviceState*), + DEFINE_PROP_LINK("uart2", Max78000GcrState, uart2, + TYPE_MAX78000_UART, DeviceState*), +}; + +static const MemoryRegionOps max78000_gcr_ops =3D { + .read =3D max78000_gcr_read, + .write =3D max78000_gcr_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, +}; + +static const VMStateDescription vmstate_max78000_gcr =3D { + .name =3D TYPE_MAX78000_GCR, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT32(sysctrl, Max78000GcrState), + VMSTATE_UINT32(rst0, Max78000GcrState), + VMSTATE_UINT32(clkctrl, Max78000GcrState), + VMSTATE_UINT32(pm, Max78000GcrState), + VMSTATE_UINT32(pclkdiv, Max78000GcrState), + VMSTATE_UINT32(pclkdis0, Max78000GcrState), + VMSTATE_UINT32(memctrl, Max78000GcrState), + VMSTATE_UINT32(memz, Max78000GcrState), + VMSTATE_UINT32(sysst, Max78000GcrState), + VMSTATE_UINT32(rst1, Max78000GcrState), + VMSTATE_UINT32(pckdis1, Max78000GcrState), + VMSTATE_UINT32(eventen, Max78000GcrState), + VMSTATE_UINT32(revision, Max78000GcrState), + VMSTATE_UINT32(sysie, Max78000GcrState), + VMSTATE_UINT32(eccerr, Max78000GcrState), + VMSTATE_UINT32(ecced, Max78000GcrState), + VMSTATE_UINT32(eccie, Max78000GcrState), + VMSTATE_UINT32(eccaddr, Max78000GcrState), + VMSTATE_END_OF_LIST() + } +}; + +static void max78000_gcr_init(Object *obj) +{ + Max78000GcrState *s =3D MAX78000_GCR(obj); + + memory_region_init_io(&s->mmio, obj, &max78000_gcr_ops, s, + TYPE_MAX78000_GCR, 0x400); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); + +} + +static void max78000_gcr_realize(DeviceState *dev, Error **errp) +{ + Max78000GcrState *s =3D MAX78000_GCR(dev); + + address_space_init(&s->sram_as, s->sram, "sram"); +} + +static void max78000_gcr_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + device_class_set_props(dc, max78000_gcr_properties); + + dc->realize =3D max78000_gcr_realize; + dc->vmsd =3D &vmstate_max78000_gcr; + rc->phases.hold =3D max78000_gcr_reset_hold; +} + +static const TypeInfo max78000_gcr_info =3D { + .name =3D TYPE_MAX78000_GCR, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(Max78000GcrState), + .instance_init =3D max78000_gcr_init, + .class_init =3D max78000_gcr_class_init, +}; + +static void max78000_gcr_register_types(void) +{ + type_register_static(&max78000_gcr_info); +} + +type_init(max78000_gcr_register_types) diff --git a/hw/misc/meson.build b/hw/misc/meson.build index a21a994ff8..283d06dad4 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -70,6 +70,7 @@ system_ss.add(when: 'CONFIG_IMX', if_true: files( 'imx_ccm.c', 'imx_rngc.c', )) +system_ss.add(when: 'CONFIG_MAX78000_GCR', if_true: files('max78000_gcr.c'= )) system_ss.add(when: 'CONFIG_MAX78000_ICC', if_true: files('max78000_icc.c'= )) system_ss.add(when: 'CONFIG_NPCM7XX', if_true: files( 'npcm_clk.c', diff --git a/include/hw/misc/max78000_gcr.h b/include/hw/misc/max78000_gcr.h new file mode 100644 index 0000000000..f04c8a3ee7 --- /dev/null +++ b/include/hw/misc/max78000_gcr.h @@ -0,0 +1,129 @@ +/* + * MAX78000 Global Control Register + * + * Copyright (c) 2025 Jackson Donaldson + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef HW_MAX78000_GCR_H +#define HW_MAX78000_GCR_H + +#include "hw/sysbus.h" +#include "qom/object.h" + +#define TYPE_MAX78000_GCR "max78000-gcr" +OBJECT_DECLARE_SIMPLE_TYPE(Max78000GcrState, MAX78000_GCR) + +#define SYSCTRL 0x0 +#define RST0 0x4 +#define CLKCTRL 0x8 +#define PM 0xc +#define PCLKDIV 0x18 +#define PCLKDIS0 0x24 +#define MEMCTRL 0x28 +#define MEMZ 0x2c +#define SYSST 0x40 +#define RST1 0x44 +#define PCKDIS1 0x48 +#define EVENTEN 0x4c +#define REVISION 0x50 +#define SYSIE 0x54 +#define ECCERR 0x64 +#define ECCED 0x68 +#define ECCIE 0x6c +#define ECCADDR 0x70 + +/* RST0 */ +#define SYSTEM_RESET (1 << 31) +#define PERIPHERAL_RESET (1 << 30) +#define SOFT_RESET (1 << 29) +#define UART2_RESET (1 << 28) + +#define ADC_RESET (1 << 26) +#define CNN_RESET (1 << 25) +#define TRNG_RESET (1 << 24) + +#define RTC_RESET (1 << 17) +#define I2C0_RESET (1 << 16) + +#define SPI1_RESET (1 << 13) +#define UART1_RESET (1 << 12) +#define UART0_RESET (1 << 11) + +#define TMR3_RESET (1 << 8) +#define TMR2_RESET (1 << 7) +#define TMR1_RESET (1 << 6) +#define TMR0_RESET (1 << 5) + +#define GPIO1_RESET (1 << 3) +#define GPIO0_RESET (1 << 2) +#define WDT0_RESET (1 << 1) +#define DMA_RESET (1 << 0) + +/* CLKCTRL */ +#define SYSCLK_RDY (1 << 13) + +/* MEMZ */ +#define ram0 (1 << 0) +#define ram1 (1 << 1) +#define ram2 (1 << 2) +#define ram3 (1 << 3) + +/* RST1 */ +#define CPU1_RESET (1 << 31) + +#define SIMO_RESET (1 << 25) +#define DVS_RESET (1 << 24) + +#define I2C2_RESET (1 << 20) +#define I2S_RESET (1 << 19) + +#define SMPHR_RESET (1 << 16) + +#define SPI0_RESET (1 << 11) +#define AES_RESET (1 << 10) +#define CRC_RESET (1 << 9) + +#define PT_RESET (1 << 1) +#define I2C1_RESET (1 << 0) + + +#define SYSRAM0_START 0x20000000 +#define SYSRAM1_START 0x20008000 +#define SYSRAM2_START 0x20010000 +#define SYSRAM3_START 0x2001C000 + +struct Max78000GcrState { + SysBusDevice parent_obj; + + MemoryRegion mmio; + + uint32_t sysctrl; + uint32_t rst0; + uint32_t clkctrl; + uint32_t pm; + uint32_t pclkdiv; + uint32_t pclkdis0; + uint32_t memctrl; + uint32_t memz; + uint32_t sysst; + uint32_t rst1; + uint32_t pckdis1; + uint32_t eventen; + uint32_t revision; + uint32_t sysie; + uint32_t eccerr; + uint32_t ecced; + uint32_t eccie; + uint32_t eccaddr; + + MemoryRegion *sram; + AddressSpace sram_as; + + DeviceState *uart0; + DeviceState *uart1; + DeviceState *uart2; + +}; + +#endif --=20 2.34.1 From nobody Sat Nov 15 14:52:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1750310658; cv=none; d=zohomail.com; s=zohoarc; b=g7fq2i3+lFh1Nq++Z1lkLOI8yY5O+dJ4zEEc4oak5I8YGVAbTUklP6YzSeSjT4ZS3maO9ZTH446c0Iuc3n7XJkcTX8ouQG13kqJeBG/Irz36HlhUAn9M725XK2XCcXUU/9PxUkm9TbSscpASWqM52JQ5kYuVoYgFnMuWmwkTCuc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750310658; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=JCEw08LPA2qfRA5wAQpdHwuFYJV3Mv0L7c31+Gr3bog=; b=PBUwI8FvyqvdeVGTXxlTikQBVm/suOvhmpkAIvS4n5eGZG9KNnadi6QMwDmzpMr3LwfqVPZmAKKNMtoxoxaVGtGMKtcPEcErbj5Qiglc0lAtpDU232zKbWr1ynRwkh5pgMSnkowsNvCTytve4A8P0zghSOoHs6LxvthEJy7XEuM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750310658437810.474222930745; Wed, 18 Jun 2025 22:24:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uS7im-0003Jy-VO; Thu, 19 Jun 2025 01:21:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uS1r6-0006sE-7F for qemu-devel@nongnu.org; Wed, 18 Jun 2025 19:06:08 -0400 Received: from mail-il1-x135.google.com ([2607:f8b0:4864:20::135]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uS1r4-000664-6p for qemu-devel@nongnu.org; Wed, 18 Jun 2025 19:06:07 -0400 Received: by mail-il1-x135.google.com with SMTP id e9e14a558f8ab-3de252f75d7so2072535ab.3 for ; Wed, 18 Jun 2025 16:06:05 -0700 (PDT) Received: from user-jcksn.hsd1.mi.comcast.net ([2601:401:101:1070:b57:773f:14d7:807b]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-50149b9df11sm3036915173.54.2025.06.18.16.06.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jun 2025 16:06:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1750287965; x=1750892765; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JCEw08LPA2qfRA5wAQpdHwuFYJV3Mv0L7c31+Gr3bog=; b=SvaGAK9R7P/J5DFT6llyORULsEco1a52+2ToV6FIKvxklw7HJpk1aspvr0G/Qure/t 3Ti+2SC+hpY9CGDmeeD2RNheugWL4evafSy7URZdkepsD86vYBFxOHtRhAuxf0rDoLmb lj0dTzRb/24JSJR6GyznGk0Uq7y2JY8prdw4JqwmV4OkzMp6BSUNWCrARxBIIR25T2mj EDvNuchgoFKObCRhQeRqk43p/D+hn4A/+SHUR+36vAuaaQspbXC4xgwdTwcFZIbWwASG IwR4U9B34xFblm+cK5wqfbzRmKxxebtk6yYQdw2rgQso9p6bwey1n919jAvQVgNfQfR4 /5dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750287965; x=1750892765; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JCEw08LPA2qfRA5wAQpdHwuFYJV3Mv0L7c31+Gr3bog=; b=MDxAXoWGEWXPYRhX++HSrszhevxUaHHsPQTQaipXWrFgWb7ton36/KhGk07595dCUD EBTp0v9DNZhZLLAb/eMGwCoFEp7Hc9l5j4Lm3QkwteIcIxyPR9QKH64DLOHiLDURzFsC bdw2vNnV8E5JJ9k/52LDaj10zWhQMJBVjEGBOHCUEt808cf+BjIF9g+fbohecIhF6vWI QB40ES6GMqSVfvTOD8T6g1bpF9kkR9hL7vyEge4fw1BrTYOMsWTtJZG5ObF2vtj6bIbr OXgN1SYU5Kw6ZWktnaDnEow6DVx/EevClIkzQxjUF009fE8W5gd6IfsbP7FqbgkPcaNd 5xXw== X-Gm-Message-State: AOJu0YzG3H7uLEWlJ7b29oFvrwH2MRCX7i6QlvQM1H6EQ4IaSI/eM/Ux lYXzg5IUfcYkgfwv9a1lTSFsWQXJb67/Hise1iew9khjSsRondF50u0Serw22UquY8M= X-Gm-Gg: ASbGncvgJpmGK38D0bu/1GNLVZ46QJPIUoxvIszYI8U/7uVfgXIFTURoWvjH/Jb9ex7 mTQye32TgAQXgIvJY7ZKsTuifoWuNTFXyNuYZ0mzn2Ae/37n+te5lbA22WKJC1/3EsMIYMbaXon sfNOhF15/IflPUfEf5Wygu1JhdNvHu3Be2EmQcol4qNzcFrIlj+LCb5W//dYvpVbL1W5nxxanXH BCCZi0/exA+VOb0NcTU5IAfjKxDaoEqGQFIhIf0bLlf+/H0kI3TGpKLKfkdBiQKbmNTQ2DMOTTA pyqlOm/Y4qYS3GTLQH7hgWG/dSg1TLGuqAiV3O2WAjjxLr5uyKwcrWbWtuLKqCgCYdoKb/Feagp MTIy6v7mW2UXRKJo= X-Google-Smtp-Source: AGHT+IFW5oT5B9ZOUAp5xnzzzPy/OeVXpZTlxatbHxlYQpBZr3mHomPisNLDXqykwR6NN6FqjtNmLg== X-Received: by 2002:a05:6e02:1541:b0:3dd:d6c2:51fb with SMTP id e9e14a558f8ab-3de07cc0d4fmr209163445ab.10.1750287964757; Wed, 18 Jun 2025 16:06:04 -0700 (PDT) From: Jackson Donaldson X-Google-Original-From: Jackson Donaldson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH v2 07/11] MAX78000: Add GCR to SOC Date: Wed, 18 Jun 2025 19:05:45 -0400 Message-Id: <20250618230549.3351152-8-jcksn@duck.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250618230549.3351152-1-jcksn@duck.com> References: <20250618230549.3351152-1-jcksn@duck.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::135; envelope-from=jackson88044@gmail.com; helo=mail-il1-x135.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 19 Jun 2025 01:21:41 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1750310658846116600 Content-Type: text/plain; charset="utf-8" This commit adds the Global Control Register to max78000_soc Signed-off-by: Jackson Donaldson --- hw/arm/max78000_soc.c | 21 +++++++++++++++++++-- include/hw/arm/max78000_soc.h | 2 ++ 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/hw/arm/max78000_soc.c b/hw/arm/max78000_soc.c index 7217924191..1a36bba2fc 100644 --- a/hw/arm/max78000_soc.c +++ b/hw/arm/max78000_soc.c @@ -30,6 +30,8 @@ static void max78000_soc_initfn(Object *obj) =20 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); =20 + object_initialize_child(obj, "gcr", &s->gcr, TYPE_MAX78000_GCR); + for (i =3D 0; i < MAX78000_NUM_ICC; i++) { object_initialize_child(obj, "icc[*]", &s->icc[i], TYPE_MAX78000_I= CC); } @@ -46,7 +48,7 @@ static void max78000_soc_realize(DeviceState *dev_soc, Er= ror **errp) { MAX78000State *s =3D MAX78000_SOC(dev_soc); MemoryRegion *system_memory =3D get_system_memory(); - DeviceState *dev, *armv7m; + DeviceState *dev, *gcrdev, *armv7m; SysBusDevice *busdev; Error *err =3D NULL; int i; @@ -67,6 +69,11 @@ static void max78000_soc_realize(DeviceState *dev_soc, E= rror **errp) =20 memory_region_init_ram(&s->sram, NULL, "MAX78000.sram", SRAM_SIZE, &err); + + gcrdev =3D DEVICE(&s->gcr); + object_property_set_link(OBJECT(gcrdev), "sram", OBJECT(&s->sram), + &err); + if (err !=3D NULL) { error_propagate(errp, err); return; @@ -92,12 +99,14 @@ static void max78000_soc_realize(DeviceState *dev_soc, = Error **errp) return; } =20 + for (i =3D 0; i < MAX78000_NUM_ICC; i++) { dev =3D DEVICE(&(s->icc[i])); sysbus_realize(SYS_BUS_DEVICE(dev), errp); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, max78000_icc_addr[i]); } =20 + for (i =3D 0; i < MAX78000_NUM_UART; i++) { dev =3D DEVICE(&(s->uart[i])); qdev_prop_set_chr(dev, "chardev", serial_hd(i)); @@ -106,13 +115,21 @@ static void max78000_soc_realize(DeviceState *dev_soc= , Error **errp) } dev->id =3D g_strdup_printf("uart%d", i); =20 + object_property_set_link(OBJECT(gcrdev), dev->id, OBJECT(dev), + &err); + busdev =3D SYS_BUS_DEVICE(dev); sysbus_mmio_map(busdev, 0, max78000_uart_addr[i]); sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, max78000_uart_irq[i= ])); } =20 - create_unimplemented_device("globalControl", 0x40000000, 0x400); + dev =3D DEVICE(&s->gcr); + sysbus_realize(SYS_BUS_DEVICE(dev), errp); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x40000000); + + + create_unimplemented_device("systemInterface", 0x40000400, 0x400); create_unimplemented_device("functionControl", 0x40000800, 0x400); create_unimplemented_device("watchdogTimer0", 0x40003000, 0x400); diff --git a/include/hw/arm/max78000_soc.h b/include/hw/arm/max78000_soc.h index 57894f0035..919aca0855 100644 --- a/include/hw/arm/max78000_soc.h +++ b/include/hw/arm/max78000_soc.h @@ -11,6 +11,7 @@ =20 #include "hw/or-irq.h" #include "hw/arm/armv7m.h" +#include "hw/misc/max78000_gcr.h" #include "hw/misc/max78000_icc.h" #include "hw/char/max78000_uart.h" #include "qom/object.h" @@ -35,6 +36,7 @@ struct MAX78000State { MemoryRegion sram; MemoryRegion flash; =20 + Max78000GcrState gcr; Max78000IccState icc[MAX78000_NUM_ICC]; Max78000UartState uart[MAX78000_NUM_UART]; =20 --=20 2.34.1 From nobody Sat Nov 15 14:52:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1750310599; cv=none; d=zohomail.com; s=zohoarc; b=b1ETh66VCau4xkByv6oxjOduRlyzBxXD63jJ03HuZJv+b0UNRTY2sKSE/jcdgxG7B9UGi9iNEhXa6gaPwl5JNATFHR/3XuWArwTsQth4im32oz8IJ3Fws4PI1011zNFMoPtvb2lZCSfuoEljmx4f8rAHWOqBi4EHvvth+gTwCWo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750310599; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=6SLCzEWpSBxp31R4JKsPKGH7xuaYhB4PdeuTSnMKsJc=; b=AkQkqtCBJmuarHvnNOxLA49e+6pfNUm7O4KBjsxxwrvcUtM6hqbxqeBmLa4AiuFEJILMiIlhmYjNbtsxn/+LoBg5PTsYr/oIMk9HyhoPh5vb2pGt22IjSkVFDbdCRvmlcO/yXx9udYgSRdO1/IFGEhAidDJ3ndtYHv7K76Dtj/8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750310599403176.05368458683165; Wed, 18 Jun 2025 22:23:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uS7ic-0003HN-H5; Thu, 19 Jun 2025 01:21:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uS1r7-0006uz-AP for qemu-devel@nongnu.org; Wed, 18 Jun 2025 19:06:09 -0400 Received: from mail-io1-xd31.google.com ([2607:f8b0:4864:20::d31]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uS1r5-00066G-7J for qemu-devel@nongnu.org; Wed, 18 Jun 2025 19:06:09 -0400 Received: by mail-io1-xd31.google.com with SMTP id ca18e2360f4ac-86a464849c2so5503839f.1 for ; Wed, 18 Jun 2025 16:06:06 -0700 (PDT) Received: from user-jcksn.hsd1.mi.comcast.net ([2601:401:101:1070:b57:773f:14d7:807b]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-50149b9df11sm3036915173.54.2025.06.18.16.06.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jun 2025 16:06:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1750287966; x=1750892766; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6SLCzEWpSBxp31R4JKsPKGH7xuaYhB4PdeuTSnMKsJc=; b=Zs30ZYLJYxvEcs0vkXluDXxqtDLfvXCJaJVyIQc6QYYXjyCfx3jsrWk3dQ0tXgxKZv jnC4wC4n8qpFh9qBjZBSR5T4rA+20EHUyQggcz/MW0a+rhDeX1MMqG7cUZViZb0QQPRf hFVr6bWtv50T3Tc16W3/zkgvXGuNdkzQkJNyBUozz1VvRKs2CFhZvNzmLe8F4MVG0zYp 0QlyDn4Fc7eAFIIoz2JrHIn80sjTJ3OqJtzsp7cjBfHN0LIBh41kwKIIYZzcX5x3Bg1R VeaMgH3k/L/0l7auo9i83UhNPJ0qV2TNQVB1W7WA8YNISM/Q7iVRGLXYBL9JiWHY/TeD 90Rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750287966; x=1750892766; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6SLCzEWpSBxp31R4JKsPKGH7xuaYhB4PdeuTSnMKsJc=; b=u0JSQu5Vwo172JjqiXY0ak6HfdmhPpNFBcPtlwwz7V5jiHD3EXK1X+I1sTQ16ZD3nH pYqu167sTQEkXUtRYWLpI30mXK/oiImGLSIX7frweL2CkhFtFvgmWunlWoCOzZumEpco BTADKRDR1y4TGuXgyi0IOK0XWQ5n18/vG47y9FPY7GhPmAQqi/s40bxRQE3nqYULQXIE PJGAafvI1EbXF7FOQHuC3qZtVIy/Pr1DMdzxqC0HoEWKmRSKMTpNV+MslsY9RjoLQo8V 3nsMDfkqjF0S1e/fq6e5J+pGNsgRHc2m+CgTW60HcdtFMEXDQFGzCZ2daFKk9M/c+00m QzSQ== X-Gm-Message-State: AOJu0Yxx4SydOdJ1VLVpOUGcbTVlnTfy+1Fr8gTKtWvZcUhD7Jsndzch 1BAAa45b/TpIaHnT9ZSTtKflppyWPE2xp/2zcLvkZ9FM1d/JLlb2xlY7EzNfSvfVk5M= X-Gm-Gg: ASbGncup6nCiE5v7jmzEPFO4XxtQlfU8kgsGx42a7THdMETzVSwDSa3L/KdBmveRRfK 0BwLrSeov7eeNztrI5oyGY7fGfKg0X0zDcHhNprp468ag+OwxcGPbvvy2aKD04sf9kAJ4ATaTvH jyIbg2mVR53ZgxFKpqYtdZamGY9OdFOpcuVEY4sbP40HcJ+dlO2rDRvUT7cvVCdHEiQtoWMCjOK aFVqIiDSdcMfgGzxlau/YsUbyetv29N+EX2L8PCkpd3YG/ZsFi5SwvlBTwlJ8bu84zyyeYqCMsN UpjSEXvAdar0orYQGbv18IWfip2SRuTvORqQ8q4asDB6fIzmsp//l7VS5NObqagmN3SiQu7CJuK zG9gS X-Google-Smtp-Source: AGHT+IEeVsRIAY6b+w4EK8/rSyU15l8sm4ydY8fPzNTFZA/AQ/0mN/l4PcBkNYvdEeJUSbPx/TTTlA== X-Received: by 2002:a05:6602:a108:b0:85e:d0ca:b635 with SMTP id ca18e2360f4ac-8761b670e64mr114269539f.2.1750287965686; Wed, 18 Jun 2025 16:06:05 -0700 (PDT) From: Jackson Donaldson X-Google-Original-From: Jackson Donaldson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH v2 08/11] MAX78000: TRNG Implementation Date: Wed, 18 Jun 2025 19:05:46 -0400 Message-Id: <20250618230549.3351152-9-jcksn@duck.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250618230549.3351152-1-jcksn@duck.com> References: <20250618230549.3351152-1-jcksn@duck.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::d31; envelope-from=jackson88044@gmail.com; helo=mail-io1-xd31.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 19 Jun 2025 01:21:41 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1750310600457116600 Content-Type: text/plain; charset="utf-8" This commit implements the True Random Number Generator for the MAX78000 Signed-off-by: Jackson Donaldson --- hw/arm/Kconfig | 1 + hw/misc/Kconfig | 3 + hw/misc/max78000_gcr.c | 6 ++ hw/misc/max78000_trng.c | 127 ++++++++++++++++++++++++++++++++ hw/misc/meson.build | 1 + include/hw/misc/max78000_gcr.h | 1 + include/hw/misc/max78000_trng.h | 35 +++++++++ 7 files changed, 174 insertions(+) create mode 100644 hw/misc/max78000_trng.c create mode 100644 include/hw/misc/max78000_trng.h diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 41bb64458f..fcac62be6f 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -369,6 +369,7 @@ config MAX78000_SOC select MAX78000_ICC select MAX78000_UART select MAX78000_GCR + select MAX78000_TRNG =20 config RASPI bool diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index fde2266b8f..dd6a6e54da 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -53,6 +53,9 @@ config MAX78000_GCR config MAX78000_ICC bool =20 +config MAX78000_TRNG + bool + config MOS6522 bool =20 diff --git a/hw/misc/max78000_gcr.c b/hw/misc/max78000_gcr.c index 8c282f3916..5916ee615a 100644 --- a/hw/misc/max78000_gcr.c +++ b/hw/misc/max78000_gcr.c @@ -14,6 +14,7 @@ #include "migration/vmstate.h" #include "hw/qdev-properties.h" #include "hw/char/max78000_uart.h" +#include "hw/misc/max78000_trng.h" #include "hw/misc/max78000_gcr.h" =20 =20 @@ -157,6 +158,9 @@ static void max78000_gcr_write(void *opaque, hwaddr add= r, if (val & UART0_RESET) { device_cold_reset(s->uart0); } + if (val & TRNG_RESET) { + device_cold_reset(s->trng); + } /* TODO: As other devices are implemented, add them here */ break; =20 @@ -257,6 +261,8 @@ static const Property max78000_gcr_properties[] =3D { TYPE_MAX78000_UART, DeviceState*), DEFINE_PROP_LINK("uart2", Max78000GcrState, uart2, TYPE_MAX78000_UART, DeviceState*), + DEFINE_PROP_LINK("trng", Max78000GcrState, trng, + TYPE_MAX78000_TRNG, DeviceState*), }; =20 static const MemoryRegionOps max78000_gcr_ops =3D { diff --git a/hw/misc/max78000_trng.c b/hw/misc/max78000_trng.c new file mode 100644 index 0000000000..f406681730 --- /dev/null +++ b/hw/misc/max78000_trng.c @@ -0,0 +1,127 @@ +/* + * MAX78000 True Random Number Generator + * + * Copyright (c) 2025 Jackson Donaldson + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "trace.h" +#include "hw/irq.h" +#include "migration/vmstate.h" +#include "hw/misc/max78000_trng.h" +#include "qemu/guest-random.h" + +static uint64_t max78000_trng_read(void *opaque, hwaddr addr, + unsigned int size) +{ + uint32_t data; + + Max78000TrngState *s =3D opaque; + switch (addr) { + case CTRL: + return s->ctrl; + + case STATUS: + return 1; + + case DATA: + qemu_guest_getrandom_nofail(&data, sizeof(data)); + return data; + + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" + HWADDR_PRIx "\n", __func__, addr); + break; + } + return 0; +} + +static void max78000_trng_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + Max78000TrngState *s =3D opaque; + uint32_t val =3D val64; + switch (addr) { + case CTRL: + /* TODO: implement AES keygen */ + s->ctrl =3D val; + if (val & RND_IE) { + qemu_set_irq(s->irq, 1); + } else{ + qemu_set_irq(s->irq, 0); + } + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" + HWADDR_PRIx "\n", __func__, addr); + break; + } +} + +static void max78000_trng_reset_hold(Object *obj, ResetType type) +{ + Max78000TrngState *s =3D MAX78000_TRNG(obj); + s->ctrl =3D 0; + s->status =3D 0; + s->data =3D 0; +} + +static const MemoryRegionOps max78000_trng_ops =3D { + .read =3D max78000_trng_read, + .write =3D max78000_trng_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, +}; + +static const VMStateDescription max78000_trng_vmstate =3D { + .name =3D TYPE_MAX78000_TRNG, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT32(ctrl, Max78000TrngState), + VMSTATE_UINT32(status, Max78000TrngState), + VMSTATE_UINT32(data, Max78000TrngState), + VMSTATE_END_OF_LIST() + } +}; + +static void max78000_trng_init(Object *obj) +{ + Max78000TrngState *s =3D MAX78000_TRNG(obj); + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); + + memory_region_init_io(&s->mmio, obj, &max78000_trng_ops, s, + TYPE_MAX78000_TRNG, 0x1000); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); + +} + +static void max78000_trng_class_init(ObjectClass *klass, const void *data) +{ + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + DeviceClass *dc =3D DEVICE_CLASS(klass); + + rc->phases.hold =3D max78000_trng_reset_hold; + dc->vmsd =3D &max78000_trng_vmstate; + +} + +static const TypeInfo max78000_trng_info =3D { + .name =3D TYPE_MAX78000_TRNG, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(Max78000TrngState), + .instance_init =3D max78000_trng_init, + .class_init =3D max78000_trng_class_init, +}; + +static void max78000_trng_register_types(void) +{ + type_register_static(&max78000_trng_info); +} + +type_init(max78000_trng_register_types) diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 283d06dad4..c7c57d924b 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -72,6 +72,7 @@ system_ss.add(when: 'CONFIG_IMX', if_true: files( )) system_ss.add(when: 'CONFIG_MAX78000_GCR', if_true: files('max78000_gcr.c'= )) system_ss.add(when: 'CONFIG_MAX78000_ICC', if_true: files('max78000_icc.c'= )) +system_ss.add(when: 'CONFIG_MAX78000_TRNG', if_true: files('max78000_trng.= c')) system_ss.add(when: 'CONFIG_NPCM7XX', if_true: files( 'npcm_clk.c', 'npcm_gcr.c', diff --git a/include/hw/misc/max78000_gcr.h b/include/hw/misc/max78000_gcr.h index f04c8a3ee7..23ddf0885b 100644 --- a/include/hw/misc/max78000_gcr.h +++ b/include/hw/misc/max78000_gcr.h @@ -123,6 +123,7 @@ struct Max78000GcrState { DeviceState *uart0; DeviceState *uart1; DeviceState *uart2; + DeviceState *trng; =20 }; =20 diff --git a/include/hw/misc/max78000_trng.h b/include/hw/misc/max78000_trn= g.h new file mode 100644 index 0000000000..c5a8129b6a --- /dev/null +++ b/include/hw/misc/max78000_trng.h @@ -0,0 +1,35 @@ +/* + * MAX78000 True Random Number Generator + * + * Copyright (c) 2025 Jackson Donaldson + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef HW_MAX78000_TRNG_H +#define HW_MAX78000_TRNG_H + +#include "hw/sysbus.h" +#include "qom/object.h" + +#define TYPE_MAX78000_TRNG "max78000-trng" +OBJECT_DECLARE_SIMPLE_TYPE(Max78000TrngState, MAX78000_TRNG) + +#define CTRL 0 +#define STATUS 4 +#define DATA 8 + +#define RND_IE (1 << 1) + +struct Max78000TrngState { + SysBusDevice parent_obj; + + MemoryRegion mmio; + + uint32_t ctrl; + uint32_t status; + uint32_t data; + + qemu_irq irq; +}; + +#endif --=20 2.34.1 From nobody Sat Nov 15 14:52:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1750310644; cv=none; d=zohomail.com; s=zohoarc; b=NwDAbPjNVMmxqhJiRKo9dqIn++RTYynIWb9IjzC9tcdhi31kA/Pwr6AfDQbtLSek7e/VPG7gl8mgQlu3rR9NgD1iTI2Iu4Z9YE7DLsoS2BUdag2F3dGPKmr7YFwTotnN+x8y32Oz/iS/g1HDmetNpoT6KJHk5JGew7JTraTP9Jw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750310644; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=AtSSDzCzP4vwLmL/8RerFdCo8WTmKn978LGUT6OIuTY=; b=EFXb5K+ZYiGHp/fgUKXhznoEY8nudAxORwHX0jkkOJsgMoAIBWhB2TB03YOBAURzx4ftuFWUQefzWOKG73xG/YGPB4gcRvFF4Y5lKJ3DwYs7R0r33vNkokzwh0f2XbadZch76nu+bE9ANe/j1pgfBkMAzYMPEIplutqPFI820Eo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17503106442801017.0705825599867; Wed, 18 Jun 2025 22:24:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uS7ig-0003Hk-J0; Thu, 19 Jun 2025 01:21:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uS1r7-0006wU-PD for qemu-devel@nongnu.org; Wed, 18 Jun 2025 19:06:09 -0400 Received: from mail-io1-xd2e.google.com ([2607:f8b0:4864:20::d2e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uS1r6-00066d-7j for qemu-devel@nongnu.org; Wed, 18 Jun 2025 19:06:09 -0400 Received: by mail-io1-xd2e.google.com with SMTP id ca18e2360f4ac-87611ac3456so4986539f.0 for ; Wed, 18 Jun 2025 16:06:07 -0700 (PDT) Received: from user-jcksn.hsd1.mi.comcast.net ([2601:401:101:1070:b57:773f:14d7:807b]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-50149b9df11sm3036915173.54.2025.06.18.16.06.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jun 2025 16:06:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1750287966; x=1750892766; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AtSSDzCzP4vwLmL/8RerFdCo8WTmKn978LGUT6OIuTY=; b=aHDcVB6bH1sh5X8Z8SYCO2/kSkti07IsunM+8ma6FFj6Zpv12IU/7I+MhDUYYJsjw6 SdoC+T0HY0bbkGUMjPXIs1+GpAtaF6OHlEcPCx3JpQNGXghM9+P6Oc727bGj9E8sz793 L+Rv0u4KsmqilXQL499YpVe5uLk5U9r+/vinyW8eTbFRHNqz5cotMAg4sAB2KWL5FAV8 19B+WBcrrRHOOa7eNANYesyjubZB2/7+1mJaCeaAZe4ckhJNCAhccWfi/ExApfcaN7zJ v/AJBSJbOj1YSC5bL01h7x5wVZtmyGXFu6/XIwjnOgwJ/NM2oUiDfNaSC6+rKU5/3uXu wEFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750287967; x=1750892767; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AtSSDzCzP4vwLmL/8RerFdCo8WTmKn978LGUT6OIuTY=; b=vcHeeLAexD6sxaofcmDQzG3mzFMpyWKJWjP1JeP5trEkR42ilWfQQYIgZgGw6OiNfd H14qXJA9YHh25VRXFWEWy3asLdh1Wcwjb+uBlII8isEyDTMVpNfwDKdISXSpevXb1F/a Ra1UTUFY4zE8haZhr5CNOIBIyNZ+c/g6dPyUzaxAdzdGAHnwcRzklE3mOviBhjnJ/DvU xJ74QhBhsWo5d3lgCgSct36Q9resZgiaIVT1UdPVakg9Dzw08JaWefQHtMoI6eF2KTY3 XrZpbRpPoFj17IK99T9mUXhClsp+by1xc+zO1boFvgmfO4/8Ux9gdfRu6UiSVpQGecxv inwA== X-Gm-Message-State: AOJu0Yz15qKvQmtb9Ft+MboUOxGlHHd10/hwh2BmyNCeDp0THbcltI8+ k2PMTFcalr9MFAd5cLIy8mm9IwjkXz1d2GcOxEhv8SNH6ynJu5hOdK+hXlPtibC8Uyo= X-Gm-Gg: ASbGncsXS1cyYbG2wujVntBrLKIqeJTRuGTaLCFz641jsK2YyEuDiZs0JeXWXdSFnHL +KilWoZrAzP5EAOVK2wtKwSSuQcnroy8W1hwkdMJi6RZksV5vMW8m/KqLfvXAd3VSS1g/ZBV0Du buXdplYCvgOav0pASLjU3IehAvhswVsHT+feQdEyuvEIkK+6hQ/aB/1AtBffxSmFMPtf9pdvusC gqzwDlvGM+jY1AwhG72ouGDr5FPpB1zft/8B8p6tYgaFvAR2HfHfvV/peuCVfOqlhpEBobIy2xd 2Z0sFv3BJpF422U9yIEL5cCx/47Mdk+T6idbkbkrmqScTbQZGgLHsFKm/NnxNavSTUOA2ZY1l5y q16rl X-Google-Smtp-Source: AGHT+IHo0yEFki1gRFvQ5EKSSjYZrBmEJmnImnyeBI8P4L9ASnGvDAlflORZNPpLSvuH+5Rg5hl76Q== X-Received: by 2002:a05:6602:3d3:b0:86d:60:702f with SMTP id ca18e2360f4ac-875dec74af9mr2171582439f.0.1750287966604; Wed, 18 Jun 2025 16:06:06 -0700 (PDT) From: Jackson Donaldson X-Google-Original-From: Jackson Donaldson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH v2 09/11] MAX78000: Add TRNG to SOC Date: Wed, 18 Jun 2025 19:05:47 -0400 Message-Id: <20250618230549.3351152-10-jcksn@duck.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250618230549.3351152-1-jcksn@duck.com> References: <20250618230549.3351152-1-jcksn@duck.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::d2e; envelope-from=jackson88044@gmail.com; helo=mail-io1-xd2e.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 19 Jun 2025 01:21:41 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1750310644632116600 Content-Type: text/plain; charset="utf-8" This commit adds TRNG to max78000_soc Signed-off-by: Jackson Donaldson --- hw/arm/max78000_soc.c | 10 +++++++++- include/hw/arm/max78000_soc.h | 2 ++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/hw/arm/max78000_soc.c b/hw/arm/max78000_soc.c index 1a36bba2fc..09667b578c 100644 --- a/hw/arm/max78000_soc.c +++ b/hw/arm/max78000_soc.c @@ -41,6 +41,8 @@ static void max78000_soc_initfn(Object *obj) TYPE_MAX78000_UART); } =20 + object_initialize_child(obj, "trng", &s->trng, TYPE_MAX78000_TRNG); + s->sysclk =3D qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); } =20 @@ -124,6 +126,13 @@ static void max78000_soc_realize(DeviceState *dev_soc,= Error **errp) max78000_uart_irq[i= ])); } =20 + dev =3D DEVICE(&s->trng); + sysbus_realize(SYS_BUS_DEVICE(dev), errp); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x4004d000); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(armv7m, 4)= ); + dev->id =3D g_strdup("trng"); + object_property_set_link(OBJECT(gcrdev), "trng", OBJECT(dev), &err); + dev =3D DEVICE(&s->gcr); sysbus_realize(SYS_BUS_DEVICE(dev), errp); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x40000000); @@ -168,7 +177,6 @@ static void max78000_soc_realize(DeviceState *dev_soc, = Error **errp) create_unimplemented_device("semaphore", 0x4003e000, 0x1000= ); =20 create_unimplemented_device("spi1", 0x40046000, 0x2000= ); - create_unimplemented_device("trng", 0x4004d000, 0x1000= ); create_unimplemented_device("i2s", 0x40060000, 0x1000= ); create_unimplemented_device("lowPowerControl", 0x40080000, 0x400); create_unimplemented_device("gpio2", 0x40080400, 0x200); diff --git a/include/hw/arm/max78000_soc.h b/include/hw/arm/max78000_soc.h index 919aca0855..528598cfcb 100644 --- a/include/hw/arm/max78000_soc.h +++ b/include/hw/arm/max78000_soc.h @@ -14,6 +14,7 @@ #include "hw/misc/max78000_gcr.h" #include "hw/misc/max78000_icc.h" #include "hw/char/max78000_uart.h" +#include "hw/misc/max78000_trng.h" #include "qom/object.h" =20 #define TYPE_MAX78000_SOC "max78000-soc" @@ -39,6 +40,7 @@ struct MAX78000State { Max78000GcrState gcr; Max78000IccState icc[MAX78000_NUM_ICC]; Max78000UartState uart[MAX78000_NUM_UART]; + Max78000TrngState trng; =20 Clock *sysclk; }; --=20 2.34.1 From nobody Sat Nov 15 14:52:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1750310643; cv=none; d=zohomail.com; s=zohoarc; b=d9PzWWKmA0GSb4tavhS+jhQgnff3jv1o00GjwXR2Z/CyCTYDQspZqqZryoIf4k14WZYcN1ekZEtaJh4zEVh/ebhkJpEWm1buJ/UNoToy0mqCYEzKnWd/POVbOLEhyxRqSBbuhU7hMDPNR8FDhWJsqroh5KVDep5FNn49fj4t5T4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750310643; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=IR9Qt33GZzopQxreTpcCe/kwQ2ad1PKQYLoQroeFvRY=; b=Ay0vnKNRey1RjtDzd3aTHYUiebAwpj1Vb9tigZ0soby9YfJyTjdwSi4RI1qrXSeQFOJUo2qLZNE9PC/33iVhOX81pvAG/6L+zZR2Ca5gsqmxz7pZFkfI7nLxCRz/y3i7/9RTV+jcK+hv4eM/OOj5lLpl6D4/dLAHC5kY1Ju517A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750310643508605.7462345744817; Wed, 18 Jun 2025 22:24:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uS7il-0003J6-Jz; Thu, 19 Jun 2025 01:21:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uS1r9-0006zx-7n for qemu-devel@nongnu.org; Wed, 18 Jun 2025 19:06:11 -0400 Received: from mail-io1-xd2d.google.com ([2607:f8b0:4864:20::d2d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uS1r7-00066t-37 for qemu-devel@nongnu.org; Wed, 18 Jun 2025 19:06:11 -0400 Received: by mail-io1-xd2d.google.com with SMTP id ca18e2360f4ac-875dd57d63bso6732739f.0 for ; Wed, 18 Jun 2025 16:06:08 -0700 (PDT) Received: from user-jcksn.hsd1.mi.comcast.net ([2601:401:101:1070:b57:773f:14d7:807b]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-50149b9df11sm3036915173.54.2025.06.18.16.06.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jun 2025 16:06:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1750287967; x=1750892767; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IR9Qt33GZzopQxreTpcCe/kwQ2ad1PKQYLoQroeFvRY=; b=huwF5UIrAXXCPoc/7i5cHvB5wIGD5JbFgcaRWe2VOG3wwVLfnGn9y84zOUhto51iJr 9SAtsz4E1N8KvJrMK6Sf/9L9PCa1AuRf8VlBk/fXqThfgHbKr2oHYEZ9heohIt02keG1 ewoZdvlSsFtW7zztuou9Ugw3oQLIoA7eA08eWthoanJGAG6DO2ICgE2y+2AA2OFJ2Wvh wNnzM41uqxFL3i6cpRpm6YLK6ViSpvh/Wo+OWIc4+z283X7mOzNJ2xB1+O63etLs/Zer yjbrTVcN3BbRSEkYswVfF/8D3hs6rQJDruIDLIewruPKN4S5FlinUpgqA32Lv0JUmsLw 66qA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750287967; x=1750892767; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IR9Qt33GZzopQxreTpcCe/kwQ2ad1PKQYLoQroeFvRY=; b=TFqHa6zGXnmxbn9iEcx6HvfTPn91KjSRAFAB3rtWxZpPlpkuCY/Sp4FSaKyrcVFO7H hl3IA6XyTpcYYyWQjRh5kaBrui3Qj/8HEneElNCeMF4iPK4cWqY4KuTcWL++oLcx74aN GxNgUrXFsVjz0V7oVRY/cw3hiY5gTlduWukJjzq/yYun161j8xVHNe8d7jPiwoFFRB5X po+5g465Q4GHHzOBeKjsjeIXUuSL5k2KhY9ZOx8iqitSfZQuYZ86QG+JIb+hBWQv/QLq N5fgvOBeQ4UiILmY5coX5Z7AK/YkXug3JZu1mqz3jqeHaW97e9AK1xKUnPRW3PFZE7H7 bLuw== X-Gm-Message-State: AOJu0Yxj8dmweguUaFbcyZWQB3H8cc45g5WVJO1sh6PBR8wyxkp7GTbK AmdQy7wavOp5ZnkzYqJXN/uSJlQyCON+kFnwRaI5hwKkSQumRuk5vUqAjTmG8pDbcgY= X-Gm-Gg: ASbGncvHYy2dHA8ugErQB7NvGR9/GQoQp3o4qwTB74AWpyG9M4K88BeigSyQuDcn2Cj d+JJnkySiNburuy75/W4hFlVxm+JdLkN7jzN+73xi9ZqMbZeCcursa37destyinBI8obY754UBP ZLDY/Cvvx1hzXoNxoH78VJQRg0gImqSYMyi3isrrJvQ3OdoJZ7AO6q20HhLxJhZ36iDG/WVfBCp qVO831JjSKxVQrw33cDvQuZo36yD2h/ApteXOnVWBh1t55rPs45ab82g+Eu5FCvRUBMEq9stre5 DV46ra8v+7aVuvsUfWOtQgs4KdDR/XwAOYmIa36Isv7+dAHrFO6PubR/WX2z5Zm4Ti4qe05PWzK J6MW9 X-Google-Smtp-Source: AGHT+IFlnbri2F84H4ZjzABExBAlLKlHlWhEyiCxykEqHVh4amzEpd6piFuPs1AdO8w8TsjVVCs+nw== X-Received: by 2002:a5d:8753:0:b0:85e:16e9:5e8d with SMTP id ca18e2360f4ac-8761b94907cmr141204039f.7.1750287967534; Wed, 18 Jun 2025 16:06:07 -0700 (PDT) From: Jackson Donaldson X-Google-Original-From: Jackson Donaldson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH v2 10/11] MAX78000: AES implementation Date: Wed, 18 Jun 2025 19:05:48 -0400 Message-Id: <20250618230549.3351152-11-jcksn@duck.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250618230549.3351152-1-jcksn@duck.com> References: <20250618230549.3351152-1-jcksn@duck.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::d2d; envelope-from=jackson88044@gmail.com; helo=mail-io1-xd2d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 19 Jun 2025 01:21:42 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1750310644737116600 Content-Type: text/plain; charset="utf-8" This commit implements AES for the MAX78000 Signed-off-by: Jackson Donaldson --- hw/arm/Kconfig | 1 + hw/misc/Kconfig | 3 + hw/misc/max78000_aes.c | 232 +++++++++++++++++++++++++++++++++ hw/misc/max78000_gcr.c | 6 + hw/misc/meson.build | 1 + include/hw/misc/max78000_aes.h | 68 ++++++++++ include/hw/misc/max78000_gcr.h | 1 + 7 files changed, 312 insertions(+) create mode 100644 hw/misc/max78000_aes.c create mode 100644 include/hw/misc/max78000_aes.h diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index fcac62be6f..3e41120c89 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -370,6 +370,7 @@ config MAX78000_SOC select MAX78000_UART select MAX78000_GCR select MAX78000_TRNG + select MAX78000_AES =20 config RASPI bool diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index dd6a6e54da..c27285b47a 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -47,6 +47,9 @@ config A9SCU config ARM11SCU bool =20 +config MAX78000_AES + bool + config MAX78000_GCR bool =20 diff --git a/hw/misc/max78000_aes.c b/hw/misc/max78000_aes.c new file mode 100644 index 0000000000..d958b6faa3 --- /dev/null +++ b/hw/misc/max78000_aes.c @@ -0,0 +1,232 @@ +/* + * MAX78000 AES + * + * Copyright (c) 2025 Jackson Donaldson + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "trace.h" +#include "hw/irq.h" +#include "migration/vmstate.h" +#include "hw/misc/max78000_aes.h" +#include "crypto/aes.h" + +static void max78000_aes_set_status(Max78000AesState *s) +{ + s->status =3D 0; + if (s->result_index >=3D 16) { + s->status |=3D OUTPUT_FULL; + } + if (s->result_index =3D=3D 0) { + s->status |=3D OUTPUT_EMPTY; + } + if (s->data_index >=3D 16) { + s->status |=3D INPUT_FULL; + } + if (s->data_index =3D=3D 0) { + s->status |=3D INPUT_EMPTY; + } +} + +static uint64_t max78000_aes_read(void *opaque, hwaddr addr, + unsigned int size) +{ + Max78000AesState *s =3D opaque; + switch (addr) { + case CTRL: + return s->ctrl; + + case STATUS: + return s->status; + + case INTFL: + return s->intfl; + + case INTEN: + return s->inten; + + case FIFO: + if (s->result_index >=3D 4) { + s->intfl &=3D ~DONE; + s->result_index -=3D 4; + max78000_aes_set_status(s); + return (s->result[s->result_index] << 24) + + (s->result[s->result_index + 1] << 16) + + (s->result[s->result_index + 2] << 8) + + s->result[s->result_index + 3]; + } else{ + return 0; + } + + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" + HWADDR_PRIx "\n", __func__, addr); + break; + + } + return 0; +} + +static void max78000_aes_do_crypto(Max78000AesState *s) +{ + int keylen =3D 256; + uint8_t *keydata =3D s->key; + if ((s->ctrl & KEY_SIZE) =3D=3D 0) { + keylen =3D 128; + keydata +=3D 16; + } else if ((s->ctrl & KEY_SIZE) =3D=3D 1 << 6) { + keylen =3D 192; + keydata +=3D 8; + } + + AES_KEY key; + if ((s->ctrl & TYPE) =3D=3D 0) { + AES_set_encrypt_key(keydata, keylen, &key); + AES_set_decrypt_key(keydata, keylen, &s->internal_key); + AES_encrypt(s->data, s->result, &key); + s->result_index =3D 16; + } else if ((s->ctrl & TYPE) =3D=3D 1 << 8) { + AES_set_decrypt_key(keydata, keylen, &key); + AES_set_decrypt_key(keydata, keylen, &s->internal_key); + AES_decrypt(s->data, s->result, &key); + s->result_index =3D 16; + } else{ + AES_decrypt(s->data, s->result, &s->internal_key); + s->result_index =3D 16; + } + s->intfl |=3D DONE; +} + +static void max78000_aes_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + Max78000AesState *s =3D opaque; + uint32_t val =3D val64; + int i; + switch (addr) { + case CTRL: + if (val & OUTPUT_FLUSH) { + s->result_index =3D 0; + val &=3D ~OUTPUT_FLUSH; + } + if (val & INPUT_FLUSH) { + s->data_index =3D 0; + val &=3D ~INPUT_FLUSH; + } + if (val & START) { + max78000_aes_do_crypto(s); + } + + /* Hardware appears to stay enabled even if 0 written */ + s->ctrl =3D val | (s->ctrl & AES_EN); + break; + + case FIFO: + for (i =3D 0; i < 4; i++) { + s->data[(12 - s->data_index) + i] =3D + (val >> ((3 - i) * 8)) & 0xff; + } + s->data_index +=3D 4; + if (s->data_index >=3D 16) { + s->data_index =3D 0; + max78000_aes_do_crypto(s); + } + break; + + case KEY_BASE ... KEY_END - 4: + for (i =3D 0; i < 4; i++) { + s->key[(KEY_END - KEY_BASE - 4) - (addr - KEY_BASE) + i] =3D + (val >> ((3 - i) * 8)) & 0xff; + } + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" + HWADDR_PRIx "\n", __func__, addr); + break; + + } + max78000_aes_set_status(s); +} + +static void max78000_aes_reset_hold(Object *obj, ResetType type) +{ + Max78000AesState *s =3D MAX78000_AES(obj); + s->ctrl =3D 0; + s->status =3D 0; + s->intfl =3D 0; + s->inten =3D 0; + + s->data_index =3D 0; + s->result_index =3D 0; + + memset(s->data, 0, sizeof(s->data)); + memset(s->key, 0, sizeof(s->key)); + memset(s->result, 0, sizeof(s->result)); + memset(&s->internal_key, 0, sizeof(s->internal_key)); +} + +static const MemoryRegionOps max78000_aes_ops =3D { + .read =3D max78000_aes_read, + .write =3D max78000_aes_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, +}; + +static const VMStateDescription vmstate_max78000_aes =3D { + .name =3D TYPE_MAX78000_AES, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT32(ctrl, Max78000AesState), + VMSTATE_UINT32(status, Max78000AesState), + VMSTATE_UINT32(intfl, Max78000AesState), + VMSTATE_UINT32(inten, Max78000AesState), + VMSTATE_UINT8_ARRAY(data, Max78000AesState, 16), + VMSTATE_UINT8_ARRAY(key, Max78000AesState, 32), + VMSTATE_UINT8_ARRAY(result, Max78000AesState, 16), + VMSTATE_UINT32_ARRAY(internal_key.rd_key, Max78000AesState, 60), + VMSTATE_INT32(internal_key.rounds, Max78000AesState), + VMSTATE_END_OF_LIST() + } +}; + +static void max78000_aes_init(Object *obj) +{ + Max78000AesState *s =3D MAX78000_AES(obj); + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); + + memory_region_init_io(&s->mmio, obj, &max78000_aes_ops, s, + TYPE_MAX78000_AES, 0xc00); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); + +} + +static void max78000_aes_class_init(ObjectClass *klass, const void *data) +{ + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + DeviceClass *dc =3D DEVICE_CLASS(klass); + + rc->phases.hold =3D max78000_aes_reset_hold; + dc->vmsd =3D &vmstate_max78000_aes; + +} + +static const TypeInfo max78000_aes_info =3D { + .name =3D TYPE_MAX78000_AES, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(Max78000AesState), + .instance_init =3D max78000_aes_init, + .class_init =3D max78000_aes_class_init, +}; + +static void max78000_aes_register_types(void) +{ + type_register_static(&max78000_aes_info); +} + +type_init(max78000_aes_register_types) diff --git a/hw/misc/max78000_gcr.c b/hw/misc/max78000_gcr.c index 5916ee615a..fbbc92cca3 100644 --- a/hw/misc/max78000_gcr.c +++ b/hw/misc/max78000_gcr.c @@ -15,6 +15,7 @@ #include "hw/qdev-properties.h" #include "hw/char/max78000_uart.h" #include "hw/misc/max78000_trng.h" +#include "hw/misc/max78000_aes.h" #include "hw/misc/max78000_gcr.h" =20 =20 @@ -161,6 +162,9 @@ static void max78000_gcr_write(void *opaque, hwaddr add= r, if (val & TRNG_RESET) { device_cold_reset(s->trng); } + if (val & AES_RESET) { + device_cold_reset(s->aes); + } /* TODO: As other devices are implemented, add them here */ break; =20 @@ -263,6 +267,8 @@ static const Property max78000_gcr_properties[] =3D { TYPE_MAX78000_UART, DeviceState*), DEFINE_PROP_LINK("trng", Max78000GcrState, trng, TYPE_MAX78000_TRNG, DeviceState*), + DEFINE_PROP_LINK("aes", Max78000GcrState, aes, + TYPE_MAX78000_AES, DeviceState*), }; =20 static const MemoryRegionOps max78000_gcr_ops =3D { diff --git a/hw/misc/meson.build b/hw/misc/meson.build index c7c57d924b..b1d8d8e5d2 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -70,6 +70,7 @@ system_ss.add(when: 'CONFIG_IMX', if_true: files( 'imx_ccm.c', 'imx_rngc.c', )) +system_ss.add(when: 'CONFIG_MAX78000_AES', if_true: files('max78000_aes.c'= )) system_ss.add(when: 'CONFIG_MAX78000_GCR', if_true: files('max78000_gcr.c'= )) system_ss.add(when: 'CONFIG_MAX78000_ICC', if_true: files('max78000_icc.c'= )) system_ss.add(when: 'CONFIG_MAX78000_TRNG', if_true: files('max78000_trng.= c')) diff --git a/include/hw/misc/max78000_aes.h b/include/hw/misc/max78000_aes.h new file mode 100644 index 0000000000..407c45ef61 --- /dev/null +++ b/include/hw/misc/max78000_aes.h @@ -0,0 +1,68 @@ +/* + * MAX78000 AES + * + * Copyright (c) 2025 Jackson Donaldson + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef HW_MAX78000_AES_H +#define HW_MAX78000_AES_H + +#include "hw/sysbus.h" +#include "crypto/aes.h" +#include "qom/object.h" + +#define TYPE_MAX78000_AES "max78000-aes" +OBJECT_DECLARE_SIMPLE_TYPE(Max78000AesState, MAX78000_AES) + +#define CTRL 0 +#define STATUS 4 +#define INTFL 8 +#define INTEN 0xc +#define FIFO 0x10 + +#define KEY_BASE 0x400 +#define KEY_END 0x420 + +/* CTRL */ +#define TYPE (1 << 9 | 1 << 8) +#define KEY_SIZE (1 << 7 | 1 << 6) +#define OUTPUT_FLUSH (1 << 5) +#define INPUT_FLUSH (1 << 4) +#define START (1 << 3) + +#define AES_EN (1 << 0) + +/* STATUS */ +#define OUTPUT_FULL (1 << 4) +#define OUTPUT_EMPTY (1 << 3) +#define INPUT_FULL (1 << 2) +#define INPUT_EMPTY (1 << 1) +#define BUSY (1 << 0) + +/* INTFL*/ +#define DONE (1 << 0) + +struct Max78000AesState { + SysBusDevice parent_obj; + + MemoryRegion mmio; + + uint32_t ctrl; + uint32_t status; + uint32_t intfl; + uint32_t inten; + uint32_t data_index; + uint8_t data[16]; + + uint8_t key[32]; + AES_KEY internal_key; + + uint32_t result_index; + uint8_t result[16]; + + + qemu_irq irq; +}; + +#endif diff --git a/include/hw/misc/max78000_gcr.h b/include/hw/misc/max78000_gcr.h index 23ddf0885b..d5858a40f3 100644 --- a/include/hw/misc/max78000_gcr.h +++ b/include/hw/misc/max78000_gcr.h @@ -124,6 +124,7 @@ struct Max78000GcrState { DeviceState *uart1; DeviceState *uart2; DeviceState *trng; + DeviceState *aes; =20 }; =20 --=20 2.34.1 From nobody Sat Nov 15 14:52:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1750310576; cv=none; d=zohomail.com; s=zohoarc; b=YHnqlgP2Cv10kvgHbN9X8mbI2egeZreIz8GwRBT07QnNvqhgtYmnzsb2ao+y/KKH26rf96Jktv/4QExPQLEoWY60xi3OE+txhUBHbLDL2fTeShVZNs6XM00LXYEyKTXhK60jUsR3tHctTPt7OnTK/qttPjMa1+ahTdiNWkw5TfA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750310576; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=dWk8Nnabsk0USBLXKPI1hm//HSAUsckOEqxWoXg2fp8=; b=D9EcvqnkOs84HUAkmThzhxzPLhZHFnlhjmNBzTcHqutQQCYeyb78ddgU2p5w/tJKHfvUSnOh/bltp7XTzdZRwws6eAgUf4QcHUdlJB7lEZYRJsa772W5e6sNo2txQy1cpolRV6iqK/7C3wnvdtSs7YdnpXnoBYNENBUo4nemfwA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750310576856209.28521472970237; Wed, 18 Jun 2025 22:22:56 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uS7in-0003KF-TT; Thu, 19 Jun 2025 01:21:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uS1r9-000703-Cp for qemu-devel@nongnu.org; Wed, 18 Jun 2025 19:06:11 -0400 Received: from mail-il1-x12a.google.com ([2607:f8b0:4864:20::12a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uS1r7-000675-QJ for qemu-devel@nongnu.org; Wed, 18 Jun 2025 19:06:11 -0400 Received: by mail-il1-x12a.google.com with SMTP id e9e14a558f8ab-3ddff24fdc4so2034525ab.2 for ; Wed, 18 Jun 2025 16:06:09 -0700 (PDT) Received: from user-jcksn.hsd1.mi.comcast.net ([2601:401:101:1070:b57:773f:14d7:807b]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-50149b9df11sm3036915173.54.2025.06.18.16.06.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jun 2025 16:06:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1750287968; x=1750892768; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dWk8Nnabsk0USBLXKPI1hm//HSAUsckOEqxWoXg2fp8=; b=cZJifoL6QzkBRwaS2t5vme2xiMa5lsQ8SOy/h9/KJWN0lRTvULnk21tgvRA2u/NjFF wQ75Gf5rjia+cef1A52W4s9K20YgFUQqhJbiwzN/3BRQwSMHmiVvs4ozOKXwrq9gOrAa 4bK2p41ta7uNCM4sEF0Wvdj2tjCv+QAxYCP1Ut2RHLHcp0/fCsKu33o4PpyOWOW1dnBl ZEZGnaYz0hxDOJFtkdNHx8X93rnARqTy4HwJg18ILujgnrmzV2hm/2Hqv4hv8qN2SJGT L+padKIDw2fTgs2IFRhUAAraluRRT3bxq8kvAnUhqHheCwh80lUEKTNGarF4JHB7TviY tOeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750287968; x=1750892768; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dWk8Nnabsk0USBLXKPI1hm//HSAUsckOEqxWoXg2fp8=; b=XaVhTDgJE9U0cfsUAmOd/4ijT1Pmv6nNXVnnhjbc5q0Mw1eGIbNtUfQ+G4rYDcIc3c uEr7PL83TH98unzBrz9fyUUY9a/VGjQQxUHJfX07yuzNuGVjGJF/PE07mjCyN5GRztVi ea8hi1/mGf5UqzrnHIU/BZX36qYvKd7Oa6ptiX/N40jWZZYIJrQhH8wsymKDzkSLNhdC 9E3404a5oCUbcUoEf68TGmUVbDtJ3S2EXsS/UhX31/L7jrpHTeCykjj66lzsjPyfJVrr J3lDSujP4l1+nGL1YBiM49S4M0Pq678wzt5rCdthuUa6IF5hqTs4NqbngZEpbqVRzj/7 iSEA== X-Gm-Message-State: AOJu0YwgCBNGk2RdvElbmIppQfQWaGY4bQAvn77pHrrojoYrcDfYLW4f A3jRrwSZBXRhxqtGJ3IvE4YEMj1wAu5nmd+0dXJywfVE7aHJW8B3ixx5emxUrjDiXB4= X-Gm-Gg: ASbGnct8YLvGM3xWA/nESTfltxVt7+5POd8q9wROvyo4csrl6Rp1nx6E9jdNyg38jAD 2bcB8Qy/aV5yrURVDiWcJlTqjFze9CsXDccax+A6zL7Rlyd9g6cc9Cp4hpdxsv4Sf+sn6GG3m9/ SayK2w+VtTP1LqMlLG+3JQJxH27Mo28Z01U8ys/Zx/I9ZVelyU4vFMsKW4+6ZyJmwB7+GjEz/Ks cERKi1K//2C6T9X2+FSGHsR3Ml/xWNgiq8KiJZojxhxyuIKNythiF4JRRUcfZa9qu8CoyGlxuxM Cfve6yL97TYaOOPBuKY4Y4rZxrI5UqdfuquIaISMJHiWga1QRnNojPlZL75q/P5b1fwue9I1R4g 2Mvyd X-Google-Smtp-Source: AGHT+IFieuf5sOL1KzNPOF91LCTlJYI5rqBGN9oXaFP+ajX1KcZZQFeVdVT69vbv5ssczzpd/khjNw== X-Received: by 2002:a05:6e02:1c05:b0:3dd:f813:64c5 with SMTP id e9e14a558f8ab-3de07cd451emr244538825ab.22.1750287968459; Wed, 18 Jun 2025 16:06:08 -0700 (PDT) From: Jackson Donaldson X-Google-Original-From: Jackson Donaldson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH v2 11/11] MAX78000: Add AES to SOC Date: Wed, 18 Jun 2025 19:05:49 -0400 Message-Id: <20250618230549.3351152-12-jcksn@duck.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250618230549.3351152-1-jcksn@duck.com> References: <20250618230549.3351152-1-jcksn@duck.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::12a; envelope-from=jackson88044@gmail.com; helo=mail-il1-x12a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 19 Jun 2025 01:21:43 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1750310578209116600 Content-Type: text/plain; charset="utf-8" This commit adds AES to max78000_soc Signed-off-by: Jackson Donaldson --- hw/arm/max78000_soc.c | 12 +++++++++--- include/hw/arm/max78000_soc.h | 2 ++ 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/hw/arm/max78000_soc.c b/hw/arm/max78000_soc.c index 09667b578c..f6d599a62e 100644 --- a/hw/arm/max78000_soc.c +++ b/hw/arm/max78000_soc.c @@ -43,6 +43,8 @@ static void max78000_soc_initfn(Object *obj) =20 object_initialize_child(obj, "trng", &s->trng, TYPE_MAX78000_TRNG); =20 + object_initialize_child(obj, "aes", &s->aes, TYPE_MAX78000_AES); + s->sysclk =3D qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); } =20 @@ -133,6 +135,13 @@ static void max78000_soc_realize(DeviceState *dev_soc,= Error **errp) dev->id =3D g_strdup("trng"); object_property_set_link(OBJECT(gcrdev), "trng", OBJECT(dev), &err); =20 + dev =3D DEVICE(&s->aes); + sysbus_realize(SYS_BUS_DEVICE(dev), errp); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x40007400); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(armv7m, 5)= ); + dev->id =3D g_strdup("aes"); + object_property_set_link(OBJECT(gcrdev), "aes", OBJECT(dev), &err); + dev =3D DEVICE(&s->gcr); sysbus_realize(SYS_BUS_DEVICE(dev), errp); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x40000000); @@ -150,9 +159,6 @@ static void max78000_soc_realize(DeviceState *dev_soc, = Error **errp) create_unimplemented_device("powerSequencer", 0x40006800, 0x400); create_unimplemented_device("miscControl", 0x40006c00, 0x400); =20 - create_unimplemented_device("aes", 0x40007400, 0x400); - create_unimplemented_device("aesKey", 0x40007800, 0x400); - create_unimplemented_device("gpio0", 0x40008000, 0x1000= ); create_unimplemented_device("gpio1", 0x40009000, 0x1000= ); =20 diff --git a/include/hw/arm/max78000_soc.h b/include/hw/arm/max78000_soc.h index 528598cfcb..a203079ee9 100644 --- a/include/hw/arm/max78000_soc.h +++ b/include/hw/arm/max78000_soc.h @@ -11,6 +11,7 @@ =20 #include "hw/or-irq.h" #include "hw/arm/armv7m.h" +#include "hw/misc/max78000_aes.h" #include "hw/misc/max78000_gcr.h" #include "hw/misc/max78000_icc.h" #include "hw/char/max78000_uart.h" @@ -41,6 +42,7 @@ struct MAX78000State { Max78000IccState icc[MAX78000_NUM_ICC]; Max78000UartState uart[MAX78000_NUM_UART]; Max78000TrngState trng; + Max78000AesState aes; =20 Clock *sysclk; }; --=20 2.34.1