From nobody Sun Feb 8 14:22:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1750233724; cv=none; d=zohomail.com; s=zohoarc; b=WvcOD4IyfEIYkiWlFDXtEgdjxB0/xoc5N+LCDJ2CDXW+irQjBj5XRJICVxrLY/bt2yhXpvGvizBPgKL7lpXc7mc5uuKvLBquUggoqlklW0ZRn5La64C8Q5rRDPSs56pF/93BLgV85cpYlRgT2L9QGvYPMpQmTwx80ojXfAvyflU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750233724; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=LRJKSeT7wcl/exEAFGNPzthmk8rgb/9+C64ErXlrV7A=; b=TkDccibeBcov2vu3cdE1Ldny86qw3FnR69llU30Py0GtSHiOF7AglgEI6u0HN+lHOjpVz8hvnMu8l2nM0Hhczm31TI9ccjrv11X9vQGuRuNqU8KqwFLmbECsCUQB+QZqiZai7d7qS1H2A9uzU6LH57iH3Y5VvPgU4A47bDxlX6c= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750233724813121.89445749709398; Wed, 18 Jun 2025 01:02:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uRnio-0001Lw-EQ; Wed, 18 Jun 2025 04:00:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uRnil-0001Ke-I8; Wed, 18 Jun 2025 04:00:35 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uRnii-0006A3-Vz; Wed, 18 Jun 2025 04:00:35 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 18 Jun 2025 16:00:06 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 18 Jun 2025 16:00:06 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 2/2] hw/misc/aspeed_scu: Support the Frequency Counter Control register for AST2700 Date: Wed, 18 Jun 2025 16:00:05 +0800 Message-ID: <20250618080006.846355-3-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250618080006.846355-1-jamin_lin@aspeedtech.com> References: <20250618080006.846355-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1750233727921116600 Content-Type: text/plain; charset="utf-8" According to the datasheet: BIT[1] (SCU_FREQ_OSC_EN) enables the oscillator frequency measurement count= er. BIT[6] (SCU_FREQ_DONE) indicates the measurement is finished. Firmware polls BIT[6] to determine when measurement is complete. The flag can be cleared by writing BIT[1] to 0. To simulate this hardware behavior in QEMU: If BIT[1] is set to 1, BIT[6] is immediately set to 1 to avoid firmware hanging during polling. If BIT[1] is cleared to 0, BIT[6] is also cleared to 0 to match hardware semantics. The initial value of this register is initialized to 0x80, reflecting the default value confirmed from an EVB register dump. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/misc/aspeed_scu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 4930e00fed..11d0739108 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -176,6 +176,7 @@ #define AST2700_SCUIO_UARTCLK_GEN TO_REG(0x330) #define AST2700_SCUIO_HUARTCLK_GEN TO_REG(0x334) #define AST2700_SCUIO_CLK_DUTY_MEAS_RST TO_REG(0x388) +#define AST2700_SCUIO_FREQ_CNT_CTL TO_REG(0x3A0) =20 #define SCU_IO_REGION_SIZE 0x1000 =20 @@ -1022,6 +1023,10 @@ static void aspeed_ast2700_scuio_write(void *opaque,= hwaddr offset, s->regs[reg - 1] ^=3D data; updated =3D true; break; + case AST2700_SCUIO_FREQ_CNT_CTL: + s->regs[reg] =3D deposit32(s->regs[reg], 6, 1, !!(data & BIT(1))); + updated =3D true; + break; default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Unhandled write at offset 0x%" HWADDR_PRIx "\n", @@ -1066,6 +1071,7 @@ static const uint32_t ast2700_a0_resets_io[ASPEED_AST= 2700_SCU_NR_REGS] =3D { [AST2700_SCUIO_UARTCLK_GEN] =3D 0x00014506, [AST2700_SCUIO_HUARTCLK_GEN] =3D 0x000145c0, [AST2700_SCUIO_CLK_DUTY_MEAS_RST] =3D 0x0c9100d2, + [AST2700_SCUIO_FREQ_CNT_CTL] =3D 0x00000080, }; =20 static void aspeed_2700_scuio_class_init(ObjectClass *klass, const void *d= ata) --=20 2.43.0