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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1750174797; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=YaN6kB6+OE48wfdUHDtzjrqOVvauOnH0tktOv818dOg=; b=SJjOYTTLKh5VeefK8d2mczM8clfDU57ZhTE5WDfwEwLdfmnHGo5QqGqZMpXOHKkjKa3zBd DgG/9/FbLSg3ACj7bU4ev4gNlyDcV3sYz1VUEhKuTZ6VDO2duYsMOIrgsKksF3upBxl4sP gEn0OqDMx5GbKAQJkpX2KWO3lbOrBVs= X-MC-Unique: ul8Sf7A3MfSQbqSQp0mERw-1 X-Mimecast-MFC-AGG-ID: ul8Sf7A3MfSQbqSQp0mERw_1750174791 From: Cornelia Huck To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com, agraf@csgraf.de Cc: shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com, Cornelia Huck Subject: [PATCH v8 01/14] arm/cpu: Add sysreg definitions in cpu-sysregs.h Date: Tue, 17 Jun 2025 17:39:18 +0200 Message-ID: <20250617153931.1330449-2-cohuck@redhat.com> In-Reply-To: <20250617153931.1330449-1-cohuck@redhat.com> References: <20250617153931.1330449-1-cohuck@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: Eric Auger This new header contains macros that define aarch64 registers. In a subsequent patch, this will be replaced by a more exhaustive version that will be generated from linux arch/arm64/tools/sysreg file. Those macros are sufficient to migrate the storage of those ID regs from named fields in isar struct to an array cell. [CH: reworked to use different structures] [CH: moved accessors from the patches first using them to here, dropped interaction with writable registers, which will happen later] [CH: use DEF magic suggested by rth] Reviewed-by: Richard Henderson Reviewed-by: Sebastian Ott Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- target/arm/cpu-sysregs.h | 42 +++++++++++++++++++++++++++++++ target/arm/cpu-sysregs.h.inc | 36 ++++++++++++++++++++++++++ target/arm/cpu.h | 49 ++++++++++++++++++++++++++++++++++++ target/arm/cpu64.c | 22 ++++++++++++++++ 4 files changed, 149 insertions(+) create mode 100644 target/arm/cpu-sysregs.h create mode 100644 target/arm/cpu-sysregs.h.inc diff --git a/target/arm/cpu-sysregs.h b/target/arm/cpu-sysregs.h new file mode 100644 index 000000000000..7877a3b06a8e --- /dev/null +++ b/target/arm/cpu-sysregs.h @@ -0,0 +1,42 @@ +/* + * Definitions for Arm ID system registers + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef ARM_CPU_SYSREGS_H +#define ARM_CPU_SYSREGS_H + +/* + * Following is similar to the coprocessor regs encodings, but with an arg= ument + * ordering that matches the ARM ARM. We also reuse the various CP_REG_ de= fines + * that actually are the same as the equivalent KVM_REG_ values. + */ +#define ENCODE_ID_REG(op0, op1, crn, crm, op2) \ + (((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ + ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ + ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ + ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ + ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) + +#define DEF(NAME, OP0, OP1, CRN, CRM, OP2) NAME##_IDX, + +typedef enum ARMIDRegisterIdx { +#include "cpu-sysregs.h.inc" + NUM_ID_IDX, +} ARMIDRegisterIdx; + +#undef DEF +#define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \ + SYS_##NAME =3D ENCODE_ID_REG(OP0, OP1, CRN, CRM, OP2), + +typedef enum ARMSysRegs { +#include "cpu-sysregs.h.inc" +} ARMSysRegs; + +#undef DEF + +extern const uint32_t id_register_sysreg[NUM_ID_IDX]; + +int get_sysreg_idx(ARMSysRegs sysreg); + +#endif /* ARM_CPU_SYSREGS_H */ diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc new file mode 100644 index 000000000000..cb99286f7048 --- /dev/null +++ b/target/arm/cpu-sysregs.h.inc @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +DEF(ID_AA64PFR0_EL1, 3, 0, 0, 4, 0) +DEF(ID_AA64PFR1_EL1, 3, 0, 0, 4, 1) +DEF(ID_AA64SMFR0_EL1, 3, 0, 0, 4, 5) +DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0) +DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1) +DEF(ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0) +DEF(ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1) +DEF(ID_AA64ISAR2_EL1, 3, 0, 0, 6, 2) +DEF(ID_AA64MMFR0_EL1, 3, 0, 0, 7, 0) +DEF(ID_AA64MMFR1_EL1, 3, 0, 0, 7, 1) +DEF(ID_AA64MMFR2_EL1, 3, 0, 0, 7, 2) +DEF(ID_AA64MMFR3_EL1, 3, 0, 0, 7, 3) +DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0) +DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1) +DEF(ID_DFR0_EL1, 3, 0, 0, 1, 2) +DEF(ID_MMFR0_EL1, 3, 0, 0, 1, 4) +DEF(ID_MMFR1_EL1, 3, 0, 0, 1, 5) +DEF(ID_MMFR2_EL1, 3, 0, 0, 1, 6) +DEF(ID_MMFR3_EL1, 3, 0, 0, 1, 7) +DEF(ID_ISAR0_EL1, 3, 0, 0, 2, 0) +DEF(ID_ISAR1_EL1, 3, 0, 0, 2, 1) +DEF(ID_ISAR2_EL1, 3, 0, 0, 2, 2) +DEF(ID_ISAR3_EL1, 3, 0, 0, 2, 3) +DEF(ID_ISAR4_EL1, 3, 0, 0, 2, 4) +DEF(ID_ISAR5_EL1, 3, 0, 0, 2, 5) +DEF(ID_MMFR4_EL1, 3, 0, 0, 2, 6) +DEF(ID_ISAR6_EL1, 3, 0, 0, 2, 7) +DEF(MVFR0_EL1, 3, 0, 0, 3, 0) +DEF(MVFR1_EL1, 3, 0, 0, 3, 1) +DEF(MVFR2_EL1, 3, 0, 0, 3, 2) +DEF(ID_PFR2_EL1, 3, 0, 0, 3, 4) +DEF(ID_DFR1_EL1, 3, 0, 0, 3, 5) +DEF(ID_MMFR5_EL1, 3, 0, 0, 3, 6) +DEF(ID_AA64ZFR0_EL1, 3, 0, 0, 4, 4) +DEF(CTR_EL0, 3, 3, 0, 0, 1) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 302c24e2324a..45409f84ef0f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -32,6 +32,7 @@ #include "qapi/qapi-types-common.h" #include "target/arm/multiprocessing.h" #include "target/arm/gtimer.h" +#include "target/arm/cpu-sysregs.h" =20 #define EXCP_UDEF 1 /* undefined instruction */ #define EXCP_SWI 2 /* software interrupt */ @@ -834,6 +835,53 @@ typedef struct { uint32_t map, init, supported; } ARMVQMap; =20 +/* REG is ID_XXX */ +#define FIELD_DP64_IDREG(ISAR, REG, FIELD, VALUE) \ + ({ \ + ARMISARegisters *i_ =3D (ISAR); \ + uint64_t regval =3D i_->idregs[REG ## _EL1_IDX]; \ + regval =3D FIELD_DP64(regval, REG, FIELD, VALUE); \ + i_->idregs[REG ## _EL1_IDX] =3D regval; \ + }) + +#define FIELD_DP32_IDREG(ISAR, REG, FIELD, VALUE) \ + ({ \ + ARMISARegisters *i_ =3D (ISAR); \ + uint64_t regval =3D i_->idregs[REG ## _EL1_IDX]; \ + regval =3D FIELD_DP32(regval, REG, FIELD, VALUE); \ + i_->idregs[REG ## _EL1_IDX] =3D regval; \ + }) + +#define FIELD_EX64_IDREG(ISAR, REG, FIELD) \ + ({ \ + const ARMISARegisters *i_ =3D (ISAR); \ + FIELD_EX64(i_->idregs[REG ## _EL1_IDX], REG, FIELD); \ + }) + +#define FIELD_EX32_IDREG(ISAR, REG, FIELD) \ + ({ \ + const ARMISARegisters *i_ =3D (ISAR); \ + FIELD_EX32(i_->idregs[REG ## _EL1_IDX], REG, FIELD); \ + }) + +#define FIELD_SEX64_IDREG(ISAR, REG, FIELD) \ + ({ \ + const ARMISARegisters *i_ =3D (ISAR); \ + FIELD_SEX64(i_->idregs[REG ## _EL1_IDX], REG, FIELD); \ + }) + +#define SET_IDREG(ISAR, REG, VALUE) \ + ({ \ + ARMISARegisters *i_ =3D (ISAR); \ + i_->idregs[REG ## _EL1_IDX] =3D VALUE; \ + }) + +#define GET_IDREG(ISAR, REG) \ + ({ \ + const ARMISARegisters *i_ =3D (ISAR); \ + i_->idregs[REG ## _EL1_IDX]; \ + }) + /** * ARMCPU: * @env: #CPUARMState @@ -1040,6 +1088,7 @@ struct ArchCPU { uint64_t id_aa64zfr0; uint64_t id_aa64smfr0; uint64_t reset_pmcr_el0; + uint64_t idregs[NUM_ID_IDX]; } isar; uint64_t midr; uint32_t revidr; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 200da1c489b8..77054e0ec384 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -36,6 +36,28 @@ #include "cpu-features.h" #include "cpregs.h" =20 +/* convert between _IDX and SYS_ */ +#define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \ + [NAME##_IDX] =3D SYS_##NAME, + +const uint32_t id_register_sysreg[NUM_ID_IDX] =3D { +#include "cpu-sysregs.h.inc" +}; + +#undef DEF +#define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \ + case SYS_##NAME: return NAME##_IDX; + +int get_sysreg_idx(ARMSysRegs sysreg) +{ + switch (sysreg) { +#include "cpu-sysregs.h.inc" + } + g_assert_not_reached(); +} + +#undef DEF + void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { /* --=20 2.49.0 From nobody Sat Nov 15 20:48:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1750175697; cv=none; d=zohomail.com; s=zohoarc; b=jl9GWxZdqF+0OQN9ibPf2br97eQhy+A2NnTrkRTpCb5FV0rMCtGzc8McWvINcIbz1KcVXwQlfI5Vvvmsohu4FrTlbBjSeHiM5jIT3w3er+mpMlvvBIYdOEO6YMD6Xeyis0KKU4MLwddWfe4oIPcOHWoj0nbfU86VZqDroWDXgWo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750175697; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Tue, 17 Jun 2025 15:39:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1750174801; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AWoWmg1+2jFBTUl2CseC41TpvUSyMyvJkDl6MrdmKIA=; b=AMgxRGRuMfezJnoeWybBzwdTMPmO8WwBx+WgJqW6aDHts41hCLRmzw+BxMjqQ5wopZtExB J+mjg+lBWCP9n3LmHcABAvDZlevIdqM2mni38utra/6RumQeMF8J4YUL6B2uio7pl1jsJD LlcoLz2iqhpNRzzWKK9KYaZupXJx+Qs= X-MC-Unique: QlRWQ6EZNxqaCuwx-Com0g-1 X-Mimecast-MFC-AGG-ID: QlRWQ6EZNxqaCuwx-Com0g_1750174798 From: Cornelia Huck To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com, agraf@csgraf.de Cc: shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com, Cornelia Huck Subject: [PATCH v8 02/14] arm/cpu: Store aa64isar0/aa64zfr0 into the idregs arrays Date: Tue, 17 Jun 2025 17:39:19 +0200 Message-ID: <20250617153931.1330449-3-cohuck@redhat.com> In-Reply-To: <20250617153931.1330449-1-cohuck@redhat.com> References: <20250617153931.1330449-1-cohuck@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: Eric Auger Also add kvm accessors for storing host features into idregs. Reviewed-by: Richard Henderson Reviewed-by: Sebastian Ott Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- target/arm/cpu-features.h | 57 ++++++++++++++++++++------------------- target/arm/cpu.c | 9 +++---- target/arm/cpu.h | 2 -- target/arm/cpu64.c | 8 +++--- target/arm/helper.c | 6 +++-- target/arm/hvf/hvf.c | 3 ++- target/arm/kvm.c | 30 ++++++++++++++++++--- target/arm/tcg/cpu64.c | 44 ++++++++++++++++++------------ 8 files changed, 97 insertions(+), 62 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 4452e7c21e37..6a47f1a6d222 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -23,6 +23,7 @@ #include "hw/registerfields.h" #include "qemu/host-utils.h" #include "cpu.h" +#include "cpu-sysregs.h" =20 /* * Naming convention for isar_feature functions: @@ -377,92 +378,92 @@ static inline bool isar_feature_aa32_doublelock(const= ARMISARegisters *id) */ static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, AES) !=3D 0; } =20 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, AES) > 1; } =20 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SHA1) !=3D 0; } =20 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SHA2) !=3D 0; } =20 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SHA2) > 1; } =20 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, CRC32) !=3D 0; } =20 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, ATOMIC) !=3D 0; } =20 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, RDM) !=3D 0; } =20 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SHA3) !=3D 0; } =20 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SM3) !=3D 0; } =20 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SM4) !=3D 0; } =20 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, DP) !=3D 0; } =20 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, FHM) !=3D 0; } =20 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, TS) !=3D 0; } =20 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, TS) >=3D 2; } =20 static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, RNDR) !=3D 0; } =20 static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) =3D=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, TLB) =3D=3D 2; } =20 static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, TLB) !=3D 0; } =20 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) @@ -928,52 +929,52 @@ static inline bool isar_feature_aa64_doublelock(const= ARMISARegisters *id) =20 static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SVEVER) !=3D 0; } =20 static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, AES) !=3D 0; } =20 static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *= id) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) >=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, AES) >=3D 2; } =20 static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *i= d) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, BITPERM) !=3D 0; } =20 static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BFLOAT16) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, BFLOAT16) !=3D 0; } =20 static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SHA3) !=3D 0; } =20 static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SM4) !=3D 0; } =20 static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, I8MM) !=3D 0; } =20 static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, F32MM) !=3D 0; } =20 static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, F64MM) !=3D 0; } =20 static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index e025e241edae..f033411b5dad 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1962,6 +1962,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) { CPUState *cs =3D CPU(dev); ARMCPU *cpu =3D ARM_CPU(dev); + ARMISARegisters *isar =3D &cpu->isar; ARMCPUClass *acc =3D ARM_CPU_GET_CLASS(dev); CPUARMState *env =3D &cpu->env; Error *local_err =3D NULL; @@ -2167,7 +2168,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) =20 unset_feature(env, ARM_FEATURE_NEON); =20 - t =3D cpu->isar.id_aa64isar0; + t =3D GET_IDREG(isar, ID_AA64ISAR0); t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 0); t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0); t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0); @@ -2175,7 +2176,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) t =3D FIELD_DP64(t, ID_AA64ISAR0, SM3, 0); t =3D FIELD_DP64(t, ID_AA64ISAR0, SM4, 0); t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 0); - cpu->isar.id_aa64isar0 =3D t; + SET_IDREG(isar, ID_AA64ISAR0, t); =20 t =3D cpu->isar.id_aa64isar1; t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); @@ -2220,9 +2221,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) uint64_t t; uint32_t u; =20 - t =3D cpu->isar.id_aa64isar0; - t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); - cpu->isar.id_aa64isar0 =3D t; + FIELD_DP64_IDREG(isar, ID_AA64ISAR0, FHM, 0); =20 t =3D cpu->isar.id_aa64isar1; t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 45409f84ef0f..7b5c7a4abc7e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1074,7 +1074,6 @@ struct ArchCPU { uint32_t dbgdidr; uint32_t dbgdevid; uint32_t dbgdevid1; - uint64_t id_aa64isar0; uint64_t id_aa64isar1; uint64_t id_aa64isar2; uint64_t id_aa64pfr0; @@ -1085,7 +1084,6 @@ struct ArchCPU { uint64_t id_aa64mmfr3; uint64_t id_aa64dfr0; uint64_t id_aa64dfr1; - uint64_t id_aa64zfr0; uint64_t id_aa64smfr0; uint64_t reset_pmcr_el0; uint64_t idregs[NUM_ID_IDX]; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 77054e0ec384..c105fcc4ea57 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -136,7 +136,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) * SVE is disabled and so are all vector lengths. Good. * Disable all SVE extensions as well. */ - cpu->isar.id_aa64zfr0 =3D 0; + SET_IDREG(&cpu->isar, ID_AA64ZFR0, 0); return; } =20 @@ -639,6 +639,7 @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) static void aarch64_a57_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,cortex-a57"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -676,7 +677,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->isar.id_isar6 =3D 0; cpu->isar.id_aa64pfr0 =3D 0x00002222; cpu->isar.id_aa64dfr0 =3D 0x10305106; - cpu->isar.id_aa64isar0 =3D 0x00011120; + SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); cpu->isar.id_aa64mmfr0 =3D 0x00001124; cpu->isar.dbgdidr =3D 0x3516d000; cpu->isar.dbgdevid =3D 0x01110f13; @@ -700,6 +701,7 @@ static void aarch64_a57_initfn(Object *obj) static void aarch64_a53_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,cortex-a53"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -737,7 +739,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->isar.id_isar6 =3D 0; cpu->isar.id_aa64pfr0 =3D 0x00002222; cpu->isar.id_aa64dfr0 =3D 0x10305106; - cpu->isar.id_aa64isar0 =3D 0x00011120; + SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); cpu->isar.id_aa64mmfr0 =3D 0x00001122; /* 40 bit physical addr */ cpu->isar.dbgdidr =3D 0x3516d000; cpu->isar.dbgdevid =3D 0x00110f13; diff --git a/target/arm/helper.c b/target/arm/helper.c index 76312102879b..2457c8853c60 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7750,6 +7750,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ CPUARMState *env =3D &cpu->env; + ARMISARegisters *isar =3D &cpu->isar; + if (arm_feature(env, ARM_FEATURE_M)) { /* M profile has no coprocessor registers */ return; @@ -7941,7 +7943,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64zfr0 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64ZFR0)}, { .name =3D "ID_AA64SMFR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, @@ -8001,7 +8003,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64isar0 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64ISAR0)}, { .name =3D "ID_AA64ISAR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 42258cc2d888..5d25260c5c36 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -19,6 +19,7 @@ #include "system/hw_accel.h" #include "hvf_arm.h" #include "cpregs.h" +#include "cpu-sysregs.h" =20 #include =20 @@ -866,7 +867,7 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.id_aa64pfr1 }, { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.id_aa64dfr0 }, { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 }, - { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.id_aa64isar0 }, + { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.idregs[ID_AA64ISAR0_EL1_= IDX] }, { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.id_aa64isar1 }, /* Add ID_AA64ISAR2_EL1 here when HVF supports it */ { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 }, diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 74fda8b80903..bd33b0f656ed 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -26,6 +26,7 @@ #include "system/kvm_int.h" #include "kvm_arm.h" #include "cpu.h" +#include "cpu-sysregs.h" #include "trace.h" #include "internals.h" #include "hw/pci/pci.h" @@ -218,6 +219,28 @@ static bool kvm_arm_pauth_supported(void) kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_GENERIC)); } =20 + +static uint64_t idregs_sysreg_to_kvm_reg(ARMSysRegs sysreg) +{ + return ARM64_SYS_REG((sysreg & CP_REG_ARM64_SYSREG_OP0_MASK) >> CP_REG= _ARM64_SYSREG_OP0_SHIFT, + (sysreg & CP_REG_ARM64_SYSREG_OP1_MASK) >> CP_REG= _ARM64_SYSREG_OP1_SHIFT, + (sysreg & CP_REG_ARM64_SYSREG_CRN_MASK) >> CP_REG= _ARM64_SYSREG_CRN_SHIFT, + (sysreg & CP_REG_ARM64_SYSREG_CRM_MASK) >> CP_REG= _ARM64_SYSREG_CRM_SHIFT, + (sysreg & CP_REG_ARM64_SYSREG_OP2_MASK) >> CP_REG= _ARM64_SYSREG_OP2_SHIFT); +} + +/* read a sysreg value and store it in the idregs */ +static int get_host_cpu_reg(int fd, ARMHostCPUFeatures *ahcf, ARMIDRegiste= rIdx index) +{ + uint64_t *reg; + int ret; + + reg =3D &ahcf->isar.idregs[index]; + ret =3D read_sys_reg64(fd, reg, + idregs_sysreg_to_kvm_reg(id_register_sysreg[index= ])); + return ret; +} + static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) { /* Identify the feature bits corresponding to the host CPU, and @@ -267,6 +290,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) =20 ahcf->target =3D init.target; ahcf->dtb_compatible =3D "arm,arm-v8"; + int fd =3D fdarray[2]; =20 err =3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0, ARM64_SYS_REG(3, 0, 0, 4, 0)); @@ -298,8 +322,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) ARM64_SYS_REG(3, 0, 0, 5, 0)); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1, ARM64_SYS_REG(3, 0, 0, 5, 1)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0, - ARM64_SYS_REG(3, 0, 0, 6, 0)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64ISAR0_EL1_IDX); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1, ARM64_SYS_REG(3, 0, 0, 6, 1)); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar2, @@ -408,8 +431,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) * enabled SVE support, which resulted in an error rather than= RAZ. * So only read the register if we set KVM_ARM_VCPU_SVE above. */ - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, - ARM64_SYS_REG(3, 0, 0, 4, 4)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64ZFR0_EL1_IDX); } } =20 diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 5d8ed2794d37..ed681ee08b0d 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -32,6 +32,7 @@ static void aarch64_a35_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,cortex-a35"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -66,7 +67,7 @@ static void aarch64_a35_initfn(Object *obj) cpu->isar.id_aa64pfr1 =3D 0; cpu->isar.id_aa64dfr0 =3D 0x10305106; cpu->isar.id_aa64dfr1 =3D 0; - cpu->isar.id_aa64isar0 =3D 0x00011120; + SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); cpu->isar.id_aa64isar1 =3D 0; cpu->isar.id_aa64mmfr0 =3D 0x00101122; cpu->isar.id_aa64mmfr1 =3D 0; @@ -204,6 +205,7 @@ static const Property arm_cpu_lpa2_property =3D static void aarch64_a55_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,cortex-a55"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -221,7 +223,7 @@ static void aarch64_a55_initfn(Object *obj) cpu->ctr =3D 0x84448004; /* L1Ip =3D VIPT */ cpu->dcz_blocksize =3D 4; /* 64 bytes */ cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; - cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; + SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; @@ -276,6 +278,7 @@ static void aarch64_a55_initfn(Object *obj) static void aarch64_a72_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,cortex-a72"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -311,7 +314,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->isar.id_isar5 =3D 0x00011121; cpu->isar.id_aa64pfr0 =3D 0x00002222; cpu->isar.id_aa64dfr0 =3D 0x10305106; - cpu->isar.id_aa64isar0 =3D 0x00011120; + SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); cpu->isar.id_aa64mmfr0 =3D 0x00001124; cpu->isar.dbgdidr =3D 0x3516d000; cpu->isar.dbgdevid =3D 0x01110f13; @@ -335,6 +338,7 @@ static void aarch64_a72_initfn(Object *obj) static void aarch64_a76_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,cortex-a76"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -352,7 +356,7 @@ static void aarch64_a76_initfn(Object *obj) cpu->ctr =3D 0x8444C004; cpu->dcz_blocksize =3D 4; cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; - cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; + SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; @@ -408,6 +412,7 @@ static void aarch64_a76_initfn(Object *obj) static void aarch64_a64fx_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,a64fx"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -431,9 +436,9 @@ static void aarch64_a64fx_initfn(Object *obj) cpu->isar.id_aa64mmfr0 =3D 0x0000000000001122; cpu->isar.id_aa64mmfr1 =3D 0x0000000011212100; cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011; - cpu->isar.id_aa64isar0 =3D 0x0000000010211120; + SET_IDREG(isar, ID_AA64ISAR0, 0x0000000010211120); cpu->isar.id_aa64isar1 =3D 0x0000000000010001; - cpu->isar.id_aa64zfr0 =3D 0x0000000000000000; + SET_IDREG(isar, ID_AA64ZFR0, 0x0000000000000000); cpu->clidr =3D 0x0000000080000023; /* 64KB L1 dcache */ cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 256, 64 * KiB,= 7); @@ -581,6 +586,7 @@ static void define_neoverse_v1_cp_reginfo(ARMCPU *cpu) static void aarch64_neoverse_n1_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,neoverse-n1"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -598,7 +604,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj) cpu->ctr =3D 0x8444c004; cpu->dcz_blocksize =3D 4; cpu->isar.id_aa64dfr0 =3D 0x0000000110305408ull; - cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; + SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; @@ -656,6 +662,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj) static void aarch64_neoverse_v1_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,neoverse-v1"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -676,7 +683,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj) cpu->id_aa64afr1 =3D 0x00000000; cpu->isar.id_aa64dfr0 =3D 0x000001f210305519ull; cpu->isar.id_aa64dfr1 =3D 0x00000000; - cpu->isar.id_aa64isar0 =3D 0x1011111110212120ull; /* with FEAT_RNG */ + SET_IDREG(isar, ID_AA64ISAR0, 0x1011111110212120ull); /* with FEAT_RNG= */ cpu->isar.id_aa64isar1 =3D 0x0011100001211032ull; cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; @@ -735,7 +742,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000043; =20 /* From 3.7.5 ID_AA64ZFR0_EL1 */ - cpu->isar.id_aa64zfr0 =3D 0x0000100000100000; + SET_IDREG(isar, ID_AA64ZFR0, 0x0000100000100000); cpu->sve_vq.supported =3D (1 << 0) /* 128bit */ | (1 << 1); /* 256bit */ =20 @@ -882,6 +889,7 @@ static const ARMCPRegInfo cortex_a710_cp_reginfo[] =3D { static void aarch64_a710_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,cortex-a710"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -919,12 +927,12 @@ static void aarch64_a710_initfn(Object *obj) cpu->isar.id_pfr2 =3D 0x00000011; cpu->isar.id_aa64pfr0 =3D 0x1201111120111112ull; /* GIC filled in lat= er */ cpu->isar.id_aa64pfr1 =3D 0x0000000000000221ull; - cpu->isar.id_aa64zfr0 =3D 0x0000110100110021ull; /* with Crypto */ + SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */ cpu->isar.id_aa64dfr0 =3D 0x000011f010305619ull; cpu->isar.id_aa64dfr1 =3D 0; cpu->id_aa64afr0 =3D 0; cpu->id_aa64afr1 =3D 0; - cpu->isar.id_aa64isar0 =3D 0x0221111110212120ull; /* with Crypto */ + SET_IDREG(isar, ID_AA64ISAR0, 0x0221111110212120ull); /* with Crypto */ cpu->isar.id_aa64isar1 =3D 0x0010111101211052ull; cpu->isar.id_aa64mmfr0 =3D 0x0000022200101122ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; @@ -983,6 +991,7 @@ static const ARMCPRegInfo neoverse_n2_cp_reginfo[] =3D { static void aarch64_neoverse_n2_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,neoverse-n2"; set_feature(&cpu->env, ARM_FEATURE_V8); @@ -1020,12 +1029,12 @@ static void aarch64_neoverse_n2_initfn(Object *obj) cpu->isar.id_pfr2 =3D 0x00000011; cpu->isar.id_aa64pfr0 =3D 0x1201111120111112ull; /* GIC filled in lat= er */ cpu->isar.id_aa64pfr1 =3D 0x0000000000000221ull; - cpu->isar.id_aa64zfr0 =3D 0x0000110100110021ull; /* with Crypto */ + SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */ cpu->isar.id_aa64dfr0 =3D 0x000011f210305619ull; cpu->isar.id_aa64dfr1 =3D 0; cpu->id_aa64afr0 =3D 0; cpu->id_aa64afr1 =3D 0; - cpu->isar.id_aa64isar0 =3D 0x1221111110212120ull; /* with Crypto and F= EAT_RNG */ + SET_IDREG(isar, ID_AA64ISAR0, 0x1221111110212120ull); /* with Crypto a= nd FEAT_RNG */ cpu->isar.id_aa64isar1 =3D 0x0011111101211052ull; cpu->isar.id_aa64mmfr0 =3D 0x0000022200101125ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; @@ -1083,6 +1092,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj) void aarch64_max_tcg_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; uint64_t t; uint32_t u; =20 @@ -1133,7 +1143,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, CTR_EL0, DIC, 1); cpu->ctr =3D t; =20 - t =3D cpu->isar.id_aa64isar0; + t =3D GET_IDREG(isar, ID_AA64ISAR0); t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */ @@ -1148,7 +1158,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */ t =3D FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ t =3D FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */ - cpu->isar.id_aa64isar0 =3D t; + SET_IDREG(isar, ID_AA64ISAR0, t); =20 t =3D cpu->isar.id_aa64isar1; t =3D FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */ @@ -1244,7 +1254,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */ cpu->isar.id_aa64mmfr3 =3D t; =20 - t =3D cpu->isar.id_aa64zfr0; + t =3D GET_IDREG(isar, ID_AA64ZFR0); t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */ t =3D FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */ @@ -1254,7 +1264,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */ t =3D FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */ t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */ - cpu->isar.id_aa64zfr0 =3D t; + SET_IDREG(isar, ID_AA64ZFR0, t); =20 t =3D cpu->isar.id_aa64dfr0; t =3D FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 10); /* FEAT_Debugv8p8 */ --=20 2.49.0 From nobody Sat Nov 15 20:48:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1750176644; cv=none; d=zohomail.com; s=zohoarc; b=m2ro67TzFJCoMSTxkj9WuDDAbzIOUDxLH6BNC14kK/oPZ/kIQ9viJcd8b+GhSqH7Dc43NXnYRPILr0s1lCskLX5PrL1ZPJVZ34i+pQJblVwFOpciX3neQA1xFCCK7ysF4QfMJDfS7C11/bahPdlLF+tWb4M6JGUxB/GDGDdWBVk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750176644; 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charset="utf-8" From: Eric Auger Reviewed-by: Richard Henderson Reviewed-by: Sebastian Ott Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- target/arm/cpu-features.h | 44 +++++++++++++++++++-------------------- target/arm/cpu.c | 13 ++++-------- target/arm/cpu.h | 2 -- target/arm/cpu64.c | 9 ++++---- target/arm/helper.c | 4 ++-- target/arm/hvf/hvf.c | 2 +- target/arm/kvm.c | 6 ++---- target/arm/tcg/cpu64.c | 24 ++++++++++----------- 8 files changed, 48 insertions(+), 56 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 6a47f1a6d222..43c9695be0d0 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -468,17 +468,17 @@ static inline bool isar_feature_aa64_tlbios(const ARM= ISARegisters *id) =20 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, JSCVT) !=3D 0; } =20 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, FCMA) !=3D 0; } =20 static inline bool isar_feature_aa64_xs(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, XS) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, XS) !=3D 0; } =20 /* @@ -502,9 +502,9 @@ isar_feature_pauth_feature(const ARMISARegisters *id) * Architecturally, only one of {APA,API,APA3} may be active (non-zero) * and the other two must be zero. Thus we may avoid conditionals. */ - return (FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) | - FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, API) | - FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3)); + return (FIELD_EX64_IDREG(id, ID_AA64ISAR1, APA) | + FIELD_EX64_IDREG(id, ID_AA64ISAR1, API) | + FIELD_EX64_IDREG(id, ID_AA64ISAR2, APA3)); } =20 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) @@ -522,7 +522,7 @@ static inline bool isar_feature_aa64_pauth_qarma5(const= ARMISARegisters *id) * Return true if pauth is enabled with the architected QARMA5 algorit= hm. * QEMU will always enable or disable both APA and GPA. */ - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, APA) !=3D 0; } =20 static inline bool isar_feature_aa64_pauth_qarma3(const ARMISARegisters *i= d) @@ -531,77 +531,77 @@ static inline bool isar_feature_aa64_pauth_qarma3(con= st ARMISARegisters *id) * Return true if pauth is enabled with the architected QARMA3 algorit= hm. * QEMU will always enable or disable both APA3 and GPA3. */ - return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR2, APA3) !=3D 0; } =20 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, SB) !=3D 0; } =20 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, SPECRES) !=3D 0; } =20 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, FRINTTS) !=3D 0; } =20 static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, DPB) !=3D 0; } =20 static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, DPB) >=3D 2; } =20 static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, BF16) !=3D 0; } =20 static inline bool isar_feature_aa64_ebf16(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) > 1; + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, BF16) > 1; } =20 static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, LRCPC) !=3D 0; } =20 static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, LRCPC) >=3D 2; } =20 static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, I8MM) !=3D 0; } =20 static inline bool isar_feature_aa64_wfxt(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, WFXT) >=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64ISAR2, WFXT) >=3D 2; } =20 static inline bool isar_feature_aa64_hbc(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, BC) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR2, BC) !=3D 0; } =20 static inline bool isar_feature_aa64_mops(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, MOPS); + return FIELD_EX64_IDREG(id, ID_AA64ISAR2, MOPS); } =20 static inline bool isar_feature_aa64_rpres(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, RPRES); + return FIELD_EX64_IDREG(id, ID_AA64ISAR2, RPRES); } =20 static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f033411b5dad..2777de729445 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2123,9 +2123,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) uint64_t t; uint32_t u; =20 - t =3D cpu->isar.id_aa64isar1; - t =3D FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); - cpu->isar.id_aa64isar1 =3D t; + FIELD_DP64_IDREG(isar, ID_AA64ISAR1, JSCVT, 0); =20 t =3D cpu->isar.id_aa64pfr0; t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); @@ -2178,11 +2176,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 0); SET_IDREG(isar, ID_AA64ISAR0, t); =20 - t =3D cpu->isar.id_aa64isar1; + t =3D GET_IDREG(isar, ID_AA64ISAR1); t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); t =3D FIELD_DP64(t, ID_AA64ISAR1, BF16, 0); t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); - cpu->isar.id_aa64isar1 =3D t; + SET_IDREG(isar, ID_AA64ISAR1, t); =20 t =3D cpu->isar.id_aa64pfr0; t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); @@ -2218,14 +2216,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) } =20 if (!cpu->has_neon && !cpu->has_vfp) { - uint64_t t; uint32_t u; =20 FIELD_DP64_IDREG(isar, ID_AA64ISAR0, FHM, 0); =20 - t =3D cpu->isar.id_aa64isar1; - t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); - cpu->isar.id_aa64isar1 =3D t; + FIELD_DP64_IDREG(isar, ID_AA64ISAR1, FRINTTS, 0); =20 u =3D cpu->isar.mvfr0; u =3D FIELD_DP32(u, MVFR0, SIMDREG, 0); diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7b5c7a4abc7e..b81bc46966f5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1074,8 +1074,6 @@ struct ArchCPU { uint32_t dbgdidr; uint32_t dbgdevid; uint32_t dbgdevid1; - uint64_t id_aa64isar1; - uint64_t id_aa64isar2; uint64_t id_aa64pfr0; uint64_t id_aa64pfr1; uint64_t id_aa64mmfr0; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index c105fcc4ea57..e2b25b004311 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -502,6 +502,7 @@ void aarch64_add_sme_properties(Object *obj) void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { ARMPauthFeature features =3D cpu_isar_feature(pauth_feature, cpu); + ARMISARegisters *isar =3D &cpu->isar; uint64_t isar1, isar2; =20 /* @@ -512,13 +513,13 @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) * * Begin by disabling all fields. */ - isar1 =3D cpu->isar.id_aa64isar1; + isar1 =3D GET_IDREG(isar, ID_AA64ISAR1); isar1 =3D FIELD_DP64(isar1, ID_AA64ISAR1, APA, 0); isar1 =3D FIELD_DP64(isar1, ID_AA64ISAR1, GPA, 0); isar1 =3D FIELD_DP64(isar1, ID_AA64ISAR1, API, 0); isar1 =3D FIELD_DP64(isar1, ID_AA64ISAR1, GPI, 0); =20 - isar2 =3D cpu->isar.id_aa64isar2; + isar2 =3D GET_IDREG(isar, ID_AA64ISAR2); isar2 =3D FIELD_DP64(isar2, ID_AA64ISAR2, APA3, 0); isar2 =3D FIELD_DP64(isar2, ID_AA64ISAR2, GPA3, 0); =20 @@ -580,8 +581,8 @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) } } =20 - cpu->isar.id_aa64isar1 =3D isar1; - cpu->isar.id_aa64isar2 =3D isar2; + SET_IDREG(isar, ID_AA64ISAR1, isar1); + SET_IDREG(isar, ID_AA64ISAR2, isar2); } =20 static const Property arm_cpu_pauth_property =3D diff --git a/target/arm/helper.c b/target/arm/helper.c index 2457c8853c60..2caaa49b91f9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8008,12 +8008,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64isar1 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64ISAR1)}, { .name =3D "ID_AA64ISAR2_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64isar2 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64ISAR2)}, { .name =3D "ID_AA64ISAR3_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 3, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 5d25260c5c36..7554282410f1 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -868,7 +868,7 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.id_aa64dfr0 }, { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 }, { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.idregs[ID_AA64ISAR0_EL1_= IDX] }, - { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.id_aa64isar1 }, + { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.idregs[ID_AA64ISAR1_EL1_= IDX] }, /* Add ID_AA64ISAR2_EL1 here when HVF supports it */ { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 }, { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 }, diff --git a/target/arm/kvm.c b/target/arm/kvm.c index bd33b0f656ed..6fa5bdff42a2 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -323,10 +323,8 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFe= atures *ahcf) err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1, ARM64_SYS_REG(3, 0, 0, 5, 1)); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64ISAR0_EL1_IDX); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1, - ARM64_SYS_REG(3, 0, 0, 6, 1)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar2, - ARM64_SYS_REG(3, 0, 0, 6, 2)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64ISAR1_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64ISAR2_EL1_IDX); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr0, ARM64_SYS_REG(3, 0, 0, 7, 0)); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1, diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index ed681ee08b0d..917502647246 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -68,7 +68,7 @@ static void aarch64_a35_initfn(Object *obj) cpu->isar.id_aa64dfr0 =3D 0x10305106; cpu->isar.id_aa64dfr1 =3D 0; SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); - cpu->isar.id_aa64isar1 =3D 0; + SET_IDREG(isar, ID_AA64ISAR1, 0); cpu->isar.id_aa64mmfr0 =3D 0x00101122; cpu->isar.id_aa64mmfr1 =3D 0; cpu->clidr =3D 0x0a200023; @@ -224,7 +224,7 @@ static void aarch64_a55_initfn(Object *obj) cpu->dcz_blocksize =3D 4; /* 64 bytes */ cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); - cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; + SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull); cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; @@ -357,7 +357,7 @@ static void aarch64_a76_initfn(Object *obj) cpu->dcz_blocksize =3D 4; cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); - cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; + SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull); cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; @@ -437,7 +437,7 @@ static void aarch64_a64fx_initfn(Object *obj) cpu->isar.id_aa64mmfr1 =3D 0x0000000011212100; cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011; SET_IDREG(isar, ID_AA64ISAR0, 0x0000000010211120); - cpu->isar.id_aa64isar1 =3D 0x0000000000010001; + SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000010001); SET_IDREG(isar, ID_AA64ZFR0, 0x0000000000000000); cpu->clidr =3D 0x0000000080000023; /* 64KB L1 dcache */ @@ -605,7 +605,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj) cpu->dcz_blocksize =3D 4; cpu->isar.id_aa64dfr0 =3D 0x0000000110305408ull; SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); - cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; + SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull); cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; @@ -684,7 +684,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj) cpu->isar.id_aa64dfr0 =3D 0x000001f210305519ull; cpu->isar.id_aa64dfr1 =3D 0x00000000; SET_IDREG(isar, ID_AA64ISAR0, 0x1011111110212120ull); /* with FEAT_RNG= */ - cpu->isar.id_aa64isar1 =3D 0x0011100001211032ull; + SET_IDREG(isar, ID_AA64ISAR1, 0x0011000001211032ull); cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; cpu->isar.id_aa64mmfr2 =3D 0x0220011102101011ull; @@ -933,7 +933,7 @@ static void aarch64_a710_initfn(Object *obj) cpu->id_aa64afr0 =3D 0; cpu->id_aa64afr1 =3D 0; SET_IDREG(isar, ID_AA64ISAR0, 0x0221111110212120ull); /* with Crypto */ - cpu->isar.id_aa64isar1 =3D 0x0010111101211052ull; + SET_IDREG(isar, ID_AA64ISAR1, 0x0010111101211052ull); cpu->isar.id_aa64mmfr0 =3D 0x0000022200101122ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; cpu->isar.id_aa64mmfr2 =3D 0x1221011110101011ull; @@ -1035,7 +1035,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj) cpu->id_aa64afr0 =3D 0; cpu->id_aa64afr1 =3D 0; SET_IDREG(isar, ID_AA64ISAR0, 0x1221111110212120ull); /* with Crypto a= nd FEAT_RNG */ - cpu->isar.id_aa64isar1 =3D 0x0011111101211052ull; + SET_IDREG(isar, ID_AA64ISAR1, 0x0011111101211052ull); cpu->isar.id_aa64mmfr0 =3D 0x0000022200101125ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; cpu->isar.id_aa64mmfr2 =3D 0x1221011112101011ull; @@ -1160,7 +1160,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */ SET_IDREG(isar, ID_AA64ISAR0, t); =20 - t =3D cpu->isar.id_aa64isar1; + t =3D GET_IDREG(isar, ID_AA64ISAR1); t =3D FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */ t =3D FIELD_DP64(t, ID_AA64ISAR1, APA, PauthFeat_FPACCOMBINED); t =3D FIELD_DP64(t, ID_AA64ISAR1, API, 1); @@ -1174,14 +1174,14 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */ t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ t =3D FIELD_DP64(t, ID_AA64ISAR1, XS, 1); /* FEAT_XS */ - cpu->isar.id_aa64isar1 =3D t; + SET_IDREG(isar, ID_AA64ISAR1, t); =20 - t =3D cpu->isar.id_aa64isar2; + t =3D GET_IDREG(isar, ID_AA64ISAR2); t =3D FIELD_DP64(t, ID_AA64ISAR2, RPRES, 1); /* FEAT_RPRES */ t =3D FIELD_DP64(t, ID_AA64ISAR2, MOPS, 1); /* FEAT_MOPS */ t =3D FIELD_DP64(t, ID_AA64ISAR2, BC, 1); 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charset="utf-8" From: Eric Auger Reviewed-by: Richard Henderson Reviewed-by: Sebastian Ott Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- target/arm/cpu-features.h | 40 ++++++++++++++++----------------- target/arm/cpu.c | 29 ++++++++---------------- target/arm/cpu.h | 2 -- target/arm/cpu64.c | 14 ++++-------- target/arm/helper.c | 6 ++--- target/arm/hvf/hvf.c | 9 ++++---- target/arm/kvm.c | 12 +++++----- target/arm/tcg/cpu64.c | 47 ++++++++++++++++++--------------------- 8 files changed, 68 insertions(+), 91 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 43c9695be0d0..3adea85b79b7 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -607,68 +607,68 @@ static inline bool isar_feature_aa64_rpres(const ARMI= SARegisters *id) static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) { /* We always set the AdvSIMD and FP fields identically. */ - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) !=3D 0xf; + return FIELD_EX64_IDREG(id, ID_AA64PFR0, FP) !=3D 0xf; } =20 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) { /* We always set the AdvSIMD and FP fields identically wrt FP16. */ - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) =3D=3D 1; + return FIELD_EX64_IDREG(id, ID_AA64PFR0, FP) =3D=3D 1; } =20 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64PFR0, EL0) >=3D 2; } =20 static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64PFR0, EL1) >=3D 2; } =20 static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL2) >=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64PFR0, EL2) >=3D 2; } =20 static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64PFR0, RAS) !=3D 0; } =20 static inline bool isar_feature_aa64_doublefault(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) >=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64PFR0, RAS) >=3D 2; } =20 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64PFR0, SVE) !=3D 0; } =20 static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64PFR0, SEL2) !=3D 0; } =20 static inline bool isar_feature_aa64_rme(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RME) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64PFR0, RME) !=3D 0; } =20 static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64PFR0, DIT) !=3D 0; } =20 static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id) { - int key =3D FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2); + int key =3D FIELD_EX64_IDREG(id, ID_AA64PFR0, CSV2); if (key >=3D 2) { return true; /* FEAT_CSV2_2 */ } if (key =3D=3D 1) { - key =3D FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC); + key =3D FIELD_EX64_IDREG(id, ID_AA64PFR1, CSV2_FRAC); return key >=3D 2; /* FEAT_CSV2_1p2 */ } return false; @@ -676,37 +676,37 @@ static inline bool isar_feature_aa64_scxtnum(const AR= MISARegisters *id) =20 static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64PFR1, SSBS) !=3D 0; } =20 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64PFR1, BT) !=3D 0; } =20 static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *i= d) { - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64PFR1, MTE) !=3D 0; } =20 static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64PFR1, MTE) >=3D 2; } =20 static inline bool isar_feature_aa64_mte3(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >=3D 3; + return FIELD_EX64_IDREG(id, ID_AA64PFR1, MTE) >=3D 3; } =20 static inline bool isar_feature_aa64_sme(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64PFR1, SME) !=3D 0; } =20 static inline bool isar_feature_aa64_nmi(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, NMI) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64PFR1, NMI) !=3D 0; } =20 static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2777de729445..d39e8dc95604 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2120,14 +2120,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) } =20 if (!cpu->has_vfp) { - uint64_t t; uint32_t u; =20 FIELD_DP64_IDREG(isar, ID_AA64ISAR1, JSCVT, 0); =20 - t =3D cpu->isar.id_aa64pfr0; - t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); - cpu->isar.id_aa64pfr0 =3D t; + FIELD_DP64_IDREG(isar, ID_AA64PFR0, FP, 0xf); =20 u =3D cpu->isar.id_isar6; u =3D FIELD_DP32(u, ID_ISAR6, JSCVT, 0); @@ -2182,9 +2179,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); SET_IDREG(isar, ID_AA64ISAR1, t); =20 - t =3D cpu->isar.id_aa64pfr0; - t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); - cpu->isar.id_aa64pfr0 =3D t; + FIELD_DP64_IDREG(isar, ID_AA64PFR0, ADVSIMD, 0xf); =20 u =3D cpu->isar.id_isar5; u =3D FIELD_DP32(u, ID_ISAR5, AES, 0); @@ -2326,12 +2321,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) */ cpu->isar.id_pfr1 =3D FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECUR= ITY, 0); cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSD= BG, 0); - cpu->isar.id_aa64pfr0 =3D FIELD_DP64(cpu->isar.id_aa64pfr0, - ID_AA64PFR0, EL3, 0); + FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL3, 0); =20 /* Disable the realm management extension, which requires EL3. */ - cpu->isar.id_aa64pfr0 =3D FIELD_DP64(cpu->isar.id_aa64pfr0, - ID_AA64PFR0, RME, 0); + FIELD_DP64_IDREG(isar, ID_AA64PFR0, RME, 0); } =20 if (!cpu->has_el2) { @@ -2366,8 +2359,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * Disable the hypervisor feature bits in the processor feature * registers if we don't have EL2. */ - cpu->isar.id_aa64pfr0 =3D FIELD_DP64(cpu->isar.id_aa64pfr0, - ID_AA64PFR0, EL2, 0); + FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL2, 0); cpu->isar.id_pfr1 =3D FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, VIRTUALIZATION, 0); } @@ -2388,8 +2380,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * This matches Cortex-A710 BROADCASTMTE input being LOW. */ if (tcg_enabled() && cpu->tag_memory =3D=3D NULL) { - cpu->isar.id_aa64pfr1 =3D - FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1); + FIELD_DP64_IDREG(isar, ID_AA64PFR1, MTE, 1); } =20 /* @@ -2397,7 +2388,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * enabled on the guest (i.e mte=3Doff), clear guest's MTE bits." */ if (kvm_enabled() && !cpu->kvm_mte) { - FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); + FIELD_DP64_IDREG(isar, ID_AA64PFR1, MTE, 0); } #endif } @@ -2436,13 +2427,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0); /* FEAT_AMU (Activity Monitors Extension) */ - cpu->isar.id_aa64pfr0 =3D - FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, AMU, 0); + FIELD_DP64_IDREG(isar, ID_AA64PFR0, AMU, 0); cpu->isar.id_pfr0 =3D FIELD_DP32(cpu->isar.id_pfr0, ID_PFR0, AMU, 0); /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */ - cpu->isar.id_aa64pfr0 =3D - FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, MPAM, 0); + FIELD_DP64_IDREG(isar, ID_AA64PFR0, MPAM, 0); } =20 /* MPU can be configured out of a PMSA CPU either by setting has-mpu diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b81bc46966f5..05157a49d75c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1074,8 +1074,6 @@ struct ArchCPU { uint32_t dbgdidr; uint32_t dbgdevid; uint32_t dbgdevid1; - uint64_t id_aa64pfr0; - uint64_t id_aa64pfr1; uint64_t id_aa64mmfr0; uint64_t id_aa64mmfr1; uint64_t id_aa64mmfr2; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index e2b25b004311..502aac91730d 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -310,16 +310,13 @@ static bool cpu_arm_get_sve(Object *obj, Error **errp) static void cpu_arm_set_sve(Object *obj, bool value, Error **errp) { ARMCPU *cpu =3D ARM_CPU(obj); - uint64_t t; =20 if (value && kvm_enabled() && !kvm_arm_sve_supported()) { error_setg(errp, "'sve' feature not supported by KVM on this host"= ); return; } =20 - t =3D cpu->isar.id_aa64pfr0; - t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, value); - cpu->isar.id_aa64pfr0 =3D t; + FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR0, SVE, value); } =20 void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp) @@ -370,11 +367,8 @@ static bool cpu_arm_get_sme(Object *obj, Error **errp) static void cpu_arm_set_sme(Object *obj, bool value, Error **errp) { ARMCPU *cpu =3D ARM_CPU(obj); - uint64_t t; =20 - t =3D cpu->isar.id_aa64pfr1; - t =3D FIELD_DP64(t, ID_AA64PFR1, SME, value); - cpu->isar.id_aa64pfr1 =3D t; + FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR1, SME, value); } =20 static bool cpu_arm_get_sme_fa64(Object *obj, Error **errp) @@ -676,7 +670,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->isar.id_isar4 =3D 0x00011142; cpu->isar.id_isar5 =3D 0x00011121; cpu->isar.id_isar6 =3D 0; - cpu->isar.id_aa64pfr0 =3D 0x00002222; + SET_IDREG(isar, ID_AA64PFR0, 0x00002222); cpu->isar.id_aa64dfr0 =3D 0x10305106; SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); cpu->isar.id_aa64mmfr0 =3D 0x00001124; @@ -738,7 +732,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->isar.id_isar4 =3D 0x00011142; cpu->isar.id_isar5 =3D 0x00011121; cpu->isar.id_isar6 =3D 0; - cpu->isar.id_aa64pfr0 =3D 0x00002222; + SET_IDREG(isar, ID_AA64PFR0, 0x00002222); cpu->isar.id_aa64dfr0 =3D 0x10305106; SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); cpu->isar.id_aa64mmfr0 =3D 0x00001122; /* 40 bit physical addr */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 2caaa49b91f9..2b7c963e026c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6943,7 +6943,7 @@ static uint64_t id_pfr1_read(CPUARMState *env, const = ARMCPRegInfo *ri) static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) { ARMCPU *cpu =3D env_archcpu(env); - uint64_t pfr0 =3D cpu->isar.id_aa64pfr0; + uint64_t pfr0 =3D GET_IDREG(&cpu->isar, ID_AA64PFR0); =20 if (env->gicv3state) { pfr0 |=3D 1 << 24; @@ -7916,7 +7916,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, #ifdef CONFIG_USER_ONLY .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->isar.id_aa64pfr0 + .resetvalue =3D GET_IDREG(isar, ID_AA64PFR0) #else .type =3D ARM_CP_NO_RAW, .accessfn =3D access_aa64_tid3, @@ -7928,7 +7928,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64pfr1}, + .resetvalue =3D GET_IDREG(isar, ID_AA64PFR1)}, { .name =3D "ID_AA64PFR2_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 7554282410f1..e1bfca5947c1 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -863,8 +863,8 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) int reg; uint64_t *val; } regs[] =3D { - { HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.id_aa64pfr0 }, - { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.id_aa64pfr1 }, + { HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.idregs[ID_AA64PFR0_EL1_ID= X] }, + { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.idregs[ID_AA64PFR1_EL1_ID= X] }, { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.id_aa64dfr0 }, { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 }, { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.idregs[ID_AA64ISAR0_EL1_= IDX] }, @@ -911,7 +911,8 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) * - fix any assumptions we made that SME implies SVE (since * on the M4 there is SME but not SVE) */ - host_isar.id_aa64pfr1 &=3D ~R_ID_AA64PFR1_SME_MASK; + SET_IDREG(&host_isar, ID_AA64PFR1, + GET_IDREG(&host_isar, ID_AA64PFR1) & ~R_ID_AA64PFR1_SME_MASK= ); =20 ahcf->isar =3D host_isar; =20 @@ -928,7 +929,7 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) ahcf->reset_sctlr |=3D 0x00800000; =20 /* Make sure we don't advertise AArch32 support for EL0/EL1 */ - if ((host_isar.id_aa64pfr0 & 0xff) !=3D 0x11) { + if ((GET_IDREG(&host_isar, ID_AA64PFR0) & 0xff) !=3D 0x11) { return false; } =20 diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 6fa5bdff42a2..1e19dba4cb07 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -292,8 +292,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) ahcf->dtb_compatible =3D "arm,arm-v8"; int fd =3D fdarray[2]; =20 - err =3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0, - ARM64_SYS_REG(3, 0, 0, 4, 0)); + err =3D get_host_cpu_reg(fd, ahcf, ID_AA64PFR0_EL1_IDX); if (unlikely(err < 0)) { /* * Before v4.15, the kernel only exposed a limited number of system @@ -311,11 +310,10 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUF= eatures *ahcf) * ??? Either of these sounds like too much effort just * to work around running a modern host kernel. */ - ahcf->isar.id_aa64pfr0 =3D 0x00000011; /* EL1&0, AArch64 only */ + SET_IDREG(&ahcf->isar, ID_AA64PFR0, 0x00000011); /* EL1&0, AArch64= only */ err =3D 0; } else { - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1, - ARM64_SYS_REG(3, 0, 0, 4, 1)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64PFR1_EL1_IDX); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0, ARM64_SYS_REG(3, 0, 0, 4, 5)); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr0, @@ -395,14 +393,14 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUF= eatures *ahcf) * arch/arm64/kvm/sys_regs.c:trap_dbgidr() does. * We only do this if the CPU supports AArch32 at EL1. */ - if (FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL1) >=3D 2) { + if (FIELD_EX32_IDREG(&ahcf->isar, ID_AA64PFR0, EL1) >=3D 2) { int wrps =3D FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, W= RPS); int brps =3D FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, B= RPS); int ctx_cmps =3D FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS); int version =3D 6; /* ARMv8 debug architecture */ bool has_el3 =3D - !!FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL3); + !!FIELD_EX32_IDREG(&ahcf->isar, ID_AA64PFR0, EL3); uint32_t dbgdidr =3D 0; =20 dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, WRPS, wrps); diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 917502647246..7a730c7974f0 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -63,8 +63,8 @@ static void aarch64_a35_initfn(Object *obj) cpu->isar.id_isar3 =3D 0x01112131; cpu->isar.id_isar4 =3D 0x00011142; cpu->isar.id_isar5 =3D 0x00011121; - cpu->isar.id_aa64pfr0 =3D 0x00002222; - cpu->isar.id_aa64pfr1 =3D 0; + SET_IDREG(isar, ID_AA64PFR0, 0x00002222); + SET_IDREG(isar, ID_AA64PFR1, 0); cpu->isar.id_aa64dfr0 =3D 0x10305106; cpu->isar.id_aa64dfr1 =3D 0; SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); @@ -158,11 +158,8 @@ static bool cpu_arm_get_rme(Object *obj, Error **errp) static void cpu_arm_set_rme(Object *obj, bool value, Error **errp) { ARMCPU *cpu =3D ARM_CPU(obj); - uint64_t t; =20 - t =3D cpu->isar.id_aa64pfr0; - t =3D FIELD_DP64(t, ID_AA64PFR0, RME, value); - cpu->isar.id_aa64pfr0 =3D t; + FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR0, RME, value); } =20 static void cpu_max_set_l0gptsz(Object *obj, Visitor *v, const char *name, @@ -228,8 +225,8 @@ static void aarch64_a55_initfn(Object *obj) cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; - cpu->isar.id_aa64pfr0 =3D 0x0000000010112222ull; - cpu->isar.id_aa64pfr1 =3D 0x0000000000000010ull; + SET_IDREG(isar, ID_AA64PFR0, 0x0000000010112222ull); + SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_dfr0 =3D 0x04010088; cpu->isar.id_isar0 =3D 0x02101110; @@ -312,7 +309,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->isar.id_isar3 =3D 0x01112131; cpu->isar.id_isar4 =3D 0x00011142; cpu->isar.id_isar5 =3D 0x00011121; - cpu->isar.id_aa64pfr0 =3D 0x00002222; + SET_IDREG(isar, ID_AA64PFR0, 0x00002222); cpu->isar.id_aa64dfr0 =3D 0x10305106; SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); cpu->isar.id_aa64mmfr0 =3D 0x00001124; @@ -361,8 +358,8 @@ static void aarch64_a76_initfn(Object *obj) cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; - cpu->isar.id_aa64pfr0 =3D 0x1100000010111112ull; /* GIC filled in lat= er */ - cpu->isar.id_aa64pfr1 =3D 0x0000000000000010ull; + SET_IDREG(isar, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in = later */ + SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_dfr0 =3D 0x04010088; cpu->isar.id_isar0 =3D 0x02101110; @@ -427,8 +424,8 @@ static void aarch64_a64fx_initfn(Object *obj) cpu->revidr =3D 0x00000000; cpu->ctr =3D 0x86668006; cpu->reset_sctlr =3D 0x30000180; - cpu->isar.id_aa64pfr0 =3D 0x0000000101111111; /* No RAS Extensions */ - cpu->isar.id_aa64pfr1 =3D 0x0000000000000000; + SET_IDREG(isar, ID_AA64PFR0, 0x0000000101111111); /* No RAS Extensions= */ + SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000000); cpu->isar.id_aa64dfr0 =3D 0x0000000010305408; cpu->isar.id_aa64dfr1 =3D 0x0000000000000000; cpu->id_aa64afr0 =3D 0x0000000000000000; @@ -609,8 +606,8 @@ static void aarch64_neoverse_n1_initfn(Object *obj) cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; - cpu->isar.id_aa64pfr0 =3D 0x1100000010111112ull; /* GIC filled in lat= er */ - cpu->isar.id_aa64pfr1 =3D 0x0000000000000020ull; + SET_IDREG(isar, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in = later */ + SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_dfr0 =3D 0x04010088; cpu->isar.id_isar0 =3D 0x02101110; @@ -688,8 +685,8 @@ static void aarch64_neoverse_v1_initfn(Object *obj) cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; cpu->isar.id_aa64mmfr2 =3D 0x0220011102101011ull; - cpu->isar.id_aa64pfr0 =3D 0x1101110120111112ull; /* GIC filled in lat= er */ - cpu->isar.id_aa64pfr1 =3D 0x0000000000000020ull; + SET_IDREG(isar, ID_AA64PFR0, 0x1101110120111112ull); /* GIC filled in = later */ + SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_dfr0 =3D 0x15011099; cpu->isar.id_isar0 =3D 0x02101110; @@ -925,8 +922,8 @@ static void aarch64_a710_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x13211111; cpu->isar.mvfr2 =3D 0x00000043; cpu->isar.id_pfr2 =3D 0x00000011; - cpu->isar.id_aa64pfr0 =3D 0x1201111120111112ull; /* GIC filled in lat= er */ - cpu->isar.id_aa64pfr1 =3D 0x0000000000000221ull; + SET_IDREG(isar, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in = later */ + SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000221ull); SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */ cpu->isar.id_aa64dfr0 =3D 0x000011f010305619ull; cpu->isar.id_aa64dfr1 =3D 0; @@ -1027,8 +1024,8 @@ static void aarch64_neoverse_n2_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x13211111; cpu->isar.mvfr2 =3D 0x00000043; cpu->isar.id_pfr2 =3D 0x00000011; - cpu->isar.id_aa64pfr0 =3D 0x1201111120111112ull; /* GIC filled in lat= er */ - cpu->isar.id_aa64pfr1 =3D 0x0000000000000221ull; + SET_IDREG(isar, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in = later */ + SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000221ull); SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */ cpu->isar.id_aa64dfr0 =3D 0x000011f210305619ull; cpu->isar.id_aa64dfr1 =3D 0; @@ -1183,7 +1180,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR2, WFXT, 2); /* FEAT_WFxT */ SET_IDREG(isar, ID_AA64ISAR2, t); =20 - t =3D cpu->isar.id_aa64pfr0; + t =3D GET_IDREG(isar, ID_AA64PFR0); t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ t =3D FIELD_DP64(t, ID_AA64PFR0, RAS, 2); /* FEAT_RASv1p1 + FEAT= _DoubleFault */ @@ -1192,9 +1189,9 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ t =3D FIELD_DP64(t, ID_AA64PFR0, CSV2, 3); /* FEAT_CSV2_3 */ t =3D FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */ - cpu->isar.id_aa64pfr0 =3D t; + SET_IDREG(isar, ID_AA64PFR0, t); =20 - t =3D cpu->isar.id_aa64pfr1; + t =3D GET_IDREG(isar, ID_AA64PFR1); t =3D FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */ t =3D FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */ /* @@ -1207,7 +1204,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */ t =3D FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_3 */ t =3D FIELD_DP64(t, ID_AA64PFR1, NMI, 1); /* FEAT_NMI */ - cpu->isar.id_aa64pfr1 =3D t; + SET_IDREG(isar, ID_AA64PFR1, t); =20 t =3D cpu->isar.id_aa64mmfr0; t =3D FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */ --=20 2.49.0 From nobody Sat Nov 15 20:48:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" From: Eric Auger Reviewed-by: Richard Henderson Reviewed-by: Sebastian Ott Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- target/arm/cpu-features.h | 74 +++++++++++++++++++-------------------- target/arm/cpu.h | 4 --- target/arm/cpu64.c | 8 ++--- target/arm/helper.c | 8 ++--- target/arm/hvf/hvf.c | 21 ++++++----- target/arm/kvm.c | 12 +++---- target/arm/ptw.c | 6 ++-- target/arm/tcg/cpu64.c | 64 ++++++++++++++++----------------- 8 files changed, 95 insertions(+), 102 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 3adea85b79b7..89c9278639bf 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -711,192 +711,192 @@ static inline bool isar_feature_aa64_nmi(const ARMI= SARegisters *id) =20 static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) { - return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >=3D 1; + return FIELD_SEX64_IDREG(id, ID_AA64MMFR0, TGRAN4) >=3D 1; } =20 static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *= id) { - unsigned t =3D FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); + unsigned t =3D FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN4_2); return t >=3D 3 || (t =3D=3D 0 && isar_feature_aa64_tgran4_lpa2(id)); } =20 static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *i= d) { - return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN16) >=3D 2; } =20 static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters = *id) { - unsigned t =3D FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); + unsigned t =3D FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN16_2); return t >=3D 3 || (t =3D=3D 0 && isar_feature_aa64_tgran16_lpa2(id)); } =20 static inline bool isar_feature_aa64_tgran4(const ARMISARegisters *id) { - return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >=3D 0; + return FIELD_SEX64_IDREG(id, ID_AA64MMFR0, TGRAN4) >=3D 0; } =20 static inline bool isar_feature_aa64_tgran16(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >=3D 1; + return FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN16) >=3D 1; } =20 static inline bool isar_feature_aa64_tgran64(const ARMISARegisters *id) { - return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64) >=3D 0; + return FIELD_SEX64_IDREG(id, ID_AA64MMFR0, TGRAN64) >=3D 0; } =20 static inline bool isar_feature_aa64_tgran4_2(const ARMISARegisters *id) { - unsigned t =3D FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); + unsigned t =3D FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN4_2); return t >=3D 2 || (t =3D=3D 0 && isar_feature_aa64_tgran4(id)); } =20 static inline bool isar_feature_aa64_tgran16_2(const ARMISARegisters *id) { - unsigned t =3D FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); + unsigned t =3D FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN16_2); return t >=3D 2 || (t =3D=3D 0 && isar_feature_aa64_tgran16(id)); } =20 static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id) { - unsigned t =3D FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64_2); + unsigned t =3D FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN64_2); return t >=3D 2 || (t =3D=3D 0 && isar_feature_aa64_tgran64(id)); } =20 static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR0, FGT) !=3D 0; } =20 static inline bool isar_feature_aa64_ecv_traps(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR0, ECV) > 0; } =20 static inline bool isar_feature_aa64_ecv(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 1; + return FIELD_EX64_IDREG(id, ID_AA64MMFR0, ECV) > 1; } =20 static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR1, VH) !=3D 0; } =20 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR1, LO) !=3D 0; } =20 static inline bool isar_feature_aa64_pan(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR1, PAN) !=3D 0; } =20 static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64MMFR1, PAN) >=3D 2; } =20 static inline bool isar_feature_aa64_pan3(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >=3D 3; + return FIELD_EX64_IDREG(id, ID_AA64MMFR1, PAN) >=3D 3; } =20 static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR1, HCX) !=3D 0; } =20 static inline bool isar_feature_aa64_afp(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, AFP) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR1, AFP) !=3D 0; } =20 static inline bool isar_feature_aa64_tidcp1(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, TIDCP1) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR1, TIDCP1) !=3D 0; } =20 static inline bool isar_feature_aa64_cmow(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, CMOW) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR1, CMOW) !=3D 0; } =20 static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR1, HAFDBS) !=3D 0; } =20 static inline bool isar_feature_aa64_hdbs(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) >=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64MMFR1, HAFDBS) >=3D 2; } =20 static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR1, XNX) !=3D 0; } =20 static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR2, UAO) !=3D 0; } =20 static inline bool isar_feature_aa64_st(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR2, ST) !=3D 0; } =20 static inline bool isar_feature_aa64_lse2(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, AT) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR2, AT) !=3D 0; } =20 static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, FWB) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR2, FWB) !=3D 0; } =20 static inline bool isar_feature_aa64_ids(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR2, IDS) !=3D 0; } =20 static inline bool isar_feature_aa64_half_evt(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >=3D 1; + return FIELD_EX64_IDREG(id, ID_AA64MMFR2, EVT) >=3D 1; } =20 static inline bool isar_feature_aa64_evt(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64MMFR2, EVT) >=3D 2; } =20 static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR2, CCIDX) !=3D 0; } =20 static inline bool isar_feature_aa64_lva(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR2, VARANGE) !=3D 0; } =20 static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, E0PD) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR2, E0PD) !=3D 0; } =20 static inline bool isar_feature_aa64_nv(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, NV) !=3D 0; + return FIELD_EX64_IDREG(id, ID_AA64MMFR2, NV) !=3D 0; } =20 static inline bool isar_feature_aa64_nv2(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, NV) >=3D 2; + return FIELD_EX64_IDREG(id, ID_AA64MMFR2, NV) >=3D 2; } =20 static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 05157a49d75c..df9b7cc8c84c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1074,10 +1074,6 @@ struct ArchCPU { uint32_t dbgdidr; uint32_t dbgdevid; uint32_t dbgdevid1; - uint64_t id_aa64mmfr0; - uint64_t id_aa64mmfr1; - uint64_t id_aa64mmfr2; - uint64_t id_aa64mmfr3; uint64_t id_aa64dfr0; uint64_t id_aa64dfr1; uint64_t id_aa64smfr0; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 502aac91730d..500f3646bfad 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -623,12 +623,12 @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) return; } =20 - t =3D cpu->isar.id_aa64mmfr0; + t =3D GET_IDREG(&cpu->isar, ID_AA64MMFR0); t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 2); /* 16k pages w/ LPA2 = */ t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN4, 1); /* 4k pages w/ LPA2 = */ t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 3); /* 16k stage2 w/ LPA2= */ t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 3); /* 4k stage2 w/ LPA2= */ - cpu->isar.id_aa64mmfr0 =3D t; + SET_IDREG(&cpu->isar, ID_AA64MMFR0, t); } =20 static void aarch64_a57_initfn(Object *obj) @@ -673,7 +673,7 @@ static void aarch64_a57_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR0, 0x00002222); cpu->isar.id_aa64dfr0 =3D 0x10305106; SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); - cpu->isar.id_aa64mmfr0 =3D 0x00001124; + SET_IDREG(isar, ID_AA64MMFR0, 0x00001124); cpu->isar.dbgdidr =3D 0x3516d000; cpu->isar.dbgdevid =3D 0x01110f13; cpu->isar.dbgdevid1 =3D 0x2; @@ -735,7 +735,7 @@ static void aarch64_a53_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR0, 0x00002222); cpu->isar.id_aa64dfr0 =3D 0x10305106; SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); - cpu->isar.id_aa64mmfr0 =3D 0x00001122; /* 40 bit physical addr */ + SET_IDREG(isar, ID_AA64MMFR0, 0x00001122); /* 40 bit physical addr */ cpu->isar.dbgdidr =3D 0x3516d000; cpu->isar.dbgdevid =3D 0x00110f13; cpu->isar.dbgdevid1 =3D 0x1; diff --git a/target/arm/helper.c b/target/arm/helper.c index 2b7c963e026c..48fcd755dcdb 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8043,22 +8043,22 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64mmfr0 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64MMFR0)}, { .name =3D "ID_AA64MMFR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64mmfr1 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64MMFR1) }, { .name =3D "ID_AA64MMFR2_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64mmfr2 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64MMFR2) }, { .name =3D "ID_AA64MMFR3_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 3, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64mmfr3 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64MMFR3) }, { .name =3D "ID_AA64MMFR4_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index e1bfca5947c1..37a6303ec2a4 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -846,14 +846,17 @@ static uint64_t hvf_get_reg(CPUState *cpu, int rt) return val; } =20 -static void clamp_id_aa64mmfr0_parange_to_ipa_size(uint64_t *id_aa64mmfr0) +static void clamp_id_aa64mmfr0_parange_to_ipa_size(ARMISARegisters *isar) { uint32_t ipa_size =3D chosen_ipa_bit_size ? chosen_ipa_bit_size : hvf_arm_get_max_ipa_bit_size(); + uint64_t id_aa64mmfr0; =20 /* Clamp down the PARange to the IPA size the kernel supports. */ uint8_t index =3D round_down_to_parange_index(ipa_size); - *id_aa64mmfr0 =3D (*id_aa64mmfr0 & ~R_ID_AA64MMFR0_PARANGE_MASK) | ind= ex; + id_aa64mmfr0 =3D GET_IDREG(isar, ID_AA64MMFR0); + id_aa64mmfr0 =3D (id_aa64mmfr0 & ~R_ID_AA64MMFR0_PARANGE_MASK) | index; + SET_IDREG(isar, ID_AA64MMFR0, id_aa64mmfr0); } =20 static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) @@ -870,9 +873,9 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.idregs[ID_AA64ISAR0_EL1_= IDX] }, { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.idregs[ID_AA64ISAR1_EL1_= IDX] }, /* Add ID_AA64ISAR2_EL1 here when HVF supports it */ - { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 }, - { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 }, - { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.id_aa64mmfr2 }, + { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.idregs[ID_AA64MMFR0_EL1_= IDX] }, + { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.idregs[ID_AA64MMFR1_EL1_= IDX] }, + { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.idregs[ID_AA64MMFR2_EL1_= IDX] }, /* Add ID_AA64MMFR3_EL1 here when HVF supports it */ }; hv_vcpu_t fd; @@ -899,7 +902,7 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) r |=3D hv_vcpu_get_sys_reg(fd, HV_SYS_REG_MIDR_EL1, &ahcf->midr); r |=3D hv_vcpu_destroy(fd); =20 - clamp_id_aa64mmfr0_parange_to_ipa_size(&host_isar.id_aa64mmfr0); + clamp_id_aa64mmfr0_parange_to_ipa_size(&host_isar); =20 /* * Disable SME, which is not properly handled by QEMU hvf yet. @@ -1067,12 +1070,12 @@ int hvf_arch_init_vcpu(CPUState *cpu) =20 /* We're limited to underlying hardware caps, override internal versio= ns */ ret =3D hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64MMFR0_EL= 1, - &arm_cpu->isar.id_aa64mmfr0); + &arm_cpu->isar.idregs[ID_AA64MMFR0_EL1_IDX]); assert_hvf_ok(ret); =20 - clamp_id_aa64mmfr0_parange_to_ipa_size(&arm_cpu->isar.id_aa64mmfr0); + clamp_id_aa64mmfr0_parange_to_ipa_size(&arm_cpu->isar); ret =3D hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64MMFR0_EL= 1, - arm_cpu->isar.id_aa64mmfr0); + arm_cpu->isar.idregs[ID_AA64MMFR0_EL1_IDX]); assert_hvf_ok(ret); =20 return 0; diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 1e19dba4cb07..1dde96fbbda7 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -323,14 +323,10 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUF= eatures *ahcf) err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64ISAR0_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64ISAR1_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64ISAR2_EL1_IDX); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr0, - ARM64_SYS_REG(3, 0, 0, 7, 0)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1, - ARM64_SYS_REG(3, 0, 0, 7, 1)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2, - ARM64_SYS_REG(3, 0, 0, 7, 2)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr3, - ARM64_SYS_REG(3, 0, 0, 7, 3)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64MMFR0_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64MMFR1_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64MMFR2_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64MMFR3_EL1_IDX); =20 /* * Note that if AArch32 support is not present in the host, diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 44170d831cca..561bf2678e5a 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -122,7 +122,7 @@ unsigned int arm_pamax(ARMCPU *cpu) { if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { unsigned int parange =3D - FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); + FIELD_EX64_IDREG(&cpu->isar, ID_AA64MMFR0, PARANGE); =20 /* * id_aa64mmfr0 is a read-only register so values outside of the @@ -332,7 +332,7 @@ static bool granule_protection_check(CPUARMState *env, = uint64_t paddress, * physical address size is invalid. */ pps =3D FIELD_EX64(gpccr, GPCCR, PPS); - if (pps > FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE)) { + if (pps > FIELD_EX64_IDREG(&cpu->isar, ID_AA64MMFR0, PARANGE)) { goto fault_walk; } pps =3D pamax_map[pps]; @@ -1703,7 +1703,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, * ID_AA64MMFR0 is a read-only register so values outside of the * supported mappings can be considered an implementation error. */ - ps =3D FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); + ps =3D FIELD_EX64_IDREG(&cpu->isar, ID_AA64MMFR0, PARANGE); ps =3D MIN(ps, param.ps); assert(ps < ARRAY_SIZE(pamax_map)); outputsize =3D pamax_map[ps]; diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 7a730c7974f0..9efb7f0ce800 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -69,8 +69,8 @@ static void aarch64_a35_initfn(Object *obj) cpu->isar.id_aa64dfr1 =3D 0; SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); SET_IDREG(isar, ID_AA64ISAR1, 0); - cpu->isar.id_aa64mmfr0 =3D 0x00101122; - cpu->isar.id_aa64mmfr1 =3D 0; + SET_IDREG(isar, ID_AA64MMFR0, 0x00101122); + SET_IDREG(isar, ID_AA64MMFR1, 0); cpu->clidr =3D 0x0a200023; cpu->dcz_blocksize =3D 4; =20 @@ -222,9 +222,9 @@ static void aarch64_a55_initfn(Object *obj) cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull); - cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; - cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; - cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; + SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101122ull); + SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull); + SET_IDREG(isar, ID_AA64MMFR2, 0x0000000000001011ull); SET_IDREG(isar, ID_AA64PFR0, 0x0000000010112222ull); SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull); cpu->id_afr0 =3D 0x00000000; @@ -312,7 +312,7 @@ static void aarch64_a72_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR0, 0x00002222); cpu->isar.id_aa64dfr0 =3D 0x10305106; SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); - cpu->isar.id_aa64mmfr0 =3D 0x00001124; + SET_IDREG(isar, ID_AA64MMFR0, 0x00001124); cpu->isar.dbgdidr =3D 0x3516d000; cpu->isar.dbgdevid =3D 0x01110f13; cpu->isar.dbgdevid1 =3D 0x2; @@ -355,9 +355,9 @@ static void aarch64_a76_initfn(Object *obj) cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull); - cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; - cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; - cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; + SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101122ull); + SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull); + SET_IDREG(isar, ID_AA64MMFR2, 0x0000000000001011ull); SET_IDREG(isar, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in = later */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull); cpu->id_afr0 =3D 0x00000000; @@ -430,9 +430,9 @@ static void aarch64_a64fx_initfn(Object *obj) cpu->isar.id_aa64dfr1 =3D 0x0000000000000000; cpu->id_aa64afr0 =3D 0x0000000000000000; cpu->id_aa64afr1 =3D 0x0000000000000000; - cpu->isar.id_aa64mmfr0 =3D 0x0000000000001122; - cpu->isar.id_aa64mmfr1 =3D 0x0000000011212100; - cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011; + SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000001122); + SET_IDREG(isar, ID_AA64MMFR1, 0x0000000011212100); + SET_IDREG(isar, ID_AA64MMFR2, 0x0000000000001011); SET_IDREG(isar, ID_AA64ISAR0, 0x0000000010211120); SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000010001); SET_IDREG(isar, ID_AA64ZFR0, 0x0000000000000000); @@ -603,9 +603,9 @@ static void aarch64_neoverse_n1_initfn(Object *obj) cpu->isar.id_aa64dfr0 =3D 0x0000000110305408ull; SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull); - cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; - cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; - cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; + SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101125ull); + SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull); + SET_IDREG(isar, ID_AA64MMFR2, 0x0000000000001011ull); SET_IDREG(isar, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in = later */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull); cpu->id_afr0 =3D 0x00000000; @@ -682,9 +682,9 @@ static void aarch64_neoverse_v1_initfn(Object *obj) cpu->isar.id_aa64dfr1 =3D 0x00000000; SET_IDREG(isar, ID_AA64ISAR0, 0x1011111110212120ull); /* with FEAT_RNG= */ SET_IDREG(isar, ID_AA64ISAR1, 0x0011000001211032ull); - cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; - cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; - cpu->isar.id_aa64mmfr2 =3D 0x0220011102101011ull; + SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101125ull); + SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull), + SET_IDREG(isar, ID_AA64MMFR2, 0x0220011102101011ull), SET_IDREG(isar, ID_AA64PFR0, 0x1101110120111112ull); /* GIC filled in = later */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull); cpu->id_afr0 =3D 0x00000000; @@ -931,9 +931,9 @@ static void aarch64_a710_initfn(Object *obj) cpu->id_aa64afr1 =3D 0; SET_IDREG(isar, ID_AA64ISAR0, 0x0221111110212120ull); /* with Crypto */ SET_IDREG(isar, ID_AA64ISAR1, 0x0010111101211052ull); - cpu->isar.id_aa64mmfr0 =3D 0x0000022200101122ull; - cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; - cpu->isar.id_aa64mmfr2 =3D 0x1221011110101011ull; + SET_IDREG(isar, ID_AA64MMFR0, 0x0000022200101122ull); + SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull); + SET_IDREG(isar, ID_AA64MMFR2, 0x1221011110101011ull); cpu->clidr =3D 0x0000001482000023ull; cpu->gm_blocksize =3D 4; cpu->ctr =3D 0x000000049444c004ull; @@ -1033,9 +1033,9 @@ static void aarch64_neoverse_n2_initfn(Object *obj) cpu->id_aa64afr1 =3D 0; SET_IDREG(isar, ID_AA64ISAR0, 0x1221111110212120ull); /* with Crypto a= nd FEAT_RNG */ SET_IDREG(isar, ID_AA64ISAR1, 0x0011111101211052ull); - cpu->isar.id_aa64mmfr0 =3D 0x0000022200101125ull; - cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; - cpu->isar.id_aa64mmfr2 =3D 0x1221011112101011ull; + SET_IDREG(isar, ID_AA64MMFR0, 0x0000022200101125ull); + SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull); + SET_IDREG(isar, ID_AA64MMFR2, 0x1221011112101011ull); cpu->clidr =3D 0x0000001482000023ull; cpu->gm_blocksize =3D 4; cpu->ctr =3D 0x00000004b444c004ull; @@ -1206,7 +1206,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR1, NMI, 1); /* FEAT_NMI */ SET_IDREG(isar, ID_AA64PFR1, t); =20 - t =3D cpu->isar.id_aa64mmfr0; + t =3D GET_IDREG(isar, ID_AA64MMFR0); t =3D FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */ t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supporte= d */ t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 support= ed */ @@ -1214,9 +1214,9 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 support= ed */ t =3D FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* FEAT_FGT */ t =3D FIELD_DP64(t, ID_AA64MMFR0, ECV, 2); /* FEAT_ECV */ - cpu->isar.id_aa64mmfr0 =3D t; + SET_IDREG(isar, ID_AA64MMFR0, t); =20 - t =3D cpu->isar.id_aa64mmfr1; + t =3D GET_IDREG(isar, ID_AA64MMFR1); t =3D FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */ t =3D FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ @@ -1229,9 +1229,9 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR1, AFP, 1); /* FEAT_AFP */ t =3D FIELD_DP64(t, ID_AA64MMFR1, TIDCP1, 1); /* FEAT_TIDCP1 */ t =3D FIELD_DP64(t, ID_AA64MMFR1, CMOW, 1); /* FEAT_CMOW */ - cpu->isar.id_aa64mmfr1 =3D t; + SET_IDREG(isar, ID_AA64MMFR1, t); =20 - t =3D cpu->isar.id_aa64mmfr2; + t =3D GET_IDREG(isar, ID_AA64MMFR2); t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ t =3D FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */ @@ -1245,11 +1245,9 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2= */ t =3D FIELD_DP64(t, ID_AA64MMFR2, EVT, 2); /* FEAT_EVT */ t =3D FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */ - cpu->isar.id_aa64mmfr2 =3D t; + SET_IDREG(isar, ID_AA64MMFR2, t); =20 - t =3D cpu->isar.id_aa64mmfr3; - t =3D FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */ - cpu->isar.id_aa64mmfr3 =3D t; + FIELD_DP64_IDREG(isar, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPE= C */ =20 t =3D GET_IDREG(isar, ID_AA64ZFR0); t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); --=20 2.49.0 From nobody Sat Nov 15 20:48:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Eric Auger Reviewed-by: Richard Henderson Reviewed-by: Sebastian Ott Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- target/arm/cpu-features.h | 16 ++++++++-------- target/arm/cpu.c | 15 +++++---------- target/arm/cpu.h | 2 -- target/arm/cpu64.c | 4 ++-- target/arm/helper.c | 4 ++-- target/arm/hvf/hvf.c | 4 ++-- target/arm/internals.h | 6 +++--- target/arm/kvm.c | 12 +++++------- target/arm/tcg/cpu64.c | 32 ++++++++++++++++---------------- 9 files changed, 43 insertions(+), 52 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 89c9278639bf..9517e8a74c83 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -901,30 +901,30 @@ static inline bool isar_feature_aa64_nv2(const ARMISA= Registers *id) =20 static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >=3D 4 && - FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) !=3D 0xf; + return FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) >=3D 4 && + FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) !=3D 0xf; } =20 static inline bool isar_feature_aa64_pmuv3p4(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >=3D 5 && - FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) !=3D 0xf; + return FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) >=3D 5 && + FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) !=3D 0xf; } =20 static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >=3D 6 && - FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) !=3D 0xf; + return FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) >=3D 6 && + FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) !=3D 0xf; } =20 static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >=3D 8; + return FIELD_EX64_IDREG(id, ID_AA64DFR0, DEBUGVER) >=3D 8; } =20 static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id) { - return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >=3D 0; + return FIELD_SEX64_IDREG(id, ID_AA64DFR0, DOUBLELOCK) >=3D 0; } =20 static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d39e8dc95604..400bee849439 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2347,8 +2347,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) cpu); #endif } else { - cpu->isar.id_aa64dfr0 =3D - FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); + FIELD_DP64_IDREG(isar, ID_AA64DFR0, PMUVER, 0); cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFM= ON, 0); cpu->pmceid0 =3D 0; cpu->pmceid1 =3D 0; @@ -2408,19 +2407,15 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) * try to access the non-existent system registers for them. */ /* FEAT_SPE (Statistical Profiling Extension) */ - cpu->isar.id_aa64dfr0 =3D - FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0); + FIELD_DP64_IDREG(isar, ID_AA64DFR0, PMSVER, 0); /* FEAT_TRBE (Trace Buffer Extension) */ - cpu->isar.id_aa64dfr0 =3D - FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0); + FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEBUFFER, 0); /* FEAT_TRF (Self-hosted Trace Extension) */ - cpu->isar.id_aa64dfr0 =3D - FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0); + FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEFILT, 0); cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, TRACEFILT, 0); /* Trace Macrocell system register access */ - cpu->isar.id_aa64dfr0 =3D - FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEVER, 0); + FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEVER, 0); cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPTRC, 0); /* Memory mapped trace */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index df9b7cc8c84c..c7935377c6f8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1074,8 +1074,6 @@ struct ArchCPU { uint32_t dbgdidr; uint32_t dbgdevid; uint32_t dbgdevid1; - uint64_t id_aa64dfr0; - uint64_t id_aa64dfr1; uint64_t id_aa64smfr0; uint64_t reset_pmcr_el0; uint64_t idregs[NUM_ID_IDX]; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 500f3646bfad..a215ba8b479c 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -671,7 +671,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->isar.id_isar5 =3D 0x00011121; cpu->isar.id_isar6 =3D 0; SET_IDREG(isar, ID_AA64PFR0, 0x00002222); - cpu->isar.id_aa64dfr0 =3D 0x10305106; + SET_IDREG(isar, ID_AA64DFR0, 0x10305106); SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); SET_IDREG(isar, ID_AA64MMFR0, 0x00001124); cpu->isar.dbgdidr =3D 0x3516d000; @@ -733,7 +733,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->isar.id_isar5 =3D 0x00011121; cpu->isar.id_isar6 =3D 0; SET_IDREG(isar, ID_AA64PFR0, 0x00002222); - cpu->isar.id_aa64dfr0 =3D 0x10305106; + SET_IDREG(isar, ID_AA64DFR0, 0x10305106); SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); SET_IDREG(isar, ID_AA64MMFR0, 0x00001122); /* 40 bit physical addr */ cpu->isar.dbgdidr =3D 0x3516d000; diff --git a/target/arm/helper.c b/target/arm/helper.c index 48fcd755dcdb..bdfc2ee9d5cc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7963,12 +7963,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64dfr0 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64DFR0) }, { .name =3D "ID_AA64DFR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64dfr1 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64DFR1) }, { .name =3D "ID_AA64DFR2_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 37a6303ec2a4..5c95ccc5b8db 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -868,8 +868,8 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) } regs[] =3D { { HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.idregs[ID_AA64PFR0_EL1_ID= X] }, { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.idregs[ID_AA64PFR1_EL1_ID= X] }, - { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.id_aa64dfr0 }, - { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 }, + { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.idregs[ID_AA64DFR0_EL1_ID= X] }, + { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.idregs[ID_AA64DFR1_EL1_ID= X] }, { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.idregs[ID_AA64ISAR0_EL1_= IDX] }, { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.idregs[ID_AA64ISAR1_EL1_= IDX] }, /* Add ID_AA64ISAR2_EL1 here when HVF supports it */ diff --git a/target/arm/internals.h b/target/arm/internals.h index 3360de9150f7..6216f68c94f1 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1175,7 +1175,7 @@ static inline bool regime_using_lpae_format(CPUARMSta= te *env, ARMMMUIdx mmu_idx) static inline int arm_num_brps(ARMCPU *cpu) { if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) + 1; + return FIELD_EX64_IDREG(&cpu->isar, ID_AA64DFR0, BRPS) + 1; } else { return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, BRPS) + 1; } @@ -1189,7 +1189,7 @@ static inline int arm_num_brps(ARMCPU *cpu) static inline int arm_num_wrps(ARMCPU *cpu) { if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) + 1; + return FIELD_EX64_IDREG(&cpu->isar, ID_AA64DFR0, WRPS) + 1; } else { return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, WRPS) + 1; } @@ -1203,7 +1203,7 @@ static inline int arm_num_wrps(ARMCPU *cpu) static inline int arm_num_ctx_cmps(ARMCPU *cpu) { if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) + = 1; + return FIELD_EX64_IDREG(&cpu->isar, ID_AA64DFR0, CTX_CMPS) + 1; } else { return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, CTX_CMPS) + 1; } diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 1dde96fbbda7..479e5860e024 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -316,10 +316,8 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFe= atures *ahcf) err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64PFR1_EL1_IDX); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0, ARM64_SYS_REG(3, 0, 0, 4, 5)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr0, - ARM64_SYS_REG(3, 0, 0, 5, 0)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1, - ARM64_SYS_REG(3, 0, 0, 5, 1)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64DFR0_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64DFR1_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64ISAR0_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64ISAR1_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64ISAR2_EL1_IDX); @@ -390,10 +388,10 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUF= eatures *ahcf) * We only do this if the CPU supports AArch32 at EL1. */ if (FIELD_EX32_IDREG(&ahcf->isar, ID_AA64PFR0, EL1) >=3D 2) { - int wrps =3D FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, W= RPS); - int brps =3D FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, B= RPS); + int wrps =3D FIELD_EX64_IDREG(&ahcf->isar, ID_AA64DFR0, WRPS); + int brps =3D FIELD_EX64_IDREG(&ahcf->isar, ID_AA64DFR0, BRPS); int ctx_cmps =3D - FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS); + FIELD_EX64_IDREG(&ahcf->isar, ID_AA64DFR0, CTX_CMPS); int version =3D 6; /* ARMv8 debug architecture */ bool has_el3 =3D !!FIELD_EX32_IDREG(&ahcf->isar, ID_AA64PFR0, EL3); diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 9efb7f0ce800..7e18d31a2535 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -65,8 +65,8 @@ static void aarch64_a35_initfn(Object *obj) cpu->isar.id_isar5 =3D 0x00011121; SET_IDREG(isar, ID_AA64PFR0, 0x00002222); SET_IDREG(isar, ID_AA64PFR1, 0); - cpu->isar.id_aa64dfr0 =3D 0x10305106; - cpu->isar.id_aa64dfr1 =3D 0; + SET_IDREG(isar, ID_AA64DFR0, 0x10305106); + SET_IDREG(isar, ID_AA64DFR1, 0); SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); SET_IDREG(isar, ID_AA64ISAR1, 0); SET_IDREG(isar, ID_AA64MMFR0, 0x00101122); @@ -219,7 +219,7 @@ static void aarch64_a55_initfn(Object *obj) cpu->clidr =3D 0x82000023; cpu->ctr =3D 0x84448004; /* L1Ip =3D VIPT */ cpu->dcz_blocksize =3D 4; /* 64 bytes */ - cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; + SET_IDREG(isar, ID_AA64DFR0, 0x0000000010305408ull); SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull); SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101122ull); @@ -310,7 +310,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->isar.id_isar4 =3D 0x00011142; cpu->isar.id_isar5 =3D 0x00011121; SET_IDREG(isar, ID_AA64PFR0, 0x00002222); - cpu->isar.id_aa64dfr0 =3D 0x10305106; + SET_IDREG(isar, ID_AA64DFR0, 0x10305106); SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); SET_IDREG(isar, ID_AA64MMFR0, 0x00001124); cpu->isar.dbgdidr =3D 0x3516d000; @@ -352,7 +352,7 @@ static void aarch64_a76_initfn(Object *obj) cpu->clidr =3D 0x82000023; cpu->ctr =3D 0x8444C004; cpu->dcz_blocksize =3D 4; - cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; + SET_IDREG(isar, ID_AA64DFR0, 0x0000000010305408ull), SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull); SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101122ull); @@ -426,8 +426,8 @@ static void aarch64_a64fx_initfn(Object *obj) cpu->reset_sctlr =3D 0x30000180; SET_IDREG(isar, ID_AA64PFR0, 0x0000000101111111); /* No RAS Extensions= */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000000); - cpu->isar.id_aa64dfr0 =3D 0x0000000010305408; - cpu->isar.id_aa64dfr1 =3D 0x0000000000000000; + SET_IDREG(isar, ID_AA64DFR0, 0x0000000010305408), + SET_IDREG(isar, ID_AA64DFR1, 0x0000000000000000), cpu->id_aa64afr0 =3D 0x0000000000000000; cpu->id_aa64afr1 =3D 0x0000000000000000; SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000001122); @@ -600,7 +600,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj) cpu->clidr =3D 0x82000023; cpu->ctr =3D 0x8444c004; cpu->dcz_blocksize =3D 4; - cpu->isar.id_aa64dfr0 =3D 0x0000000110305408ull; + SET_IDREG(isar, ID_AA64DFR0, 0x0000000110305408ull); SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull); SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101125ull); @@ -678,8 +678,8 @@ static void aarch64_neoverse_v1_initfn(Object *obj) cpu->dcz_blocksize =3D 4; cpu->id_aa64afr0 =3D 0x00000000; cpu->id_aa64afr1 =3D 0x00000000; - cpu->isar.id_aa64dfr0 =3D 0x000001f210305519ull; - cpu->isar.id_aa64dfr1 =3D 0x00000000; + SET_IDREG(isar, ID_AA64DFR0, 0x000001f210305519ull), + SET_IDREG(isar, ID_AA64DFR1, 0x00000000), SET_IDREG(isar, ID_AA64ISAR0, 0x1011111110212120ull); /* with FEAT_RNG= */ SET_IDREG(isar, ID_AA64ISAR1, 0x0011000001211032ull); SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101125ull); @@ -925,8 +925,8 @@ static void aarch64_a710_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in = later */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000221ull); SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */ - cpu->isar.id_aa64dfr0 =3D 0x000011f010305619ull; - cpu->isar.id_aa64dfr1 =3D 0; + SET_IDREG(isar, ID_AA64DFR0, 0x000011f010305619ull); + SET_IDREG(isar, ID_AA64DFR1, 0); cpu->id_aa64afr0 =3D 0; cpu->id_aa64afr1 =3D 0; SET_IDREG(isar, ID_AA64ISAR0, 0x0221111110212120ull); /* with Crypto */ @@ -1027,8 +1027,8 @@ static void aarch64_neoverse_n2_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in = later */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000221ull); SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */ - cpu->isar.id_aa64dfr0 =3D 0x000011f210305619ull; - cpu->isar.id_aa64dfr1 =3D 0; + SET_IDREG(isar, ID_AA64DFR0, 0x000011f210305619ull); + SET_IDREG(isar, ID_AA64DFR1, 0); cpu->id_aa64afr0 =3D 0; cpu->id_aa64afr1 =3D 0; SET_IDREG(isar, ID_AA64ISAR0, 0x1221111110212120ull); /* with Crypto a= nd FEAT_RNG */ @@ -1261,11 +1261,11 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */ SET_IDREG(isar, ID_AA64ZFR0, t); =20 - t =3D cpu->isar.id_aa64dfr0; + t =3D GET_IDREG(isar, ID_AA64DFR0); t =3D FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 10); /* FEAT_Debugv8p8 */ t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); 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Tue, 17 Jun 2025 15:40:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1750174835; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xTD4VIeiVvYAk0yGQRr3unh/O18nIAWV5D1LTna5VBE=; b=YwFXhHg4GTu+tuUzMxON6hjzzuxmlvSzBt+ul72cK6dmy2+nn+DjEIDidl3O/wea3x5U9s kbJt3uKwqZ/4EbOdJquW4RKz3XF/6xyQx6TD84rAqPYHaISOBikjYmcuEFu0MJ4qOjskoc vRxBCPSENzcNzt2HRP9J1cGHpzIsBDk= X-MC-Unique: HgImXl-rNcOmj1HVUCogHg-1 X-Mimecast-MFC-AGG-ID: HgImXl-rNcOmj1HVUCogHg_1750174828 From: Cornelia Huck To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com, agraf@csgraf.de Cc: shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com, Cornelia Huck Subject: [PATCH v8 07/14] arm/cpu: Store aa64smfr0 into the idregs array Date: Tue, 17 Jun 2025 17:39:24 +0200 Message-ID: <20250617153931.1330449-8-cohuck@redhat.com> In-Reply-To: <20250617153931.1330449-1-cohuck@redhat.com> References: <20250617153931.1330449-1-cohuck@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: Eric Auger Reviewed-by: Richard Henderson Reviewed-by: Sebastian Ott Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- target/arm/cpu-features.h | 6 +++--- target/arm/cpu.h | 1 - target/arm/cpu64.c | 7 ++----- target/arm/helper.c | 2 +- target/arm/kvm.c | 3 +-- target/arm/tcg/cpu64.c | 4 ++-- 6 files changed, 9 insertions(+), 14 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 9517e8a74c83..051ed7b8847a 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -979,17 +979,17 @@ static inline bool isar_feature_aa64_sve_f64mm(const = ARMISARegisters *id) =20 static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, F64F64); + return FIELD_EX64_IDREG(id, ID_AA64SMFR0, F64F64); } =20 static inline bool isar_feature_aa64_sme_i16i64(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, I16I64) =3D=3D 0xf; + return FIELD_EX64_IDREG(id, ID_AA64SMFR0, I16I64) =3D=3D 0xf; } =20 static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, FA64); + return FIELD_EX64_IDREG(id, ID_AA64SMFR0, FA64); } =20 /* diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c7935377c6f8..1083ae7623b1 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1074,7 +1074,6 @@ struct ArchCPU { uint32_t dbgdidr; uint32_t dbgdevid; uint32_t dbgdevid1; - uint64_t id_aa64smfr0; uint64_t reset_pmcr_el0; uint64_t idregs[NUM_ID_IDX]; } isar; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index a215ba8b479c..0f938155d28e 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -328,7 +328,7 @@ void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp) =20 if (vq_map =3D=3D 0) { if (!cpu_isar_feature(aa64_sme, cpu)) { - cpu->isar.id_aa64smfr0 =3D 0; + SET_IDREG(&cpu->isar, ID_AA64SMFR0, 0); return; } =20 @@ -381,11 +381,8 @@ static bool cpu_arm_get_sme_fa64(Object *obj, Error **= errp) static void cpu_arm_set_sme_fa64(Object *obj, bool value, Error **errp) { ARMCPU *cpu =3D ARM_CPU(obj); - uint64_t t; =20 - t =3D cpu->isar.id_aa64smfr0; - t =3D FIELD_DP64(t, ID_AA64SMFR0, FA64, value); - cpu->isar.id_aa64smfr0 =3D t; + FIELD_DP64_IDREG(&cpu->isar, ID_AA64SMFR0, FA64, value); } =20 #ifdef CONFIG_USER_ONLY diff --git a/target/arm/helper.c b/target/arm/helper.c index bdfc2ee9d5cc..6ca85ea0cb5a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7948,7 +7948,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64smfr0 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64SMFR0)}, { .name =3D "ID_AA64PFR6_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 479e5860e024..873685586147 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -314,8 +314,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) err =3D 0; } else { err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64PFR1_EL1_IDX); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0, - ARM64_SYS_REG(3, 0, 0, 4, 5)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64SMFR0_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64DFR0_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64DFR1_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64ISAR0_EL1_IDX); diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 7e18d31a2535..80a99ab025da 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1267,7 +1267,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* FEAT_HPMN0 */ SET_IDREG(isar, ID_AA64DFR0, t); =20 - t =3D cpu->isar.id_aa64smfr0; + t =3D GET_IDREG(isar, ID_AA64SMFR0); t =3D FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */ t =3D FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* FEAT_SME */ t =3D FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* FEAT_SME */ @@ -1275,7 +1275,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* FEAT_SME_F64F64 */ t =3D FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* FEAT_SME_I16I64 */ t =3D FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* FEAT_SME_FA64 */ - cpu->isar.id_aa64smfr0 =3D t; + SET_IDREG(isar, ID_AA64SMFR0, t); =20 /* Replicate the same data to the 32-bit id registers. */ aa32_max_features(cpu); --=20 2.49.0 From nobody Sat Nov 15 20:48:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1750176265; cv=none; d=zohomail.com; s=zohoarc; b=DB3dp+m7Wr4usnRc/Up3PTBec1ShBOT+eE91hnschVKJK1drfFjR80bRjZ8bp4OYWx0timM4IiBc59rxkpjV/2QTwe39rVVU+0Yg76IPOgUIU9gIYdxIW+hMiYMhwn620pniOHfNZR9uaG9t5T688wB6uuUYYG1ho2VP+IuExyY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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charset="utf-8" From: Eric Auger Reviewed-by: Richard Henderson Reviewed-by: Sebastian Ott Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- hw/intc/armv7m_nvic.c | 12 ++-- target/arm/cpu-features.h | 36 +++++----- target/arm/cpu.c | 24 +++---- target/arm/cpu.h | 7 -- target/arm/cpu64.c | 28 ++++---- target/arm/helper.c | 14 ++-- target/arm/kvm.c | 21 ++---- target/arm/tcg/cpu-v7m.c | 90 +++++++++++++----------- target/arm/tcg/cpu32.c | 144 +++++++++++++++++++++----------------- target/arm/tcg/cpu64.c | 108 ++++++++++++++-------------- 10 files changed, 243 insertions(+), 241 deletions(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 83ff74f899f6..fdb7f58e3678 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1303,32 +1303,32 @@ static uint32_t nvic_readl(NVICState *s, uint32_t o= ffset, MemTxAttrs attrs) if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_isar0; + return GET_IDREG(&cpu->isar, ID_ISAR0); case 0xd64: /* ISAR1. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_isar1; + return GET_IDREG(&cpu->isar, ID_ISAR1); case 0xd68: /* ISAR2. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_isar2; + return GET_IDREG(&cpu->isar, ID_ISAR2); case 0xd6c: /* ISAR3. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_isar3; + return GET_IDREG(&cpu->isar, ID_ISAR3); case 0xd70: /* ISAR4. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_isar4; + return GET_IDREG(&cpu->isar, ID_ISAR4); case 0xd74: /* ISAR5. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_isar5; + return GET_IDREG(&cpu->isar, ID_ISAR5); case 0xd78: /* CLIDR */ return cpu->clidr; case 0xd7c: /* CTR */ diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 051ed7b8847a..75a2cc407793 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -46,93 +46,93 @@ */ static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR0, DIVIDE) !=3D 0; } =20 static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; + return FIELD_EX32_IDREG(id, ID_ISAR0, DIVIDE) > 1; } =20 static inline bool isar_feature_aa32_lob(const ARMISARegisters *id) { /* (M-profile) low-overhead loops and branch future */ - return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >=3D 3; + return FIELD_EX32_IDREG(id, ID_ISAR0, CMPBRANCH) >=3D 3; } =20 static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR1, JAZELLE) !=3D 0; } =20 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR5, AES) !=3D 0; } =20 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; + return FIELD_EX32_IDREG(id, ID_ISAR5, AES) > 1; } =20 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR5, SHA1) !=3D 0; } =20 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR5, SHA2) !=3D 0; } =20 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR5, CRC32) !=3D 0; } =20 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR5, RDM) !=3D 0; } =20 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR5, VCMA) !=3D 0; } =20 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR6, JSCVT) !=3D 0; } =20 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR6, DP) !=3D 0; } =20 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR6, FHM) !=3D 0; } =20 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR6, SB) !=3D 0; } =20 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR6, SPECRES) !=3D 0; } =20 static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar6, ID_ISAR6, BF16) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR6, BF16) !=3D 0; } =20 static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id) { - return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) !=3D 0; + return FIELD_EX32_IDREG(id, ID_ISAR6, I8MM) !=3D 0; } =20 static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 400bee849439..cf811e47d996 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2126,10 +2126,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) =20 FIELD_DP64_IDREG(isar, ID_AA64PFR0, FP, 0xf); =20 - u =3D cpu->isar.id_isar6; + u =3D GET_IDREG(isar, ID_ISAR6); u =3D FIELD_DP32(u, ID_ISAR6, JSCVT, 0); u =3D FIELD_DP32(u, ID_ISAR6, BF16, 0); - cpu->isar.id_isar6 =3D u; + SET_IDREG(isar, ID_ISAR6, u); =20 u =3D cpu->isar.mvfr0; u =3D FIELD_DP32(u, MVFR0, FPSP, 0); @@ -2181,20 +2181,20 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) =20 FIELD_DP64_IDREG(isar, ID_AA64PFR0, ADVSIMD, 0xf); =20 - u =3D cpu->isar.id_isar5; + u =3D GET_IDREG(isar, ID_ISAR5); u =3D FIELD_DP32(u, ID_ISAR5, AES, 0); u =3D FIELD_DP32(u, ID_ISAR5, SHA1, 0); u =3D FIELD_DP32(u, ID_ISAR5, SHA2, 0); u =3D FIELD_DP32(u, ID_ISAR5, RDM, 0); u =3D FIELD_DP32(u, ID_ISAR5, VCMA, 0); - cpu->isar.id_isar5 =3D u; + SET_IDREG(isar, ID_ISAR5, u); =20 - u =3D cpu->isar.id_isar6; + u =3D GET_IDREG(isar, ID_ISAR6); u =3D FIELD_DP32(u, ID_ISAR6, DP, 0); u =3D FIELD_DP32(u, ID_ISAR6, FHM, 0); u =3D FIELD_DP32(u, ID_ISAR6, BF16, 0); u =3D FIELD_DP32(u, ID_ISAR6, I8MM, 0); - cpu->isar.id_isar6 =3D u; + SET_IDREG(isar, ID_ISAR6, u); =20 if (!arm_feature(env, ARM_FEATURE_M)) { u =3D cpu->isar.mvfr1; @@ -2232,19 +2232,17 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) =20 unset_feature(env, ARM_FEATURE_THUMB_DSP); =20 - u =3D cpu->isar.id_isar1; - u =3D FIELD_DP32(u, ID_ISAR1, EXTEND, 1); - cpu->isar.id_isar1 =3D u; + FIELD_DP32_IDREG(isar, ID_ISAR1, EXTEND, 1); =20 - u =3D cpu->isar.id_isar2; + u =3D GET_IDREG(isar, ID_ISAR2); u =3D FIELD_DP32(u, ID_ISAR2, MULTU, 1); u =3D FIELD_DP32(u, ID_ISAR2, MULTS, 1); - cpu->isar.id_isar2 =3D u; + SET_IDREG(isar, ID_ISAR2, u); =20 - u =3D cpu->isar.id_isar3; + u =3D GET_IDREG(isar, ID_ISAR3); u =3D FIELD_DP32(u, ID_ISAR3, SIMD, 1); u =3D FIELD_DP32(u, ID_ISAR3, SATURATE, 0); - cpu->isar.id_isar3 =3D u; + SET_IDREG(isar, ID_ISAR3, u); } =20 =20 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1083ae7623b1..353c18e67993 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1050,13 +1050,6 @@ struct ArchCPU { * field by reading the value from the KVM vCPU. */ struct ARMISARegisters { - uint32_t id_isar0; - uint32_t id_isar1; - uint32_t id_isar2; - uint32_t id_isar3; - uint32_t id_isar4; - uint32_t id_isar5; - uint32_t id_isar6; uint32_t id_mmfr0; uint32_t id_mmfr1; uint32_t id_mmfr2; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 0f938155d28e..6be62c0711b2 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -660,13 +660,13 @@ static void aarch64_a57_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02102211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00011142; - cpu->isar.id_isar5 =3D 0x00011121; - cpu->isar.id_isar6 =3D 0; + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232042); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00011142); + SET_IDREG(isar, ID_ISAR5, 0x00011121); + SET_IDREG(isar, ID_ISAR6, 0); SET_IDREG(isar, ID_AA64PFR0, 0x00002222); SET_IDREG(isar, ID_AA64DFR0, 0x10305106); SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); @@ -722,13 +722,13 @@ static void aarch64_a53_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02102211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00011142; - cpu->isar.id_isar5 =3D 0x00011121; - cpu->isar.id_isar6 =3D 0; + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232042); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00011142); + SET_IDREG(isar, ID_ISAR5, 0x00011121); + SET_IDREG(isar, ID_ISAR6, 0); SET_IDREG(isar, ID_AA64PFR0, 0x00002222); SET_IDREG(isar, ID_AA64DFR0, 0x10305106); SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); diff --git a/target/arm/helper.c b/target/arm/helper.c index 6ca85ea0cb5a..669b7a84284a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7830,32 +7830,32 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_isar0 }, + .resetvalue =3D GET_IDREG(isar, ID_ISAR0)}, { .name =3D "ID_ISAR1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_isar1 }, + .resetvalue =3D GET_IDREG(isar, ID_ISAR1)}, { .name =3D "ID_ISAR2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_isar2 }, + .resetvalue =3D GET_IDREG(isar, ID_ISAR2)}, { .name =3D "ID_ISAR3", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 3, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_isar3 }, + .resetvalue =3D GET_IDREG(isar, ID_ISAR3) }, { .name =3D "ID_ISAR4", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_isar4 }, + .resetvalue =3D GET_IDREG(isar, ID_ISAR4) }, { .name =3D "ID_ISAR5", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_isar5 }, + .resetvalue =3D GET_IDREG(isar, ID_ISAR5) }, { .name =3D "ID_MMFR4", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, @@ -7865,7 +7865,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_isar6 }, + .resetvalue =3D GET_IDREG(isar, ID_ISAR6) }, }; define_arm_cp_regs(cpu, v6_idregs); define_arm_cp_regs(cpu, v6_cp_reginfo); diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 873685586147..eef9481737b5 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -346,22 +346,15 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUF= eatures *ahcf) ARM64_SYS_REG(3, 0, 0, 1, 6)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3, ARM64_SYS_REG(3, 0, 0, 1, 7)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, - ARM64_SYS_REG(3, 0, 0, 2, 0)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, - ARM64_SYS_REG(3, 0, 0, 2, 1)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2, - ARM64_SYS_REG(3, 0, 0, 2, 2)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3, - ARM64_SYS_REG(3, 0, 0, 2, 3)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4, - ARM64_SYS_REG(3, 0, 0, 2, 4)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5, - ARM64_SYS_REG(3, 0, 0, 2, 5)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_ISAR0_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_ISAR1_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_ISAR2_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_ISAR3_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_ISAR4_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_ISAR5_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_ISAR6_EL1_IDX); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4, ARM64_SYS_REG(3, 0, 0, 2, 6)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6, - ARM64_SYS_REG(3, 0, 0, 2, 7)); =20 err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, ARM64_SYS_REG(3, 0, 0, 3, 0)); diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 8e1a083b9118..198c9f3e98c3 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -45,6 +45,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int = interrupt_request) static void cortex_m0_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; set_feature(&cpu->env, ARM_FEATURE_V6); set_feature(&cpu->env, ARM_FEATURE_M); =20 @@ -66,18 +67,19 @@ static void cortex_m0_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x00000000; cpu->isar.id_mmfr2 =3D 0x00000000; cpu->isar.id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01141110; - cpu->isar.id_isar1 =3D 0x02111000; - cpu->isar.id_isar2 =3D 0x21112231; - cpu->isar.id_isar3 =3D 0x01111110; - cpu->isar.id_isar4 =3D 0x01310102; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; + SET_IDREG(isar, ID_ISAR0, 0x01141110); + SET_IDREG(isar, ID_ISAR1, 0x02111000); + SET_IDREG(isar, ID_ISAR2, 0x21112231); + SET_IDREG(isar, ID_ISAR3, 0x01111110); + SET_IDREG(isar, ID_ISAR4, 0x01310102); + SET_IDREG(isar, ID_ISAR5, 0x00000000); + SET_IDREG(isar, ID_ISAR6, 0x00000000); } =20 static void cortex_m3_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; set_feature(&cpu->env, ARM_FEATURE_V7); set_feature(&cpu->env, ARM_FEATURE_M); set_feature(&cpu->env, ARM_FEATURE_M_MAIN); @@ -91,18 +93,19 @@ static void cortex_m3_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x00000000; cpu->isar.id_mmfr2 =3D 0x00000000; cpu->isar.id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01141110; - cpu->isar.id_isar1 =3D 0x02111000; - cpu->isar.id_isar2 =3D 0x21112231; - cpu->isar.id_isar3 =3D 0x01111110; - cpu->isar.id_isar4 =3D 0x01310102; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; + SET_IDREG(isar, ID_ISAR0, 0x01141110); + SET_IDREG(isar, ID_ISAR1, 0x02111000); + SET_IDREG(isar, ID_ISAR2, 0x21112231); + SET_IDREG(isar, ID_ISAR3, 0x01111110); + SET_IDREG(isar, ID_ISAR4, 0x01310102); + SET_IDREG(isar, ID_ISAR5, 0x00000000); + SET_IDREG(isar, ID_ISAR6, 0x00000000); } =20 static void cortex_m4_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 set_feature(&cpu->env, ARM_FEATURE_V7); set_feature(&cpu->env, ARM_FEATURE_M); @@ -121,18 +124,19 @@ static void cortex_m4_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x00000000; cpu->isar.id_mmfr2 =3D 0x00000000; cpu->isar.id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01141110; - cpu->isar.id_isar1 =3D 0x02111000; - cpu->isar.id_isar2 =3D 0x21112231; - cpu->isar.id_isar3 =3D 0x01111110; - cpu->isar.id_isar4 =3D 0x01310102; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; + SET_IDREG(isar, ID_ISAR0, 0x01141110); + SET_IDREG(isar, ID_ISAR1, 0x02111000); + SET_IDREG(isar, ID_ISAR2, 0x21112231); + SET_IDREG(isar, ID_ISAR3, 0x01111110); + SET_IDREG(isar, ID_ISAR4, 0x01310102); + SET_IDREG(isar, ID_ISAR5, 0x00000000); + SET_IDREG(isar, ID_ISAR6, 0x00000000); } =20 static void cortex_m7_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 set_feature(&cpu->env, ARM_FEATURE_V7); set_feature(&cpu->env, ARM_FEATURE_M); @@ -151,18 +155,19 @@ static void cortex_m7_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x00000000; cpu->isar.id_mmfr2 =3D 0x01000000; cpu->isar.id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01101110; - cpu->isar.id_isar1 =3D 0x02112000; - cpu->isar.id_isar2 =3D 0x20232231; - cpu->isar.id_isar3 =3D 0x01111131; - cpu->isar.id_isar4 =3D 0x01310132; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; + SET_IDREG(isar, ID_ISAR0, 0x01101110); + SET_IDREG(isar, ID_ISAR1, 0x02112000); + SET_IDREG(isar, ID_ISAR2, 0x20232231); + SET_IDREG(isar, ID_ISAR3, 0x01111131); + SET_IDREG(isar, ID_ISAR4, 0x01310132); + SET_IDREG(isar, ID_ISAR5, 0x00000000); + SET_IDREG(isar, ID_ISAR6, 0x00000000); } =20 static void cortex_m33_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_M); @@ -183,13 +188,13 @@ static void cortex_m33_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x00000000; cpu->isar.id_mmfr2 =3D 0x01000000; cpu->isar.id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01101110; - cpu->isar.id_isar1 =3D 0x02212000; - cpu->isar.id_isar2 =3D 0x20232232; - cpu->isar.id_isar3 =3D 0x01111131; - cpu->isar.id_isar4 =3D 0x01310132; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; + SET_IDREG(isar, ID_ISAR0, 0x01101110); + SET_IDREG(isar, ID_ISAR1, 0x02212000); + SET_IDREG(isar, ID_ISAR2, 0x20232232); + SET_IDREG(isar, ID_ISAR3, 0x01111131); + SET_IDREG(isar, ID_ISAR4, 0x01310132); + SET_IDREG(isar, ID_ISAR5, 0x00000000); + SET_IDREG(isar, ID_ISAR6, 0x00000000); cpu->clidr =3D 0x00000000; cpu->ctr =3D 0x8000c000; } @@ -197,6 +202,7 @@ static void cortex_m33_initfn(Object *obj) static void cortex_m55_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_V8_1M); @@ -220,13 +226,13 @@ static void cortex_m55_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x00000000; cpu->isar.id_mmfr2 =3D 0x01000000; cpu->isar.id_mmfr3 =3D 0x00000011; - cpu->isar.id_isar0 =3D 0x01103110; - cpu->isar.id_isar1 =3D 0x02212000; - cpu->isar.id_isar2 =3D 0x20232232; - cpu->isar.id_isar3 =3D 0x01111131; - cpu->isar.id_isar4 =3D 0x01310132; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; + SET_IDREG(isar, ID_ISAR0, 0x01103110); + SET_IDREG(isar, ID_ISAR1, 0x02212000); + SET_IDREG(isar, ID_ISAR2, 0x20232232); + SET_IDREG(isar, ID_ISAR3, 0x01111131); + SET_IDREG(isar, ID_ISAR4, 0x01310132); + SET_IDREG(isar, ID_ISAR5, 0x00000000); + SET_IDREG(isar, ID_ISAR6, 0x00000000); cpu->clidr =3D 0x00000000; /* caches not implemented */ cpu->ctr =3D 0x8303c003; } diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 2c45b7eddda7..937a72b12c9b 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -23,18 +23,19 @@ void aa32_max_features(ARMCPU *cpu) { uint32_t t; + ARMISARegisters *isar =3D &cpu->isar; =20 /* Add additional features supported by QEMU */ - t =3D cpu->isar.id_isar5; + t =3D GET_IDREG(isar, ID_ISAR5); t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */ t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */ t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */ t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */ t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */ - cpu->isar.id_isar5 =3D t; + SET_IDREG(isar, ID_ISAR5, t); =20 - t =3D cpu->isar.id_isar6; + t =3D GET_IDREG(isar, ID_ISAR6); t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */ t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */ t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */ @@ -42,7 +43,7 @@ void aa32_max_features(ARMCPU *cpu) t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */ t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */ t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */ - cpu->isar.id_isar6 =3D t; + SET_IDREG(isar, ID_ISAR6, t); =20 t =3D cpu->isar.mvfr1; t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */ @@ -140,7 +141,7 @@ static void arm926_initfn(Object *obj) * ARMv5 does not have the ID_ISAR registers, but we can still * set the field to indicate Jazelle support within QEMU. */ - cpu->isar.id_isar1 =3D FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELL= E, 1); + FIELD_DP32_IDREG(&cpu->isar, ID_ISAR1, JAZELLE, 1); /* * Similarly, we need to set MVFR0 fields to enable vfp and short vect= or * support even though ARMv5 doesn't have this register. @@ -182,7 +183,7 @@ static void arm1026_initfn(Object *obj) * ARMv5 does not have the ID_ISAR registers, but we can still * set the field to indicate Jazelle support within QEMU. */ - cpu->isar.id_isar1 =3D FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELL= E, 1); + FIELD_DP32_IDREG(&cpu->isar, ID_ISAR1, JAZELLE, 1); /* * Similarly, we need to set MVFR0 fields to enable vfp and short vect= or * support even though ARMv5 doesn't have this register. @@ -206,6 +207,7 @@ static void arm1026_initfn(Object *obj) static void arm1136_r2_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; /* * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an * older core than plain "arm1136". In particular this does not @@ -233,17 +235,18 @@ static void arm1136_r2_initfn(Object *obj) cpu->isar.id_mmfr0 =3D 0x01130003; cpu->isar.id_mmfr1 =3D 0x10030302; cpu->isar.id_mmfr2 =3D 0x01222110; - cpu->isar.id_isar0 =3D 0x00140011; - cpu->isar.id_isar1 =3D 0x12002111; - cpu->isar.id_isar2 =3D 0x11231111; - cpu->isar.id_isar3 =3D 0x01102131; - cpu->isar.id_isar4 =3D 0x141; + SET_IDREG(isar, ID_ISAR0, 0x00140011); + SET_IDREG(isar, ID_ISAR1, 0x12002111); + SET_IDREG(isar, ID_ISAR2, 0x11231111); + SET_IDREG(isar, ID_ISAR3, 0x01102131); + SET_IDREG(isar, ID_ISAR4, 0x141); cpu->reset_auxcr =3D 7; } =20 static void arm1136_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,arm1136"; set_feature(&cpu->env, ARM_FEATURE_V6K); @@ -264,17 +267,18 @@ static void arm1136_initfn(Object *obj) cpu->isar.id_mmfr0 =3D 0x01130003; cpu->isar.id_mmfr1 =3D 0x10030302; cpu->isar.id_mmfr2 =3D 0x01222110; - cpu->isar.id_isar0 =3D 0x00140011; - cpu->isar.id_isar1 =3D 0x12002111; - cpu->isar.id_isar2 =3D 0x11231111; - cpu->isar.id_isar3 =3D 0x01102131; - cpu->isar.id_isar4 =3D 0x141; + SET_IDREG(isar, ID_ISAR0, 0x00140011); + SET_IDREG(isar, ID_ISAR1, 0x12002111); + SET_IDREG(isar, ID_ISAR2, 0x11231111); + SET_IDREG(isar, ID_ISAR3, 0x01102131); + SET_IDREG(isar, ID_ISAR4, 0x141); cpu->reset_auxcr =3D 7; } =20 static void arm1176_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,arm1176"; set_feature(&cpu->env, ARM_FEATURE_V6K); @@ -296,17 +300,18 @@ static void arm1176_initfn(Object *obj) cpu->isar.id_mmfr0 =3D 0x01130003; cpu->isar.id_mmfr1 =3D 0x10030302; cpu->isar.id_mmfr2 =3D 0x01222100; - cpu->isar.id_isar0 =3D 0x0140011; - cpu->isar.id_isar1 =3D 0x12002111; - cpu->isar.id_isar2 =3D 0x11231121; - cpu->isar.id_isar3 =3D 0x01102131; - cpu->isar.id_isar4 =3D 0x01141; + SET_IDREG(isar, ID_ISAR0, 0x0140011); + SET_IDREG(isar, ID_ISAR1, 0x12002111); + SET_IDREG(isar, ID_ISAR2, 0x11231121); + SET_IDREG(isar, ID_ISAR3, 0x01102131); + SET_IDREG(isar, ID_ISAR4, 0x01141); cpu->reset_auxcr =3D 7; } =20 static void arm11mpcore_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,arm11mpcore"; set_feature(&cpu->env, ARM_FEATURE_V6K); @@ -325,11 +330,11 @@ static void arm11mpcore_initfn(Object *obj) cpu->isar.id_mmfr0 =3D 0x01100103; cpu->isar.id_mmfr1 =3D 0x10020302; cpu->isar.id_mmfr2 =3D 0x01222000; - cpu->isar.id_isar0 =3D 0x00100011; - cpu->isar.id_isar1 =3D 0x12002111; - cpu->isar.id_isar2 =3D 0x11221011; - cpu->isar.id_isar3 =3D 0x01102131; - cpu->isar.id_isar4 =3D 0x141; + SET_IDREG(isar, ID_ISAR0, 0x00100011); + SET_IDREG(isar, ID_ISAR1, 0x12002111); + SET_IDREG(isar, ID_ISAR2, 0x11221011); + SET_IDREG(isar, ID_ISAR3, 0x01102131); + SET_IDREG(isar, ID_ISAR4, 0x141); cpu->reset_auxcr =3D 1; } =20 @@ -343,6 +348,7 @@ static const ARMCPRegInfo cortexa8_cp_reginfo[] =3D { static void cortex_a8_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,cortex-a8"; set_feature(&cpu->env, ARM_FEATURE_V7); @@ -365,11 +371,11 @@ static void cortex_a8_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x20000000; cpu->isar.id_mmfr2 =3D 0x01202000; cpu->isar.id_mmfr3 =3D 0x11; - cpu->isar.id_isar0 =3D 0x00101111; - cpu->isar.id_isar1 =3D 0x12112111; - cpu->isar.id_isar2 =3D 0x21232031; - cpu->isar.id_isar3 =3D 0x11112131; - cpu->isar.id_isar4 =3D 0x00111142; + SET_IDREG(isar, ID_ISAR0, 0x00101111); + SET_IDREG(isar, ID_ISAR1, 0x12112111); + SET_IDREG(isar, ID_ISAR2, 0x21232031); + SET_IDREG(isar, ID_ISAR3, 0x11112131); + SET_IDREG(isar, ID_ISAR4, 0x00111142); cpu->isar.dbgdidr =3D 0x15141000; cpu->clidr =3D (1 << 27) | (2 << 24) | 3; cpu->ccsidr[0] =3D 0xe007e01a; /* 16k L1 dcache. */ @@ -412,6 +418,7 @@ static const ARMCPRegInfo cortexa9_cp_reginfo[] =3D { static void cortex_a9_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,cortex-a9"; set_feature(&cpu->env, ARM_FEATURE_V7); @@ -440,11 +447,11 @@ static void cortex_a9_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x20000000; cpu->isar.id_mmfr2 =3D 0x01230000; cpu->isar.id_mmfr3 =3D 0x00002111; - cpu->isar.id_isar0 =3D 0x00101111; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232041; - cpu->isar.id_isar3 =3D 0x11112131; - cpu->isar.id_isar4 =3D 0x00111142; + SET_IDREG(isar, ID_ISAR0, 0x00101111); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232041); + SET_IDREG(isar, ID_ISAR3, 0x11112131); + SET_IDREG(isar, ID_ISAR4, 0x00111142); cpu->isar.dbgdidr =3D 0x35141000; cpu->clidr =3D (1 << 27) | (1 << 24) | 3; cpu->ccsidr[0] =3D 0xe00fe019; /* 16k L1 dcache. */ @@ -479,6 +486,7 @@ static const ARMCPRegInfo cortexa15_cp_reginfo[] =3D { static void cortex_a7_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,cortex-a7"; set_feature(&cpu->env, ARM_FEATURE_V7VE); @@ -509,11 +517,11 @@ static void cortex_a7_initfn(Object *obj) * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but * table 4-41 gives 0x02101110, which includes the arm div insns. */ - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232041; - cpu->isar.id_isar3 =3D 0x11112131; - cpu->isar.id_isar4 =3D 0x10011142; + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232041); + SET_IDREG(isar, ID_ISAR3, 0x11112131); + SET_IDREG(isar, ID_ISAR4, 0x10011142); cpu->isar.dbgdidr =3D 0x3515f005; cpu->isar.dbgdevid =3D 0x01110f13; cpu->isar.dbgdevid1 =3D 0x1; @@ -528,6 +536,7 @@ static void cortex_a7_initfn(Object *obj) static void cortex_a15_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 cpu->dtb_compatible =3D "arm,cortex-a15"; set_feature(&cpu->env, ARM_FEATURE_V7VE); @@ -556,11 +565,11 @@ static void cortex_a15_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x20000000; cpu->isar.id_mmfr2 =3D 0x01240000; cpu->isar.id_mmfr3 =3D 0x02102211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232041; - cpu->isar.id_isar3 =3D 0x11112131; - cpu->isar.id_isar4 =3D 0x10011142; + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232041); + SET_IDREG(isar, ID_ISAR3, 0x11112131); + SET_IDREG(isar, ID_ISAR4, 0x10011142); cpu->isar.dbgdidr =3D 0x3515f021; cpu->isar.dbgdevid =3D 0x01110f13; cpu->isar.dbgdevid1 =3D 0x0; @@ -585,6 +594,7 @@ static const ARMCPRegInfo cortexr5_cp_reginfo[] =3D { static void cortex_r5_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 set_feature(&cpu->env, ARM_FEATURE_V7); set_feature(&cpu->env, ARM_FEATURE_V7MP); @@ -599,13 +609,13 @@ static void cortex_r5_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x00000000; cpu->isar.id_mmfr2 =3D 0x01200000; cpu->isar.id_mmfr3 =3D 0x0211; - cpu->isar.id_isar0 =3D 0x02101111; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232141; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x0010142; - cpu->isar.id_isar5 =3D 0x0; - cpu->isar.id_isar6 =3D 0x0; + SET_IDREG(isar, ID_ISAR0, 0x02101111); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232141); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x0010142); + SET_IDREG(isar, ID_ISAR5, 0x0); + SET_IDREG(isar, ID_ISAR6, 0x0); cpu->mp_is_up =3D true; cpu->pmsav7_dregion =3D 16; cpu->isar.reset_pmcr_el0 =3D 0x41151800; @@ -720,6 +730,7 @@ static const ARMCPRegInfo cortex_r52_cp_reginfo[] =3D { static void cortex_r52_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 set_feature(&cpu->env, ARM_FEATURE_V8); set_feature(&cpu->env, ARM_FEATURE_EL2); @@ -746,12 +757,12 @@ static void cortex_r52_initfn(Object *obj) cpu->isar.id_mmfr2 =3D 0x01200000; cpu->isar.id_mmfr3 =3D 0xf0102211; cpu->isar.id_mmfr4 =3D 0x00000010; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232142; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00010142; - cpu->isar.id_isar5 =3D 0x00010001; + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232142); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00010142); + SET_IDREG(isar, ID_ISAR5, 0x00010001); cpu->isar.dbgdidr =3D 0x77168000; cpu->clidr =3D (1 << 27) | (1 << 24) | 0x3; cpu->ccsidr[0] =3D 0x700fe01a; /* 32KB L1 dcache */ @@ -949,6 +960,7 @@ static void pxa270c5_initfn(Object *obj) static void arm_max_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; =20 /* aarch64_a57_initfn, advertising none of the aarch64 features */ cpu->dtb_compatible =3D "arm,cortex-a57"; @@ -976,13 +988,13 @@ static void arm_max_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02102211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00011142; - cpu->isar.id_isar5 =3D 0x00011121; - cpu->isar.id_isar6 =3D 0; + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232042); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00011142); + SET_IDREG(isar, ID_ISAR5, 0x00011121); + SET_IDREG(isar, ID_ISAR6, 0); cpu->isar.reset_pmcr_el0 =3D 0x41013000; cpu->clidr =3D 0x0a200023; cpu->ccsidr[0] =3D 0x701fe00a; /* 32KB L1 dcache */ diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 80a99ab025da..dd4dc8ada564 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -57,12 +57,12 @@ static void aarch64_a35_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02102211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00011142; - cpu->isar.id_isar5 =3D 0x00011121; + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232042); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00011142); + SET_IDREG(isar, ID_ISAR5, 0x00011121); SET_IDREG(isar, ID_AA64PFR0, 0x00002222); SET_IDREG(isar, ID_AA64PFR1, 0); SET_IDREG(isar, ID_AA64DFR0, 0x10305106); @@ -229,13 +229,13 @@ static void aarch64_a55_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_dfr0 =3D 0x04010088; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00011142; - cpu->isar.id_isar5 =3D 0x01011121; - cpu->isar.id_isar6 =3D 0x00000010; + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232042); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00011142); + SET_IDREG(isar, ID_ISAR5, 0x01011121); + SET_IDREG(isar, ID_ISAR6, 0x00000010); cpu->isar.id_mmfr0 =3D 0x10201105; cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; @@ -303,12 +303,12 @@ static void aarch64_a72_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02102211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00011142; - cpu->isar.id_isar5 =3D 0x00011121; + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232042); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00011142); + SET_IDREG(isar, ID_ISAR5, 0x00011121); SET_IDREG(isar, ID_AA64PFR0, 0x00002222); SET_IDREG(isar, ID_AA64DFR0, 0x10305106); SET_IDREG(isar, ID_AA64ISAR0, 0x00011120); @@ -362,13 +362,13 @@ static void aarch64_a76_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_dfr0 =3D 0x04010088; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00010142; - cpu->isar.id_isar5 =3D 0x01011121; - cpu->isar.id_isar6 =3D 0x00000010; + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232042); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00010142); + SET_IDREG(isar, ID_ISAR5, 0x01011121); + SET_IDREG(isar, ID_ISAR6, 0x00000010); cpu->isar.id_mmfr0 =3D 0x10201105; cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; @@ -610,13 +610,13 @@ static void aarch64_neoverse_n1_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_dfr0 =3D 0x04010088; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00010142; - cpu->isar.id_isar5 =3D 0x01011121; - cpu->isar.id_isar6 =3D 0x00000010; + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232042); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00010142); + SET_IDREG(isar, ID_ISAR5, 0x01011121); + SET_IDREG(isar, ID_ISAR6, 0x00000010); cpu->isar.id_mmfr0 =3D 0x10201105; cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; @@ -689,13 +689,13 @@ static void aarch64_neoverse_v1_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_dfr0 =3D 0x15011099; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00010142; - cpu->isar.id_isar5 =3D 0x11011121; - cpu->isar.id_isar6 =3D 0x01100111; + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232042); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00010142); + SET_IDREG(isar, ID_ISAR5, 0x11011121); + SET_IDREG(isar, ID_ISAR6, 0x01100111); cpu->isar.id_mmfr0 =3D 0x10201105; cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; @@ -910,14 +910,14 @@ static void aarch64_a710_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02122211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00010142; - cpu->isar.id_isar5 =3D 0x11011121; /* with Crypto */ + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232042); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00010142); + SET_IDREG(isar, ID_ISAR5, 0x11011121); /* with Crypto */ cpu->isar.id_mmfr4 =3D 0x21021110; - cpu->isar.id_isar6 =3D 0x01111111; + SET_IDREG(isar, ID_ISAR6, 0x01111111); cpu->isar.mvfr0 =3D 0x10110222; cpu->isar.mvfr1 =3D 0x13211111; cpu->isar.mvfr2 =3D 0x00000043; @@ -1012,14 +1012,14 @@ static void aarch64_neoverse_n2_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02122211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232042; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x00010142; - cpu->isar.id_isar5 =3D 0x11011121; /* with Crypto */ + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232042); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00010142); + SET_IDREG(isar, ID_ISAR5, 0x11011121); /* with Crypto */ cpu->isar.id_mmfr4 =3D 0x01021110; - cpu->isar.id_isar6 =3D 0x01111111; + SET_IDREG(isar, ID_ISAR6, 0x01111111); cpu->isar.mvfr0 =3D 0x10110222; cpu->isar.mvfr1 =3D 0x13211111; cpu->isar.mvfr2 =3D 0x00000043; --=20 2.49.0 From nobody Sat Nov 15 20:48:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1750175977; cv=none; d=zohomail.com; s=zohoarc; b=KdDdmqRA8o6sP08e7lYmxG5sJJYFMjwqMK+ycIvSX+RmjfKqOY54RO6nJ4jvXEu26SM/b2aQsPm8/OPvlCVrt9vfAFw2aPOPMKU/Z8DP3ctA9IbUK/IJKnhTX+uLB7CM53VdsqHQvWDtUI+mj67XrmapPcoduKxdqNTIy5mRWO0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750175977; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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charset="utf-8" From: Eric Auger Reviewed-by: Richard Henderson Reviewed-by: Sebastian Ott Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- hw/intc/armv7m_nvic.c | 5 ++-- target/arm/cpu-features.h | 10 ++++---- target/arm/cpu.c | 8 +++--- target/arm/cpu.h | 3 --- target/arm/cpu64.c | 8 +++--- target/arm/helper.c | 8 +++--- target/arm/kvm.c | 9 +++---- target/arm/tcg/cpu-v7m.c | 24 +++++++++--------- target/arm/tcg/cpu32.c | 52 +++++++++++++++++++-------------------- target/arm/tcg/cpu64.c | 44 ++++++++++++++++----------------- 10 files changed, 82 insertions(+), 89 deletions(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index fdb7f58e3678..330205fa342d 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -988,6 +988,7 @@ static void nvic_nmi_trigger(void *opaque, int n, int l= evel) static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) { ARMCPU *cpu =3D s->cpu; + ARMISARegisters *isar =3D &cpu->isar; uint32_t val; =20 switch (offset) { @@ -1263,12 +1264,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t o= ffset, MemTxAttrs attrs) if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_pfr0; + return GET_IDREG(isar, ID_PFR0); case 0xd44: /* PFR1. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_pfr1; + return GET_IDREG(isar, ID_PFR1); case 0xd48: /* DFR0. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 75a2cc407793..a34378577f08 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -137,12 +137,12 @@ static inline bool isar_feature_aa32_i8mm(const ARMIS= ARegisters *id) =20 static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) { - return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) !=3D 0; + return FIELD_EX32_IDREG(id, ID_PFR0, RAS) !=3D 0; } =20 static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id) { - return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) !=3D 0; + return FIELD_EX32_IDREG(id, ID_PFR1, MPROGMOD) !=3D 0; } =20 static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id) @@ -151,7 +151,7 @@ static inline bool isar_feature_aa32_m_sec_state(const = ARMISARegisters *id) * Return true if M-profile state handling insns * (VSCCLRM, CLRM, FPCTX access insns) are implemented */ - return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >=3D 3; + return FIELD_EX32_IDREG(id, ID_PFR1, SECURITY) >=3D 3; } =20 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) @@ -350,12 +350,12 @@ static inline bool isar_feature_aa32_evt(const ARMISA= Registers *id) =20 static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) { - return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) !=3D 0; + return FIELD_EX32_IDREG(id, ID_PFR0, DIT) !=3D 0; } =20 static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id) { - return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) !=3D 0; + return FIELD_EX32_IDREG(id, ID_PFR2, SSBS) !=3D 0; } =20 static inline bool isar_feature_aa32_debugv7p1(const ARMISARegisters *id) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index cf811e47d996..62c06c7269c9 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2317,7 +2317,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * Disable the security extension feature bits in the processor * feature registers as well. */ - cpu->isar.id_pfr1 =3D FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECUR= ITY, 0); + FIELD_DP32_IDREG(isar, ID_PFR1, SECURITY, 0); cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSD= BG, 0); FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL3, 0); =20 @@ -2357,8 +2357,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * registers if we don't have EL2. */ FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL2, 0); - cpu->isar.id_pfr1 =3D FIELD_DP32(cpu->isar.id_pfr1, - ID_PFR1, VIRTUALIZATION, 0); + FIELD_DP32_IDREG(isar, ID_PFR1, VIRTUALIZATION, 0); } =20 if (cpu_isar_feature(aa64_mte, cpu)) { @@ -2421,8 +2420,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0); /* FEAT_AMU (Activity Monitors Extension) */ FIELD_DP64_IDREG(isar, ID_AA64PFR0, AMU, 0); - cpu->isar.id_pfr0 =3D - FIELD_DP32(cpu->isar.id_pfr0, ID_PFR0, AMU, 0); + FIELD_DP32_IDREG(isar, ID_PFR0, AMU, 0); /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */ FIELD_DP64_IDREG(isar, ID_AA64PFR0, MPAM, 0); } diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 353c18e67993..30401926e115 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1056,9 +1056,6 @@ struct ArchCPU { uint32_t id_mmfr3; uint32_t id_mmfr4; uint32_t id_mmfr5; - uint32_t id_pfr0; - uint32_t id_pfr1; - uint32_t id_pfr2; uint32_t mvfr0; uint32_t mvfr1; uint32_t mvfr2; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 6be62c0711b2..5b628aa7ebf4 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -652,8 +652,8 @@ static void aarch64_a57_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000043; cpu->ctr =3D 0x8444c004; cpu->reset_sctlr =3D 0x00c50838; - cpu->isar.id_pfr0 =3D 0x00000131; - cpu->isar.id_pfr1 =3D 0x00011011; + SET_IDREG(isar, ID_PFR0, 0x00000131); + SET_IDREG(isar, ID_PFR1, 0x00011011); cpu->isar.id_dfr0 =3D 0x03010066; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10101105; @@ -714,8 +714,8 @@ static void aarch64_a53_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000043; cpu->ctr =3D 0x84448004; /* L1Ip =3D VIPT */ cpu->reset_sctlr =3D 0x00c50838; - cpu->isar.id_pfr0 =3D 0x00000131; - cpu->isar.id_pfr1 =3D 0x00011011; + SET_IDREG(isar, ID_PFR0, 0x00000131); + SET_IDREG(isar, ID_PFR1, 0x00011011); cpu->isar.id_dfr0 =3D 0x03010066; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10101105; diff --git a/target/arm/helper.c b/target/arm/helper.c index 669b7a84284a..e9eb345ab23a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6932,7 +6932,7 @@ static void define_pmu_regs(ARMCPU *cpu) static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) { ARMCPU *cpu =3D env_archcpu(env); - uint64_t pfr1 =3D cpu->isar.id_pfr1; + uint64_t pfr1 =3D GET_IDREG(&cpu->isar, ID_PFR1); =20 if (env->gicv3state) { pfr1 |=3D 1 << 28; @@ -7777,7 +7777,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_pfr0 }, + .resetvalue =3D GET_IDREG(isar, ID_PFR0)}, /* * ID_PFR1 is not a plain ARM_CP_CONST because we don't know * the value of the GIC field until after we define these regs. @@ -7788,7 +7788,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .accessfn =3D access_aa32_tid3, #ifdef CONFIG_USER_ONLY .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->isar.id_pfr1, + .resetvalue =3D GET_IDREG(isar, ID_PFR1), #else .type =3D ARM_CP_NO_RAW, .accessfn =3D access_aa32_tid3, @@ -8130,7 +8130,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_pfr2 }, + .resetvalue =3D GET_IDREG(isar, ID_PFR2)}, { .name =3D "ID_DFR1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/kvm.c b/target/arm/kvm.c index eef9481737b5..d945e652b3ee 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -332,10 +332,8 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFe= atures *ahcf) * than skipping the reads and leaving 0, as we must avoid * considering the values in every case. */ - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr0, - ARM64_SYS_REG(3, 0, 0, 1, 0)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr1, - ARM64_SYS_REG(3, 0, 0, 1, 1)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_PFR0_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_PFR1_EL1_IDX); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0, ARM64_SYS_REG(3, 0, 0, 1, 2)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0, @@ -362,8 +360,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) ARM64_SYS_REG(3, 0, 0, 3, 1)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2, ARM64_SYS_REG(3, 0, 0, 3, 2)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr2, - ARM64_SYS_REG(3, 0, 0, 3, 4)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_PFR2_EL1_IDX); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr1, ARM64_SYS_REG(3, 0, 0, 3, 5)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr5, diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 198c9f3e98c3..4a2c3bd01a36 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -59,8 +59,8 @@ static void cortex_m0_initfn(Object *obj) * by looking at ID register fields. We use the same values as * for the M3. */ - cpu->isar.id_pfr0 =3D 0x00000030; - cpu->isar.id_pfr1 =3D 0x00000200; + SET_IDREG(isar, ID_PFR0, 0x00000030); + SET_IDREG(isar, ID_PFR1, 0x00000200); cpu->isar.id_dfr0 =3D 0x00100000; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00000030; @@ -85,8 +85,8 @@ static void cortex_m3_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_M_MAIN); cpu->midr =3D 0x410fc231; cpu->pmsav7_dregion =3D 8; - cpu->isar.id_pfr0 =3D 0x00000030; - cpu->isar.id_pfr1 =3D 0x00000200; + SET_IDREG(isar, ID_PFR0, 0x00000030); + SET_IDREG(isar, ID_PFR1, 0x00000200); cpu->isar.id_dfr0 =3D 0x00100000; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00000030; @@ -116,8 +116,8 @@ static void cortex_m4_initfn(Object *obj) cpu->isar.mvfr0 =3D 0x10110021; cpu->isar.mvfr1 =3D 0x11000011; cpu->isar.mvfr2 =3D 0x00000000; - cpu->isar.id_pfr0 =3D 0x00000030; - cpu->isar.id_pfr1 =3D 0x00000200; + SET_IDREG(isar, ID_PFR0, 0x00000030); + SET_IDREG(isar, ID_PFR1, 0x00000200); cpu->isar.id_dfr0 =3D 0x00100000; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00000030; @@ -147,8 +147,8 @@ static void cortex_m7_initfn(Object *obj) cpu->isar.mvfr0 =3D 0x10110221; cpu->isar.mvfr1 =3D 0x12000011; cpu->isar.mvfr2 =3D 0x00000040; - cpu->isar.id_pfr0 =3D 0x00000030; - cpu->isar.id_pfr1 =3D 0x00000200; + SET_IDREG(isar, ID_PFR0, 0x00000030); + SET_IDREG(isar, ID_PFR1, 0x00000200); cpu->isar.id_dfr0 =3D 0x00100000; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00100030; @@ -180,8 +180,8 @@ static void cortex_m33_initfn(Object *obj) cpu->isar.mvfr0 =3D 0x10110021; cpu->isar.mvfr1 =3D 0x11000011; cpu->isar.mvfr2 =3D 0x00000040; - cpu->isar.id_pfr0 =3D 0x00000030; - cpu->isar.id_pfr1 =3D 0x00000210; + SET_IDREG(isar, ID_PFR0, 0x00000030); + SET_IDREG(isar, ID_PFR1, 0x00000210); cpu->isar.id_dfr0 =3D 0x00200000; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00101F40; @@ -218,8 +218,8 @@ static void cortex_m55_initfn(Object *obj) cpu->isar.mvfr0 =3D 0x10110221; cpu->isar.mvfr1 =3D 0x12100211; cpu->isar.mvfr2 =3D 0x00000040; - cpu->isar.id_pfr0 =3D 0x20000030; - cpu->isar.id_pfr1 =3D 0x00000230; + SET_IDREG(isar, ID_PFR0, 0x20000030); + SET_IDREG(isar, ID_PFR1, 0x00000230); cpu->isar.id_dfr0 =3D 0x10200000; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00111040; diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 937a72b12c9b..56374db2692f 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -71,16 +71,16 @@ void aa32_max_features(ARMCPU *cpu) t =3D FIELD_DP32(t, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */ cpu->isar.id_mmfr5 =3D t; =20 - t =3D cpu->isar.id_pfr0; + t =3D GET_IDREG(isar, ID_PFR0); t =3D FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */ t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ t =3D FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ - cpu->isar.id_pfr0 =3D t; + SET_IDREG(isar, ID_PFR0, t); =20 - t =3D cpu->isar.id_pfr2; + t =3D GET_IDREG(isar, ID_PFR2); t =3D FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */ t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ - cpu->isar.id_pfr2 =3D t; + SET_IDREG(isar, ID_PFR2, t); =20 t =3D cpu->isar.id_dfr0; t =3D FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */ @@ -228,8 +228,8 @@ static void arm1136_r2_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x00000000; cpu->ctr =3D 0x1dd20d2; cpu->reset_sctlr =3D 0x00050078; - cpu->isar.id_pfr0 =3D 0x111; - cpu->isar.id_pfr1 =3D 0x1; + SET_IDREG(isar, ID_PFR0, 0x111); + SET_IDREG(isar, ID_PFR1, 0x1); cpu->isar.id_dfr0 =3D 0x2; cpu->id_afr0 =3D 0x3; cpu->isar.id_mmfr0 =3D 0x01130003; @@ -260,8 +260,8 @@ static void arm1136_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x00000000; cpu->ctr =3D 0x1dd20d2; cpu->reset_sctlr =3D 0x00050078; - cpu->isar.id_pfr0 =3D 0x111; - cpu->isar.id_pfr1 =3D 0x1; + SET_IDREG(isar, ID_PFR0, 0x111); + SET_IDREG(isar, ID_PFR1, 0x1); cpu->isar.id_dfr0 =3D 0x2; cpu->id_afr0 =3D 0x3; cpu->isar.id_mmfr0 =3D 0x01130003; @@ -293,8 +293,8 @@ static void arm1176_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x00000000; cpu->ctr =3D 0x1dd20d2; cpu->reset_sctlr =3D 0x00050078; - cpu->isar.id_pfr0 =3D 0x111; - cpu->isar.id_pfr1 =3D 0x11; + SET_IDREG(isar, ID_PFR0, 0x111); + SET_IDREG(isar, ID_PFR1, 0x11); cpu->isar.id_dfr0 =3D 0x33; cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x01130003; @@ -323,8 +323,8 @@ static void arm11mpcore_initfn(Object *obj) cpu->isar.mvfr0 =3D 0x11111111; cpu->isar.mvfr1 =3D 0x00000000; cpu->ctr =3D 0x1d192992; /* 32K icache 32K dcache */ - cpu->isar.id_pfr0 =3D 0x111; - cpu->isar.id_pfr1 =3D 0x1; + SET_IDREG(isar, ID_PFR0, 0x111); + SET_IDREG(isar, ID_PFR1, 0x1); cpu->isar.id_dfr0 =3D 0; cpu->id_afr0 =3D 0x2; cpu->isar.id_mmfr0 =3D 0x01100103; @@ -363,8 +363,8 @@ static void cortex_a8_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x00011111; cpu->ctr =3D 0x82048004; cpu->reset_sctlr =3D 0x00c50078; - cpu->isar.id_pfr0 =3D 0x1031; - cpu->isar.id_pfr1 =3D 0x11; + SET_IDREG(isar, ID_PFR0, 0x1031); + SET_IDREG(isar, ID_PFR1, 0x11); cpu->isar.id_dfr0 =3D 0x400; cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x31100003; @@ -439,8 +439,8 @@ static void cortex_a9_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x01111111; cpu->ctr =3D 0x80038003; cpu->reset_sctlr =3D 0x00c50078; - cpu->isar.id_pfr0 =3D 0x1031; - cpu->isar.id_pfr1 =3D 0x11; + SET_IDREG(isar, ID_PFR0, 0x1031); + SET_IDREG(isar, ID_PFR1, 0x11); cpu->isar.id_dfr0 =3D 0x000; cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x00100103; @@ -505,8 +505,8 @@ static void cortex_a7_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x11111111; cpu->ctr =3D 0x84448003; cpu->reset_sctlr =3D 0x00c50078; - cpu->isar.id_pfr0 =3D 0x00001131; - cpu->isar.id_pfr1 =3D 0x00011011; + SET_IDREG(isar, ID_PFR0, 0x00001131); + SET_IDREG(isar, ID_PFR1, 0x00011011); cpu->isar.id_dfr0 =3D 0x02010555; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10101105; @@ -557,8 +557,8 @@ static void cortex_a15_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x11111111; cpu->ctr =3D 0x8444c004; cpu->reset_sctlr =3D 0x00c50078; - cpu->isar.id_pfr0 =3D 0x00001131; - cpu->isar.id_pfr1 =3D 0x00011011; + SET_IDREG(isar, ID_PFR0, 0x00001131); + SET_IDREG(isar, ID_PFR1, 0x00011011); cpu->isar.id_dfr0 =3D 0x02010555; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10201105; @@ -601,8 +601,8 @@ static void cortex_r5_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_PMSA); set_feature(&cpu->env, ARM_FEATURE_PMU); cpu->midr =3D 0x411fc153; /* r1p3 */ - cpu->isar.id_pfr0 =3D 0x0131; - cpu->isar.id_pfr1 =3D 0x001; + SET_IDREG(isar, ID_PFR0, 0x0131); + SET_IDREG(isar, ID_PFR1, 0x001); cpu->isar.id_dfr0 =3D 0x010400; cpu->id_afr0 =3D 0x0; cpu->isar.id_mmfr0 =3D 0x0210030; @@ -748,8 +748,8 @@ static void cortex_r52_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000043; cpu->ctr =3D 0x8144c004; cpu->reset_sctlr =3D 0x30c50838; - cpu->isar.id_pfr0 =3D 0x00000131; - cpu->isar.id_pfr1 =3D 0x10111001; + SET_IDREG(isar, ID_PFR0, 0x00000131); + SET_IDREG(isar, ID_PFR1, 0x10111001); cpu->isar.id_dfr0 =3D 0x03010006; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00211040; @@ -980,8 +980,8 @@ static void arm_max_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000043; cpu->ctr =3D 0x8444c004; cpu->reset_sctlr =3D 0x00c50838; - cpu->isar.id_pfr0 =3D 0x00000131; - cpu->isar.id_pfr1 =3D 0x00011011; + SET_IDREG(isar, ID_PFR0, 0x00000131); + SET_IDREG(isar, ID_PFR1, 0x00011011); cpu->isar.id_dfr0 =3D 0x03010066; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10101105; diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index dd4dc8ada564..c3f90e9d1357 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -49,8 +49,8 @@ static void aarch64_a35_initfn(Object *obj) cpu->midr =3D 0x411fd040; cpu->revidr =3D 0; cpu->ctr =3D 0x84448004; - cpu->isar.id_pfr0 =3D 0x00000131; - cpu->isar.id_pfr1 =3D 0x00011011; + SET_IDREG(isar, ID_PFR0, 0x00000131); + SET_IDREG(isar, ID_PFR1, 0x00011011); cpu->isar.id_dfr0 =3D 0x03010066; cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x10201105; @@ -241,9 +241,9 @@ static void aarch64_a55_initfn(Object *obj) cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02122211; cpu->isar.id_mmfr4 =3D 0x00021110; - cpu->isar.id_pfr0 =3D 0x10010131; - cpu->isar.id_pfr1 =3D 0x00011011; - cpu->isar.id_pfr2 =3D 0x00000011; + SET_IDREG(isar, ID_PFR0, 0x10010131); + SET_IDREG(isar, ID_PFR1, 0x00011011); + SET_IDREG(isar, ID_PFR2, 0x00000011); cpu->midr =3D 0x412FD050; /* r2p0 */ cpu->revidr =3D 0; =20 @@ -295,8 +295,8 @@ static void aarch64_a72_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000043; cpu->ctr =3D 0x8444c004; cpu->reset_sctlr =3D 0x00c50838; - cpu->isar.id_pfr0 =3D 0x00000131; - cpu->isar.id_pfr1 =3D 0x00011011; + SET_IDREG(isar, ID_PFR0, 0x00000131); + SET_IDREG(isar, ID_PFR1, 0x00011011); cpu->isar.id_dfr0 =3D 0x03010066; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10201105; @@ -374,9 +374,9 @@ static void aarch64_a76_initfn(Object *obj) cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02122211; cpu->isar.id_mmfr4 =3D 0x00021110; - cpu->isar.id_pfr0 =3D 0x10010131; - cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ - cpu->isar.id_pfr2 =3D 0x00000011; + SET_IDREG(isar, ID_PFR0, 0x10010131); + SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ + SET_IDREG(isar, ID_PFR2, 0x00000011); cpu->midr =3D 0x414fd0b1; /* r4p1 */ cpu->revidr =3D 0; =20 @@ -622,9 +622,9 @@ static void aarch64_neoverse_n1_initfn(Object *obj) cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02122211; cpu->isar.id_mmfr4 =3D 0x00021110; - cpu->isar.id_pfr0 =3D 0x10010131; - cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ - cpu->isar.id_pfr2 =3D 0x00000011; + SET_IDREG(isar, ID_PFR0, 0x10010131); + SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ + SET_IDREG(isar, ID_PFR2, 0x00000011); cpu->midr =3D 0x414fd0c1; /* r4p1 */ cpu->revidr =3D 0; =20 @@ -701,9 +701,9 @@ static void aarch64_neoverse_v1_initfn(Object *obj) cpu->isar.id_mmfr2 =3D 0x01260000; cpu->isar.id_mmfr3 =3D 0x02122211; cpu->isar.id_mmfr4 =3D 0x01021110; - cpu->isar.id_pfr0 =3D 0x21110131; - cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ - cpu->isar.id_pfr2 =3D 0x00000011; + SET_IDREG(isar, ID_PFR0, 0x21110131); + SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ + SET_IDREG(isar, ID_PFR2, 0x00000011); cpu->midr =3D 0x411FD402; /* r1p2 */ cpu->revidr =3D 0; =20 @@ -902,8 +902,8 @@ static void aarch64_a710_initfn(Object *obj) /* Ordered by Section B.4: AArch64 registers */ cpu->midr =3D 0x412FD471; /* r2p1 */ cpu->revidr =3D 0; - cpu->isar.id_pfr0 =3D 0x21110131; - cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ + SET_IDREG(isar, ID_PFR0, 0x21110131); + SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ cpu->isar.id_dfr0 =3D 0x16011099; cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x10201105; @@ -921,7 +921,7 @@ static void aarch64_a710_initfn(Object *obj) cpu->isar.mvfr0 =3D 0x10110222; cpu->isar.mvfr1 =3D 0x13211111; cpu->isar.mvfr2 =3D 0x00000043; - cpu->isar.id_pfr2 =3D 0x00000011; + SET_IDREG(isar, ID_PFR2, 0x00000011); SET_IDREG(isar, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in = later */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000221ull); SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */ @@ -1004,8 +1004,8 @@ static void aarch64_neoverse_n2_initfn(Object *obj) /* Ordered by Section B.5: AArch64 ID registers */ cpu->midr =3D 0x410FD493; /* r0p3 */ cpu->revidr =3D 0; - cpu->isar.id_pfr0 =3D 0x21110131; - cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ + SET_IDREG(isar, ID_PFR0, 0x21110131); + SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ cpu->isar.id_dfr0 =3D 0x16011099; cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x10201105; @@ -1023,7 +1023,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj) cpu->isar.mvfr0 =3D 0x10110222; cpu->isar.mvfr1 =3D 0x13211111; cpu->isar.mvfr2 =3D 0x00000043; - cpu->isar.id_pfr2 =3D 0x00000011; + SET_IDREG(isar, ID_PFR2, 0x00000011); SET_IDREG(isar, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in = later */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000221ull); SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */ --=20 2.49.0 From nobody Sat Nov 15 20:48:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Eric Auger Reviewed-by: Richard Henderson Reviewed-by: Sebastian Ott Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- hw/intc/armv7m_nvic.c | 2 +- target/arm/cpu-features.h | 16 ++++++++-------- target/arm/cpu.c | 13 +++++-------- target/arm/cpu.h | 2 -- target/arm/cpu64.c | 4 ++-- target/arm/helper.c | 4 ++-- target/arm/kvm.c | 6 ++---- target/arm/tcg/cpu-v7m.c | 12 ++++++------ target/arm/tcg/cpu32.c | 30 ++++++++++++++---------------- target/arm/tcg/cpu64.c | 16 ++++++++-------- 10 files changed, 48 insertions(+), 57 deletions(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 330205fa342d..2566dd634318 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1274,7 +1274,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t off= set, MemTxAttrs attrs) if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_dfr0; + return GET_IDREG(isar, ID_DFR0); case 0xd4c: /* AFR0. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index a34378577f08..0292a7cd6ec2 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -300,22 +300,22 @@ static inline bool isar_feature_aa32_ats1e1(const ARM= ISARegisters *id) static inline bool isar_feature_aa32_pmuv3p1(const ARMISARegisters *id) { /* 0xf means "non-standard IMPDEF PMU" */ - return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >=3D 4 && - FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) !=3D 0xf; + return FIELD_EX32_IDREG(id, ID_DFR0, PERFMON) >=3D 4 && + FIELD_EX32_IDREG(id, ID_DFR0, PERFMON) !=3D 0xf; } =20 static inline bool isar_feature_aa32_pmuv3p4(const ARMISARegisters *id) { /* 0xf means "non-standard IMPDEF PMU" */ - return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >=3D 5 && - FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) !=3D 0xf; + return FIELD_EX32_IDREG(id, ID_DFR0, PERFMON) >=3D 5 && + FIELD_EX32_IDREG(id, ID_DFR0, PERFMON) !=3D 0xf; } =20 static inline bool isar_feature_aa32_pmuv3p5(const ARMISARegisters *id) { /* 0xf means "non-standard IMPDEF PMU" */ - return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >=3D 6 && - FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) !=3D 0xf; + return FIELD_EX32_IDREG(id, ID_DFR0, PERFMON) >=3D 6 && + FIELD_EX32_IDREG(id, ID_DFR0, PERFMON) !=3D 0xf; } =20 static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) @@ -360,12 +360,12 @@ static inline bool isar_feature_aa32_ssbs(const ARMIS= ARegisters *id) =20 static inline bool isar_feature_aa32_debugv7p1(const ARMISARegisters *id) { - return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >=3D 5; + return FIELD_EX32_IDREG(id, ID_DFR0, COPDBG) >=3D 5; } =20 static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id) { - return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >=3D 8; + return FIELD_EX32_IDREG(id, ID_DFR0, COPDBG) >=3D 8; } =20 static inline bool isar_feature_aa32_doublelock(const ARMISARegisters *id) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 62c06c7269c9..8e77414c2b93 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2318,7 +2318,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * feature registers as well. */ FIELD_DP32_IDREG(isar, ID_PFR1, SECURITY, 0); - cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSD= BG, 0); + FIELD_DP32_IDREG(isar, ID_DFR0, COPSDBG, 0); FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL3, 0); =20 /* Disable the realm management extension, which requires EL3. */ @@ -2346,7 +2346,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) #endif } else { FIELD_DP64_IDREG(isar, ID_AA64DFR0, PMUVER, 0); - cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFM= ON, 0); + FIELD_DP32_IDREG(isar, ID_DFR0, PERFMON, 0); cpu->pmceid0 =3D 0; cpu->pmceid1 =3D 0; } @@ -2409,15 +2409,12 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEBUFFER, 0); /* FEAT_TRF (Self-hosted Trace Extension) */ FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEFILT, 0); - cpu->isar.id_dfr0 =3D - FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, TRACEFILT, 0); + FIELD_DP32_IDREG(isar, ID_DFR0, TRACEFILT, 0); /* Trace Macrocell system register access */ FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEVER, 0); - cpu->isar.id_dfr0 =3D - FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPTRC, 0); + FIELD_DP32_IDREG(isar, ID_DFR0, COPTRC, 0); /* Memory mapped trace */ - cpu->isar.id_dfr0 =3D - FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0); + FIELD_DP32_IDREG(isar, ID_DFR0, MMAPTRC, 0); /* FEAT_AMU (Activity Monitors Extension) */ FIELD_DP64_IDREG(isar, ID_AA64PFR0, AMU, 0); FIELD_DP32_IDREG(isar, ID_PFR0, AMU, 0); diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 30401926e115..c799105eeb21 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1059,8 +1059,6 @@ struct ArchCPU { uint32_t mvfr0; uint32_t mvfr1; uint32_t mvfr2; - uint32_t id_dfr0; - uint32_t id_dfr1; uint32_t dbgdidr; uint32_t dbgdevid; uint32_t dbgdevid1; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 5b628aa7ebf4..47c2eed3c991 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -654,7 +654,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50838; SET_IDREG(isar, ID_PFR0, 0x00000131); SET_IDREG(isar, ID_PFR1, 0x00011011); - cpu->isar.id_dfr0 =3D 0x03010066; + SET_IDREG(isar, ID_DFR0, 0x03010066); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10101105; cpu->isar.id_mmfr1 =3D 0x40000000; @@ -716,7 +716,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50838; SET_IDREG(isar, ID_PFR0, 0x00000131); SET_IDREG(isar, ID_PFR1, 0x00011011); - cpu->isar.id_dfr0 =3D 0x03010066; + SET_IDREG(isar, ID_DFR0, 0x03010066); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10101105; cpu->isar.id_mmfr1 =3D 0x40000000; diff --git a/target/arm/helper.c b/target/arm/helper.c index e9eb345ab23a..c4022dd69a87 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7800,7 +7800,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_dfr0 }, + .resetvalue =3D GET_IDREG(isar, ID_DFR0)}, { .name =3D "ID_AFR0", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 3, .access =3D PL1_R, .type =3D ARM_CP_CONST, @@ -8135,7 +8135,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_dfr1 }, + .resetvalue =3D GET_IDREG(isar, ID_DFR1)}, { .name =3D "ID_MMFR5", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/kvm.c b/target/arm/kvm.c index d945e652b3ee..2a6a5329b439 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -334,8 +334,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) */ err |=3D get_host_cpu_reg(fd, ahcf, ID_PFR0_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_PFR1_EL1_IDX); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0, - ARM64_SYS_REG(3, 0, 0, 1, 2)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_DFR0_EL1_IDX); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0, ARM64_SYS_REG(3, 0, 0, 1, 4)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1, @@ -361,8 +360,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2, ARM64_SYS_REG(3, 0, 0, 3, 2)); err |=3D get_host_cpu_reg(fd, ahcf, ID_PFR2_EL1_IDX); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr1, - ARM64_SYS_REG(3, 0, 0, 3, 5)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_DFR1_EL1_IDX); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr5, ARM64_SYS_REG(3, 0, 0, 3, 6)); =20 diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 4a2c3bd01a36..9697c362c19b 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -61,7 +61,7 @@ static void cortex_m0_initfn(Object *obj) */ SET_IDREG(isar, ID_PFR0, 0x00000030); SET_IDREG(isar, ID_PFR1, 0x00000200); - cpu->isar.id_dfr0 =3D 0x00100000; + SET_IDREG(isar, ID_DFR0, 0x00100000); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00000030; cpu->isar.id_mmfr1 =3D 0x00000000; @@ -87,7 +87,7 @@ static void cortex_m3_initfn(Object *obj) cpu->pmsav7_dregion =3D 8; SET_IDREG(isar, ID_PFR0, 0x00000030); SET_IDREG(isar, ID_PFR1, 0x00000200); - cpu->isar.id_dfr0 =3D 0x00100000; + SET_IDREG(isar, ID_DFR0, 0x00100000); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00000030; cpu->isar.id_mmfr1 =3D 0x00000000; @@ -118,7 +118,7 @@ static void cortex_m4_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000000; SET_IDREG(isar, ID_PFR0, 0x00000030); SET_IDREG(isar, ID_PFR1, 0x00000200); - cpu->isar.id_dfr0 =3D 0x00100000; + SET_IDREG(isar, ID_DFR0, 0x00100000); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00000030; cpu->isar.id_mmfr1 =3D 0x00000000; @@ -149,7 +149,7 @@ static void cortex_m7_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000040; SET_IDREG(isar, ID_PFR0, 0x00000030); SET_IDREG(isar, ID_PFR1, 0x00000200); - cpu->isar.id_dfr0 =3D 0x00100000; + SET_IDREG(isar, ID_DFR0, 0x00100000); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00100030; cpu->isar.id_mmfr1 =3D 0x00000000; @@ -182,7 +182,7 @@ static void cortex_m33_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000040; SET_IDREG(isar, ID_PFR0, 0x00000030); SET_IDREG(isar, ID_PFR1, 0x00000210); - cpu->isar.id_dfr0 =3D 0x00200000; + SET_IDREG(isar, ID_DFR0, 0x00200000); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00101F40; cpu->isar.id_mmfr1 =3D 0x00000000; @@ -220,7 +220,7 @@ static void cortex_m55_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000040; SET_IDREG(isar, ID_PFR0, 0x20000030); SET_IDREG(isar, ID_PFR1, 0x00000230); - cpu->isar.id_dfr0 =3D 0x10200000; + SET_IDREG(isar, ID_DFR0, 0x10200000); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00111040; cpu->isar.id_mmfr1 =3D 0x00000000; diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 56374db2692f..bec69fe52e47 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -82,11 +82,11 @@ void aa32_max_features(ARMCPU *cpu) t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ SET_IDREG(isar, ID_PFR2, t); =20 - t =3D cpu->isar.id_dfr0; + t =3D GET_IDREG(isar, ID_DFR0); t =3D FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */ t =3D FIELD_DP32(t, ID_DFR0, COPSDBG, 10); /* FEAT_Debugv8p8 */ t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */ - cpu->isar.id_dfr0 =3D t; + SET_IDREG(isar, ID_DFR0, t); =20 /* Debug ID registers. */ =20 @@ -116,9 +116,7 @@ void aa32_max_features(ARMCPU *cpu) t =3D FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2); cpu->isar.dbgdevid1 =3D t; =20 - t =3D cpu->isar.id_dfr1; - t =3D FIELD_DP32(t, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */ - cpu->isar.id_dfr1 =3D t; + FIELD_DP32_IDREG(isar, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */ } =20 /* CPU models. These are not needed for the AArch64 linux-user build. */ @@ -230,7 +228,7 @@ static void arm1136_r2_initfn(Object *obj) cpu->reset_sctlr =3D 0x00050078; SET_IDREG(isar, ID_PFR0, 0x111); SET_IDREG(isar, ID_PFR1, 0x1); - cpu->isar.id_dfr0 =3D 0x2; + SET_IDREG(isar, ID_DFR0, 0x2); cpu->id_afr0 =3D 0x3; cpu->isar.id_mmfr0 =3D 0x01130003; cpu->isar.id_mmfr1 =3D 0x10030302; @@ -262,7 +260,7 @@ static void arm1136_initfn(Object *obj) cpu->reset_sctlr =3D 0x00050078; SET_IDREG(isar, ID_PFR0, 0x111); SET_IDREG(isar, ID_PFR1, 0x1); - cpu->isar.id_dfr0 =3D 0x2; + SET_IDREG(isar, ID_DFR0, 0x2); cpu->id_afr0 =3D 0x3; cpu->isar.id_mmfr0 =3D 0x01130003; cpu->isar.id_mmfr1 =3D 0x10030302; @@ -295,7 +293,7 @@ static void arm1176_initfn(Object *obj) cpu->reset_sctlr =3D 0x00050078; SET_IDREG(isar, ID_PFR0, 0x111); SET_IDREG(isar, ID_PFR1, 0x11); - cpu->isar.id_dfr0 =3D 0x33; + SET_IDREG(isar, ID_DFR0, 0x33); cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x01130003; cpu->isar.id_mmfr1 =3D 0x10030302; @@ -325,7 +323,7 @@ static void arm11mpcore_initfn(Object *obj) cpu->ctr =3D 0x1d192992; /* 32K icache 32K dcache */ SET_IDREG(isar, ID_PFR0, 0x111); SET_IDREG(isar, ID_PFR1, 0x1); - cpu->isar.id_dfr0 =3D 0; + SET_IDREG(isar, ID_DFR0, 0); cpu->id_afr0 =3D 0x2; cpu->isar.id_mmfr0 =3D 0x01100103; cpu->isar.id_mmfr1 =3D 0x10020302; @@ -365,7 +363,7 @@ static void cortex_a8_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50078; SET_IDREG(isar, ID_PFR0, 0x1031); SET_IDREG(isar, ID_PFR1, 0x11); - cpu->isar.id_dfr0 =3D 0x400; + SET_IDREG(isar, ID_DFR0, 0x400); cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x31100003; cpu->isar.id_mmfr1 =3D 0x20000000; @@ -441,7 +439,7 @@ static void cortex_a9_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50078; SET_IDREG(isar, ID_PFR0, 0x1031); SET_IDREG(isar, ID_PFR1, 0x11); - cpu->isar.id_dfr0 =3D 0x000; + SET_IDREG(isar, ID_DFR0, 0x000); cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x00100103; cpu->isar.id_mmfr1 =3D 0x20000000; @@ -507,7 +505,7 @@ static void cortex_a7_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50078; SET_IDREG(isar, ID_PFR0, 0x00001131); SET_IDREG(isar, ID_PFR1, 0x00011011); - cpu->isar.id_dfr0 =3D 0x02010555; + SET_IDREG(isar, ID_DFR0, 0x02010555); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10101105; cpu->isar.id_mmfr1 =3D 0x40000000; @@ -559,7 +557,7 @@ static void cortex_a15_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50078; SET_IDREG(isar, ID_PFR0, 0x00001131); SET_IDREG(isar, ID_PFR1, 0x00011011); - cpu->isar.id_dfr0 =3D 0x02010555; + SET_IDREG(isar, ID_DFR0, 0x02010555); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10201105; cpu->isar.id_mmfr1 =3D 0x20000000; @@ -603,7 +601,7 @@ static void cortex_r5_initfn(Object *obj) cpu->midr =3D 0x411fc153; /* r1p3 */ SET_IDREG(isar, ID_PFR0, 0x0131); SET_IDREG(isar, ID_PFR1, 0x001); - cpu->isar.id_dfr0 =3D 0x010400; + SET_IDREG(isar, ID_DFR0, 0x010400); cpu->id_afr0 =3D 0x0; cpu->isar.id_mmfr0 =3D 0x0210030; cpu->isar.id_mmfr1 =3D 0x00000000; @@ -750,7 +748,7 @@ static void cortex_r52_initfn(Object *obj) cpu->reset_sctlr =3D 0x30c50838; SET_IDREG(isar, ID_PFR0, 0x00000131); SET_IDREG(isar, ID_PFR1, 0x10111001); - cpu->isar.id_dfr0 =3D 0x03010006; + SET_IDREG(isar, ID_DFR0, 0x03010006); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00211040; cpu->isar.id_mmfr1 =3D 0x40000000; @@ -982,7 +980,7 @@ static void arm_max_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50838; SET_IDREG(isar, ID_PFR0, 0x00000131); SET_IDREG(isar, ID_PFR1, 0x00011011); - cpu->isar.id_dfr0 =3D 0x03010066; + SET_IDREG(isar, ID_DFR0, 0x03010066); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10101105; cpu->isar.id_mmfr1 =3D 0x40000000; diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index c3f90e9d1357..aeaade488fe3 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -51,7 +51,7 @@ static void aarch64_a35_initfn(Object *obj) cpu->ctr =3D 0x84448004; SET_IDREG(isar, ID_PFR0, 0x00000131); SET_IDREG(isar, ID_PFR1, 0x00011011); - cpu->isar.id_dfr0 =3D 0x03010066; + SET_IDREG(isar, ID_DFR0, 0x03010066); cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x10201105; cpu->isar.id_mmfr1 =3D 0x40000000; @@ -228,7 +228,7 @@ static void aarch64_a55_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR0, 0x0000000010112222ull); SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_dfr0 =3D 0x04010088; + SET_IDREG(isar, ID_DFR0, 0x04010088); SET_IDREG(isar, ID_ISAR0, 0x02101110); SET_IDREG(isar, ID_ISAR1, 0x13112111); SET_IDREG(isar, ID_ISAR2, 0x21232042); @@ -297,7 +297,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50838; SET_IDREG(isar, ID_PFR0, 0x00000131); SET_IDREG(isar, ID_PFR1, 0x00011011); - cpu->isar.id_dfr0 =3D 0x03010066; + SET_IDREG(isar, ID_DFR0, 0x03010066); cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10201105; cpu->isar.id_mmfr1 =3D 0x40000000; @@ -361,7 +361,7 @@ static void aarch64_a76_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in = later */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_dfr0 =3D 0x04010088; + SET_IDREG(isar, ID_DFR0, 0x04010088); SET_IDREG(isar, ID_ISAR0, 0x02101110); SET_IDREG(isar, ID_ISAR1, 0x13112111); SET_IDREG(isar, ID_ISAR2, 0x21232042); @@ -609,7 +609,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in = later */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_dfr0 =3D 0x04010088; + SET_IDREG(isar, ID_DFR0, 0x04010088); SET_IDREG(isar, ID_ISAR0, 0x02101110); SET_IDREG(isar, ID_ISAR1, 0x13112111); SET_IDREG(isar, ID_ISAR2, 0x21232042); @@ -688,7 +688,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR0, 0x1101110120111112ull); /* GIC filled in = later */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_dfr0 =3D 0x15011099; + SET_IDREG(isar, ID_DFR0, 0x15011099); SET_IDREG(isar, ID_ISAR0, 0x02101110); SET_IDREG(isar, ID_ISAR1, 0x13112111); SET_IDREG(isar, ID_ISAR2, 0x21232042); @@ -904,7 +904,7 @@ static void aarch64_a710_initfn(Object *obj) cpu->revidr =3D 0; SET_IDREG(isar, ID_PFR0, 0x21110131); SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ - cpu->isar.id_dfr0 =3D 0x16011099; + SET_IDREG(isar, ID_DFR0, 0x16011099); cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x10201105; cpu->isar.id_mmfr1 =3D 0x40000000; @@ -1006,7 +1006,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj) cpu->revidr =3D 0; SET_IDREG(isar, ID_PFR0, 0x21110131); SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ - cpu->isar.id_dfr0 =3D 0x16011099; + SET_IDREG(isar, ID_DFR0, 0x16011099); cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x10201105; cpu->isar.id_mmfr1 =3D 0x40000000; --=20 2.49.0 From nobody Sat Nov 15 20:48:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" From: Eric Auger Reviewed-by: Richard Henderson Reviewed-by: Sebastian Ott Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- hw/intc/armv7m_nvic.c | 8 ++-- target/arm/cpu-features.h | 18 ++++---- target/arm/cpu.h | 6 --- target/arm/cpu64.c | 16 +++---- target/arm/helper.c | 12 ++--- target/arm/kvm.c | 18 +++----- target/arm/tcg/cpu-v7m.c | 48 ++++++++++---------- target/arm/tcg/cpu32.c | 94 +++++++++++++++++++-------------------- target/arm/tcg/cpu64.c | 76 +++++++++++++++---------------- 9 files changed, 140 insertions(+), 156 deletions(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 2566dd634318..6d85720f1b46 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1284,22 +1284,22 @@ static uint32_t nvic_readl(NVICState *s, uint32_t o= ffset, MemTxAttrs attrs) if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_mmfr0; + return GET_IDREG(isar, ID_MMFR0); case 0xd54: /* MMFR1. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_mmfr1; + return GET_IDREG(isar, ID_MMFR1); case 0xd58: /* MMFR2. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_mmfr2; + return GET_IDREG(isar, ID_MMFR2); case 0xd5c: /* MMFR3. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->isar.id_mmfr3; + return GET_IDREG(isar, ID_MMFR3); case 0xd60: /* ISAR0. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 0292a7cd6ec2..5d8adfb73b65 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -284,17 +284,17 @@ static inline bool isar_feature_aa32_vminmaxnm(const = ARMISARegisters *id) =20 static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id) { - return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >=3D 4; + return FIELD_EX32_IDREG(id, ID_MMFR0, VMSA) >=3D 4; } =20 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) { - return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) !=3D 0; + return FIELD_EX32_IDREG(id, ID_MMFR3, PAN) !=3D 0; } =20 static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) { - return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >=3D 2; + return FIELD_EX32_IDREG(id, ID_MMFR3, PAN) >=3D 2; } =20 static inline bool isar_feature_aa32_pmuv3p1(const ARMISARegisters *id) @@ -320,32 +320,32 @@ static inline bool isar_feature_aa32_pmuv3p5(const AR= MISARegisters *id) =20 static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) { - return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) !=3D 0; + return FIELD_EX32_IDREG(id, ID_MMFR4, HPDS) !=3D 0; } =20 static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id) { - return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) !=3D 0; + return FIELD_EX32_IDREG(id, ID_MMFR4, AC2) !=3D 0; } =20 static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id) { - return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) !=3D 0; + return FIELD_EX32_IDREG(id, ID_MMFR4, CCIDX) !=3D 0; } =20 static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id) { - return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) !=3D 0; + return FIELD_EX32_IDREG(id, ID_MMFR4, XNX) !=3D 0; } =20 static inline bool isar_feature_aa32_half_evt(const ARMISARegisters *id) { - return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >=3D 1; + return FIELD_EX32_IDREG(id, ID_MMFR4, EVT) >=3D 1; } =20 static inline bool isar_feature_aa32_evt(const ARMISARegisters *id) { - return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >=3D 2; + return FIELD_EX32_IDREG(id, ID_MMFR4, EVT) >=3D 2; } =20 static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c799105eeb21..8744922330df 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1050,12 +1050,6 @@ struct ArchCPU { * field by reading the value from the KVM vCPU. */ struct ARMISARegisters { - uint32_t id_mmfr0; - uint32_t id_mmfr1; - uint32_t id_mmfr2; - uint32_t id_mmfr3; - uint32_t id_mmfr4; - uint32_t id_mmfr5; uint32_t mvfr0; uint32_t mvfr1; uint32_t mvfr2; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 47c2eed3c991..1f3406708bd7 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -656,10 +656,10 @@ static void aarch64_a57_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x00011011); SET_IDREG(isar, ID_DFR0, 0x03010066); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x10101105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02102211; + SET_IDREG(isar, ID_MMFR0, 0x10101105); + SET_IDREG(isar, ID_MMFR1, 0x40000000); + SET_IDREG(isar, ID_MMFR2, 0x01260000); + SET_IDREG(isar, ID_MMFR3, 0x02102211); SET_IDREG(isar, ID_ISAR0, 0x02101110); SET_IDREG(isar, ID_ISAR1, 0x13112111); SET_IDREG(isar, ID_ISAR2, 0x21232042); @@ -718,10 +718,10 @@ static void aarch64_a53_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x00011011); SET_IDREG(isar, ID_DFR0, 0x03010066); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x10101105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02102211; + SET_IDREG(isar, ID_MMFR0, 0x10101105); + SET_IDREG(isar, ID_MMFR1, 0x40000000); + SET_IDREG(isar, ID_MMFR2, 0x01260000); + SET_IDREG(isar, ID_MMFR3, 0x02102211); SET_IDREG(isar, ID_ISAR0, 0x02101110); SET_IDREG(isar, ID_ISAR1, 0x13112111); SET_IDREG(isar, ID_ISAR2, 0x21232042); diff --git a/target/arm/helper.c b/target/arm/helper.c index c4022dd69a87..14647ff3888d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7810,22 +7810,22 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_mmfr0 }, + .resetvalue =3D GET_IDREG(isar, ID_MMFR0)}, { .name =3D "ID_MMFR1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_mmfr1 }, + .resetvalue =3D GET_IDREG(isar, ID_MMFR1)}, { .name =3D "ID_MMFR2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_mmfr2 }, + .resetvalue =3D GET_IDREG(isar, ID_MMFR2)}, { .name =3D "ID_MMFR3", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_mmfr3 }, + .resetvalue =3D GET_IDREG(isar, ID_MMFR3)}, { .name =3D "ID_ISAR0", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, @@ -7860,7 +7860,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_mmfr4 }, + .resetvalue =3D GET_IDREG(isar, ID_MMFR4)}, { .name =3D "ID_ISAR6", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, @@ -8140,7 +8140,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_mmfr5 }, + .resetvalue =3D GET_IDREG(isar, ID_MMFR5)}, { .name =3D "RES_0_C0_C3_7", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 2a6a5329b439..3df046b2b911 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -335,14 +335,10 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUF= eatures *ahcf) err |=3D get_host_cpu_reg(fd, ahcf, ID_PFR0_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_PFR1_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_DFR0_EL1_IDX); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0, - ARM64_SYS_REG(3, 0, 0, 1, 4)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1, - ARM64_SYS_REG(3, 0, 0, 1, 5)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr2, - ARM64_SYS_REG(3, 0, 0, 1, 6)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3, - ARM64_SYS_REG(3, 0, 0, 1, 7)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_MMFR0_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_MMFR1_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_MMFR2_EL1_IDX); + err |=3D get_host_cpu_reg(fd, ahcf, ID_MMFR3_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_ISAR0_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_ISAR1_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_ISAR2_EL1_IDX); @@ -350,8 +346,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) err |=3D get_host_cpu_reg(fd, ahcf, ID_ISAR4_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_ISAR5_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_ISAR6_EL1_IDX); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4, - ARM64_SYS_REG(3, 0, 0, 2, 6)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_MMFR4_EL1_IDX); =20 err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, ARM64_SYS_REG(3, 0, 0, 3, 0)); @@ -361,8 +356,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) ARM64_SYS_REG(3, 0, 0, 3, 2)); err |=3D get_host_cpu_reg(fd, ahcf, ID_PFR2_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_DFR1_EL1_IDX); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr5, - ARM64_SYS_REG(3, 0, 0, 3, 6)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_MMFR5_EL1_IDX); =20 /* * DBGDIDR is a bit complicated because the kernel doesn't diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 9697c362c19b..eddd7117d5bb 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -63,10 +63,10 @@ static void cortex_m0_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x00000200); SET_IDREG(isar, ID_DFR0, 0x00100000); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x00000030; - cpu->isar.id_mmfr1 =3D 0x00000000; - cpu->isar.id_mmfr2 =3D 0x00000000; - cpu->isar.id_mmfr3 =3D 0x00000000; + SET_IDREG(isar, ID_MMFR0, 0x00000030); + SET_IDREG(isar, ID_MMFR1, 0x00000000); + SET_IDREG(isar, ID_MMFR2, 0x00000000); + SET_IDREG(isar, ID_MMFR3, 0x00000000); SET_IDREG(isar, ID_ISAR0, 0x01141110); SET_IDREG(isar, ID_ISAR1, 0x02111000); SET_IDREG(isar, ID_ISAR2, 0x21112231); @@ -89,10 +89,10 @@ static void cortex_m3_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x00000200); SET_IDREG(isar, ID_DFR0, 0x00100000); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x00000030; - cpu->isar.id_mmfr1 =3D 0x00000000; - cpu->isar.id_mmfr2 =3D 0x00000000; - cpu->isar.id_mmfr3 =3D 0x00000000; + SET_IDREG(isar, ID_MMFR0, 0x00000030); + SET_IDREG(isar, ID_MMFR1, 0x00000000); + SET_IDREG(isar, ID_MMFR2, 0x00000000); + SET_IDREG(isar, ID_MMFR3, 0x00000000); SET_IDREG(isar, ID_ISAR0, 0x01141110); SET_IDREG(isar, ID_ISAR1, 0x02111000); SET_IDREG(isar, ID_ISAR2, 0x21112231); @@ -120,10 +120,10 @@ static void cortex_m4_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x00000200); SET_IDREG(isar, ID_DFR0, 0x00100000); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x00000030; - cpu->isar.id_mmfr1 =3D 0x00000000; - cpu->isar.id_mmfr2 =3D 0x00000000; - cpu->isar.id_mmfr3 =3D 0x00000000; + SET_IDREG(isar, ID_MMFR0, 0x00000030); + SET_IDREG(isar, ID_MMFR1, 0x00000000); + SET_IDREG(isar, ID_MMFR2, 0x00000000); + SET_IDREG(isar, ID_MMFR3, 0x00000000); SET_IDREG(isar, ID_ISAR0, 0x01141110); SET_IDREG(isar, ID_ISAR1, 0x02111000); SET_IDREG(isar, ID_ISAR2, 0x21112231); @@ -151,10 +151,10 @@ static void cortex_m7_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x00000200); SET_IDREG(isar, ID_DFR0, 0x00100000); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x00100030; - cpu->isar.id_mmfr1 =3D 0x00000000; - cpu->isar.id_mmfr2 =3D 0x01000000; - cpu->isar.id_mmfr3 =3D 0x00000000; + SET_IDREG(isar, ID_MMFR0, 0x00100030); + SET_IDREG(isar, ID_MMFR1, 0x00000000); + SET_IDREG(isar, ID_MMFR2, 0x01000000); + SET_IDREG(isar, ID_MMFR3, 0x00000000); SET_IDREG(isar, ID_ISAR0, 0x01101110); SET_IDREG(isar, ID_ISAR1, 0x02112000); SET_IDREG(isar, ID_ISAR2, 0x20232231); @@ -184,10 +184,10 @@ static void cortex_m33_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x00000210); SET_IDREG(isar, ID_DFR0, 0x00200000); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x00101F40; - cpu->isar.id_mmfr1 =3D 0x00000000; - cpu->isar.id_mmfr2 =3D 0x01000000; - cpu->isar.id_mmfr3 =3D 0x00000000; + SET_IDREG(isar, ID_MMFR0, 0x00101F40); + SET_IDREG(isar, ID_MMFR1, 0x00000000); + SET_IDREG(isar, ID_MMFR2, 0x01000000); + SET_IDREG(isar, ID_MMFR3, 0x00000000); SET_IDREG(isar, ID_ISAR0, 0x01101110); SET_IDREG(isar, ID_ISAR1, 0x02212000); SET_IDREG(isar, ID_ISAR2, 0x20232232); @@ -222,10 +222,10 @@ static void cortex_m55_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x00000230); SET_IDREG(isar, ID_DFR0, 0x10200000); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x00111040; - cpu->isar.id_mmfr1 =3D 0x00000000; - cpu->isar.id_mmfr2 =3D 0x01000000; - cpu->isar.id_mmfr3 =3D 0x00000011; + SET_IDREG(isar, ID_MMFR0, 0x00111040); + SET_IDREG(isar, ID_MMFR1, 0x00000000); + SET_IDREG(isar, ID_MMFR2, 0x01000000); + SET_IDREG(isar, ID_MMFR3, 0x00000011); SET_IDREG(isar, ID_ISAR0, 0x01103110); SET_IDREG(isar, ID_ISAR1, 0x02212000); SET_IDREG(isar, ID_ISAR2, 0x20232232); diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index bec69fe52e47..942b636aa5bd 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -55,21 +55,17 @@ void aa32_max_features(ARMCPU *cpu) t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ cpu->isar.mvfr2 =3D t; =20 - t =3D cpu->isar.id_mmfr3; - t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */ - cpu->isar.id_mmfr3 =3D t; + FIELD_DP32_IDREG(isar, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */ =20 - t =3D cpu->isar.id_mmfr4; + t =3D GET_IDREG(isar, ID_MMFR4); t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 2); /* FEAT_HPDS2 */ t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */ t =3D FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT */ - cpu->isar.id_mmfr4 =3D t; + SET_IDREG(isar, ID_MMFR4, t); =20 - t =3D cpu->isar.id_mmfr5; - t =3D FIELD_DP32(t, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */ - cpu->isar.id_mmfr5 =3D t; + FIELD_DP32_IDREG(isar, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */ =20 t =3D GET_IDREG(isar, ID_PFR0); t =3D FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */ @@ -230,9 +226,9 @@ static void arm1136_r2_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x1); SET_IDREG(isar, ID_DFR0, 0x2); cpu->id_afr0 =3D 0x3; - cpu->isar.id_mmfr0 =3D 0x01130003; - cpu->isar.id_mmfr1 =3D 0x10030302; - cpu->isar.id_mmfr2 =3D 0x01222110; + SET_IDREG(isar, ID_MMFR0, 0x01130003); + SET_IDREG(isar, ID_MMFR1, 0x10030302); + SET_IDREG(isar, ID_MMFR2, 0x01222110); SET_IDREG(isar, ID_ISAR0, 0x00140011); SET_IDREG(isar, ID_ISAR1, 0x12002111); SET_IDREG(isar, ID_ISAR2, 0x11231111); @@ -262,9 +258,9 @@ static void arm1136_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x1); SET_IDREG(isar, ID_DFR0, 0x2); cpu->id_afr0 =3D 0x3; - cpu->isar.id_mmfr0 =3D 0x01130003; - cpu->isar.id_mmfr1 =3D 0x10030302; - cpu->isar.id_mmfr2 =3D 0x01222110; + SET_IDREG(isar, ID_MMFR0, 0x01130003); + SET_IDREG(isar, ID_MMFR1, 0x10030302); + SET_IDREG(isar, ID_MMFR2, 0x01222110); SET_IDREG(isar, ID_ISAR0, 0x00140011); SET_IDREG(isar, ID_ISAR1, 0x12002111); SET_IDREG(isar, ID_ISAR2, 0x11231111); @@ -295,9 +291,9 @@ static void arm1176_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x11); SET_IDREG(isar, ID_DFR0, 0x33); cpu->id_afr0 =3D 0; - cpu->isar.id_mmfr0 =3D 0x01130003; - cpu->isar.id_mmfr1 =3D 0x10030302; - cpu->isar.id_mmfr2 =3D 0x01222100; + SET_IDREG(isar, ID_MMFR0, 0x01130003); + SET_IDREG(isar, ID_MMFR1, 0x10030302); + SET_IDREG(isar, ID_MMFR2, 0x01222100); SET_IDREG(isar, ID_ISAR0, 0x0140011); SET_IDREG(isar, ID_ISAR1, 0x12002111); SET_IDREG(isar, ID_ISAR2, 0x11231121); @@ -325,9 +321,9 @@ static void arm11mpcore_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x1); SET_IDREG(isar, ID_DFR0, 0); cpu->id_afr0 =3D 0x2; - cpu->isar.id_mmfr0 =3D 0x01100103; - cpu->isar.id_mmfr1 =3D 0x10020302; - cpu->isar.id_mmfr2 =3D 0x01222000; + SET_IDREG(isar, ID_MMFR0, 0x01100103); + SET_IDREG(isar, ID_MMFR1, 0x10020302); + SET_IDREG(isar, ID_MMFR2, 0x01222000); SET_IDREG(isar, ID_ISAR0, 0x00100011); SET_IDREG(isar, ID_ISAR1, 0x12002111); SET_IDREG(isar, ID_ISAR2, 0x11221011); @@ -365,10 +361,10 @@ static void cortex_a8_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x11); SET_IDREG(isar, ID_DFR0, 0x400); cpu->id_afr0 =3D 0; - cpu->isar.id_mmfr0 =3D 0x31100003; - cpu->isar.id_mmfr1 =3D 0x20000000; - cpu->isar.id_mmfr2 =3D 0x01202000; - cpu->isar.id_mmfr3 =3D 0x11; + SET_IDREG(isar, ID_MMFR0, 0x31100003); + SET_IDREG(isar, ID_MMFR1, 0x20000000); + SET_IDREG(isar, ID_MMFR2, 0x01202000); + SET_IDREG(isar, ID_MMFR3, 0x11); SET_IDREG(isar, ID_ISAR0, 0x00101111); SET_IDREG(isar, ID_ISAR1, 0x12112111); SET_IDREG(isar, ID_ISAR2, 0x21232031); @@ -441,10 +437,10 @@ static void cortex_a9_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x11); SET_IDREG(isar, ID_DFR0, 0x000); cpu->id_afr0 =3D 0; - cpu->isar.id_mmfr0 =3D 0x00100103; - cpu->isar.id_mmfr1 =3D 0x20000000; - cpu->isar.id_mmfr2 =3D 0x01230000; - cpu->isar.id_mmfr3 =3D 0x00002111; + SET_IDREG(isar, ID_MMFR0, 0x00100103); + SET_IDREG(isar, ID_MMFR1, 0x20000000); + SET_IDREG(isar, ID_MMFR2, 0x01230000); + SET_IDREG(isar, ID_MMFR3, 0x00002111); SET_IDREG(isar, ID_ISAR0, 0x00101111); SET_IDREG(isar, ID_ISAR1, 0x13112111); SET_IDREG(isar, ID_ISAR2, 0x21232041); @@ -507,10 +503,10 @@ static void cortex_a7_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x00011011); SET_IDREG(isar, ID_DFR0, 0x02010555); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x10101105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01240000; - cpu->isar.id_mmfr3 =3D 0x02102211; + SET_IDREG(isar, ID_MMFR0, 0x10101105); + SET_IDREG(isar, ID_MMFR1, 0x40000000); + SET_IDREG(isar, ID_MMFR2, 0x01240000); + SET_IDREG(isar, ID_MMFR3, 0x02102211); /* * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but * table 4-41 gives 0x02101110, which includes the arm div insns. @@ -559,10 +555,10 @@ static void cortex_a15_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x00011011); SET_IDREG(isar, ID_DFR0, 0x02010555); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x20000000; - cpu->isar.id_mmfr2 =3D 0x01240000; - cpu->isar.id_mmfr3 =3D 0x02102211; + SET_IDREG(isar, ID_MMFR0, 0x10201105); + SET_IDREG(isar, ID_MMFR1, 0x20000000); + SET_IDREG(isar, ID_MMFR2, 0x01240000); + SET_IDREG(isar, ID_MMFR3, 0x02102211); SET_IDREG(isar, ID_ISAR0, 0x02101110); SET_IDREG(isar, ID_ISAR1, 0x13112111); SET_IDREG(isar, ID_ISAR2, 0x21232041); @@ -603,10 +599,10 @@ static void cortex_r5_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x001); SET_IDREG(isar, ID_DFR0, 0x010400); cpu->id_afr0 =3D 0x0; - cpu->isar.id_mmfr0 =3D 0x0210030; - cpu->isar.id_mmfr1 =3D 0x00000000; - cpu->isar.id_mmfr2 =3D 0x01200000; - cpu->isar.id_mmfr3 =3D 0x0211; + SET_IDREG(isar, ID_MMFR0, 0x0210030); + SET_IDREG(isar, ID_MMFR1, 0x00000000); + SET_IDREG(isar, ID_MMFR2, 0x01200000); + SET_IDREG(isar, ID_MMFR3, 0x0211); SET_IDREG(isar, ID_ISAR0, 0x02101111); SET_IDREG(isar, ID_ISAR1, 0x13112111); SET_IDREG(isar, ID_ISAR2, 0x21232141); @@ -750,11 +746,11 @@ static void cortex_r52_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x10111001); SET_IDREG(isar, ID_DFR0, 0x03010006); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x00211040; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01200000; - cpu->isar.id_mmfr3 =3D 0xf0102211; - cpu->isar.id_mmfr4 =3D 0x00000010; + SET_IDREG(isar, ID_MMFR0, 0x00211040); + SET_IDREG(isar, ID_MMFR1, 0x40000000); + SET_IDREG(isar, ID_MMFR2, 0x01200000); + SET_IDREG(isar, ID_MMFR3, 0xf0102211); + SET_IDREG(isar, ID_MMFR4, 0x00000010); SET_IDREG(isar, ID_ISAR0, 0x02101110); SET_IDREG(isar, ID_ISAR1, 0x13112111); SET_IDREG(isar, ID_ISAR2, 0x21232142); @@ -982,10 +978,10 @@ static void arm_max_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x00011011); SET_IDREG(isar, ID_DFR0, 0x03010066); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x10101105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02102211; + SET_IDREG(isar, ID_MMFR0, 0x10101105); + SET_IDREG(isar, ID_MMFR1, 0x40000000); + SET_IDREG(isar, ID_MMFR2, 0x01260000); + SET_IDREG(isar, ID_MMFR3, 0x02102211); SET_IDREG(isar, ID_ISAR0, 0x02101110); SET_IDREG(isar, ID_ISAR1, 0x13112111); SET_IDREG(isar, ID_ISAR2, 0x21232042); diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index aeaade488fe3..937f29e253d7 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -53,10 +53,10 @@ static void aarch64_a35_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x00011011); SET_IDREG(isar, ID_DFR0, 0x03010066); cpu->id_afr0 =3D 0; - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02102211; + SET_IDREG(isar, ID_MMFR0, 0x10201105); + SET_IDREG(isar, ID_MMFR1, 0x40000000); + SET_IDREG(isar, ID_MMFR2, 0x01260000); + SET_IDREG(isar, ID_MMFR3, 0x02102211); SET_IDREG(isar, ID_ISAR0, 0x02101110); SET_IDREG(isar, ID_ISAR1, 0x13112111); SET_IDREG(isar, ID_ISAR2, 0x21232042); @@ -236,11 +236,11 @@ static void aarch64_a55_initfn(Object *obj) SET_IDREG(isar, ID_ISAR4, 0x00011142); SET_IDREG(isar, ID_ISAR5, 0x01011121); SET_IDREG(isar, ID_ISAR6, 0x00000010); - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02122211; - cpu->isar.id_mmfr4 =3D 0x00021110; + SET_IDREG(isar, ID_MMFR0, 0x10201105); + SET_IDREG(isar, ID_MMFR1, 0x40000000); + SET_IDREG(isar, ID_MMFR2, 0x01260000); + SET_IDREG(isar, ID_MMFR3, 0x02122211); + SET_IDREG(isar, ID_MMFR4, 0x00021110); SET_IDREG(isar, ID_PFR0, 0x10010131); SET_IDREG(isar, ID_PFR1, 0x00011011); SET_IDREG(isar, ID_PFR2, 0x00000011); @@ -299,10 +299,10 @@ static void aarch64_a72_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x00011011); SET_IDREG(isar, ID_DFR0, 0x03010066); cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02102211; + SET_IDREG(isar, ID_MMFR0, 0x10201105); + SET_IDREG(isar, ID_MMFR1, 0x40000000); + SET_IDREG(isar, ID_MMFR2, 0x01260000); + SET_IDREG(isar, ID_MMFR3, 0x02102211); SET_IDREG(isar, ID_ISAR0, 0x02101110); SET_IDREG(isar, ID_ISAR1, 0x13112111); SET_IDREG(isar, ID_ISAR2, 0x21232042); @@ -369,11 +369,11 @@ static void aarch64_a76_initfn(Object *obj) SET_IDREG(isar, ID_ISAR4, 0x00010142); SET_IDREG(isar, ID_ISAR5, 0x01011121); SET_IDREG(isar, ID_ISAR6, 0x00000010); - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02122211; - cpu->isar.id_mmfr4 =3D 0x00021110; + SET_IDREG(isar, ID_MMFR0, 0x10201105); + SET_IDREG(isar, ID_MMFR1, 0x40000000); + SET_IDREG(isar, ID_MMFR2, 0x01260000); + SET_IDREG(isar, ID_MMFR3, 0x02122211); + SET_IDREG(isar, ID_MMFR4, 0x00021110); SET_IDREG(isar, ID_PFR0, 0x10010131); SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ SET_IDREG(isar, ID_PFR2, 0x00000011); @@ -617,11 +617,11 @@ static void aarch64_neoverse_n1_initfn(Object *obj) SET_IDREG(isar, ID_ISAR4, 0x00010142); SET_IDREG(isar, ID_ISAR5, 0x01011121); SET_IDREG(isar, ID_ISAR6, 0x00000010); - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02122211; - cpu->isar.id_mmfr4 =3D 0x00021110; + SET_IDREG(isar, ID_MMFR0, 0x10201105); + SET_IDREG(isar, ID_MMFR1, 0x40000000); + SET_IDREG(isar, ID_MMFR2, 0x01260000); + SET_IDREG(isar, ID_MMFR3, 0x02122211); + SET_IDREG(isar, ID_MMFR4, 0x00021110); SET_IDREG(isar, ID_PFR0, 0x10010131); SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ SET_IDREG(isar, ID_PFR2, 0x00000011); @@ -696,11 +696,11 @@ static void aarch64_neoverse_v1_initfn(Object *obj) SET_IDREG(isar, ID_ISAR4, 0x00010142); SET_IDREG(isar, ID_ISAR5, 0x11011121); SET_IDREG(isar, ID_ISAR6, 0x01100111); - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02122211; - cpu->isar.id_mmfr4 =3D 0x01021110; + SET_IDREG(isar, ID_MMFR0, 0x10201105); + SET_IDREG(isar, ID_MMFR1, 0x40000000); + SET_IDREG(isar, ID_MMFR2, 0x01260000); + SET_IDREG(isar, ID_MMFR3, 0x02122211); + SET_IDREG(isar, ID_MMFR4, 0x01021110); SET_IDREG(isar, ID_PFR0, 0x21110131); SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ SET_IDREG(isar, ID_PFR2, 0x00000011); @@ -906,17 +906,17 @@ static void aarch64_a710_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ SET_IDREG(isar, ID_DFR0, 0x16011099); cpu->id_afr0 =3D 0; - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02122211; + SET_IDREG(isar, ID_MMFR0, 0x10201105); + SET_IDREG(isar, ID_MMFR1, 0x40000000); + SET_IDREG(isar, ID_MMFR2, 0x01260000); + SET_IDREG(isar, ID_MMFR3, 0x02122211); SET_IDREG(isar, ID_ISAR0, 0x02101110); SET_IDREG(isar, ID_ISAR1, 0x13112111); SET_IDREG(isar, ID_ISAR2, 0x21232042); SET_IDREG(isar, ID_ISAR3, 0x01112131); SET_IDREG(isar, ID_ISAR4, 0x00010142); SET_IDREG(isar, ID_ISAR5, 0x11011121); /* with Crypto */ - cpu->isar.id_mmfr4 =3D 0x21021110; + SET_IDREG(isar, ID_MMFR4, 0x21021110); SET_IDREG(isar, ID_ISAR6, 0x01111111); cpu->isar.mvfr0 =3D 0x10110222; cpu->isar.mvfr1 =3D 0x13211111; @@ -1008,17 +1008,17 @@ static void aarch64_neoverse_n2_initfn(Object *obj) SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ SET_IDREG(isar, ID_DFR0, 0x16011099); cpu->id_afr0 =3D 0; - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01260000; - cpu->isar.id_mmfr3 =3D 0x02122211; + SET_IDREG(isar, ID_MMFR0, 0x10201105); + SET_IDREG(isar, ID_MMFR1, 0x40000000); + SET_IDREG(isar, ID_MMFR2, 0x01260000); + SET_IDREG(isar, ID_MMFR3, 0x02122211); SET_IDREG(isar, ID_ISAR0, 0x02101110); SET_IDREG(isar, ID_ISAR1, 0x13112111); SET_IDREG(isar, ID_ISAR2, 0x21232042); SET_IDREG(isar, ID_ISAR3, 0x01112131); SET_IDREG(isar, ID_ISAR4, 0x00010142); SET_IDREG(isar, ID_ISAR5, 0x11011121); /* with Crypto */ - cpu->isar.id_mmfr4 =3D 0x01021110; + SET_IDREG(isar, ID_MMFR4, 0x01021110); SET_IDREG(isar, ID_ISAR6, 0x01111111); cpu->isar.mvfr0 =3D 0x10110222; cpu->isar.mvfr1 =3D 0x13211111; --=20 2.49.0 From nobody Sat Nov 15 20:48:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1750175976; cv=none; d=zohomail.com; s=zohoarc; b=mJuHH+jstUBCnR/hhyN8kQyOaVewDNnjxU6+QByTZPQvV/vTIggAEy7kaXnjVlt6ciePa0SnPDyT41bcNiu+xBBzbSCRSqVShfsQkb1ZO65es57CCegnHXkXCoQPjh5f1NQJNQYi6IvVlYifRrVPHL39wrVP3xQTFxi0EbaEYDM= ARC-Message-Signature: i=1; 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charset="utf-8" From: Eric Auger Introduce scripts that automate the generation of system register definitions from a given linux source tree arch/arm64/tools/sysreg. Invocation of ./update-aarch64-sysreg-code.sh $PATH_TO_LINUX_SOURCE_TREE in scripts directory generates target/arm/cpu-sysregs.h.inc containing defines for all system registers. [CH: update to handle current kernel sysregs structure, and to emit the re-worked register structures; cpu properties will be added later] Reviewed-by: Sebastian Ott Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- MAINTAINERS | 1 + scripts/arm-gen-cpu-sysregs-header.awk | 37 ++++++++++++++++++++++++++ scripts/update-aarch64-sysreg-code.sh | 32 ++++++++++++++++++++++ 3 files changed, 70 insertions(+) create mode 100755 scripts/arm-gen-cpu-sysregs-header.awk create mode 100755 scripts/update-aarch64-sysreg-code.sh diff --git a/MAINTAINERS b/MAINTAINERS index 28b3dd2684b4..01334cb93ca1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -443,6 +443,7 @@ M: Peter Maydell L: qemu-arm@nongnu.org S: Maintained F: target/arm/kvm.c +F: scripts/*-sysreg* =20 MIPS KVM CPUs M: Huacai Chen diff --git a/scripts/arm-gen-cpu-sysregs-header.awk b/scripts/arm-gen-cpu-s= ysregs-header.awk new file mode 100755 index 000000000000..f92bbbafa727 --- /dev/null +++ b/scripts/arm-gen-cpu-sysregs-header.awk @@ -0,0 +1,37 @@ +#!/bin/awk -f +# SPDX-License-Identifier: GPL-2.0-or-later +# arm-gen-cpu-sysregs-header.awk: arm64 sysreg header include generator +# +# Usage: awk -f arm-gen-cpu-sysregs-header.awk $LINUX_PATH/arch/arm64/tool= s/sysreg + +BEGIN { + print "/* SPDX-License-Identifier: GPL-2.0-or-later */" + print "/* GENERATED FILE, DO NOT EDIT */" + print "/* use arm-gen-cpu-sysregs-header.awk to regenerate */" +} END { + print "" +} + +# skip blank lines and comment lines +/^$/ { next } +/^[\t ]*#/ { next } + +/^Sysreg\t/ || /^Sysreg /{ + + reg =3D $2 + op0 =3D $3 + op1 =3D $4 + crn =3D $5 + crm =3D $6 + op2 =3D $7 + + if (op0 =3D=3D 3 && (op1=3D=3D0 || op1=3D=3D1 || op1=3D=3D3) && crn=3D=3D= 0 && (crm>=3D0 && crm<=3D7) && (op2>=3D0 && op2<=3D7)) { + print "DEF("reg", "op0", "op1", "crn", "crm", "op2")" + } + next +} + +{ + /* skip all other lines */ + next +} diff --git a/scripts/update-aarch64-sysreg-code.sh b/scripts/update-aarch64= -sysreg-code.sh new file mode 100755 index 000000000000..7bba0bcd6f66 --- /dev/null +++ b/scripts/update-aarch64-sysreg-code.sh @@ -0,0 +1,32 @@ +#!/bin/sh -e +# +# SPDX-License-Identifier: GPL-2.0-or-later +# Update target/arm/cpu-sysregs.h +# from a linux source tree (arch/arm64/tools/sysreg) +# +# Copyright Red Hat, Inc. 2024 +# +# Authors: +# Eric Auger +# + +scripts=3D"$(dirname "$0")" +linux=3D"$1" +output=3D"$2" + +if [ -z "$linux" ] || ! [ -d "$linux" ]; then + cat << EOF +usage: update-aarch64-sysreg-code.sh LINUX_PATH [OUTPUT_PATH] + +LINUX_PATH Linux kernel directory to obtain the register definitions = from +OUTPUT_PATH output directory, usually the qemu source tree (default: $= PWD) +EOF + exit 1 +fi + +if [ -z "$output" ]; then + output=3D"$PWD" +fi + +awk -f $scripts/arm-gen-cpu-sysregs-header.awk \ + $linux/arch/arm64/tools/sysreg > $output/target/arm/cpu-sysregs.h.inc --=20 2.49.0 From nobody Sat Nov 15 20:48:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1750175976; cv=none; d=zohomail.com; s=zohoarc; b=TASzANo8WhJLHSC6V8RkdXI4TBL1DvpD9ENhdWDY+//v+duKmQTZmN77A+01HMAfMyt/Z3k7+gDkLvoP4Ut3+mpwWEBkfXOxDV0Wy8swsMCw5TO/4f12Faez90PNkuJb3h4FMeKGibEec2PVAX/Oe77aP5eKNHCzPhZspWDgOUw= ARC-Message-Signature: i=1; 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Tue, 17 Jun 2025 15:41:06 +0000 (UTC) Received: from gondolin.str.redhat.com (pixel-6a.str.redhat.com [10.33.192.205]) by mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 4739E180035C; Tue, 17 Jun 2025 15:41:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1750174872; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=pbxMR4zpyo3J6LniePBWyJnj/wYIipfJzeHg05b32x8=; b=bEeC3+XsqVVJ+DWqQ5u5Nhr7HcHm6PFBv09qdigkmBLwbNpHDS4p+diBOmGkFKYYh6UcVr Z0kqTtsECdk1zKeIEHIIHibYRJ5fU7bJCjuS5i21QeBnMBdl5N9uljiSHZ400JHtrqjY/4 uBD3yk5RJPGwBHLpPLcx1+4x1GYUh+Y= X-MC-Unique: FaV9E22xOnSpzilSqE6qkw-1 X-Mimecast-MFC-AGG-ID: FaV9E22xOnSpzilSqE6qkw_1750174866 From: Cornelia Huck To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com, agraf@csgraf.de Cc: shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com, Cornelia Huck Subject: [PATCH v8 13/14] arm/cpu: switch to a generated cpu-sysregs.h.inc Date: Tue, 17 Jun 2025 17:39:30 +0200 Message-ID: <20250617153931.1330449-14-cohuck@redhat.com> In-Reply-To: <20250617153931.1330449-1-cohuck@redhat.com> References: <20250617153931.1330449-1-cohuck@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Generated against Linux 6.15. Reviewed-by: Sebastian Ott Reviewed-by: Eric Auger Signed-off-by: Cornelia Huck --- target/arm/cpu-sysregs.h.inc | 43 +++++++++++++++++++++++++----------- 1 file changed, 30 insertions(+), 13 deletions(-) diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc index cb99286f7048..1dddd3d357eb 100644 --- a/target/arm/cpu-sysregs.h.inc +++ b/target/arm/cpu-sysregs.h.inc @@ -1,19 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -DEF(ID_AA64PFR0_EL1, 3, 0, 0, 4, 0) -DEF(ID_AA64PFR1_EL1, 3, 0, 0, 4, 1) -DEF(ID_AA64SMFR0_EL1, 3, 0, 0, 4, 5) -DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0) -DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1) -DEF(ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0) -DEF(ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1) -DEF(ID_AA64ISAR2_EL1, 3, 0, 0, 6, 2) -DEF(ID_AA64MMFR0_EL1, 3, 0, 0, 7, 0) -DEF(ID_AA64MMFR1_EL1, 3, 0, 0, 7, 1) -DEF(ID_AA64MMFR2_EL1, 3, 0, 0, 7, 2) -DEF(ID_AA64MMFR3_EL1, 3, 0, 0, 7, 3) +/* GENERATED FILE, DO NOT EDIT */ +/* use arm-gen-cpu-sysregs-header.awk to regenerate */ DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0) DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1) DEF(ID_DFR0_EL1, 3, 0, 0, 1, 2) +DEF(ID_AFR0_EL1, 3, 0, 0, 1, 3) DEF(ID_MMFR0_EL1, 3, 0, 0, 1, 4) DEF(ID_MMFR1_EL1, 3, 0, 0, 1, 5) DEF(ID_MMFR2_EL1, 3, 0, 0, 1, 6) @@ -24,13 +15,39 @@ DEF(ID_ISAR2_EL1, 3, 0, 0, 2, 2) DEF(ID_ISAR3_EL1, 3, 0, 0, 2, 3) DEF(ID_ISAR4_EL1, 3, 0, 0, 2, 4) DEF(ID_ISAR5_EL1, 3, 0, 0, 2, 5) -DEF(ID_MMFR4_EL1, 3, 0, 0, 2, 6) DEF(ID_ISAR6_EL1, 3, 0, 0, 2, 7) +DEF(ID_MMFR4_EL1, 3, 0, 0, 2, 6) DEF(MVFR0_EL1, 3, 0, 0, 3, 0) DEF(MVFR1_EL1, 3, 0, 0, 3, 1) DEF(MVFR2_EL1, 3, 0, 0, 3, 2) DEF(ID_PFR2_EL1, 3, 0, 0, 3, 4) DEF(ID_DFR1_EL1, 3, 0, 0, 3, 5) DEF(ID_MMFR5_EL1, 3, 0, 0, 3, 6) +DEF(ID_AA64PFR0_EL1, 3, 0, 0, 4, 0) +DEF(ID_AA64PFR1_EL1, 3, 0, 0, 4, 1) +DEF(ID_AA64PFR2_EL1, 3, 0, 0, 4, 2) DEF(ID_AA64ZFR0_EL1, 3, 0, 0, 4, 4) +DEF(ID_AA64SMFR0_EL1, 3, 0, 0, 4, 5) +DEF(ID_AA64FPFR0_EL1, 3, 0, 0, 4, 7) +DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0) +DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1) +DEF(ID_AA64DFR2_EL1, 3, 0, 0, 5, 2) +DEF(ID_AA64AFR0_EL1, 3, 0, 0, 5, 4) +DEF(ID_AA64AFR1_EL1, 3, 0, 0, 5, 5) +DEF(ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0) +DEF(ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1) +DEF(ID_AA64ISAR2_EL1, 3, 0, 0, 6, 2) +DEF(ID_AA64ISAR3_EL1, 3, 0, 0, 6, 3) +DEF(ID_AA64MMFR0_EL1, 3, 0, 0, 7, 0) +DEF(ID_AA64MMFR1_EL1, 3, 0, 0, 7, 1) +DEF(ID_AA64MMFR2_EL1, 3, 0, 0, 7, 2) +DEF(ID_AA64MMFR3_EL1, 3, 0, 0, 7, 3) +DEF(ID_AA64MMFR4_EL1, 3, 0, 0, 7, 4) +DEF(CCSIDR_EL1, 3, 1, 0, 0, 0) +DEF(CLIDR_EL1, 3, 1, 0, 0, 1) +DEF(CCSIDR2_EL1, 3, 1, 0, 0, 2) +DEF(GMID_EL1, 3, 1, 0, 0, 4) +DEF(SMIDR_EL1, 3, 1, 0, 0, 6) DEF(CTR_EL0, 3, 3, 0, 0, 1) +DEF(DCZID_EL0, 3, 3, 0, 0, 7) + --=20 2.49.0 From nobody Sat Nov 15 20:48:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1750174881; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=aSFgDrP9kHSG5CJCRypPsuwvrYcuRcBe7vg+Zrvp1qY=; b=BB6uHH5xGQtI1XL63lHYSzRbZfTSwKEha5899JGGIyXCYRZ9VmzRgVes71nHyEQparE8UI Sb+Y/uqu8JxdM+NbA8sWyvSfZc7mJGVm46qKuhAnxeJpZ27SE8JdjtfsLjJ6LvYyNeUfd7 +298UQAAjcjugzm0LInfSDEqe/ebuLY= X-MC-Unique: 4FPw8sDeNuyYaJs4eO6ETg-1 X-Mimecast-MFC-AGG-ID: 4FPw8sDeNuyYaJs4eO6ETg_1750174872 From: Cornelia Huck To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com, agraf@csgraf.de Cc: shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com, Cornelia Huck Subject: [PATCH v8 14/14] arm/kvm: use fd instead of fdarray[2] Date: Tue, 17 Jun 2025 17:39:31 +0200 Message-ID: <20250617153931.1330449-15-cohuck@redhat.com> In-Reply-To: <20250617153931.1330449-1-cohuck@redhat.com> References: <20250617153931.1330449-1-cohuck@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" We have fd, so might as well neaten things up. Suggested-by: Eric Auger Reviewed-by: Eric Auger Signed-off-by: Cornelia Huck --- target/arm/kvm.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 3df046b2b911..70919aedd0a4 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -348,11 +348,11 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUF= eatures *ahcf) err |=3D get_host_cpu_reg(fd, ahcf, ID_ISAR6_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_MMFR4_EL1_IDX); =20 - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, + err |=3D read_sys_reg32(fd, &ahcf->isar.mvfr0, ARM64_SYS_REG(3, 0, 0, 3, 0)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1, + err |=3D read_sys_reg32(fd, &ahcf->isar.mvfr1, ARM64_SYS_REG(3, 0, 0, 3, 1)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2, + err |=3D read_sys_reg32(fd, &ahcf->isar.mvfr2, ARM64_SYS_REG(3, 0, 0, 3, 2)); err |=3D get_host_cpu_reg(fd, ahcf, ID_PFR2_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_DFR1_EL1_IDX); @@ -390,7 +390,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) =20 if (pmu_supported) { /* PMCR_EL0 is only accessible if the vCPU has feature PMU_V3 = */ - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, + err |=3D read_sys_reg64(fd, &ahcf->isar.reset_pmcr_el0, ARM64_SYS_REG(3, 3, 9, 12, 0)); } =20 --=20 2.49.0