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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4532e13c192sm146561975e9.26.2025.06.16.07.06.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jun 2025 07:06:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1750082800; x=1750687600; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=LChNT2oan2dCMkf7YUp2ghN9GIJ92+FXAYXzABpNUw8=; b=yplTDK2QVw1f7Pv+/Dt86BXSznEG39wVACjtlZIP8bEZAqYLWpFcxQlgmR92k3Cu/M alj6gSWF5nKSNw5NXfmm51qG7j2pUlv0stLMy/iOg+oivCsxWDyosb/cByDtWPQpMxXy lC+nMsETsq6gcJareYU4TGAKmjxwHxLXgvcvbTwGXwFtBcuG2GYT49CU3JuvYib5hsQ6 tceaOW9aeVauCOAi9OWVmg61QCR0DNolhXT28VfsKnWs1wEamThONLDQVEX8+sQalVCt hn/fo7XIt58CqExRzM34lMxJlVUdt6dHkzxpxNuZ5m4Ox3ortLurGmcct0cMMZIhi8Zu y0Lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750082800; x=1750687600; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LChNT2oan2dCMkf7YUp2ghN9GIJ92+FXAYXzABpNUw8=; b=j0s+i3XnBfYkubB5imNWLmHIPD3lejyv9xe+s2/GdsTCsVDwz7BWVMKjrqyj7qq0Rz a//zsxggmZHr/GbiuVdBsbIGcIwdDvqFHl340VdSKr4bt5P6ATwV2P/B+Ap+f7N9ET2r kOWJ0nrlZYoDzJ8IfNJ1HOuxg+v3f5XC+S8xdUz1orKG+SV21XFUQuVq5GbuEYWjR4/h hc4cfS+lp0u/76NE4xjEfW98uq9YB7IQmcFLQ9K5/d/YDssMHi65r9YthQsbvIab400U iSiG9kgP3YAV1sKncpdichDsrEnGxNgPHRD5LGOYSSZlQrBpMPCPgW0FJxH0aijKfFq7 n7uQ== X-Gm-Message-State: AOJu0YxDe16DVTaRBsa2REC7EY5hM4MOqkRlmKKJXw3iL57T1aaKW57r 1seqmj3FqJ7vaFeKVaTnBehmBkn96yhw4kycvXAC+zN6s3taoPvj7cQ9IDLUcKpGKX1QqFScJBB akbbZ X-Gm-Gg: ASbGnctHe7IsRR13E5qm37ItCQzLgESft+VE7PFDJdl/gqCEcZx6zao3oPeLVjx10L2 t4/KvFVHY4JR9ujLo0IkHFVHPCE5TgQXvT+6TF/5Z/vH0Kn0mhtM/O6SGneeaYQpBpoc4poTjPY I4mKTBYy3FbuI2gHDN0cvl1FZl3JbZUpVFUO8elBvldKMZd872V66Qg8Guq+xRi9+bRPOwPli43 cwlEQBoq7xcNcYRbP3REJh+ZNXGHyQp5uYSQw6/JZya7MmODZczSM5SCuBZxurGLO5ePbu7ET7J ZlBozsMKtfeumfUEvBSK0gvLqf0CyoUn8aaigPeBxA54G4D6VHxQAwWEU/+oMPJjA9Bc X-Google-Smtp-Source: AGHT+IGJqHXYcba1VCswTvfaxnwCn7dIqydzLTDOlZAKGF5MFlnGtikP7ITD9CNBuvxnHo7lVRItJg== X-Received: by 2002:a05:600c:1549:b0:43d:fa5f:7d30 with SMTP id 5b1f17b1804b1-4533c97c5eamr85760065e9.16.1750082796972; Mon, 16 Jun 2025 07:06:36 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 4/9] target/arm: Define raw write for PMU CLR registers Date: Mon, 16 Jun 2025 15:06:25 +0100 Message-ID: <20250616140630.2273870-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250616140630.2273870-1-peter.maydell@linaro.org> References: <20250616140630.2273870-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1750082870002116600 Content-Type: text/plain; charset="utf-8" From: Akihiko Odaki Raw writes to PMCNTENCLR and PMCNTENCLR_EL0 incorrectly used their default write function, which clears written bits instead of writes the raw value. PMINTENCLR and PMINTENCLR_EL1 are similar registers, but they instead had ARM_CP_NO_RAW. Commit 7a0e58fa6487 ("target-arm: Split NO_MIGRATE into ALIAS and NO_RAW") sugguests ARM_CP_ALIAS should be used instead of ARM_CP_NO_RAW in such a case: > We currently mark ARM coprocessor/system register definitions with > the flag ARM_CP_NO_MIGRATE for two different reasons: > 1) register is an alias on to state that's also visible via > some other register, and that other register is the one > responsible for migrating the state > 2) register is not actually state at all (for instance the TLB > or cache maintenance operation "registers") and it makes no > sense to attempt to migrate it or otherwise access the raw state > > This works fine for identifying which registers should be ignored > when performing migration, but we also use the same functions for > synchronizing system register state between QEMU and the kernel > when using KVM. In this case we don't want to try to sync state > into registers in category 2, but we do want to sync into registers > in category 1, because the kernel might have picked a different > one of the aliases as its choice for which one to expose for > migration. These registers fall in category 1 (ARM_CP_ALIAS), not category 2 (ARM_CP_NO_RAW). ARM_CP_NO_RAW also has another undesired side effect that hides registers from GDB. Properly set raw write functions and drop the ARM_CP_NO_RAW flag from PMINTENCLR and PMINTENCLR_EL1; this fixes GDB/KVM state synchronization of PMCNTENCLR and PMCNTENCLR_EL0, and exposes all these four registers to GDB. It is not necessary to add ARM_CP_ALIAS to these registers because the flag is already set. Signed-off-by: Akihiko Odaki Message-id: 20250531-clr-v3-1-377f9bf1746d@rsg.ci.i.u-tokyo.ac.jp Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 76312102879..889d3088079 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1904,7 +1904,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcnten), .accessfn =3D pmreg_access, .fgt =3D FGT_PMCNTEN, - .writefn =3D pmcntenclr_write, + .writefn =3D pmcntenclr_write, .raw_writefn =3D raw_write, .type =3D ARM_CP_ALIAS | ARM_CP_IO }, { .name =3D "PMCNTENCLR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 2, @@ -1912,7 +1912,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .fgt =3D FGT_PMCNTEN, .type =3D ARM_CP_ALIAS | ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcnten), - .writefn =3D pmcntenclr_write }, + .writefn =3D pmcntenclr_write, .raw_writefn =3D raw_write }, { .name =3D "PMOVSR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 3, .access =3D PL0_RW, .type =3D ARM_CP_IO, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmovsr), @@ -2029,16 +2029,16 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { { .name =3D "PMINTENCLR", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 2, .access =3D PL1_RW, .accessfn =3D access_tpm, .fgt =3D FGT_PMINTEN, - .type =3D ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, + .type =3D ARM_CP_ALIAS | ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pminten), - .writefn =3D pmintenclr_write, }, + .writefn =3D pmintenclr_write, .raw_writefn =3D raw_write }, { .name =3D "PMINTENCLR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D 2, .access =3D PL1_RW, .accessfn =3D access_tpm, .fgt =3D FGT_PMINTEN, - .type =3D ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, + .type =3D ARM_CP_ALIAS | ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pminten), - .writefn =3D pmintenclr_write }, + .writefn =3D pmintenclr_write, .raw_writefn =3D raw_write }, { .name =3D "CCSIDR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, .opc2 =3D 0, .access =3D PL1_R, --=20 2.43.0