From nobody Sat Nov 15 14:52:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1750082938; cv=none; d=zohomail.com; s=zohoarc; b=IwMry7NSLBijiya+mX7o88U+Fdhg+gUpRDl5LKLVeEp9UUNjcsSvAC19lfqkTkNdWNcvAopW+gZoN0b2t9wgiDEsNhmgZCwkYYl2YX/sRVooAv0U9HEpFwpXXvkqgjcbdl9VDOfZ2dq3w4U8GTkFnM+RAPqyoiYSvQ0XiHD2HIE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750082938; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=L67vA0aSsh45bJksX1C5CfPxf17pRwQQix91wLS7SE4=; b=hx1plUs6p1DlLU5zT4Y0zXkrQDtTl/JA9aomVwAc/5peRNxmfHp8oWCFG/Q5P+zSmP8li4EslQu5DVdqg897X+0uR4irg/VJeFRdl2daqQ0CJ5xUYbmu3cDqaQZ9lsbuwGsOgTfuFRJQMzG9YZBOb3i6tMrfEwZE0zX6SOwRDxw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175008293817835.43178329766715; Mon, 16 Jun 2025 07:08:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uRAUY-0001Dq-Pn; Mon, 16 Jun 2025 10:07:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uRATw-00015D-L7 for qemu-devel@nongnu.org; Mon, 16 Jun 2025 10:06:41 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uRATs-0003yp-A9 for qemu-devel@nongnu.org; Mon, 16 Jun 2025 10:06:40 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-450cb2ddd46so25427055e9.2 for ; Mon, 16 Jun 2025 07:06:35 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4532e13c192sm146561975e9.26.2025.06.16.07.06.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jun 2025 07:06:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1750082794; x=1750687594; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=L67vA0aSsh45bJksX1C5CfPxf17pRwQQix91wLS7SE4=; b=jq2LosOgQgZ33brD1TpJW/g043PR3InznTWReX4YxzisjocGbaaoCiwNMBgtGFcEsY hHaQnGEO4GxTsyXzZOxla5YBG0GwiuX0RSKFQhKaxNu85GnhTJvZnx5XCBWHP8nAj8Ug qt2dWDw7fYFiMlSkZzVCrcmg4LfwzyfLWKe1T/1QlwanHppSPK/4XPb5bsEKLwEN1tVF LTOOwQ9vF67jbKfqkpdjWF/qTCzdWTSoFG4pzQQjbZ2Z+vTBMm/DAy3I/3IQ/xpIbYBH JKegYdGV5+Gxu7Fi3gBZXmxfr5t+m571HzNrV2vP6eQ7dORf+WNUk/k6v0fUNp/8kNsc ekmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750082794; x=1750687594; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=L67vA0aSsh45bJksX1C5CfPxf17pRwQQix91wLS7SE4=; b=IMCCklH38+dIoWajhEOLnfXoqa7G7Jf5KCGEwLNPLVHQI8TSCl5mn8wp0hyy9DGEwd A40rEEjM7yhH+Z2Ex1VUUOr9I9YhLr3J+sV2lWAbOBHB9yMdi+HLYMN88EaHMxayN7qx 6DkLEUNcirnUqBAzRYFqmaPqwhixwZBo/2K1U8X5NeMxnMknfzNaiHSN+UKLoMgrJc8X O4sYeK/zuaq2ou0lOslWbBQYlromyF642Xe6FPKpf4AJW0hJ5j2Sruq+ZyX+XMx6NLPl xSSyZTx3orQgdp1vyCkgN3q7OWIZKqJcKSynih8BucLug1YdNG7cBLSfByfnsMKuJvfF ZeCA== X-Gm-Message-State: AOJu0Yx0nTqlfoJYBa2yF5YIE4AZMC1AJxUxefrGCC+TNQY8b4xqVgY/ vQm2NUalLloY9UMqyvo2bqNWQ9JUbujNbpe/k1i9uoyyxsPwwEGL6i3uPf4S9oUdQ4LHIXMizQg f1KUV X-Gm-Gg: ASbGnctAAHxBTHk+ZNnWwh9frwrG/Sd+0rq6R0Xh7+lHXL+SQDwgeqGLOMNNxkDJAQG NW3AzfMbaOs9ieIoBoht6TmdWe+q5RDPlNp1P5Dh5NDOH56AuzFKfNk7WYr0UQqF5yvb0lnrIXf uyyZ7NTb7h48pBa6hCIduMLO7/PnTTgMpds58kMKeN1ZR4VA3DkW0nym7l5GtqyrSV9JMMx8VQZ PdEl0M+OHxYIKI4Ha7hXYTf0v9MnW99GxpWQYyUzwXXUFAtrYag9k1AnsM5owqv/7K5So0MsBq2 ajikbF0TENTUfESg6/SkMBINlt8E3o/zynUGXj5ZS5zdGT8o80DJl+8M6vKqoA7Db+5f X-Google-Smtp-Source: AGHT+IHxCWgaBTRw2GeBSmjAqYVyl5rb36FJuSMae1Djyy0cZsVMLQ70IgWxwMWNUxcJP24aCmXGNQ== X-Received: by 2002:a05:600c:4e14:b0:44a:ac77:26d5 with SMTP id 5b1f17b1804b1-4533ca572f5mr94117475e9.14.1750082793726; Mon, 16 Jun 2025 07:06:33 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 1/9] hw/arm/virt: Check bypass iommu is not set for iommu-map DT property Date: Mon, 16 Jun 2025 15:06:22 +0100 Message-ID: <20250616140630.2273870-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250616140630.2273870-1-peter.maydell@linaro.org> References: <20250616140630.2273870-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1750082940840116600 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum default_bus_bypass_iommu tells us whether the bypass_iommu is set for the default PCIe root bus. Make sure we check that before adding the "iommu-map" DT property. Cc: qemu-stable@nongnu.org Fixes: 6d7a85483a06 ("hw/arm/virt: Add default_bus_bypass_iommu machine opt= ion") Suggested-by: Eric Auger Signed-off-by: Shameer Kolothum Reviewed-by: Donald Dutile Reviewed-by: Eric Auger Message-id: 20250602114655.42920-1-shameerali.kolothum.thodi@huawei.com Signed-off-by: Peter Maydell --- hw/arm/virt.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 9a6cd085a37..99fde5836c9 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1487,9 +1487,12 @@ static void create_virtio_iommu_dt_bindings(VirtMach= ineState *vms) qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); g_free(node); =20 - qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map", - 0x0, vms->iommu_phandle, 0x0, bdf, - bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - = bdf); + if (!vms->default_bus_bypass_iommu) { + qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map", + 0x0, vms->iommu_phandle, 0x0, bdf, + bdf + 1, vms->iommu_phandle, bdf + 1, + 0xffff - bdf); + } } =20 static void create_pcie(VirtMachineState *vms) @@ -1612,8 +1615,10 @@ static void create_pcie(VirtMachineState *vms) switch (vms->iommu) { case VIRT_IOMMU_SMMUV3: create_smmu(vms, vms->bus); - qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map", - 0x0, vms->iommu_phandle, 0x0, 0x10000); + if (!vms->default_bus_bypass_iommu) { + qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map", + 0x0, vms->iommu_phandle, 0x0, 0x100= 00); + } break; default: g_assert_not_reached(); --=20 2.43.0 From nobody Sat Nov 15 14:52:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1750082896; cv=none; d=zohomail.com; s=zohoarc; b=e0AQTsi4drPDSoLkG3SvLtoA2nXc4sji+l3BOLTOnscagF3NgoRI6UjlrSn8PS9P7hAWDCJyseCrTu3luWBI1qeq/d42YIn9VkMGdOx22O3me/Qs16UE9SIxgRM8+DBmW+dQoXG19P22QBOw9zpghAGUXNsUGO6IaYbs3XNYdjU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750082896; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=jixPME6Y9feGFUr2gudtz74NxDsb7swpzH58eMF9CFw=; b=JIP5NPSXtRUMmoNEMXZOr6fm8AeKEylOTBtSm5+kKwSWRTo6Qj1EUZQcnWGsZndw1giLaoKOtwQw9WbUuKwFjkQ1WntkgSPVhk5lSK/s3iZLbj09M8S3wdq3o94kIOLDbc5bTvNc6k7hQ39Jx83OJhSAYFvI48hihy/9M0ZKQEw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750082896460761.4635499436383; Mon, 16 Jun 2025 07:08:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uRAUQ-00018y-FF; Mon, 16 Jun 2025 10:07:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uRATw-00015H-ST for qemu-devel@nongnu.org; Mon, 16 Jun 2025 10:06:41 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uRATs-0003zI-NE for qemu-devel@nongnu.org; Mon, 16 Jun 2025 10:06:40 -0400 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-3a50fc819f2so3868148f8f.2 for ; Mon, 16 Jun 2025 07:06:36 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4532e13c192sm146561975e9.26.2025.06.16.07.06.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jun 2025 07:06:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1750082795; x=1750687595; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=jixPME6Y9feGFUr2gudtz74NxDsb7swpzH58eMF9CFw=; b=c4BvAI3aP+DZb0/5fFLkm6i3Ja/8D4yj9bDWC0/mbJCrUVLD6uEjaoSj41kMf+hdTz zePK2otMHDGfeNum9uAz/WZVKmWD6kMTkTGJk01frq7wJxBkZnguR3bCAnosjdtichtA 3C9NXaqybj4fNn+1GGRPttTCJSglbJW81hdhh1mWQpWqsxuulm6tEzVFUkyqjtZfgHmL /FR6BXvnQ2tuOWLIb18Pk5VvSYerZOQCfuidAYcAWljDNi+i2zVCi8JYwmUM53a7BLax U+/iAIiIpR7lhCOS0/Oo+r0NKuGKOT9XoU3K41tbzSCleePoulBCu8qIp5WTDTQX4itn z7ZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750082795; x=1750687595; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jixPME6Y9feGFUr2gudtz74NxDsb7swpzH58eMF9CFw=; b=n0oMu7mFRzjHH2jDBTZp6mzS4hahhTMzkmIf7in82J9LBL2c+UlKPTNm/Vb/R+7qc9 Hok0MdKv6kvlqKGB5fT5FJlNO3ef3Dz3+mCqnrZhL/HsO9dXpmRVX7mgv5s/TD7k5XQy Y/jrgUryEioMhTSadjwBx9enmXcYo7UYD3aPwM7Pjtvjvp+/j1jv5+7bfLEkV8LNgDc+ Lp0r1W6me7pZ2wZHfotpqs+wf9KSj0/DmHY10H4TeUK3YjboNAh2uUUkvBXW4iMfmFwI 85VCVf75a8BY8aCZhfj+HTSnGrzSzKVVVmnkjQU4nhr70R5gyYopTDpmys93nSufK4gX kFtA== X-Gm-Message-State: AOJu0Yw59s4mhBCX9cKzprE7NwQP320M+erWAjB7i5gOkktvsDXSqwhq SnggYgVwhAS+qhF3iaA8CYnxO79hgbFdVSu7zaycCWRRKzfnACX5JtG0T8pNXSSWV2ndMBcdfDO 1lybH X-Gm-Gg: ASbGncsNq8UGFoJ2Ry6jNMBlquVX+B1NRnDrvNio3R9d8VppD5qzptGOTcuBd3KELUu LzCL+JubtOllwT1UM83C0fGBqqcCWGaN31fnYFHab1BaZtJqRsRpB7lSNEzA3/czuT/AEtivILs rgjD+uGe3RqJyXCAjfSgeGlwBVumEP8LlyJaCgVDiTg16W8FfB+muw1X4JucOqBhxae19R1BGya ZOKIQ+SGi2ADr3Nq3yQOGTfTu6qYdET8fFMQEnp38P3HMBEHot7iIazhcVMNSD3R5W2IqxwR/Lm EZz8WsWo/XQLKhahghAxD6lhFMOoTdd1zKHYgkCMWjj8SKr277wpQ8cDAHAgDOLXJk48 X-Google-Smtp-Source: AGHT+IFhLI+YgZ1RBnSwN49Bl/7SRvER3Q1cJSWUy1baxCQ2fSYShSn6YHYQ3RLAO7kSFQNaEak1Yg== X-Received: by 2002:a05:6000:653:b0:3a5:783f:5289 with SMTP id ffacd0b85a97d-3a5783f5758mr6080641f8f.49.1750082794556; Mon, 16 Jun 2025 07:06:34 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 2/9] tests/functional: Add a test for the realview-eb-mpcore machine Date: Mon, 16 Jun 2025 15:06:23 +0100 Message-ID: <20250616140630.2273870-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250616140630.2273870-1-peter.maydell@linaro.org> References: <20250616140630.2273870-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1750082898620116600 Content-Type: text/plain; charset="utf-8" From: Thomas Huth Check that we can boot a Linux kernel here and that we can at least send one ping network packet. Signed-off-by: Thomas Huth Message-id: 20250603101526.21217-1-thuth@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- MAINTAINERS | 1 + tests/functional/meson.build | 1 + tests/functional/test_arm_realview.py | 47 +++++++++++++++++++++++++++ 3 files changed, 49 insertions(+) create mode 100755 tests/functional/test_arm_realview.py diff --git a/MAINTAINERS b/MAINTAINERS index 28b3dd2684b..84cfef835eb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -955,6 +955,7 @@ F: hw/cpu/realview_mpcore.c F: hw/intc/realview_gic.c F: include/hw/intc/realview_gic.h F: docs/system/arm/realview.rst +F: tests/functional/test_arm_realview.py =20 SABRELITE / i.MX6 M: Peter Maydell diff --git a/tests/functional/meson.build b/tests/functional/meson.build index 7faa2b6e3c0..e7e051ef3c8 100644 --- a/tests/functional/meson.build +++ b/tests/functional/meson.build @@ -135,6 +135,7 @@ tests_arm_system_thorough =3D [ 'arm_orangepi', 'arm_quanta_gsj', 'arm_raspi2', + 'arm_realview', 'arm_replay', 'arm_smdkc210', 'arm_stellaris', diff --git a/tests/functional/test_arm_realview.py b/tests/functional/test_= arm_realview.py new file mode 100755 index 00000000000..82cc964333e --- /dev/null +++ b/tests/functional/test_arm_realview.py @@ -0,0 +1,47 @@ +#!/usr/bin/env python3 +# +# Functional test that boots a Linux kernel on a realview arm machine +# and checks the console +# +# SPDX-License-Identifier: GPL-2.0-or-later + +from qemu_test import LinuxKernelTest, exec_command_and_wait_for_pattern +from qemu_test import Asset + + +class RealviewMachine(LinuxKernelTest): + + ASSET_REALVIEW_MPCORE =3D Asset( + ('https://archive.openwrt.org/chaos_calmer/15.05.1/realview/generi= c/' + 'openwrt-15.05.1-realview-vmlinux-initramfs.elf'), + 'd3a01037f33e7512d46d50975588d5c3a0e0cbf25f37afab44775c2a2be523e6') + + def test_realview_ep_mpcore(self): + self.require_netdev('user') + self.set_machine('realview-eb-mpcore') + kernel_path =3D self.ASSET_REALVIEW_MPCORE.fetch() + self.vm.set_console() + kernel_param =3D 'console=3DttyAMA0 mem=3D128M quiet' + self.vm.add_args('-kernel', kernel_path, + '-append', kernel_param) + self.vm.launch() + self.wait_for_console_pattern('Please press Enter to activate') + prompt =3D ':/#' + exec_command_and_wait_for_pattern(self, '', prompt) + exec_command_and_wait_for_pattern(self, 'dmesg', kernel_param) + self.wait_for_console_pattern(prompt) + exec_command_and_wait_for_pattern(self, + ('while ! dmesg | grep "br-lan: port 1(eth0) entered" ;' + ' do sleep 1 ; done'), + 'entered forwarding state') + self.wait_for_console_pattern(prompt) + exec_command_and_wait_for_pattern(self, + 'while ! ifconfig | grep "10.0.2.15" ; do sleep 1 ; done', + 'addr:10.0.2.15') + self.wait_for_console_pattern(prompt) + exec_command_and_wait_for_pattern(self, 'ping -c 1 10.0.2.2', + '1 packets received, 0% packet l= oss') + + +if __name__ =3D=3D '__main__': + LinuxKernelTest.main() --=20 2.43.0 From nobody Sat Nov 15 14:52:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1750082963; cv=none; d=zohomail.com; s=zohoarc; b=BIUZjnK2ve62HGEX/d3brCJ7cX+Y0XQnov6f3YsE8Sdel+hHXvLArdFGAx4cXlk2rISZ+/R0qlDC43FIiCBoDrUE2V6atBVNyEMI05uxuFVWaFFxwpQdN5nep4UyZu5fHkMu+InmZAj3Glqfh0/452NSHIzAwoQ9UABGObjmfPQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750082963; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=eEpF1bq+uDdit1cKP/leNUs+euxU/so4YJjiIr0qDj4=; b=aPI2SbOhKREkZQydzuk4tWACSj7mQzUMuC6JNOGSPgEwGQfvdEQ5tFFQc4MikpQYeQqqJ2S+92FKAEIp1D1vGpOuCwLOsQD50VucdUOTw2y+xC+ebgsJstj7Rh8lvr/Tr+W72UZmpZa5ix3OkeU/92NSIGw79HX1v245xmcCTok= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175008296354924.38879007270566; Mon, 16 Jun 2025 07:09:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uRAUa-0001G2-Pk; Mon, 16 Jun 2025 10:07:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uRATx-00015I-5w for qemu-devel@nongnu.org; Mon, 16 Jun 2025 10:06:41 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uRATt-0003zQ-Gb for qemu-devel@nongnu.org; Mon, 16 Jun 2025 10:06:40 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-450cb2ddd46so25427295e9.2 for ; Mon, 16 Jun 2025 07:06:37 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Based on the actual implementation and system behavior, the effects of sleep=3Don and sleep=3Doff were inadvertently reve= rsed. This commit updates the description to reflect their intended functionality. Cc: qemu-stable@nongnu.org Fixes: fa647905e6ba ("qemu-options.hx: Fix minor issues in icount documenta= tion") Signed-off-by: Ethan Chen Message-id: 20250606095728.3672832-1-ethan84@andestech.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- qemu-options.hx | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/qemu-options.hx b/qemu-options.hx index 7eb8e02b4b9..1f862b19a67 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -4936,13 +4936,13 @@ SRST with actual performance. =20 When the virtual cpu is sleeping, the virtual time will advance at - default speed unless ``sleep=3Don`` is specified. With - ``sleep=3Don``, the virtual time will jump to the next timer + default speed unless ``sleep=3Doff`` is specified. With + ``sleep=3Doff``, the virtual time will jump to the next timer deadline instantly whenever the virtual cpu goes to sleep mode and will not advance if no timer is enabled. This behavior gives deterministic execution times from the guest point of view. - The default if icount is enabled is ``sleep=3Doff``. - ``sleep=3Don`` cannot be used together with either ``shift=3Dauto`` + The default if icount is enabled is ``sleep=3Don``. + ``sleep=3Doff`` cannot be used together with either ``shift=3Dauto`` or ``align=3Don``. =20 ``align=3Don`` will activate the delay algorithm which will try to --=20 2.43.0 From nobody Sat Nov 15 14:52:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1750082868; cv=none; d=zohomail.com; s=zohoarc; b=YqB5si0LfMkspeuFSJTpe4/LYmktp/kb2zipGK6oBIRubKuXRPuD7ZatjPMGTGwZgCSNBSweuHH7+JrpR5z81hDsKme+eBUy1WmgkxafmMRJxAlQ6gkyLEG9CDI2Nih8Gmp5YS5msHhJpI9a9v6fQf6DA4+adhxiWGDWgy2iS0Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750082868; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=LChNT2oan2dCMkf7YUp2ghN9GIJ92+FXAYXzABpNUw8=; b=dP0vYtpe27+TnIfVa8qGinRLZPcv7e3RguLnI5iJX7TBhaq6khVpQTcR296GxI6xzruU3LoDBThQVYuopMq8lRLlFjxGVREul/MYR7lFJi6ALggWvxXJ2TROk+MXg9I9/S55G/7V/biYKGWlPwcXWPIKF/4nAyk1MP7sx4IjBMY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750082868924377.03144449227784; Mon, 16 Jun 2025 07:07:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uRAUc-0001Ha-4D; Mon, 16 Jun 2025 10:07:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uRAU7-00016a-4o for qemu-devel@nongnu.org; Mon, 16 Jun 2025 10:06:54 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uRATz-00040y-2W for qemu-devel@nongnu.org; Mon, 16 Jun 2025 10:06:49 -0400 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-4533a53a6efso10971335e9.0 for ; Mon, 16 Jun 2025 07:06:41 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4532e13c192sm146561975e9.26.2025.06.16.07.06.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jun 2025 07:06:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1750082800; x=1750687600; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=LChNT2oan2dCMkf7YUp2ghN9GIJ92+FXAYXzABpNUw8=; b=yplTDK2QVw1f7Pv+/Dt86BXSznEG39wVACjtlZIP8bEZAqYLWpFcxQlgmR92k3Cu/M alj6gSWF5nKSNw5NXfmm51qG7j2pUlv0stLMy/iOg+oivCsxWDyosb/cByDtWPQpMxXy lC+nMsETsq6gcJareYU4TGAKmjxwHxLXgvcvbTwGXwFtBcuG2GYT49CU3JuvYib5hsQ6 tceaOW9aeVauCOAi9OWVmg61QCR0DNolhXT28VfsKnWs1wEamThONLDQVEX8+sQalVCt hn/fo7XIt58CqExRzM34lMxJlVUdt6dHkzxpxNuZ5m4Ox3ortLurGmcct0cMMZIhi8Zu y0Lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750082800; x=1750687600; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LChNT2oan2dCMkf7YUp2ghN9GIJ92+FXAYXzABpNUw8=; b=j0s+i3XnBfYkubB5imNWLmHIPD3lejyv9xe+s2/GdsTCsVDwz7BWVMKjrqyj7qq0Rz a//zsxggmZHr/GbiuVdBsbIGcIwdDvqFHl340VdSKr4bt5P6ATwV2P/B+Ap+f7N9ET2r kOWJ0nrlZYoDzJ8IfNJ1HOuxg+v3f5XC+S8xdUz1orKG+SV21XFUQuVq5GbuEYWjR4/h hc4cfS+lp0u/76NE4xjEfW98uq9YB7IQmcFLQ9K5/d/YDssMHi65r9YthQsbvIab400U iSiG9kgP3YAV1sKncpdichDsrEnGxNgPHRD5LGOYSSZlQrBpMPCPgW0FJxH0aijKfFq7 n7uQ== X-Gm-Message-State: AOJu0YxDe16DVTaRBsa2REC7EY5hM4MOqkRlmKKJXw3iL57T1aaKW57r 1seqmj3FqJ7vaFeKVaTnBehmBkn96yhw4kycvXAC+zN6s3taoPvj7cQ9IDLUcKpGKX1QqFScJBB akbbZ X-Gm-Gg: ASbGnctHe7IsRR13E5qm37ItCQzLgESft+VE7PFDJdl/gqCEcZx6zao3oPeLVjx10L2 t4/KvFVHY4JR9ujLo0IkHFVHPCE5TgQXvT+6TF/5Z/vH0Kn0mhtM/O6SGneeaYQpBpoc4poTjPY I4mKTBYy3FbuI2gHDN0cvl1FZl3JbZUpVFUO8elBvldKMZd872V66Qg8Guq+xRi9+bRPOwPli43 cwlEQBoq7xcNcYRbP3REJh+ZNXGHyQp5uYSQw6/JZya7MmODZczSM5SCuBZxurGLO5ePbu7ET7J ZlBozsMKtfeumfUEvBSK0gvLqf0CyoUn8aaigPeBxA54G4D6VHxQAwWEU/+oMPJjA9Bc X-Google-Smtp-Source: AGHT+IGJqHXYcba1VCswTvfaxnwCn7dIqydzLTDOlZAKGF5MFlnGtikP7ITD9CNBuvxnHo7lVRItJg== X-Received: by 2002:a05:600c:1549:b0:43d:fa5f:7d30 with SMTP id 5b1f17b1804b1-4533c97c5eamr85760065e9.16.1750082796972; Mon, 16 Jun 2025 07:06:36 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 4/9] target/arm: Define raw write for PMU CLR registers Date: Mon, 16 Jun 2025 15:06:25 +0100 Message-ID: <20250616140630.2273870-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250616140630.2273870-1-peter.maydell@linaro.org> References: <20250616140630.2273870-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1750082870002116600 Content-Type: text/plain; charset="utf-8" From: Akihiko Odaki Raw writes to PMCNTENCLR and PMCNTENCLR_EL0 incorrectly used their default write function, which clears written bits instead of writes the raw value. PMINTENCLR and PMINTENCLR_EL1 are similar registers, but they instead had ARM_CP_NO_RAW. Commit 7a0e58fa6487 ("target-arm: Split NO_MIGRATE into ALIAS and NO_RAW") sugguests ARM_CP_ALIAS should be used instead of ARM_CP_NO_RAW in such a case: > We currently mark ARM coprocessor/system register definitions with > the flag ARM_CP_NO_MIGRATE for two different reasons: > 1) register is an alias on to state that's also visible via > some other register, and that other register is the one > responsible for migrating the state > 2) register is not actually state at all (for instance the TLB > or cache maintenance operation "registers") and it makes no > sense to attempt to migrate it or otherwise access the raw state > > This works fine for identifying which registers should be ignored > when performing migration, but we also use the same functions for > synchronizing system register state between QEMU and the kernel > when using KVM. In this case we don't want to try to sync state > into registers in category 2, but we do want to sync into registers > in category 1, because the kernel might have picked a different > one of the aliases as its choice for which one to expose for > migration. These registers fall in category 1 (ARM_CP_ALIAS), not category 2 (ARM_CP_NO_RAW). ARM_CP_NO_RAW also has another undesired side effect that hides registers from GDB. Properly set raw write functions and drop the ARM_CP_NO_RAW flag from PMINTENCLR and PMINTENCLR_EL1; this fixes GDB/KVM state synchronization of PMCNTENCLR and PMCNTENCLR_EL0, and exposes all these four registers to GDB. It is not necessary to add ARM_CP_ALIAS to these registers because the flag is already set. Signed-off-by: Akihiko Odaki Message-id: 20250531-clr-v3-1-377f9bf1746d@rsg.ci.i.u-tokyo.ac.jp Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 76312102879..889d3088079 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1904,7 +1904,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcnten), .accessfn =3D pmreg_access, .fgt =3D FGT_PMCNTEN, - .writefn =3D pmcntenclr_write, + .writefn =3D pmcntenclr_write, .raw_writefn =3D raw_write, .type =3D ARM_CP_ALIAS | ARM_CP_IO }, { .name =3D "PMCNTENCLR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 2, @@ -1912,7 +1912,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .fgt =3D FGT_PMCNTEN, .type =3D ARM_CP_ALIAS | ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcnten), - .writefn =3D pmcntenclr_write }, + .writefn =3D pmcntenclr_write, .raw_writefn =3D raw_write }, { .name =3D "PMOVSR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 3, .access =3D PL0_RW, .type =3D ARM_CP_IO, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmovsr), @@ -2029,16 +2029,16 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { { .name =3D "PMINTENCLR", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 2, .access =3D PL1_RW, .accessfn =3D access_tpm, .fgt =3D FGT_PMINTEN, - .type =3D ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, + .type =3D ARM_CP_ALIAS | ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pminten), - .writefn =3D pmintenclr_write, }, + .writefn =3D pmintenclr_write, .raw_writefn =3D raw_write }, { .name =3D "PMINTENCLR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D 2, .access =3D PL1_RW, .accessfn =3D access_tpm, .fgt =3D FGT_PMINTEN, - .type =3D ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, + .type =3D ARM_CP_ALIAS | ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pminten), - .writefn =3D pmintenclr_write }, + .writefn =3D pmintenclr_write, .raw_writefn =3D raw_write }, { .name =3D "CCSIDR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, .opc2 =3D 0, .access =3D PL1_R, --=20 2.43.0 From nobody Sat Nov 15 14:52:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1750082858; cv=none; d=zohomail.com; s=zohoarc; b=R3Qd2XXEmh3Zt3AFOJc40a9UtgczRHm9YZ8yVizQHr80ub3Z1quLTb5paeDjobw3LbyCtN85CdfOHxU4yS6cNPc0MIq++M2t2wMdBfxK6u20ViYOyoQO0R4VQ/+WKDtim73ZRtPqhoat1NqsfmVZwaYKeys+BGIzSF/H4I9IB+M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750082858; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=QdO1TRVyU9YNCEAr0pruHF+mbDwtSG805YxNKFeiJsk=; b=XtmygDmpfrke4iyQE0JMyBAOmCWxYjEtroogopaKBMFeMosq6fBtX4nYt3AzqjHg+KUMIKxBP+k3YSKZGcCNdZ8pZ7LoikjcEHcROZENSLgRGuksk3JeDeD2PDJX3EKmwVAcP8YZm1bOXnsrYLGjjX6nrvbEm8eebuHOWOrv7MU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750082858217147.15818760177888; Mon, 16 Jun 2025 07:07:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uRAUb-0001G7-3Z; Mon, 16 Jun 2025 10:07:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uRAU6-00016Y-TA for qemu-devel@nongnu.org; Mon, 16 Jun 2025 10:06:54 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uRATy-00040l-RU for qemu-devel@nongnu.org; Mon, 16 Jun 2025 10:06:45 -0400 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-451e2f0d9c2so39441535e9.1 for ; Mon, 16 Jun 2025 07:06:41 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Mon, 16 Jun 2025 07:06:38 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 5/9] docs/interop: convert qed_spec.txt to reStructuredText format Date: Mon, 16 Jun 2025 15:06:26 +0100 Message-ID: <20250616140630.2273870-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250616140630.2273870-1-peter.maydell@linaro.org> References: <20250616140630.2273870-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1750082860113116600 Content-Type: text/plain; charset="utf-8" From: Souleymane Conte Convert the qed_spec.txt file to reStructuredText and include it in the manual. buglink: https://gitlab.com/qemu-project/qemu/-/issues/527 Signed-off-by: Souleymane Conte Message-id: 20250609135124.45078-1-conte.souleymane@gmail.com Reviewed-by: Peter Maydell [PMM: adjusted position of doc in the table of contents; bulked up commit message; added file to MAINTAINERS section for QED; made 'Consistency checking' a higher level section; fixed one preexisting grammar nit (s/by from/from/)] Signed-off-by: Peter Maydell --- MAINTAINERS | 1 + docs/interop/index.rst | 1 + docs/interop/qed_spec.rst | 219 ++++++++++++++++++++++++++++++++++++++ docs/interop/qed_spec.txt | 138 ------------------------ 4 files changed, 221 insertions(+), 138 deletions(-) create mode 100644 docs/interop/qed_spec.rst delete mode 100644 docs/interop/qed_spec.txt diff --git a/MAINTAINERS b/MAINTAINERS index 84cfef835eb..94c40761278 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4117,6 +4117,7 @@ M: Stefan Hajnoczi L: qemu-block@nongnu.org S: Supported F: block/qed.c +F: docs/interop/qed_spec.rst =20 raw M: Kevin Wolf diff --git a/docs/interop/index.rst b/docs/interop/index.rst index 4b951ae4162..972f3e49ce9 100644 --- a/docs/interop/index.rst +++ b/docs/interop/index.rst @@ -18,6 +18,7 @@ are useful for making QEMU interoperate with other softwa= re. parallels prl-xml qcow2 + qed_spec pr-helper qmp-spec qemu-ga diff --git a/docs/interop/qed_spec.rst b/docs/interop/qed_spec.rst new file mode 100644 index 00000000000..cd6c7d90051 --- /dev/null +++ b/docs/interop/qed_spec.rst @@ -0,0 +1,219 @@ +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +QED Image File Format Specification +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The file format looks like this:: + + +----------+----------+----------+-----+ + | cluster0 | cluster1 | cluster2 | ... | + +----------+----------+----------+-----+ + +The first cluster begins with the ``header``. The header contains informat= ion +about where regular clusters start; this allows the header to be extensibl= e and +store extra information about the image file. A regular cluster may be +a ``data cluster``, an ``L2``, or an ``L1 table``. L1 and L2 tables are co= mposed +of one or more contiguous clusters. + +Normally the file size will be a multiple of the cluster size. If the fil= e size +is not a multiple, extra information after the last cluster may not be pre= served +if data is written. Legitimate extra information should use space between = the header +and the first regular cluster. + +All fields are little-endian. + +Header +------ + +:: + + Header { + uint32_t magic; /* QED\0 */ + + uint32_t cluster_size; /* in bytes */ + uint32_t table_size; /* for L1 and L2 tables, in clusters */ + uint32_t header_size; /* in clusters */ + + uint64_t features; /* format feature bits */ + uint64_t compat_features; /* compat feature bits */ + uint64_t autoclear_features; /* self-resetting feature bits */ + + uint64_t l1_table_offset; /* in bytes */ + uint64_t image_size; /* total logical image size, in bytes */ + + /* if (features & QED_F_BACKING_FILE) */ + uint32_t backing_filename_offset; /* in bytes from start of header */ + uint32_t backing_filename_size; /* in bytes */ + } + +Field descriptions: +~~~~~~~~~~~~~~~~~~~ + +- ``cluster_size`` must be a power of 2 in range [2^12, 2^26]. +- ``table_size`` must be a power of 2 in range [1, 16]. +- ``header_size`` is the number of clusters used by the header and any add= itional + information stored before regular clusters. +- ``features``, ``compat_features``, and ``autoclear_features`` are file f= ormat + extension bitmaps. They work as follows: + + - An image with unknown ``features`` bits enabled must not be opened. Fi= le format + changes that are not backwards-compatible must use ``features`` bits. + - An image with unknown ``compat_features`` bits enabled can be opened s= afely. + The unknown features are simply ignored and represent backwards-compat= ible + changes to the file format. + - An image with unknown ``autoclear_features`` bits enable can be opened= safely + after clearing the unknown bits. This allows for backwards-compatible = changes + to the file format which degrade gracefully and can be re-enabled agai= n by a + new program later. +- ``l1_table_offset`` is the offset of the first byte of the L1 table in t= he image + file and must be a multiple of ``cluster_size``. +- ``image_size`` is the block device size seen by the guest and must be a = multiple + of 512 bytes. +- ``backing_filename_offset`` and ``backing_filename_size`` describe a str= ing in + (byte offset, byte size) form. It is not NUL-terminated and has no align= ment constraints. + The string must be stored within the first ``header_size`` clusters. The= backing filename + may be an absolute path or relative to the image file. + +Feature bits: +~~~~~~~~~~~~~ + +- ``QED_F_BACKING_FILE =3D 0x01``. The image uses a backing file. +- ``QED_F_NEED_CHECK =3D 0x02``. The image needs a consistency check befor= e use. +- ``QED_F_BACKING_FORMAT_NO_PROBE =3D 0x04``. The backing file is a raw di= sk image + and no file format autodetection should be attempted. This should be us= ed to + ensure that raw backing files are never detected as an image format if t= hey happen + to contain magic constants. + +There are currently no defined ``compat_features`` or ``autoclear_features= `` bits. + +Fields predicated on a feature bit are only used when that feature is set. +The fields always take up header space, regardless of whether or not the f= eature +bit is set. + +Tables +------ + +Tables provide the translation from logical offsets in the block device to= cluster +offsets in the file. + +:: + + #define TABLE_NOFFSETS (table_size * cluster_size / sizeof(uint64_t)) + + Table { + uint64_t offsets[TABLE_NOFFSETS]; + } + +The tables are organized as follows:: + + +----------+ + | L1 table | + +----------+ + ,------' | '------. + +----------+ | +----------+ + | L2 table | ... | L2 table | + +----------+ +----------+ + ,------' | '------. + +----------+ | +----------+ + | Data | ... | Data | + +----------+ +----------+ + +A table is made up of one or more contiguous clusters. The ``table_size``= header +field determines table size for an image file. For example, ``cluster_size= =3D64 KB`` +and ``table_size=3D4`` results in 256 KB tables. + +The logical image size must be less than or equal to the maximum possible = size of +clusters rooted by the L1 table: + +.. code:: + + header.image_size <=3D TABLE_NOFFSETS * TABLE_NOFFSETS * header.cluster_s= ize + +L1, L2, and data cluster offsets must be aligned to ``header.cluster_size`= `. +The following offsets have special meanings: + +L2 table offsets +~~~~~~~~~~~~~~~~ + +- 0 - unallocated. The L2 table is not yet allocated. + +Data cluster offsets +~~~~~~~~~~~~~~~~~~~~ + +- 0 - unallocated. The data cluster is not yet allocated. +- 1 - zero. The data cluster contents are all zeroes and no cluster is all= ocated. + +Future format extensions may wish to store per-offset information. The lea= st +significant 12 bits of an offset are reserved for this purpose and must be= set +to zero. Image files with ``cluster_size`` > 2^12 will have more unused bi= ts +which should also be zeroed. + +Unallocated L2 tables and data clusters +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Reads to an unallocated area of the image file access the backing file. If= there +is no backing file, then zeroes are produced. The backing file may be smal= ler +than the image file and reads of unallocated areas beyond the end of the b= acking +file produce zeroes. + +Writes to an unallocated area cause a new data clusters to be allocated, a= nd a new +L2 table if that is also unallocated. The new data cluster is populated wi= th data +from the backing file (or zeroes if no backing file) and the data being wr= itten. + +Zero data clusters +~~~~~~~~~~~~~~~~~~ + +Zero data clusters are a space-efficient way of storing zeroed regions of = the image. + +Reads to a zero data cluster produce zeroes. + +.. note:: + The difference between an unallocated and a zero data cluster is that = zero data + clusters stop the reading of contents from the backing file. + +Writes to a zero data cluster cause a new data cluster to be allocated. T= he new +data cluster is populated with zeroes and the data being written. + +Logical offset translation +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Logical offsets are translated into cluster offsets as follows:: + + table_bits table_bits cluster_bits + <--------> <--------> <---------------> + +----------+----------+-----------------+ + | L1 index | L2 index | byte offset | + +----------+----------+-----------------+ + + Structure of a logical offset + + offset_mask =3D ~(cluster_size - 1) # mask for the image file byte offset + + def logical_to_cluster_offset(l1_index, l2_index, byte_offset): + l2_offset =3D l1_table[l1_index] + l2_table =3D load_table(l2_offset) + cluster_offset =3D l2_table[l2_index] & offset_mask + return cluster_offset + byte_offset + +Consistency checking +-------------------- + +This section is informational and included to provide background on the use +of the ``QED_F_NEED_CHECK features`` bit. + +The ``QED_F_NEED_CHECK`` bit is used to mark an image as dirty before star= ting +an operation that could leave the image in an inconsistent state if interr= upted +by a crash or power failure. A dirty image must be checked on open becaus= e its +metadata may not be consistent. + +Consistency check includes the following invariants: + +- Each cluster is referenced once and only once. It is an inconsistency to= have + a cluster referenced more than once by L1 or L2 tables. A cluster has be= en leaked + if it has no references. +- Offsets must be within the image file size and must be ``cluster_size`` = aligned. +- Table offsets must at least ``table_size`` * ``cluster_size`` bytes from= the end + of the image file so that there is space for the entire table. + +The consistency check process starts from ``l1_table_offset`` and scans al= l L2 tables. +After the check completes with no other errors besides leaks, the ``QED_F_= NEED_CHECK`` +bit can be cleared and the image can be accessed. diff --git a/docs/interop/qed_spec.txt b/docs/interop/qed_spec.txt deleted file mode 100644 index 7982e058b2c..00000000000 --- a/docs/interop/qed_spec.txt +++ /dev/null @@ -1,138 +0,0 @@ -=3DSpecification=3D - -The file format looks like this: - - +----------+----------+----------+-----+ - | cluster0 | cluster1 | cluster2 | ... | - +----------+----------+----------+-----+ - -The first cluster begins with the '''header'''. The header contains infor= mation about where regular clusters start; this allows the header to be ext= ensible and store extra information about the image file. A regular cluste= r may be a '''data cluster''', an '''L2''', or an '''L1 table'''. L1 and L= 2 tables are composed of one or more contiguous clusters. - -Normally the file size will be a multiple of the cluster size. If the fil= e size is not a multiple, extra information after the last cluster may not = be preserved if data is written. Legitimate extra information should use s= pace between the header and the first regular cluster. - -All fields are little-endian. - -=3D=3DHeader=3D=3D - Header { - uint32_t magic; /* QED\0 */ -=20 - uint32_t cluster_size; /* in bytes */ - uint32_t table_size; /* for L1 and L2 tables, in clusters */ - uint32_t header_size; /* in clusters */ -=20 - uint64_t features; /* format feature bits */ - uint64_t compat_features; /* compat feature bits */ - uint64_t autoclear_features; /* self-resetting feature bits */ - - uint64_t l1_table_offset; /* in bytes */ - uint64_t image_size; /* total logical image size, in bytes */ -=20 - /* if (features & QED_F_BACKING_FILE) */ - uint32_t backing_filename_offset; /* in bytes from start of header */ - uint32_t backing_filename_size; /* in bytes */ - } - -Field descriptions: -* ''cluster_size'' must be a power of 2 in range [2^12, 2^26]. -* ''table_size'' must be a power of 2 in range [1, 16]. -* ''header_size'' is the number of clusters used by the header and any add= itional information stored before regular clusters. -* ''features'', ''compat_features'', and ''autoclear_features'' are file f= ormat extension bitmaps. They work as follows: -** An image with unknown ''features'' bits enabled must not be opened. Fi= le format changes that are not backwards-compatible must use ''features'' b= its. -** An image with unknown ''compat_features'' bits enabled can be opened sa= fely. The unknown features are simply ignored and represent backwards-comp= atible changes to the file format. -** An image with unknown ''autoclear_features'' bits enable can be opened = safely after clearing the unknown bits. This allows for backwards-compatib= le changes to the file format which degrade gracefully and can be re-enable= d again by a new program later. -* ''l1_table_offset'' is the offset of the first byte of the L1 table in t= he image file and must be a multiple of ''cluster_size''. -* ''image_size'' is the block device size seen by the guest and must be a = multiple of 512 bytes. -* ''backing_filename_offset'' and ''backing_filename_size'' describe a str= ing in (byte offset, byte size) form. It is not NUL-terminated and has no = alignment constraints. The string must be stored within the first ''header= _size'' clusters. The backing filename may be an absolute path or relative= to the image file. - -Feature bits: -* QED_F_BACKING_FILE =3D 0x01. The image uses a backing file. -* QED_F_NEED_CHECK =3D 0x02. The image needs a consistency check before u= se. -* QED_F_BACKING_FORMAT_NO_PROBE =3D 0x04. The backing file is a raw disk = image and no file format autodetection should be attempted. This should be= used to ensure that raw backing files are never detected as an image forma= t if they happen to contain magic constants. - -There are currently no defined ''compat_features'' or ''autoclear_features= '' bits. - -Fields predicated on a feature bit are only used when that feature is set.= The fields always take up header space, regardless of whether or not the = feature bit is set. - -=3D=3DTables=3D=3D - -Tables provide the translation from logical offsets in the block device to= cluster offsets in the file. - - #define TABLE_NOFFSETS (table_size * cluster_size / sizeof(uint64_t)) - =20 - Table { - uint64_t offsets[TABLE_NOFFSETS]; - } - -The tables are organized as follows: - - +----------+ - | L1 table | - +----------+ - ,------' | '------. - +----------+ | +----------+ - | L2 table | ... | L2 table | - +----------+ +----------+ - ,------' | '------. - +----------+ | +----------+ - | Data | ... | Data | - +----------+ +----------+ - -A table is made up of one or more contiguous clusters. The table_size hea= der field determines table size for an image file. For example, cluster_si= ze=3D64 KB and table_size=3D4 results in 256 KB tables. - -The logical image size must be less than or equal to the maximum possible = size of clusters rooted by the L1 table: - header.image_size <=3D TABLE_NOFFSETS * TABLE_NOFFSETS * header.cluster_s= ize - -L1, L2, and data cluster offsets must be aligned to header.cluster_size. = The following offsets have special meanings: - -=3D=3D=3DL2 table offsets=3D=3D=3D -* 0 - unallocated. The L2 table is not yet allocated. - -=3D=3D=3DData cluster offsets=3D=3D=3D -* 0 - unallocated. The data cluster is not yet allocated. -* 1 - zero. The data cluster contents are all zeroes and no cluster is al= located. - -Future format extensions may wish to store per-offset information. The le= ast significant 12 bits of an offset are reserved for this purpose and must= be set to zero. Image files with cluster_size > 2^12 will have more unuse= d bits which should also be zeroed. - -=3D=3D=3DUnallocated L2 tables and data clusters=3D=3D=3D -Reads to an unallocated area of the image file access the backing file. I= f there is no backing file, then zeroes are produced. The backing file may= be smaller than the image file and reads of unallocated areas beyond the e= nd of the backing file produce zeroes. - -Writes to an unallocated area cause a new data clusters to be allocated, a= nd a new L2 table if that is also unallocated. The new data cluster is pop= ulated with data from the backing file (or zeroes if no backing file) and t= he data being written. - -=3D=3D=3DZero data clusters=3D=3D=3D -Zero data clusters are a space-efficient way of storing zeroed regions of = the image. - -Reads to a zero data cluster produce zeroes. Note that the difference bet= ween an unallocated and a zero data cluster is that zero data clusters stop= the reading of contents from the backing file. - -Writes to a zero data cluster cause a new data cluster to be allocated. T= he new data cluster is populated with zeroes and the data being written. - -=3D=3D=3DLogical offset translation=3D=3D=3D -Logical offsets are translated into cluster offsets as follows: - - table_bits table_bits cluster_bits - <--------> <--------> <---------------> - +----------+----------+-----------------+ - | L1 index | L2 index | byte offset | - +----------+----------+-----------------+ -=20 - Structure of a logical offset - - offset_mask =3D ~(cluster_size - 1) # mask for the image file byte offset -=20 - def logical_to_cluster_offset(l1_index, l2_index, byte_offset): - l2_offset =3D l1_table[l1_index] - l2_table =3D load_table(l2_offset) - cluster_offset =3D l2_table[l2_index] & offset_mask - return cluster_offset + byte_offset - -=3D=3DConsistency checking=3D=3D - -This section is informational and included to provide background on the us= e of the QED_F_NEED_CHECK ''features'' bit. - -The QED_F_NEED_CHECK bit is used to mark an image as dirty before starting= an operation that could leave the image in an inconsistent state if interr= upted by a crash or power failure. A dirty image must be checked on open b= ecause its metadata may not be consistent. - -Consistency check includes the following invariants: -# Each cluster is referenced once and only once. It is an inconsistency t= o have a cluster referenced more than once by L1 or L2 tables. A cluster h= as been leaked if it has no references. -# Offsets must be within the image file size and must be ''cluster_size'' = aligned. -# Table offsets must at least ''table_size'' * ''cluster_size'' bytes from= the end of the image file so that there is space for the entire table. - -The consistency check process starts by from ''l1_table_offset'' and scans= all L2 tables. After the check completes with no other errors besides lea= ks, the QED_F_NEED_CHECK bit can be cleared and the image can be accessed. --=20 2.43.0 From nobody Sat Nov 15 14:52:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1750082864; cv=none; d=zohomail.com; s=zohoarc; b=H3RM862mSdjI0vsDA+bzrFBGHI4CMgILl7TtQwO2ZdLpdKlL/eftRwj5chKljVngyrXUPeBTmOzWUPMNh7kq2NuSm4asr1amSZP+mFeR5/GyTEaYopl6zvllDdPj2o2bsUzgRB3Cz1ePMLZhTSHfrKiX05n00PoWSin7rCuLoAY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750082864; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=ZqawsmPR4ehVDHHaDoceEn6Ki+J71wY97xtw/kIEj3I=; b=BpsjSbBRQc2m4iM7SPWmQ8tVe9SVOpUXTII9LLhSaOoATuXxTByKrEGtoqSYsr1WBmrpB3houtND8GM/GwDmjdW2TjYrUL9UjMJRiYeODiwquQetVLs5yL9Wxl04w9jzcakCf/i/s80KY0wOlahooamb3xnp+QRLvaSmzP6xsZI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750082864516401.894565656136; Mon, 16 Jun 2025 07:07:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uRAUZ-0001FS-So; Mon, 16 Jun 2025 10:07:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uRATz-00015S-I1 for qemu-devel@nongnu.org; Mon, 16 Jun 2025 10:06:45 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uRATw-00040Y-Vr for qemu-devel@nongnu.org; Mon, 16 Jun 2025 10:06:42 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-451d54214adso35522155e9.3 for ; Mon, 16 Jun 2025 07:06:40 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4532e13c192sm146561975e9.26.2025.06.16.07.06.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jun 2025 07:06:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1750082799; x=1750687599; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ZqawsmPR4ehVDHHaDoceEn6Ki+J71wY97xtw/kIEj3I=; b=gekuyvyE+u9qZDPMCX29Nb04NYcvJGdQWfU/nnCKUzEPTMYMuc1jerYn/DUlqKow+W t2XmMeaIgxFljk2NSSXP7TMAxaYxdsgtxDra4RYBlzyJGArtXo4nO52JENay5xGJdoIF xIFKcpXlf/YN9BJ7YQuD62XU1yXkZiNp5iCO1t59L9jiljMlqPjZiIttUN7V1duK4cYm KgGl9bMGMiKwuGvydV+GmjqkBHoTdKkrXP5K22po/tGenhm1KwXw2YQKM+Dt08c38GCb qx1lu0owf6FjBFyp5JvLICANmStBrFHR1qtVVZoGOUyz5OblUkRwaEpGiBQK0od0PWBA aRLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750082799; x=1750687599; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZqawsmPR4ehVDHHaDoceEn6Ki+J71wY97xtw/kIEj3I=; b=CBDjtw8lDZw2uQF/8XDWp/V3fuFlaXoK1yFxhfc8j4S85AR+fipKvlp1xGnF0bO6lZ fNi9xTr1YuxIB1KVpXJ1kn6GP0R9O8cbhyxCX1LOQxH4IUbp3pWPUFjh9xK4joXr3zgg g2HXZKwoRzK4OrS6K617c1kPwJQmDnOpE//z4nrjnyzNS94NKG05MVC+2Zbuj3VOLNwH 80IIwEImls5bVFsQtzNtEUoeKPrKPeMzoeJcoYq7k5pQX7ecOR1oynqLUEv+QE59Ys1K 25G9m1Tf2hHmEWe9qziY4ZruVWpEE8zFUF3NDLQrXJQagVpYLXmUMadRoa64zF1GbJUt PeVw== X-Gm-Message-State: AOJu0YyTOlO6Jedq/2upVqsoxYqmz1Ywxd5cDihuars1SMsBY6+3/FuO Io/+5zQcHAmnfCyjRmT/5RglZAkB7//OYBIge0TLqLa2JY7WehA99jppu7oPnAMcywXn3SJ6m8H 1OuQh X-Gm-Gg: ASbGncsYNn5lz8smqgVhJaag3RNk3tFyh5H6EPw/Y+Z/3FfZi9OJbx4SoZ+pAMuibJ1 8axbKhu+87C9f/4hLnfNVdMWLJJoXC78OurUeKWXQ3AzzrYbojC+rPzpEo615Twf9sFh6iYKw2q nrnz2+V0wNgGPmZUWKTv8XbufAF9CUFRX2PxLujZ8zk5ofg/5P5bUSkndVmeHLMNg0kQmnSdq3O NSVavc7yvihhCU92PUyaBx3j/HPyw9pLSF+9Kd+opRji7TiXOMbgIMQlnnbcXe0iWP8TuU0Xiu0 eCVCRZafQu7CeP15KAG6bFgyWtIqPKWe6crChAcJFTr0UZ4P/XwQefZVMAzuSgWj+dd+y4lsqxL bEP4= X-Google-Smtp-Source: AGHT+IEX2DI7JYStwQFK2tnGjXV9hjUYzpRNHJ9YmF/RQgDa8LaMNs3abLEmTZxKc0gZb0Wm1buajA== X-Received: by 2002:a05:600c:34c4:b0:43d:94:2d1e with SMTP id 5b1f17b1804b1-4533ca55a90mr96777105e9.13.1750082799247; Mon, 16 Jun 2025 07:06:39 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 6/9] hw/arm: make cpu targeted by arm_load_kernel the primary CPU. Date: Mon, 16 Jun 2025 15:06:27 +0100 Message-ID: <20250616140630.2273870-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250616140630.2273870-1-peter.maydell@linaro.org> References: <20250616140630.2273870-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1750082865865116600 From: Cl=C3=A9ment Chigot Currently, arm booting processus assumes that the first_cpu is the CPU that will boot: `arm_load_kernel` is powering off all but the `first_cpu`; `do_cpu_reset` is setting the loader address only for this `first_cpu`. For most of the boards, this isn't an issue as the kernel is loaded and booted on the first CPU anyway. However, for zynqmp, the option "boot-cpu" allows to choose any CPUs. Create a new arm_boot_info entry `primary_cpu` recording which CPU will be boot first. This one is set when `arm_boot_kernel` is called. Signed-off-by: Cl=C3=A9ment Chigot Reviewed-by: Peter Maydell Message-id: 20250526085523.809003-2-chigot@adacore.com Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- include/hw/arm/boot.h | 3 +++ hw/arm/boot.c | 15 +++++++-------- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/include/hw/arm/boot.h b/include/hw/arm/boot.h index b12bf61ca81..a2e22bda8a5 100644 --- a/include/hw/arm/boot.h +++ b/include/hw/arm/boot.h @@ -132,6 +132,9 @@ struct arm_boot_info { bool secure_board_setup; =20 arm_endianness endianness; + + /* CPU having load the kernel and that should be the first to boot. */ + ARMCPU *primary_cpu; }; =20 /** diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 79afb51b8a5..3c93d879857 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -744,7 +744,7 @@ static void do_cpu_reset(void *opaque) } else { if (arm_feature(env, ARM_FEATURE_EL3) && (info->secure_boot || - (info->secure_board_setup && cs =3D=3D first_cpu))) { + (info->secure_board_setup && cpu =3D=3D info->primary= _cpu))) { /* Start this CPU in Secure SVC */ target_el =3D 3; } @@ -752,7 +752,7 @@ static void do_cpu_reset(void *opaque) =20 arm_emulate_firmware_reset(cs, target_el); =20 - if (cs =3D=3D first_cpu) { + if (cpu =3D=3D info->primary_cpu) { AddressSpace *as =3D arm_boot_address_space(cpu, info); =20 cpu_set_pc(cs, info->loader_start); @@ -1239,6 +1239,9 @@ void arm_load_kernel(ARMCPU *cpu, MachineState *ms, s= truct arm_boot_info *info) info->dtb_filename =3D ms->dtb; info->dtb_limit =3D 0; =20 + /* We assume the CPU passed as argument is the primary CPU. */ + info->primary_cpu =3D cpu; + /* Load the kernel. */ if (!info->kernel_filename || info->firmware_loaded) { arm_setup_firmware_boot(cpu, info); @@ -1288,12 +1291,8 @@ void arm_load_kernel(ARMCPU *cpu, MachineState *ms, = struct arm_boot_info *info) =20 object_property_set_int(cpuobj, "psci-conduit", info->psci_con= duit, &error_abort); - /* - * Secondary CPUs start in PSCI powered-down state. Like the - * code in do_cpu_reset(), we assume first_cpu is the primary - * CPU. - */ - if (cs !=3D first_cpu) { + /* Secondary CPUs start in PSCI powered-down state. */ + if (ARM_CPU(cs) !=3D info->primary_cpu) { object_property_set_bool(cpuobj, "start-powered-off", true, &error_abort); } --=20 2.43.0 From nobody Sat Nov 15 14:52:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1750082928; cv=none; d=zohomail.com; s=zohoarc; b=evFmpPdFzdarnY5kCoArXVeikekAcI91kBo2qci4wqefs+tTh0Ivj9bSMLDZUaXq6F4wpbX6a8raYKYHiiyS2Kp3ZAYFdm4W/gZkyn09d7E6+4Wonxf6+84p6jboCjB9GWq6ynLo8lGWKvAb0R5xWLO7cJ8cMn8Gy6xNbV6Sm3M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750082928; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Sj4CFhPbE7Fh5CPRnVAD3jRmQ3BeYvsxrXes/KZEpoQ=; b=BYxbHzbkom9sXl0GfjOsFdFjRwtuSQgoK06UhPFZ5rpXY1s4eLEuCaIowzKvJCcmyWc5Kn/xpMrgI4T13u6QUC5T3aVyP5uGM0igDEGXD5pfP5qfl3rp7AZUdEQr618qV6ckUNBk/S92L9NaGtvv3RfR+KWJuaXKmDoR8ZR+JMU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750082928170974.6009783663256; Mon, 16 Jun 2025 07:08:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uRAUZ-0001Ey-DB; Mon, 16 Jun 2025 10:07:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uRAU1-000163-9N for qemu-devel@nongnu.org; Mon, 16 Jun 2025 10:06:50 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uRATy-00040w-4d for qemu-devel@nongnu.org; Mon, 16 Jun 2025 10:06:44 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-450cf214200so39262575e9.1 for ; Mon, 16 Jun 2025 07:06:41 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4532e13c192sm146561975e9.26.2025.06.16.07.06.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jun 2025 07:06:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1750082800; x=1750687600; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Sj4CFhPbE7Fh5CPRnVAD3jRmQ3BeYvsxrXes/KZEpoQ=; b=LAiN1SP+pVGkN2EnZjn+Htif4VseWjDrywjeuBOI458D4mOaXuy7B/2Ux2EcJPuX4l h2kP87t0mSJILmP4GmSvAkj99kxWpHV4rlJrAYp2Hi5vTX9Wyj0EW/ulkdrN1iCYjxhT So9YVdVHekn9eJzMZUR/A6yn3tTspKQRnTTqPOoBqTekYDYf8O9xTs3Y/VoQXyKia3Ur VlKwMC1pRlv1H+drxkXvUA6Fo9L6sy/RFNh8zqWnozE5Tk9HSsQxlcUQocbM5/97Z/T4 V92ZXpMcO7jbuBZuoHS1iRga7ZMg7nC5EdsCpPMi4+uHfEsGBmlDA7YsnW6AMXwxNDLa QW9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750082800; x=1750687600; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Sj4CFhPbE7Fh5CPRnVAD3jRmQ3BeYvsxrXes/KZEpoQ=; b=CgRR8MToHldddH0NxOdUm/pCthy7AvSG5do+6Tb5mUGg14zdw+ZaCkJRnsKaOZBaaC VppYT9OoJDWNnhKcdwAQD5/x/rlegmLJFKuX9IE3yue7lM4aryvEbaVk7lSJH+Ld4uF5 hrQ+K+HgtYuwftnC3hi7ULpVVwA1h1WYE0yUCoXvi6j8RqJCPW8bjK7p2fQVvMbGuWXY wmwmv+aL8SIoJQ1nA03atvZZmH2JFfK9zKaete4WATG03Qt7qy9QV23d3p/SrKpluz/a V4dJMCfLr67aqKGFb5gvIKxbmrrNMblTcJdVB9HxHh3zVxKWJXG0REKmOlNftPWs0cww 0vHA== X-Gm-Message-State: AOJu0YxLPEb7WFomnGYE/pCtOXJq+NwWos3QWsfcFwN8VzADM+uKBHtE hJ60x1AeFPf4qOFM+R+EFEk8KG98J208qYckJPu+9eA2ERPfmIuTO4XPkylF1BxJFKuNOzKBhC0 qpnw8 X-Gm-Gg: ASbGncvdHTG3oDyfmvKK3vsLAaBi2/TDd/J91NObcQW4zr7tIYPQTwqLxshZuGCxd6r aEAz7f7S3EySOIQhZ/w0kajj9eQO+WuAoTEMioYlgqznvyUajMyl95cP9excDHL/lgyeU553PjB HRmWkK1XLe/GbuxIT8NBzrXe8eSpjD2lBm23O0BQt31hMQvLH1HwzP6tUCrZ7yAs7IL0P7VthU/ 0caICvIKWNS3CKv/83HFO99aggp0T+kMdSvdnS6V1KQ+qtBIN2CbH6M/PWSYhhJvxBAylTa0chD 4NRucgK6rhBZobg6n5fc+AS5fTKaWelixQlLM+1e77NHT7H2ipDFBE2000TvtdpGZY+i X-Google-Smtp-Source: AGHT+IGFmhAVDSya/9P+SzwgzU2UrVfjD2n4LmwpgdeuGDLLgxykPCn9JQhHI3b6OdWVsESYDrNDnQ== X-Received: by 2002:a05:600c:3513:b0:453:a88:d509 with SMTP id 5b1f17b1804b1-4533ca7443cmr115999655e9.10.1750082800095; Mon, 16 Jun 2025 07:06:40 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 7/9] hw/intc/arm_gic: introduce a first-cpu-index property Date: Mon, 16 Jun 2025 15:06:28 +0100 Message-ID: <20250616140630.2273870-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250616140630.2273870-1-peter.maydell@linaro.org> References: <20250616140630.2273870-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1750082928735116600 From: Frederic Konrad This introduces a first-cpu-index property to the arm-gic, as some SOCs could have two separate GIC (ie: the zynqmp). Signed-off-by: Cl=C3=A9ment Chigot Message-id: 20250526085523.809003-3-chigot@adacore.com Reviewed-by: Peter Maydell [PMM: slightly expanded comment documenting GIC property] Signed-off-by: Peter Maydell --- include/hw/intc/arm_gic.h | 3 +++ include/hw/intc/arm_gic_common.h | 2 ++ hw/intc/arm_gic.c | 2 +- hw/intc/arm_gic_common.c | 1 + 4 files changed, 7 insertions(+), 1 deletion(-) diff --git a/include/hw/intc/arm_gic.h b/include/hw/intc/arm_gic.h index 48f6a51a70a..be923f7ed88 100644 --- a/include/hw/intc/arm_gic.h +++ b/include/hw/intc/arm_gic.h @@ -27,6 +27,9 @@ * implement the security extensions * + QOM property "has-virtualization-extensions": set true if the GIC sh= ould * implement the virtualization extensions + * + QOM property "first-cpu-index": index of the first cpu attached to t= he + * GIC (default 0). The CPUs connected to the GIC are assumed to be + * first-cpu-index, first-cpu-index + 1, ... first-cpu-index + num-cpu = - 1. * + unnamed GPIO inputs: (where P is number of SPIs, i.e. num-irq - 32) * [0..P-1] SPIs * [P..P+31] PPIs for CPU 0 diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_com= mon.h index 97fea4102d3..93a3cc2bf81 100644 --- a/include/hw/intc/arm_gic_common.h +++ b/include/hw/intc/arm_gic_common.h @@ -129,6 +129,8 @@ struct GICState { uint32_t num_lrs; =20 uint32_t num_cpu; + /* cpu_index of the first CPU, attached to this GIC. */ + uint32_t first_cpu_index; =20 MemoryRegion iomem; /* Distributor */ /* This is just so we can have an opaque pointer which identifies diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index d18bef40fcc..899f1333633 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -59,7 +59,7 @@ static const uint8_t gic_id_gicv2[] =3D { static inline int gic_get_current_cpu(GICState *s) { if (!qtest_enabled() && s->num_cpu > 1) { - return current_cpu->cpu_index; + return current_cpu->cpu_index - s->first_cpu_index; } return 0; } diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index 0f0c48d89ab..ed5be056452 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -350,6 +350,7 @@ static void arm_gic_common_linux_init(ARMLinuxBootIf *o= bj, =20 static const Property arm_gic_common_properties[] =3D { DEFINE_PROP_UINT32("num-cpu", GICState, num_cpu, 1), + DEFINE_PROP_UINT32("first-cpu-index", GICState, first_cpu_index, 0), DEFINE_PROP_UINT32("num-irq", GICState, num_irq, 32), /* Revision can be 1 or 2 for GIC architecture specification * versions 1 or 2, or 0 to indicate the legacy 11MPCore GIC. --=20 2.43.0 From nobody Sat Nov 15 14:52:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1750082891; cv=none; d=zohomail.com; s=zohoarc; b=CttXT7tQKlkt2mAG3Tox+KPTFHxD3a0F8OQ66OW5oYFlHdOKyjWtTdiVIZw7/O1bw/ZRog7bQ9a//nsxXcOO6HX0rqMlA0oiThyrKBQuKPyCFXp1z96aGBbf0n9ayNPv+9+EOX/ool9dV6prSUddgdjDH54ZoCLO6DGiJQbq1Rg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750082891; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=h8VneX6jvIb39sL+b3h3e8ynlMbxT5M4RcGTGS18RQw=; b=AMxB5z9F6cNedF7V0z5yT+fJk1iyGFNo+9tIaI5E35lg4xvw1qNzfPO8VI+96L6IlOdQbO+sathCT08OxBOcVEeUVcBnnuVgBGTA4FtFhT1jWz8+V0+jhYhfQjL0HXc5bBxDOSyBDX34Uj9A2qbQ1PzuW+b+JFIz7CMQb0uowbE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750082891563531.60450883549; Mon, 16 Jun 2025 07:08:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uRAUe-0001II-9p; Mon, 16 Jun 2025 10:07:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uRAU8-00016k-Up for qemu-devel@nongnu.org; Mon, 16 Jun 2025 10:06:58 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uRAU1-00041E-1x for qemu-devel@nongnu.org; Mon, 16 Jun 2025 10:06:51 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-45300c82c1cso14610065e9.3 for ; Mon, 16 Jun 2025 07:06:43 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4532e13c192sm146561975e9.26.2025.06.16.07.06.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jun 2025 07:06:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1750082801; x=1750687601; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=h8VneX6jvIb39sL+b3h3e8ynlMbxT5M4RcGTGS18RQw=; b=sBPVineeVA9oLzGzW+lz1LWpcb12d9tKRyI6he3Qm5eDcmgevzYE5auT4TtxxmLG2i RaSS091CCexL8jNxh/n7wl4jP1VXeZRW2zM9wuiOaYy4pwW+dY5PASR/89pFoc4dZMyP AP+WxCB28YPxqUjlE3vkaju+x6aGL7QvVYG8EtyVPZm5VmJoZfJLGSYfXecIlk6DXJ1S 2ee0C13q3hlZpHlVc2JfFeFSqBqlsuftAWxxDUb7cyFdQ8pao+WErYtlTt4cT21NORJE CMc+aOWlt226g9Iz/Ty3tIPCrlHLPVXH6Tt/aF2FudemzbwY/BIkC7IfBGxCozq+xHWv nZDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750082801; x=1750687601; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=h8VneX6jvIb39sL+b3h3e8ynlMbxT5M4RcGTGS18RQw=; b=Khl/2qj98N00u241hjirQ2o4qtAz/8DkWRnT0R7uL36OkXf97JyXZU3d3uyqlw2MDY wda/Z1OoibLnltvkEmLapRzEwDyXvfblDuuAiKBLXYgNRfKBVbhxK0//aC56f+oayz0P 4fiHtMAXKNJlzneAUJVN8qycs39r/D3YPJi7V1ewcxulUl/tzU+j6LT/TWZNyibhb9oq hV1omK2NwXwhiu+9KCyItD+a3JLlM0Z2EhcDdhlPEPn9Nmm5kLj4hESfcDAVm8QZOGHL doLfQ8GqMmIJtB5/VXFbhGpZYnuREO/l8d6f9Ld+DoDdhfiYzrPSElHFEjLJDFfP/VxB cNDQ== X-Gm-Message-State: AOJu0Yx6sWdKlkJU2+9yta233+3JB4COCrwsKraaIuX9BhJa2HE/3LSF 5++s2f3OM0sjjugOVInsF+VGVoglNowKlGQM547Dh5SHGKK6zogLAtKnrggoogKt24pFsufeVfa F3RUy X-Gm-Gg: ASbGncsA3AwgcW31Q/yCtCTRdRFEm8no275awr6YPh2hk9JqpjLsI2ZSftf0wCkR7+m PqURcoxSOcNQ+jesJBg068WiMILiZT8NNp9SBKcKguEpHct97LAV3IILubElaIayWKjE6c2Pofc ZhFAFsYirFnx1c5R+WyMPfuPV1QoFIVmUeM/ypY+rsVtpo9im2WqI5XkCIDbScsnKCbwVdXCgPn +79STIbHOAxIFSASMw9NBIHbgIoUKhSe6IreaY4OiVitFXWrKCgTGvJByyulyNXyn4r+ZUsvOP0 4r2ALS7nTuVN82GQ7+nmMFCk880BFCpRuqG+Orq6dx1M5XdK04tDGHBRKEmmSXCBhz4Y X-Google-Smtp-Source: AGHT+IGEUbNS6fUD2J+4+c6mukXCxf+pqV4qLJ3+rIwndQaAvFO+UBg2GetW05FzLWsmZ77I5yv0CQ== X-Received: by 2002:a05:600c:4ed1:b0:442:d9fb:d9f1 with SMTP id 5b1f17b1804b1-4533cacf7c0mr95856955e9.4.1750082801226; Mon, 16 Jun 2025 07:06:41 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 8/9] hw/arm/mps2: Configure the AN500 CPU with 16 MPU regions Date: Mon, 16 Jun 2025 15:06:29 +0100 Message-ID: <20250616140630.2273870-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250616140630.2273870-1-peter.maydell@linaro.org> References: <20250616140630.2273870-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1750082892376116600 The AN500 application note documents that it configures the Cortex-M7 CPU to have 16 MPU regions. We weren't doing this in our emulation, so the CPU had only the default 8 MPU regions. Set the mpu-ns-regions property to 16 for this board. This bug doesn't affect any of the other board types we model in this source file, because they all use either the Cortex-M3 or Cortex-M4. Those CPUs do not have an RTL configurable number of MPU regions, and always provide 8 regions if the MPU is built in. Cc: qemu-stable@nongnu.org Reported-by: Corentin GENDRE Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Message-id: 20250605141801.1083266-1-peter.maydell@linaro.org --- hw/arm/mps2.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index 58efb41e6db..bd378e360b0 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -224,7 +224,11 @@ static void mps2_common_init(MachineState *machine) switch (mmc->fpga_type) { case FPGA_AN385: case FPGA_AN386: + qdev_prop_set_uint32(armv7m, "num-irq", 32); + break; case FPGA_AN500: + /* The AN500 configures its Cortex-M7 with 16 MPU regions */ + qdev_prop_set_uint32(armv7m, "mpu-ns-regions", 16); qdev_prop_set_uint32(armv7m, "num-irq", 32); break; case FPGA_AN511: --=20 2.43.0 From nobody Sat Nov 15 14:52:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1750082892; cv=none; d=zohomail.com; s=zohoarc; b=buYn6TIYVm7YWSgv+lnHxTIfFYPKzlgV8RowoB2PMmFt6eSpYZjzzRTLbTPthVZ4q5PzUPvzybzw9VZDE6D0j57EqZfAsB1FCHbIB5aJYmLO9fGmdye7gVjgNutOc/oD5MImi6EokVRL4UIRcA0nIm8bkgBcfyDQ486xFN7sKPE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1750082892; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=x7phbzrAcVyuXp2vszvsdZCmriphcffSkgR9/9ccTkE=; b=m3iGRlVWAnptRk7smIX08GMyjsBqXlWArynbz9XxqE3pVmJ0mnhgEArRfe0rUFTZ/g6E3cxH8scMImH+gnG3YlCQcVgqKnG8K++fh5m85Q3UxzzwnaM1Mtlg1ppq5GDF/4/+l2KN9NWLqFcmDxWaS5/RH+WB8UcRoVV5fRimeNY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1750082892917999.5026103765168; Mon, 16 Jun 2025 07:08:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uRAUc-0001ID-Td; Mon, 16 Jun 2025 10:07:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uRAU8-00016j-Ue for qemu-devel@nongnu.org; Mon, 16 Jun 2025 10:06:58 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uRAU1-00041S-2I for qemu-devel@nongnu.org; Mon, 16 Jun 2025 10:06:51 -0400 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-45305c280a3so18286455e9.3 for ; Mon, 16 Jun 2025 07:06:44 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4532e13c192sm146561975e9.26.2025.06.16.07.06.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jun 2025 07:06:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1750082803; x=1750687603; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=x7phbzrAcVyuXp2vszvsdZCmriphcffSkgR9/9ccTkE=; b=mgqijibzGr5OnC1XmAcUsnKnK7hG5RiAXWEvEZZI1kiRJe0LnkUuf671p1DuWSNeDv QG2bEeBl7pDC/qBzvrAEf5qiG8mzDPshhI+y208mwRJ4bojxGUyDtRtDndD9dPFLl3AO 93G4PjzbZGBLHXIQmK2Czkvn31xbJmrKfIe2CL/qU38Jcx/O+ProFLuTJzx8CwCnvp1v /uYuETu1YG+z44Cx/GJSY/DuWHsccjBHohWYIxfsJKQWBFAkKsDe1CXL+wCTTDJl2FI7 jLYpn502gFoMJcWFSBt7qCWeEzsh/H16D1sJKrUKveol5hDhma1jNlIj2lrN7OnJvZxY Je1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750082803; x=1750687603; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=x7phbzrAcVyuXp2vszvsdZCmriphcffSkgR9/9ccTkE=; b=I92vGtRIuuTzMp7rdIaOyvyd4BdisjR4xQ7apdb6w4jWQs1rzSWJycRn6a+nOxc6t0 I5b1raIAjgVxPQlfdbGEFP67VjuMfeONyAk+yDpaLjJmqiwWlb3PMZdGCz8oFLJp3k23 qsXDXzWBIf69KHgI+KzpWVMb7juiYXW2+YjUqg2ldkoj54r5pjA/bP9/TGqvc5rfMVoG toRcU27etdHAyhg+kYgL6X2+SbDt9/Gfvq7UExd9nH7+LFWkaVnT8o077stXi9zMwNrm vuLaxNs+LIN+OO6VuEDJBNCxVfgfAV3p1t2Jkdz/JV+2z5L8BRrkWsPHQubiZRbLOSez +AJQ== X-Gm-Message-State: AOJu0Yx7wU3CUJmzYZbILZdQw1OQ2GSPSKj6Qi/34zGovA8O/f4Zkh8r Gy3jXeGOsQ09P/BAMgEJzuM+cr6g1C/eeArA6kzvB5KZQXWq6vDTvsalgw7xIl5cVMcpXqaRVXW 3H4px X-Gm-Gg: ASbGncsTcSXkdOY5KTsR6SmIcfclJViqPtur4+cOxCzhyOq98eFKZM2WkTwH5gArOaS kO66poPy/uK11Tr87ogTgWWPiGYQwtRV+HMH8uacE8KhqELnYbC7SHoI/1Hmv5htZb91pk/ogV6 e0xybt+nbOhp98WJZcZjwwmZaOHy6rtuKhTZdMQ0g730EOo2Z+jJHn0JTO73kvzylh9F0gSvYkx uS5wB/hli1/9yebLBcSmbh16vv+0JRmKtR3QfkngxMQw1aySy5tGslgRiFWDF7GpyWLCMfY12R9 KbLPAzPFfw4bGEquY32afOjOg021v2oeRlMrI0HCrJFfrdCIurslnwbT9u931SRJiqLS X-Google-Smtp-Source: AGHT+IEa5xjXpsFFzA3KKMBBUcCPoXdpiN4Jt5ZFICWxO6c4FcvwgHsoHMCPByWmTdgLddatwZUY+w== X-Received: by 2002:a5d:5c0f:0:b0:3a4:d64a:3df6 with SMTP id ffacd0b85a97d-3a57238b99amr6410218f8f.3.1750082802777; Mon, 16 Jun 2025 07:06:42 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 9/9] linux-user/arm: Fix return value of SYS_cacheflush Date: Mon, 16 Jun 2025 15:06:30 +0100 Message-ID: <20250616140630.2273870-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250616140630.2273870-1-peter.maydell@linaro.org> References: <20250616140630.2273870-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1750082894389116600 From: J. Neusch=C3=A4fer Although the emulated cacheflush syscall does nothing, it still needs to return zero to indicate success. Cc: qemu-stable@nongnu.org Signed-off-by: J. Neusch=C3=A4fer Message-id: 20250613-cache-v1-1-ee9f4a9ba81b@gmx.net Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- linux-user/arm/cpu_loop.c | 1 + 1 file changed, 1 insertion(+) diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index e8417d04069..33f63951a95 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -363,6 +363,7 @@ void cpu_loop(CPUARMState *env) switch (n) { case ARM_NR_cacheflush: /* nop */ + env->regs[0] =3D 0; break; case ARM_NR_set_tls: cpu_set_tls(env, env->regs[0]); --=20 2.43.0