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Thu, 12 Jun 2025 17:04:33 -0700 (PDT) Date: Fri, 13 Jun 2025 00:04:07 +0000 In-Reply-To: <20250613000411.1516521-1-komlodi@google.com> Mime-Version: 1.0 References: <20250613000411.1516521-1-komlodi@google.com> X-Mailer: git-send-email 2.50.0.rc1.591.g9c95f17f64-goog Message-ID: <20250613000411.1516521-16-komlodi@google.com> Subject: [PATCH 15/19] hw/i3c/dw-i3c: Add controller resets From: Joe Komlodi To: qemu-devel@nongnu.org Cc: venture@google.com, komlodi@google.com, clg@kaod.org, peter.maydell@linaro.org, steven_lee@aspeedtech.com, leetroy@gmail.com, jamin_lin@aspeedtech.com, andrew@codeconstruct.com.au, joel@jms.id.au, qemu-arm@nongnu.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::549; envelope-from=3EWtLaAcKCl4GKIHK9ECKKCHA.8KIMAIQ-9ARAHJKJCJQ.KNC@flex--komlodi.bounces.google.com; helo=mail-pg1-x549.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1749773275022116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Adds behavior to the device reset register. Signed-off-by: Joe Komlodi Reviewed-by: Patrick Venture Reviewed-by: Stephen Longfield --- hw/i3c/dw-i3c.c | 117 ++++++++++++++++++++++++++++++++++++++++++++ hw/i3c/trace-events | 1 + 2 files changed, 118 insertions(+) diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c index 61845c909f..fff3a3591f 100644 --- a/hw/i3c/dw-i3c.c +++ b/hw/i3c/dw-i3c.c @@ -877,6 +877,122 @@ static void dw_i3c_intr_force_w(DWI3C *s, uint32_t va= l) dw_i3c_update_irq(s); } =20 +static void dw_i3c_cmd_queue_reset(DWI3C *s) +{ + fifo32_reset(&s->cmd_queue); + + ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, CMD_QUEUE_EMPTY_LOC, + fifo32_num_free(&s->cmd_queue)); + uint8_t empty_threshold =3D ARRAY_FIELD_EX32(s->regs, QUEUE_THLD_CTRL, + CMD_BUF_EMPTY_THLD); + if (fifo32_num_free(&s->cmd_queue) >=3D empty_threshold) { + ARRAY_FIELD_DP32(s->regs, INTR_STATUS, CMD_QUEUE_RDY, 1); + dw_i3c_update_irq(s); + }; +} + +static void dw_i3c_resp_queue_reset(DWI3C *s) +{ + fifo32_reset(&s->resp_queue); + + ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, RESP_BUF_BLR, + fifo32_num_used(&s->resp_queue)); + /* + * This interrupt will always be cleared because the threshold is a mi= nimum + * of 1 and the queue size is 0. + */ + ARRAY_FIELD_DP32(s->regs, INTR_STATUS, RESP_RDY, 0); + dw_i3c_update_irq(s); +} + +static void dw_i3c_ibi_queue_reset(DWI3C *s) +{ + fifo32_reset(&s->ibi_queue); + + ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, IBI_BUF_BLR, + fifo32_num_used(&s->resp_queue)); + /* + * This interrupt will always be cleared because the threshold is a mi= nimum + * of 1 and the queue size is 0. + */ + ARRAY_FIELD_DP32(s->regs, INTR_STATUS, IBI_THLD, 0); + dw_i3c_update_irq(s); +} + +static void dw_i3c_tx_queue_reset(DWI3C *s) +{ + fifo32_reset(&s->tx_queue); + + ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, TX_BUF_EMPTY_LOC, + fifo32_num_free(&s->tx_queue)); + /* TX buf is empty, so this interrupt will always be set. */ + ARRAY_FIELD_DP32(s->regs, INTR_STATUS, TX_THLD, 1); + dw_i3c_update_irq(s); +} + +static void dw_i3c_rx_queue_reset(DWI3C *s) +{ + fifo32_reset(&s->rx_queue); + + ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, RX_BUF_BLR, + fifo32_num_used(&s->resp_queue)); + /* + * This interrupt will always be cleared because the threshold is a mi= nimum + * of 1 and the queue size is 0. + */ + ARRAY_FIELD_DP32(s->regs, INTR_STATUS, RX_THLD, 0); + dw_i3c_update_irq(s); +} + +static void dw_i3c_reset(DeviceState *dev) +{ + DWI3C *s =3D DW_I3C(dev); + trace_dw_i3c_reset(s->cfg.id); + + memcpy(s->regs, dw_i3c_resets, sizeof(s->regs)); + /* + * The user config for these may differ from our resets array, set them + * manually. + */ + ARRAY_FIELD_DP32(s->regs, DEVICE_ADDR_TABLE_POINTER, ADDR, + s->cfg.dev_addr_table_pointer); + ARRAY_FIELD_DP32(s->regs, DEVICE_ADDR_TABLE_POINTER, DEPTH, + s->cfg.dev_addr_table_depth); + ARRAY_FIELD_DP32(s->regs, DEV_CHAR_TABLE_POINTER, + P_DEV_CHAR_TABLE_START_ADDR, + s->cfg.dev_char_table_pointer); + ARRAY_FIELD_DP32(s->regs, DEV_CHAR_TABLE_POINTER, DEV_CHAR_TABLE_DEPTH, + s->cfg.dev_char_table_depth); + + dw_i3c_cmd_queue_reset(s); + dw_i3c_resp_queue_reset(s); + dw_i3c_ibi_queue_reset(s); + dw_i3c_tx_queue_reset(s); + dw_i3c_rx_queue_reset(s); +} + +static void dw_i3c_reset_ctrl_w(DWI3C *s, uint32_t val) +{ + if (FIELD_EX32(val, RESET_CTRL, CORE_RESET)) { + dw_i3c_reset(DEVICE(s)); + } + if (FIELD_EX32(val, RESET_CTRL, CMD_QUEUE_RESET)) { + dw_i3c_cmd_queue_reset(s); + } + if (FIELD_EX32(val, RESET_CTRL, RESP_QUEUE_RESET)) { + dw_i3c_resp_queue_reset(s); + } + if (FIELD_EX32(val, RESET_CTRL, TX_BUF_RESET)) { + dw_i3c_tx_queue_reset(s); + } + if (FIELD_EX32(val, RESET_CTRL, RX_BUF_RESET)) { + dw_i3c_rx_queue_reset(s); + } + if (FIELD_EX32(val, RESET_CTRL, IBI_QUEUE_RESET)) { + dw_i3c_ibi_queue_reset(s); + } +} + static uint32_t dw_i3c_pop_rx(DWI3C *s) { if (fifo32_is_empty(&s->rx_queue)) { @@ -1634,6 +1750,7 @@ static void dw_i3c_write(void *opaque, hwaddr offset,= uint64_t value, dw_i3c_cmd_queue_port_w(s, val32); break; case R_RESET_CTRL: + dw_i3c_reset_ctrl_w(s, val32); break; case R_INTR_STATUS: dw_i3c_intr_status_w(s, val32); diff --git a/hw/i3c/trace-events b/hw/i3c/trace-events index a262fcce39..39f33d9a50 100644 --- a/hw/i3c/trace-events +++ b/hw/i3c/trace-events @@ -11,6 +11,7 @@ dw_i3c_send(uint32_t deviceid, uint32_t num_bytes) "I3C D= ev[%u] send %" PRId32 " dw_i3c_recv_data(uint32_t deviceid, uint32_t num_bytes) "I3C Dev[%u] recv = %" PRId32 " bytes from bus" dw_i3c_ibi_recv(uint32_t deviceid, uint8_t ibi_byte) "I3C Dev[%u] recv IBI= byte 0x%" PRIx8 dw_i3c_ibi_handle(uint32_t deviceid, uint8_t addr, bool rnw) "I3C Dev[%u] = handle IBI from address 0x%" PRIx8 " RnW=3D%d" +dw_i3c_reset(uint32_t deviceid) "I3C Dev[%u] reset" dw_i3c_pop_rx(uint32_t deviceid, uint32_t data) "I3C Dev[%u] pop 0x%" PRIx= 32 " from RX FIFO" dw_i3c_resp_queue_push(uint32_t deviceid, uint32_t data) "I3C Dev[%u] push= 0x%" PRIx32 " to response queue" dw_i3c_push_tx(uint32_t deviceid, uint32_t data) "I3C Dev[%u] push 0x%" PR= Ix32 " to TX FIFO" --=20 2.50.0.rc1.591.g9c95f17f64-goog