From nobody Sat Nov 15 17:09:40 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17494710122735.966809364860069; Mon, 9 Jun 2025 05:10:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uOaPO-0005EK-Jf; Mon, 09 Jun 2025 07:11:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uOaPL-0005CZ-A2 for qemu-devel@nongnu.org; Mon, 09 Jun 2025 07:11:15 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uOaPH-00075O-35 for qemu-devel@nongnu.org; Mon, 09 Jun 2025 07:11:15 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8CxG6xHwUZoRm4RAQ--.3336S3; Mon, 09 Jun 2025 19:11:03 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowMAxzxtFwUZoiU0SAQ--.4222S3; Mon, 09 Jun 2025 19:11:02 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org, philmd@linaro.org, jiaxun.yang@flygoat.com Subject: [PATCH 01/10] hw/loongarch: add a new type iocsr read for Avdance interrupt controller Date: Mon, 9 Jun 2025 18:48:24 +0800 Message-Id: <20250609104833.839811-2-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250609104833.839811-1-gaosong@loongson.cn> References: <20250609104833.839811-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMAxzxtFwUZoiU0SAQ--.4222S3 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1749471013857116600 Content-Type: text/plain; charset="utf-8" Use the IOCSRF_AVEC bit for avdance interrupt controller drivers avecintc_enable[1] and set the default value of the MISC_FUNC_REG bit IOCSR= M_AVEC_EN. and set the default value of the MISC_FUNC_REG bit IOCSRM_AVEC_EN. [1]:https://github.com/torvalds/linux/blob/master/drivers/irqchip/irq-loong= arch-avec.c Signed-off-by: Song Gao --- hw/loongarch/virt.c | 4 ++++ target/loongarch/cpu.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 1b504047db..90d4643721 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -548,6 +548,8 @@ static MemTxResult virt_iocsr_misc_read(void *opaque, h= waddr addr, break; case FEATURE_REG: ret =3D BIT(IOCSRF_MSI) | BIT(IOCSRF_EXTIOI) | BIT(IOCSRF_CSRIPI); + /*TODO: check bit IOCSRF_AVEC with virt_is_avec_enabled */ + ret |=3D BIT(IOCSRF_AVEC); if (kvm_enabled()) { ret |=3D BIT(IOCSRF_VM); } @@ -573,6 +575,8 @@ static MemTxResult virt_iocsr_misc_read(void *opaque, h= waddr addr, if (features & BIT(EXTIOI_ENABLE_INT_ENCODE)) { ret |=3D BIT_ULL(IOCSRM_EXTIOI_INT_ENCODE); } + /* enable avec default */ + ret |=3D BIT_ULL(IOCSRM_AVEC_EN); break; default: g_assert_not_reached(); diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 262bf87f7b..7cceec1204 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -31,6 +31,7 @@ #define IOCSRF_DVFSV1 7 #define IOCSRF_GMOD 9 #define IOCSRF_VM 11 +#define IOCSRF_AVEC 15 =20 #define VERSION_REG 0x0 #define FEATURE_REG 0x8 @@ -39,6 +40,7 @@ #define MISC_FUNC_REG 0x420 #define IOCSRM_EXTIOI_EN 48 #define IOCSRM_EXTIOI_INT_ENCODE 49 +#define IOCSRM_AVEC_EN 51 =20 #define IOCSR_MEM_SIZE 0x428 =20 --=20 2.34.1