From nobody Sat Nov 15 15:30:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17494710122735.966809364860069; Mon, 9 Jun 2025 05:10:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uOaPO-0005EK-Jf; Mon, 09 Jun 2025 07:11:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uOaPL-0005CZ-A2 for qemu-devel@nongnu.org; Mon, 09 Jun 2025 07:11:15 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uOaPH-00075O-35 for qemu-devel@nongnu.org; Mon, 09 Jun 2025 07:11:15 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8CxG6xHwUZoRm4RAQ--.3336S3; Mon, 09 Jun 2025 19:11:03 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowMAxzxtFwUZoiU0SAQ--.4222S3; Mon, 09 Jun 2025 19:11:02 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org, philmd@linaro.org, jiaxun.yang@flygoat.com Subject: [PATCH 01/10] hw/loongarch: add a new type iocsr read for Avdance interrupt controller Date: Mon, 9 Jun 2025 18:48:24 +0800 Message-Id: <20250609104833.839811-2-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250609104833.839811-1-gaosong@loongson.cn> References: <20250609104833.839811-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMAxzxtFwUZoiU0SAQ--.4222S3 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1749471013857116600 Content-Type: text/plain; charset="utf-8" Use the IOCSRF_AVEC bit for avdance interrupt controller drivers avecintc_enable[1] and set the default value of the MISC_FUNC_REG bit IOCSR= M_AVEC_EN. and set the default value of the MISC_FUNC_REG bit IOCSRM_AVEC_EN. [1]:https://github.com/torvalds/linux/blob/master/drivers/irqchip/irq-loong= arch-avec.c Signed-off-by: Song Gao --- hw/loongarch/virt.c | 4 ++++ target/loongarch/cpu.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 1b504047db..90d4643721 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -548,6 +548,8 @@ static MemTxResult virt_iocsr_misc_read(void *opaque, h= waddr addr, break; case FEATURE_REG: ret =3D BIT(IOCSRF_MSI) | BIT(IOCSRF_EXTIOI) | BIT(IOCSRF_CSRIPI); + /*TODO: check bit IOCSRF_AVEC with virt_is_avec_enabled */ + ret |=3D BIT(IOCSRF_AVEC); if (kvm_enabled()) { ret |=3D BIT(IOCSRF_VM); } @@ -573,6 +575,8 @@ static MemTxResult virt_iocsr_misc_read(void *opaque, h= waddr addr, if (features & BIT(EXTIOI_ENABLE_INT_ENCODE)) { ret |=3D BIT_ULL(IOCSRM_EXTIOI_INT_ENCODE); } + /* enable avec default */ + ret |=3D BIT_ULL(IOCSRM_AVEC_EN); break; default: g_assert_not_reached(); diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 262bf87f7b..7cceec1204 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -31,6 +31,7 @@ #define IOCSRF_DVFSV1 7 #define IOCSRF_GMOD 9 #define IOCSRF_VM 11 +#define IOCSRF_AVEC 15 =20 #define VERSION_REG 0x0 #define FEATURE_REG 0x8 @@ -39,6 +40,7 @@ #define MISC_FUNC_REG 0x420 #define IOCSRM_EXTIOI_EN 48 #define IOCSRM_EXTIOI_INT_ENCODE 49 +#define IOCSRM_AVEC_EN 51 =20 #define IOCSR_MEM_SIZE 0x428 =20 --=20 2.34.1 From nobody Sat Nov 15 15:30:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 174946900718876.07437269660113; Mon, 9 Jun 2025 04:36:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uOaPR-0005FH-Oe; Mon, 09 Jun 2025 07:11:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uOaPO-0005Dy-1P for qemu-devel@nongnu.org; Mon, 09 Jun 2025 07:11:18 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uOaPH-00075P-CD for qemu-devel@nongnu.org; Mon, 09 Jun 2025 07:11:16 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8CxbWtHwUZoSW4RAQ--.43897S3; Mon, 09 Jun 2025 19:11:03 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowMAxzxtFwUZoiU0SAQ--.4222S4; Mon, 09 Jun 2025 19:11:03 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org, philmd@linaro.org, jiaxun.yang@flygoat.com Subject: [PATCH 02/10] loongarch: add virt feature avecintc support Date: Mon, 9 Jun 2025 18:48:25 +0800 Message-Id: <20250609104833.839811-3-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250609104833.839811-1-gaosong@loongson.cn> References: <20250609104833.839811-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMAxzxtFwUZoiU0SAQ--.4222S4 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1749469010055116600 Content-Type: text/plain; charset="utf-8" LoongArchVirtMachinState add avecintc features, and it use to check whether virt machine support advance interrupt controller and default is on. Signed-off-by: Song Gao --- hw/loongarch/virt.c | 31 +++++++++++++++++++++++++++---- include/hw/loongarch/virt.h | 9 +++++++++ 2 files changed, 36 insertions(+), 4 deletions(-) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 90d4643721..35643a4e0b 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -47,6 +47,23 @@ #include "hw/virtio/virtio-iommu.h" #include "qemu/error-report.h" =20 +static void virt_get_avecintc(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + LoongArchVirtMachineState *lvms =3D LOONGARCH_VIRT_MACHINE(obj); + OnOffAuto avecintc =3D lvms->avecintc; + + visit_type_OnOffAuto(v, name, &avecintc, errp); + +} +static void virt_set_avecintc(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + LoongArchVirtMachineState *lvms =3D LOONGARCH_VIRT_MACHINE(obj); + + visit_type_OnOffAuto(v, name, &lvms->avecintc, errp); +} + static void virt_get_veiointc(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -548,8 +565,9 @@ static MemTxResult virt_iocsr_misc_read(void *opaque, h= waddr addr, break; case FEATURE_REG: ret =3D BIT(IOCSRF_MSI) | BIT(IOCSRF_EXTIOI) | BIT(IOCSRF_CSRIPI); - /*TODO: check bit IOCSRF_AVEC with virt_is_avec_enabled */ - ret |=3D BIT(IOCSRF_AVEC); + if (virt_is_avecintc_enabled(lvms)) { + ret |=3D BIT(IOCSRF_AVEC); + } if (kvm_enabled()) { ret |=3D BIT(IOCSRF_VM); } @@ -575,8 +593,9 @@ static MemTxResult virt_iocsr_misc_read(void *opaque, h= waddr addr, if (features & BIT(EXTIOI_ENABLE_INT_ENCODE)) { ret |=3D BIT_ULL(IOCSRM_EXTIOI_INT_ENCODE); } - /* enable avec default */ - ret |=3D BIT_ULL(IOCSRM_AVEC_EN); + if (virt_is_avecintc_enabled(lvms)) { + ret |=3D BIT_ULL(IOCSRM_AVEC_EN); + } break; default: g_assert_not_reached(); @@ -1212,6 +1231,10 @@ static void virt_class_init(ObjectClass *oc, const v= oid *data) NULL, NULL); object_class_property_set_description(oc, "v-eiointc", "Enable Virt Extend I/O Interrupt Controller."= ); + object_class_property_add(oc, "avecintc", "OnOffAuto", + virt_get_avecintc, virt_set_avecintc, NULL, NULL); + object_class_property_set_description(oc, "avecintc", + "Enable Advance Interrupt Controller."); machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); machine_class_allow_dynamic_sysbus_dev(mc, TYPE_UEFI_VARS_SYSBUS); #ifdef CONFIG_TPM diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index 2b7d19953f..3a81f048e8 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -50,6 +50,7 @@ struct LoongArchVirtMachineState { Notifier powerdown_notifier; OnOffAuto acpi; OnOffAuto veiointc; + OnOffAuto avecintc; char *oem_id; char *oem_table_id; DeviceState *acpi_ged; @@ -70,6 +71,14 @@ OBJECT_DECLARE_SIMPLE_TYPE(LoongArchVirtMachineState, LO= ONGARCH_VIRT_MACHINE) void virt_acpi_setup(LoongArchVirtMachineState *lvms); void virt_fdt_setup(LoongArchVirtMachineState *lvms); =20 +static inline bool virt_is_avecintc_enabled(LoongArchVirtMachineState *lvm= s) +{ + if (lvms->avecintc =3D=3D ON_OFF_AUTO_OFF) { + return false; + } + return true; +} + static inline bool virt_is_veiointc_enabled(LoongArchVirtMachineState *lvm= s) { if (lvms->veiointc =3D=3D ON_OFF_AUTO_OFF) { --=20 2.34.1 From nobody Sat Nov 15 15:30:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1749471451199784.4815343842266; Mon, 9 Jun 2025 05:17:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uOaPQ-0005Et-TZ; Mon, 09 Jun 2025 07:11:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uOaPL-0005Cm-DO for qemu-devel@nongnu.org; Mon, 09 Jun 2025 07:11:15 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uOaPH-00075Q-8J for qemu-devel@nongnu.org; Mon, 09 Jun 2025 07:11:15 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8BxYa9HwUZoTG4RAQ--.4109S3; Mon, 09 Jun 2025 19:11:04 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowMAxzxtFwUZoiU0SAQ--.4222S5; Mon, 09 Jun 2025 19:11:03 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org, philmd@linaro.org, jiaxun.yang@flygoat.com Subject: [PATCH 03/10] loongarch: add a advance interrupt controller device Date: Mon, 9 Jun 2025 18:48:26 +0800 Message-Id: <20250609104833.839811-4-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250609104833.839811-1-gaosong@loongson.cn> References: <20250609104833.839811-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMAxzxtFwUZoiU0SAQ--.4222S5 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1749471454057116600 Content-Type: text/plain; charset="utf-8" Add Loongarch advance interrupt controller device base Definition. Signed-off-by: Song Gao --- hw/intc/Kconfig | 3 ++ hw/intc/loongarch_avec.c | 68 ++++++++++++++++++++++++++++++++ hw/intc/meson.build | 1 + hw/loongarch/Kconfig | 1 + include/hw/intc/loongarch_avec.h | 35 ++++++++++++++++ 5 files changed, 108 insertions(+) create mode 100644 hw/intc/loongarch_avec.c create mode 100644 include/hw/intc/loongarch_avec.h diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index 7547528f2c..b9266dc269 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -109,3 +109,6 @@ config LOONGARCH_PCH_MSI =20 config LOONGARCH_EXTIOI bool + +config LOONGARCH_AVEC + bool diff --git a/hw/intc/loongarch_avec.c b/hw/intc/loongarch_avec.c new file mode 100644 index 0000000000..5a3e7ecc03 --- /dev/null +++ b/hw/intc/loongarch_avec.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * QEMU Loongson Advance interrupt controller. + * + * Copyright (C) 2025 Loongson Technology Corporation Limited + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/irq.h" +#include "hw/intc/loongarch_pch_msi.h" +#include "hw/intc/loongarch_pch_pic.h" +#include "hw/intc/loongarch_avec.h" +#include "hw/pci/msi.h" +#include "hw/misc/unimp.h" +#include "migration/vmstate.h" +#include "trace.h" +#include "hw/qdev-properties.h" + + +static void loongarch_avec_realize(DeviceState *dev, Error **errp) +{ + LoongArchAVECClass *lac =3D LOONGARCH_AVEC_GET_CLASS(dev); + + Error *local_err =3D NULL; + lac->parent_realize(dev, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + return; +} + +static void loongarch_avec_unrealize(DeviceState *dev) +{ + return; +} + +static void loongarch_avec_init(Object *obj) +{ + return; +} + +static void loongarch_avec_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + LoongArchAVECClass *lac =3D LOONGARCH_AVEC_CLASS(klass); + + dc->unrealize =3D loongarch_avec_unrealize; + device_class_set_parent_realize(dc, loongarch_avec_realize, + &lac->parent_realize); +} + +static const TypeInfo loongarch_avec_info =3D { + .name =3D TYPE_LOONGARCH_AVEC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(LoongArchAVECState), + .instance_init =3D loongarch_avec_init, + .class_init =3D loongarch_avec_class_init, +}; + +static void loongarch_avec_register_types(void) +{ + type_register_static(&loongarch_avec_info); +} + +type_init(loongarch_avec_register_types) diff --git a/hw/intc/meson.build b/hw/intc/meson.build index 602da304b0..6c7c0c6468 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -74,3 +74,4 @@ specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true: fi= les('loongarch_ipi.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarc= h_pch_pic.c', 'loongarch_pic_common.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true: files('loongarc= h_pch_msi.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_EXTIOI', if_true: files('loongarch= _extioi.c', 'loongarch_extioi_common.c')) +specific_ss.add(when: 'CONFIG_LOONGARCH_AVEC', if_true: files('loongarch_a= vec.c')) diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig index bb2838b7b5..1bf240b1e2 100644 --- a/hw/loongarch/Kconfig +++ b/hw/loongarch/Kconfig @@ -15,6 +15,7 @@ config LOONGARCH_VIRT select LOONGARCH_PCH_PIC select LOONGARCH_PCH_MSI select LOONGARCH_EXTIOI + select LOONGARCH_AVEC select LS7A_RTC select SMBIOS select ACPI_CPU_HOTPLUG diff --git a/include/hw/intc/loongarch_avec.h b/include/hw/intc/loongarch_a= vec.h new file mode 100644 index 0000000000..3c68593a7c --- /dev/null +++ b/include/hw/intc/loongarch_avec.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * LoongArch Advance interrupt controller definitions + * + * Copyright (C) 2025 Loongson Technology Corporation Limited + */ + +#include "qom/object.h" +#include "hw/sysbus.h" +#include "hw/loongarch/virt.h" + + +#define NR_VECTORS 256 + +#define TYPE_LOONGARCH_AVEC "loongarch_avec" +OBJECT_DECLARE_TYPE(LoongArchAVECState, LoongArchAVECClass, LOONGARCH_AVEC) + +typedef struct AVECCore { + CPUState *cpu; + qemu_irq parent_irq[NR_VECTORS]; + uint64_t arch_id; +} AVECCore; + +struct LoongArchAVECState { + SysBusDevice parent_obj; + AVECCore *cpu; + uint32_t num_cpu; +}; + +struct LoongArchAVECClass { + SysBusDeviceClass parent_class; + + DeviceRealize parent_realize; + DeviceUnrealize parent_unrealize; +}; --=20 2.34.1 From nobody Sat Nov 15 15:30:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1749472161352507.3760028906328; Mon, 9 Jun 2025 05:29:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uOaPT-0005FZ-6J; Mon, 09 Jun 2025 07:11:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uOaPL-0005CX-88 for qemu-devel@nongnu.org; Mon, 09 Jun 2025 07:11:15 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uOaPH-00075R-82 for qemu-devel@nongnu.org; Mon, 09 Jun 2025 07:11:15 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8BxnmtIwUZoT24RAQ--.3265S3; Mon, 09 Jun 2025 19:11:04 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowMAxzxtFwUZoiU0SAQ--.4222S6; Mon, 09 Jun 2025 19:11:03 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org, philmd@linaro.org, jiaxun.yang@flygoat.com Subject: [PATCH 04/10] target/loongarch: add msg interrupt CSR registers Date: Mon, 9 Jun 2025 18:48:27 +0800 Message-Id: <20250609104833.839811-5-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250609104833.839811-1-gaosong@loongson.cn> References: <20250609104833.839811-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMAxzxtFwUZoiU0SAQ--.4222S6 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1749472163922116600 Content-Type: text/plain; charset="utf-8" include CSR_MSGIS0-3, CSR_MSGIR and CSR_MSGIE. Signed-off-by: Song Gao --- target/loongarch/cpu.c | 7 +++++++ target/loongarch/cpu.h | 10 ++++++++++ target/loongarch/machine.c | 5 +++++ 3 files changed, 22 insertions(+) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index abad84c054..bde9f917fc 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -523,6 +523,13 @@ static void loongarch_la464_initfn(Object *obj) env->CSR_PRCFG3 =3D FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS,= 7); env->CSR_PRCFG3 =3D FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS,= 8); =20 + env->CSR_MSGIS[0] =3D 0; + env->CSR_MSGIS[1] =3D 0; + env->CSR_MSGIS[2] =3D 0; + env->CSR_MSGIS[3] =3D 0; + env->CSR_MSGIR =3D 0; + env->CSR_MSGIE =3D 0; + loongarch_la464_init_csr(obj); loongarch_cpu_post_init(obj); } diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 7cceec1204..a1918a85da 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -256,6 +256,12 @@ FIELD(TLB_MISC, ASID, 1, 10) FIELD(TLB_MISC, VPPN, 13, 35) FIELD(TLB_MISC, PS, 48, 6) =20 +/*Msg interrupt registers */ +FIELD(CSR_MSGIS, IS, 0, 63) +FIELD(CSR_MSGIR, INTNUM, 0, 8) +FIELD(CSR_MSGIR, ACTIVE, 31, 1) +FIELD(CSR_MSGIE, PT, 0, 8) + #define LSX_LEN (128) #define LASX_LEN (256) =20 @@ -373,6 +379,10 @@ typedef struct CPUArchState { uint64_t CSR_DBG; uint64_t CSR_DERA; uint64_t CSR_DSAVE; + /* Msg interrupt registers */ + uint64_t CSR_MSGIS[4]; + uint64_t CSR_MSGIR; + uint64_t CSR_MSGIE; struct { uint64_t guest_addr; } stealtime; diff --git a/target/loongarch/machine.c b/target/loongarch/machine.c index 4e70f5c879..7d5ee34f90 100644 --- a/target/loongarch/machine.c +++ b/target/loongarch/machine.c @@ -231,6 +231,11 @@ const VMStateDescription vmstate_loongarch_cpu =3D { VMSTATE_UINT64(env.CSR_DERA, LoongArchCPU), VMSTATE_UINT64(env.CSR_DSAVE, LoongArchCPU), =20 + /* Msg interrupt CSRs */ + VMSTATE_UINT64_ARRAY(env.CSR_MSGIS, LoongArchCPU, 4), + VMSTATE_UINT64(env.CSR_MSGIR, LoongArchCPU), + VMSTATE_UINT64(env.CSR_MSGIE, LoongArchCPU), + VMSTATE_UINT64(kvm_state_counter, LoongArchCPU), /* PV steal time */ VMSTATE_UINT64(env.stealtime.guest_addr, LoongArchCPU), --=20 2.34.1 From nobody Sat Nov 15 15:30:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17494705926276.233823400442134; Mon, 9 Jun 2025 05:03:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uOaPN-0005Cy-Do; Mon, 09 Jun 2025 07:11:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uOaPJ-0005C8-Tg for qemu-devel@nongnu.org; Mon, 09 Jun 2025 07:11:13 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uOaPG-00075S-Tm for qemu-devel@nongnu.org; Mon, 09 Jun 2025 07:11:13 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8DxDeNIwUZoUm4RAQ--.8877S3; Mon, 09 Jun 2025 19:11:04 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowMAxzxtFwUZoiU0SAQ--.4222S7; Mon, 09 Jun 2025 19:11:04 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org, philmd@linaro.org, jiaxun.yang@flygoat.com Subject: [PATCH 05/10] hw/loongarch: AVEC controller add a MemoryRegion Date: Mon, 9 Jun 2025 18:48:28 +0800 Message-Id: <20250609104833.839811-6-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250609104833.839811-1-gaosong@loongson.cn> References: <20250609104833.839811-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMAxzxtFwUZoiU0SAQ--.4222S7 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1749470599370116600 Content-Type: text/plain; charset="utf-8" the AVEC controller use 2ff00000-2fffffff Memory. Signed-off-by: Song Gao --- hw/intc/loongarch_avec.c | 25 ++++++++++++++++++++ hw/loongarch/virt.c | 39 +++++++++++++++++++++++++++++++- include/hw/intc/loongarch_avec.h | 1 + include/hw/loongarch/virt.h | 1 + 4 files changed, 65 insertions(+), 1 deletion(-) diff --git a/hw/intc/loongarch_avec.c b/hw/intc/loongarch_avec.c index 5a3e7ecc03..50956e7e4e 100644 --- a/hw/intc/loongarch_avec.c +++ b/hw/intc/loongarch_avec.c @@ -17,6 +17,24 @@ #include "trace.h" #include "hw/qdev-properties.h" =20 +static uint64_t loongarch_avec_mem_read(void *opaque, + hwaddr addr, unsigned size) +{ + return 0; +} + +static void loongarch_avec_mem_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + return; +} + + +static const MemoryRegionOps loongarch_avec_ops =3D { + .read =3D loongarch_avec_mem_read, + .write =3D loongarch_avec_mem_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; =20 static void loongarch_avec_realize(DeviceState *dev, Error **errp) { @@ -39,6 +57,13 @@ static void loongarch_avec_unrealize(DeviceState *dev) =20 static void loongarch_avec_init(Object *obj) { + LoongArchAVECState *s =3D LOONGARCH_AVEC(obj); + SysBusDevice *shd =3D SYS_BUS_DEVICE(obj); + memory_region_init_io(&s->avec_mmio, OBJECT(s), &loongarch_avec_ops, + s, TYPE_LOONGARCH_AVEC, 0x100000); + sysbus_init_mmio(shd, &s->avec_mmio); + msi_nonbroken =3D true; + return; } =20 diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 35643a4e0b..272355da2d 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -28,6 +28,7 @@ #include "hw/intc/loongarch_extioi.h" #include "hw/intc/loongarch_pch_pic.h" #include "hw/intc/loongarch_pch_msi.h" +#include "hw/intc/loongarch_avec.h" #include "hw/pci-host/ls7a.h" #include "hw/pci-host/gpex.h" #include "hw/misc/unimp.h" @@ -365,7 +366,7 @@ static void virt_cpu_irq_init(LoongArchVirtMachineState= *lvms) static void virt_irq_init(LoongArchVirtMachineState *lvms) { DeviceState *pch_pic, *pch_msi; - DeviceState *ipi, *extioi; + DeviceState *ipi, *extioi, *avec; SysBusDevice *d; int i, start, num; =20 @@ -411,6 +412,33 @@ static void virt_irq_init(LoongArchVirtMachineState *l= vms) * +--------+ +---------+ +---------+ * | UARTs | | Devices | | Devices | * +--------+ +---------+ +---------+ + * + * + * Advanced Extended IRQ model + * + * +-----+ +-----------------------+ +-------+ + * | IPI | --> | CPUINTC | <-- | Timer | + * +-----+ +-----------------------+ +-------+ + * ^ ^ ^ + * | | | + * +---------+ +----------+ +---------+ +-------+ + * | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs | + * +---------+ +----------+ +---------+ +-------+ + * ^ ^ + * | | + * +---------+ +---------+ + * | PCH-PIC | | PCH-MSI | + * +---------+ +---------+ + * ^ ^ ^ + * | | | + * +---------+ +---------+ +---------+ + * | Devices | | PCH-LPC | | Devices | + * +---------+ +---------+ +---------+ + * ^ + * | + * +---------+ + * | Devices | + * +---------+ */ =20 /* Create IPI device */ @@ -424,6 +452,15 @@ static void virt_irq_init(LoongArchVirtMachineState *l= vms) memory_region_add_subregion(&lvms->system_iocsr, MAIL_SEND_ADDR, sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1)); =20 + /* Create AVEC device*/ + if (virt_is_avecintc_enabled(lvms)) { + avec =3D qdev_new(TYPE_LOONGARCH_AVEC); + lvms->avec =3D avec; + sysbus_realize_and_unref(SYS_BUS_DEVICE(avec), &error_fatal); + memory_region_add_subregion(get_system_memory(), VIRT_PCH_MSI_ADDR= _LOW, + sysbus_mmio_get_region(SYS_BUS_DEVICE(avec), 0)); + } + /* Create EXTIOI device */ extioi =3D qdev_new(TYPE_LOONGARCH_EXTIOI); lvms->extioi =3D extioi; diff --git a/include/hw/intc/loongarch_avec.h b/include/hw/intc/loongarch_a= vec.h index 3c68593a7c..274b284641 100644 --- a/include/hw/intc/loongarch_avec.h +++ b/include/hw/intc/loongarch_avec.h @@ -23,6 +23,7 @@ typedef struct AVECCore { =20 struct LoongArchAVECState { SysBusDevice parent_obj; + MemoryRegion avec_mmio; AVECCore *cpu; uint32_t num_cpu; }; diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index 3a81f048e8..172f40711d 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -64,6 +64,7 @@ struct LoongArchVirtMachineState { struct loongarch_boot_info bootinfo; DeviceState *ipi; DeviceState *extioi; + DeviceState *avec; }; =20 #define TYPE_LOONGARCH_VIRT_MACHINE MACHINE_TYPE_NAME("virt") --=20 2.34.1 From nobody Sat Nov 15 15:30:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1749472223167973.6683182633016; Mon, 9 Jun 2025 05:30:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uOaPP-0005Ef-R7; Mon, 09 Jun 2025 07:11:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uOaPL-0005CY-9Q for qemu-devel@nongnu.org; Mon, 09 Jun 2025 07:11:15 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uOaPH-00075T-0Y for qemu-devel@nongnu.org; Mon, 09 Jun 2025 07:11:15 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8DxQK9IwUZoVW4RAQ--.9089S3; Mon, 09 Jun 2025 19:11:04 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowMAxzxtFwUZoiU0SAQ--.4222S8; Mon, 09 Jun 2025 19:11:04 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org, philmd@linaro.org, jiaxun.yang@flygoat.com Subject: [PATCH 06/10] hw/loongarch: Implement avec controller imput and output pins Date: Mon, 9 Jun 2025 18:48:29 +0800 Message-Id: <20250609104833.839811-7-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250609104833.839811-1-gaosong@loongson.cn> References: <20250609104833.839811-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMAxzxtFwUZoiU0SAQ--.4222S8 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1749472224654116600 Content-Type: text/plain; charset="utf-8" the AVEC controller supports 256*256 irqs, all the irqs connect CPU INT_AVE= C irq Signed-off-by: Song Gao --- hw/intc/loongarch_avec.c | 28 ++++++++++++++++++++++++++++ hw/loongarch/virt.c | 11 +++++++++-- target/loongarch/cpu.h | 3 ++- 3 files changed, 39 insertions(+), 3 deletions(-) diff --git a/hw/intc/loongarch_avec.c b/hw/intc/loongarch_avec.c index 50956e7e4e..c692fef43c 100644 --- a/hw/intc/loongarch_avec.c +++ b/hw/intc/loongarch_avec.c @@ -36,9 +36,19 @@ static const MemoryRegionOps loongarch_avec_ops =3D { .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 +static void avec_irq_handler(void *opaque, int irq, int level) +{ + return; +} + static void loongarch_avec_realize(DeviceState *dev, Error **errp) { + LoongArchAVECState *s =3D LOONGARCH_AVEC(dev); LoongArchAVECClass *lac =3D LOONGARCH_AVEC_GET_CLASS(dev); + MachineState *machine =3D MACHINE(qdev_get_machine()); + MachineClass *mc =3D MACHINE_GET_CLASS(machine); + const CPUArchIdList *id_list; + int i, irq; =20 Error *local_err =3D NULL; lac->parent_realize(dev, &local_err); @@ -47,6 +57,24 @@ static void loongarch_avec_realize(DeviceState *dev, Err= or **errp) return; } =20 + assert(mc->possible_cpu_arch_ids); + id_list =3D mc->possible_cpu_arch_ids(machine); + s->num_cpu =3D id_list->len; + s->cpu =3D g_new(AVECCore, s->num_cpu); + if (s->cpu =3D=3D NULL) { + error_setg(errp, "Memory allocation for AVECCore fail"); + return; + } + + for (i =3D 0; i < s->num_cpu; i++) { + s->cpu[i].arch_id =3D id_list->cpus[i].arch_id; + s->cpu[i].cpu =3D CPU(id_list->cpus[i].cpu); + for (irq =3D 0; irq < NR_VECTORS; irq++) { + qdev_init_gpio_out(dev, &s->cpu[i].parent_irq[irq], 1); + } + } + qdev_init_gpio_in(dev, avec_irq_handler, NR_VECTORS * s->num_cpu); + return; } =20 diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 272355da2d..718b5b4f92 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -363,7 +363,7 @@ static void virt_cpu_irq_init(LoongArchVirtMachineState= *lvms) } } =20 -static void virt_irq_init(LoongArchVirtMachineState *lvms) +static void virt_irq_init(LoongArchVirtMachineState *lvms, MachineState *m= s) { DeviceState *pch_pic, *pch_msi; DeviceState *ipi, *extioi, *avec; @@ -459,6 +459,13 @@ static void virt_irq_init(LoongArchVirtMachineState *l= vms) sysbus_realize_and_unref(SYS_BUS_DEVICE(avec), &error_fatal); memory_region_add_subregion(get_system_memory(), VIRT_PCH_MSI_ADDR= _LOW, sysbus_mmio_get_region(SYS_BUS_DEVICE(avec), 0)); + CPUState *cpu_state; + DeviceState *cpudev; + for (int cpu =3D 0; cpu < ms->smp.cpus; cpu++) { + cpu_state =3D qemu_get_cpu(cpu); + cpudev =3D DEVICE(cpu_state); + qdev_connect_gpio_out(avec, cpu, qdev_get_gpio_in(cpudev, INT_= AVEC)); + } } =20 /* Create EXTIOI device */ @@ -799,7 +806,7 @@ static void virt_init(MachineState *machine) } =20 /* Initialize the IO interrupt subsystem */ - virt_irq_init(lvms); + virt_irq_init(lvms, machine); lvms->machine_done.notify =3D virt_done; qemu_add_machine_init_done_notifier(&lvms->machine_done); /* connect powerdown request */ diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index a1918a85da..b96df1cb2a 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -240,9 +240,10 @@ FIELD(CSR_CRMD, WE, 9, 1) extern const char * const regnames[32]; extern const char * const fregnames[32]; =20 -#define N_IRQS 13 +#define N_IRQS 15 #define IRQ_TIMER 11 #define IRQ_IPI 12 +#define INT_AVEC 14 =20 #define LOONGARCH_STLB 2048 /* 2048 STLB */ #define LOONGARCH_MTLB 64 /* 64 MTLB */ --=20 2.34.1 From nobody Sat Nov 15 15:30:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1749471765307611.1645366115704; Mon, 9 Jun 2025 05:22:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uOaPQ-0005Ek-E5; Mon, 09 Jun 2025 07:11:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uOaPL-0005CW-6k for qemu-devel@nongnu.org; Mon, 09 Jun 2025 07:11:15 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uOaPH-00075U-3l for qemu-devel@nongnu.org; Mon, 09 Jun 2025 07:11:14 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8DxbKxJwUZoWG4RAQ--.44350S3; Mon, 09 Jun 2025 19:11:05 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowMAxzxtFwUZoiU0SAQ--.4222S9; Mon, 09 Jun 2025 19:11:04 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org, philmd@linaro.org, jiaxun.yang@flygoat.com Subject: [PATCH 07/10] hw/loongarch: connect pch_msi controller to avec controller Date: Mon, 9 Jun 2025 18:48:30 +0800 Message-Id: <20250609104833.839811-8-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250609104833.839811-1-gaosong@loongson.cn> References: <20250609104833.839811-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMAxzxtFwUZoiU0SAQ--.4222S9 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1749471767261116600 Content-Type: text/plain; charset="utf-8" Signed-off-by: Song Gao --- hw/loongarch/virt.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 718b5b4f92..6b670e7936 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -503,11 +503,19 @@ static void virt_irq_init(LoongArchVirtMachineState *= lvms, MachineState *ms) qdev_prop_set_uint32(pch_msi, "msi_irq_num", num); d =3D SYS_BUS_DEVICE(pch_msi); sysbus_realize_and_unref(d, &error_fatal); - sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW); - for (i =3D 0; i < num; i++) { - /* Connect pch_msi irqs to extioi */ - qdev_connect_gpio_out(DEVICE(d), i, - qdev_get_gpio_in(extioi, i + start)); + if (virt_is_avecintc_enabled(lvms)) { + for (i =3D 0; i < num; i++) { + /* Connect pch_msi irqs to avec */ + qdev_connect_gpio_out(DEVICE(d), i, + qdev_get_gpio_in(avec, i + start)); + } + } else { + sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW); + for (i =3D 0; i < num; i++) { + /* Connect pch_msi irqs to extioi */ + qdev_connect_gpio_out(DEVICE(d), i, + qdev_get_gpio_in(extioi, i + start)); + } } =20 virt_devices_init(pch_pic, lvms); --=20 2.34.1 From nobody Sat Nov 15 15:30:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1749472051114541.0883740800018; Mon, 9 Jun 2025 05:27:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uOaPT-0005GC-RB; Mon, 09 Jun 2025 07:11:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uOaPN-0005Dx-WE for qemu-devel@nongnu.org; Mon, 09 Jun 2025 07:11:18 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uOaPH-00075c-TT for qemu-devel@nongnu.org; Mon, 09 Jun 2025 07:11:16 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8Ax3eJJwUZoXm4RAQ--.5636S3; Mon, 09 Jun 2025 19:11:05 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowMAxzxtFwUZoiU0SAQ--.4222S10; Mon, 09 Jun 2025 19:11:05 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org, philmd@linaro.org, jiaxun.yang@flygoat.com Subject: [PATCH 08/10] hw/loongarch: Implement avec set_irq Date: Mon, 9 Jun 2025 18:48:31 +0800 Message-Id: <20250609104833.839811-9-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250609104833.839811-1-gaosong@loongson.cn> References: <20250609104833.839811-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMAxzxtFwUZoiU0SAQ--.4222S10 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1749472054716116600 Content-Type: text/plain; charset="utf-8" Signed-off-by: Song Gao --- hw/intc/loongarch_avec.c | 37 ++++++++++++++++++++++++++++++++++--- 1 file changed, 34 insertions(+), 3 deletions(-) diff --git a/hw/intc/loongarch_avec.c b/hw/intc/loongarch_avec.c index c692fef43c..f609ed9aaa 100644 --- a/hw/intc/loongarch_avec.c +++ b/hw/intc/loongarch_avec.c @@ -16,6 +16,12 @@ #include "migration/vmstate.h" #include "trace.h" #include "hw/qdev-properties.h" +#include "target/loongarch/cpu.h" + +/* msg addr field */ +FIELD(MSG_ADDR, IRQ_NUM, 4, 8) +FIELD(MSG_ADDR, CPU_NUM, 12, 8) +FIELD(MSG_ADDR, FIX, 28, 12) =20 static uint64_t loongarch_avec_mem_read(void *opaque, hwaddr addr, unsigned size) @@ -23,12 +29,32 @@ static uint64_t loongarch_avec_mem_read(void *opaque, return 0; } =20 +static void avec_set_irq(LoongArchAVECState *s, int cpu_num, int irq_num, = int level) +{ + MachineState *machine =3D MACHINE(qdev_get_machine()); + MachineClass *mc =3D MACHINE_GET_CLASS(machine); + const CPUArchIdList *id_list =3D NULL; + + assert(mc->possible_cpu_arch_ids(machine)); + id_list =3D mc->possible_cpu_arch_ids(machine); + CPUState *cpu =3D id_list->cpus[cpu_num].cpu; + CPULoongArchState *env =3D &LOONGARCH_CPU(cpu)->env; + set_bit(irq_num, &env->CSR_MSGIS[irq_num / 64]); + qemu_set_irq(s->cpu[cpu_num].parent_irq[irq_num], 1); +} + static void loongarch_avec_mem_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { - return; -} + int irq_num, cpu_num =3D 0; + LoongArchAVECState *s =3D LOONGARCH_AVEC(opaque); + uint64_t msg_addr =3D addr + VIRT_PCH_MSI_ADDR_LOW; + + cpu_num =3D FIELD_EX64(msg_addr, MSG_ADDR, IRQ_NUM); + irq_num =3D FIELD_EX64(msg_addr, MSG_ADDR, CPU_NUM); =20 + avec_set_irq(s, cpu_num, irq_num, 1); +} =20 static const MemoryRegionOps loongarch_avec_ops =3D { .read =3D loongarch_avec_mem_read, @@ -38,7 +64,12 @@ static const MemoryRegionOps loongarch_avec_ops =3D { =20 static void avec_irq_handler(void *opaque, int irq, int level) { - return; + int cpu_num, irq_num =3D 0; + LoongArchAVECState *s =3D LOONGARCH_AVEC(opaque); + cpu_num =3D irq / 256; + irq_num =3D irq % 256; + + avec_set_irq(s, cpu_num, irq_num, level); } =20 static void loongarch_avec_realize(DeviceState *dev, Error **errp) --=20 2.34.1 From nobody Sat Nov 15 15:30:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1749467529852830.0575494371099; Mon, 9 Jun 2025 04:12:09 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uOaPS-0005FV-OJ; Mon, 09 Jun 2025 07:11:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uOaPN-0005Du-PP for qemu-devel@nongnu.org; Mon, 09 Jun 2025 07:11:17 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uOaPH-00075d-CL for qemu-devel@nongnu.org; Mon, 09 Jun 2025 07:11:16 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8AxmnFJwUZoXW4RAQ--.43940S3; Mon, 09 Jun 2025 19:11:05 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowMAxzxtFwUZoiU0SAQ--.4222S11; Mon, 09 Jun 2025 19:11:05 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org, philmd@linaro.org, jiaxun.yang@flygoat.com Subject: [PATCH 09/10] target/loongarch: loongarch CPU supoort avec irqs Date: Mon, 9 Jun 2025 18:48:32 +0800 Message-Id: <20250609104833.839811-10-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250609104833.839811-1-gaosong@loongson.cn> References: <20250609104833.839811-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMAxzxtFwUZoiU0SAQ--.4222S11 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1749467535902116600 Content-Type: text/plain; charset="utf-8" Signed-off-by: Song Gao --- target/loongarch/cpu-csr.h | 1 + target/loongarch/cpu.c | 17 +++++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h index 0834e91f30..83f6cb081a 100644 --- a/target/loongarch/cpu-csr.h +++ b/target/loongarch/cpu-csr.h @@ -39,6 +39,7 @@ FIELD(CSR_ECFG, VS, 16, 3) =20 #define LOONGARCH_CSR_ESTAT 0x5 /* Exception status */ FIELD(CSR_ESTAT, IS, 0, 13) +FIELD(CSR_ESTAT, MSGINT, 14, 1) FIELD(CSR_ESTAT, ECODE, 16, 6) FIELD(CSR_ESTAT, ESUBCODE, 22, 9) =20 diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index bde9f917fc..207d11266f 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -127,6 +127,23 @@ void loongarch_cpu_set_irq(void *opaque, int irq, int = level) return; } =20 + /* do INTC_AVEC irqs */ + if (irq =3D=3D INT_AVEC) { + for (int i =3D 256; i >=3D 0; i--) { + if (test_bit(i, &(env->CSR_MSGIS[i / 64]))) { + env->CSR_MSGIR =3D FIELD_DP64(env->CSR_MSGIR, CSR_MSGIR, I= NTNUM, i); + env->CSR_MSGIR =3D FIELD_DP64(env->CSR_MSGIR, CSR_MSGIR, A= CTIVE, 0); + env->CSR_ESTAT =3D FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, M= SGINT, 1); + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + clear_bit(i, &(env->CSR_MSGIS[i / 64])); + } + } + } else { + env->CSR_ESTAT =3D FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, MSGINT, 0); + env->CSR_MSGIR =3D FIELD_DP64(env->CSR_MSGIR, CSR_MSGIR, ACTIVE, 1); + return; + } + if (kvm_enabled()) { kvm_loongarch_set_interrupt(cpu, irq, level); } else if (tcg_enabled()) { --=20 2.34.1 From nobody Sat Nov 15 15:30:22 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 174947065845047.748054655929195; Mon, 9 Jun 2025 05:04:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uOaPN-0005CV-Do; Mon, 09 Jun 2025 07:11:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uOaPJ-0005C6-RN for qemu-devel@nongnu.org; Mon, 09 Jun 2025 07:11:13 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uOaPH-00075e-49 for qemu-devel@nongnu.org; Mon, 09 Jun 2025 07:11:13 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8DxCeFJwUZoYW4RAQ--.3066S3; Mon, 09 Jun 2025 19:11:05 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowMAxzxtFwUZoiU0SAQ--.4222S12; Mon, 09 Jun 2025 19:11:05 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org, philmd@linaro.org, jiaxun.yang@flygoat.com Subject: [PATCH 10/10] target/loongarch: cpu do interrupt support msg interrupt. Date: Mon, 9 Jun 2025 18:48:33 +0800 Message-Id: <20250609104833.839811-11-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250609104833.839811-1-gaosong@loongson.cn> References: <20250609104833.839811-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMAxzxtFwUZoiU0SAQ--.4222S12 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1749470660040116600 Content-Type: text/plain; charset="utf-8" we use CSR_ESTAT and CSR_ECFG bit 15 for msg interrupt. and loongarch_cpu_do_interrupt support msg interrupts. Signed-off-by: Song Gao --- target/loongarch/cpu-csr.h | 3 ++- target/loongarch/cpu.c | 35 ++++++++++++++++++++++++++++++----- 2 files changed, 32 insertions(+), 6 deletions(-) diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h index 83f6cb081a..5a00cf3366 100644 --- a/target/loongarch/cpu-csr.h +++ b/target/loongarch/cpu-csr.h @@ -35,11 +35,12 @@ FIELD(CSR_MISC, DWPL, 16, 3) =20 #define LOONGARCH_CSR_ECFG 0x4 /* Exception config */ FIELD(CSR_ECFG, LIE, 0, 13) +FIELD(CSR_ECFG, MSGINT, 14, 1) /* used for msg */ FIELD(CSR_ECFG, VS, 16, 3) =20 #define LOONGARCH_CSR_ESTAT 0x5 /* Exception status */ FIELD(CSR_ESTAT, IS, 0, 13) -FIELD(CSR_ESTAT, MSGINT, 14, 1) +FIELD(CSR_ESTAT, MSGINT, 14, 1) /* used for msg */ FIELD(CSR_ESTAT, ECODE, 16, 6) FIELD(CSR_ESTAT, ESUBCODE, 22, 9) =20 diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 207d11266f..b92463101e 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -117,6 +117,13 @@ static vaddr loongarch_cpu_get_pc(CPUState *cs) #ifndef CONFIG_USER_ONLY #include "hw/loongarch/virt.h" =20 +static uint32_t loongarch_cpu_has_interrupt(CPULoongArchState *env) +{ + uint32_t ret =3D 0; + ret =3D FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); + ret |=3D FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, MSGINT); + return ret; +} void loongarch_cpu_set_irq(void *opaque, int irq, int level) { LoongArchCPU *cpu =3D opaque; @@ -134,21 +141,20 @@ void loongarch_cpu_set_irq(void *opaque, int irq, int= level) env->CSR_MSGIR =3D FIELD_DP64(env->CSR_MSGIR, CSR_MSGIR, I= NTNUM, i); env->CSR_MSGIR =3D FIELD_DP64(env->CSR_MSGIR, CSR_MSGIR, A= CTIVE, 0); env->CSR_ESTAT =3D FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, M= SGINT, 1); - cpu_interrupt(cs, CPU_INTERRUPT_HARD); + env->CSR_ECFG =3D FIELD_DP64(env->CSR_ECFG, CSR_ECFG, MSGI= NT, 1); clear_bit(i, &(env->CSR_MSGIS[i / 64])); } } } else { env->CSR_ESTAT =3D FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, MSGINT, 0); - env->CSR_MSGIR =3D FIELD_DP64(env->CSR_MSGIR, CSR_MSGIR, ACTIVE, 1); - return; + env->CSR_ECFG =3D FIELD_DP64(env->CSR_ECFG, CSR_ECFG, MSGINT, 0); } =20 if (kvm_enabled()) { kvm_loongarch_set_interrupt(cpu, irq, level); } else if (tcg_enabled()) { env->CSR_ESTAT =3D deposit64(env->CSR_ESTAT, irq, 1, level !=3D 0); - if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) { + if (loongarch_cpu_has_interrupt(env)) { cpu_interrupt(cs, CPU_INTERRUPT_HARD); } else { cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); @@ -166,12 +172,24 @@ static inline bool cpu_loongarch_hw_interrupts_enable= d(CPULoongArchState *env) return ret; } =20 +static inline bool cpu_loongarch_hw_interrupt_msg_pending(CPULoongArchStat= e *env) +{ + bool pending_msg =3D 0; + bool status_msg =3D 0; + + pending_msg =3D FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, MSGINT); + status_msg =3D FIELD_EX64(env->CSR_ECFG, CSR_ECFG, MSGINT); + + return (pending_msg & status_msg) !=3D 0; +} /* Check if there is pending and not masked out interrupt */ static inline bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *= env) { uint32_t pending; uint32_t status; - + if (cpu_loongarch_hw_interrupt_msg_pending(env)) { + return true; + } pending =3D FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); status =3D FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE); =20 @@ -285,6 +303,13 @@ static void loongarch_cpu_do_interrupt(CPUState *cs) uint32_t vector =3D 0; uint32_t pending =3D FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); pending &=3D FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE); + if (cpu_loongarch_hw_interrupt_msg_pending(env)) { + env->CSR_ESTAT =3D FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, MSGIN= T, 0); + env->CSR_ECFG =3D FIELD_DP64(env->CSR_ECFG, CSR_ECFG, MSGINT, = 0); + set_pc(env, env->CSR_EENTRY + \ + (EXCCODE_EXTERNAL_INT + INT_AVEC) * vec_size); + return; + } =20 /* Find the highest-priority interrupt. */ vector =3D 31 - clz32(pending); --=20 2.34.1