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Tsirkin" , Dmitry Osipenko , Paolo Bonzini , Peter Maydell , John Snow , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Pierrick Bouvier , Peter Xu , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Fabiano Rosas , qemu-arm@nongnu.org, Thomas Huth , Alexandre Iooss , Gustavo Romero , Markus Armbruster , David Hildenbrand , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mahmoud Mandour , Yiwei Zhang , qemu-stable@nongnu.org Subject: [PATCH v4 12/17] virtio-gpu: support context init multiple timeline Date: Tue, 3 Jun 2025 12:01:59 +0100 Message-ID: <20250603110204.838117-13-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250603110204.838117-1-alex.bennee@linaro.org> References: <20250603110204.838117-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52b; envelope-from=alex.bennee@linaro.org; helo=mail-ed1-x52b.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1748948724030116600 From: Yiwei Zhang Venus and later native contexts have their own fence context along with multiple timelines within. Fences wtih VIRTIO_GPU_FLAG_INFO_RING_IDX in the flags must be dispatched to be created on the target context. Fence signaling also has to be handled on the specific timeline within that target context. Before this change, venus fencing is completely broken if the host driver doesn't support implicit fencing with external memory objects. Frames can go backwards along with random artifacts on screen if the host driver doesn't attach an implicit fence to the render target. The symptom could be hidden by certain guest wsi backend that waits on a venus native VkFence object for the actual payload with limited present modes or under special configs. e.g. x11 mailbox or xwayland. After this change, everything related to venus fencing starts making sense. Confirmed this via guest and host side perfetto tracing. Cc: Fixes: 94d0ea1c1928 ("virtio-gpu: Support Venus context") Signed-off-by: Yiwei Zhang Reviewed-by: Dmitry Osipenko Message-Id: <20250518152651.334115-1-zzyiwei@gmail.com> [AJB: remove version history from commit message] Signed-off-by: Alex Benn=C3=A9e Tested-by: Dmitry Osipenko --- hw/display/virtio-gpu-virgl.c | 44 +++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/hw/display/virtio-gpu-virgl.c b/hw/display/virtio-gpu-virgl.c index b4aa8abb96..cea2e12eb9 100644 --- a/hw/display/virtio-gpu-virgl.c +++ b/hw/display/virtio-gpu-virgl.c @@ -978,6 +978,15 @@ void virtio_gpu_virgl_process_cmd(VirtIOGPU *g, } =20 trace_virtio_gpu_fence_ctrl(cmd->cmd_hdr.fence_id, cmd->cmd_hdr.type); +#if VIRGL_VERSION_MAJOR >=3D 1 + if (cmd->cmd_hdr.flags & VIRTIO_GPU_FLAG_INFO_RING_IDX) { + virgl_renderer_context_create_fence(cmd->cmd_hdr.ctx_id, + VIRGL_RENDERER_FENCE_FLAG_MERG= EABLE, + cmd->cmd_hdr.ring_idx, + cmd->cmd_hdr.fence_id); + return; + } +#endif virgl_renderer_create_fence(cmd->cmd_hdr.fence_id, cmd->cmd_hdr.type); } =20 @@ -991,6 +1000,11 @@ static void virgl_write_fence(void *opaque, uint32_t = fence) * the guest can end up emitting fences out of order * so we should check all fenced cmds not just the first one. */ +#if VIRGL_VERSION_MAJOR >=3D 1 + if (cmd->cmd_hdr.flags & VIRTIO_GPU_FLAG_INFO_RING_IDX) { + continue; + } +#endif if (cmd->cmd_hdr.fence_id > fence) { continue; } @@ -1005,6 +1019,29 @@ static void virgl_write_fence(void *opaque, uint32_t= fence) } } =20 +#if VIRGL_VERSION_MAJOR >=3D 1 +static void virgl_write_context_fence(void *opaque, uint32_t ctx_id, + uint32_t ring_idx, uint64_t fence_id= ) { + VirtIOGPU *g =3D opaque; + struct virtio_gpu_ctrl_command *cmd, *tmp; + + QTAILQ_FOREACH_SAFE(cmd, &g->fenceq, next, tmp) { + if (cmd->cmd_hdr.flags & VIRTIO_GPU_FLAG_INFO_RING_IDX && + cmd->cmd_hdr.ctx_id =3D=3D ctx_id && cmd->cmd_hdr.ring_idx =3D= =3D ring_idx && + cmd->cmd_hdr.fence_id <=3D fence_id) { + trace_virtio_gpu_fence_resp(cmd->cmd_hdr.fence_id); + virtio_gpu_ctrl_response_nodata(g, cmd, VIRTIO_GPU_RESP_OK_NOD= ATA); + QTAILQ_REMOVE(&g->fenceq, cmd, next); + g_free(cmd); + g->inflight--; + if (virtio_gpu_stats_enabled(g->parent_obj.conf)) { + trace_virtio_gpu_dec_inflight_fences(g->inflight); + } + } + } +} +#endif + static virgl_renderer_gl_context virgl_create_context(void *opaque, int scanout_idx, struct virgl_renderer_gl_ctx_param *params) @@ -1039,11 +1076,18 @@ static int virgl_make_context_current(void *opaque,= int scanout_idx, } =20 static struct virgl_renderer_callbacks virtio_gpu_3d_cbs =3D { +#if VIRGL_VERSION_MAJOR >=3D 1 + .version =3D 3, +#else .version =3D 1, +#endif .write_fence =3D virgl_write_fence, .create_gl_context =3D virgl_create_context, .destroy_gl_context =3D virgl_destroy_context, .make_current =3D virgl_make_context_current, +#if VIRGL_VERSION_MAJOR >=3D 1 + .write_context_fence =3D virgl_write_context_fence, +#endif }; =20 static void virtio_gpu_print_stats(void *opaque) --=20 2.47.2