From nobody Sat Nov 15 17:46:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1748879016; cv=none; d=zohomail.com; s=zohoarc; b=eszmu9kJE3tkLA8bJkU23buLtMNEbBVPFGJSem7vb2HIYpK9Ibf/C3dp6DehnzKiBXTxub7tEgcy1OemR+pkHoHu2suRNpSBM3/vNSGwcqbBnQ7ZdpxL+QNcvLO+Fv1OSffNIVuxqIFqBI4M87+ifVjEF9oeBb7zmZFSu29fwq4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1748879016; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=kE86r3nOWbGkCk+7FHRVNVkWlB3O+jA2NnpzK1z5q4k=; b=Ua9uyQ0SItyI65Oh8DTO3APiS12JsxJQ8ICx1+BWAtWPhNlrh0FJOyiJufQimf6pJhuLvlDTQqcPfXLim2YplAkx+xLaEtv6Ky6u8bq6CntE+lgv3SbllxRI93hvQijfa/Ngy9+wxqzNrOcv0e9JDdTMiM8wyO8k+ZneMQon2p8= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1748879016829692.7679425164453; Mon, 2 Jun 2025 08:43:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uM7Iv-0002uR-SL; Mon, 02 Jun 2025 11:42:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uM7Ik-0002tA-14; Mon, 02 Jun 2025 11:42:16 -0400 Received: from [185.176.79.56] (helo=frasgout.his.huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uM7Ih-0003HZ-V5; Mon, 02 Jun 2025 11:42:13 -0400 Received: from mail.maildlp.com (unknown [172.18.186.216]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4b9yfc5PGvz6DLQr; Mon, 2 Jun 2025 23:38:16 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id 568881401DC; Mon, 2 Jun 2025 23:42:06 +0800 (CST) Received: from A2303104131.china.huawei.com (10.203.177.241) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Mon, 2 Jun 2025 17:41:58 +0200 To: , CC: , , , , , , , , , , , , , Subject: [PATCH v3 2/6] =?UTF-8?q?hw/arm/virt-acpi-build:=20Re-arrange?= =?UTF-8?q?=C2=A0SMMUv3=20IORT=20build?= Date: Mon, 2 Jun 2025 16:41:06 +0100 Message-ID: <20250602154110.48392-3-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20250602154110.48392-1-shameerali.kolothum.thodi@huawei.com> References: <20250602154110.48392-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To frapeml500008.china.huawei.com (7.182.85.71) X-Host-Lookup-Failed: Reverse DNS lookup failed for 185.176.79.56 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1748879017910116600 Introduces=C2=A0a new struct AcpiIortSMMUv3Dev to hold all the information required for SMMUv3 IORT node and use that=C2=A0for populating the node. The current=C2=A0machine wide SMMUv3 is named as legacy SMMUv3 as we will soon add support for user-creatable SMMUv3 devices. These changes will be useful to have common code paths when we add that support. Signed-off-by: Shameer Kolothum --- hw/arm/virt-acpi-build.c | 112 +++++++++++++++++++++++++++------------ hw/arm/virt.c | 1 + include/hw/arm/virt.h | 1 + 3 files changed, 80 insertions(+), 34 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 7e8e0f0298..bd26853ef6 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -266,6 +266,28 @@ static int iort_idmap_compare(gconstpointer a, gconstp= ointer b) return idmap_a->input_base - idmap_b->input_base; } =20 +struct AcpiIortSMMUv3Dev { + int irq; + hwaddr base; + GArray *idmaps; + size_t offset; +}; +typedef struct AcpiIortSMMUv3Dev AcpiIortSMMUv3Dev; + +static void +get_smmuv3_legacy_dev(VirtMachineState *vms, void *opaque) +{ + GArray *sdev_blob =3D opaque; + AcpiIortSMMUv3Dev sdev; + + sdev.idmaps =3D g_array_new(false, true, sizeof(AcpiIortIdMapping)); + object_child_foreach_recursive(object_get_root(), + iort_host_bridges, sdev.idmaps); + sdev.base =3D vms->memmap[VIRT_SMMU].base; + sdev.irq =3D vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; + g_array_append_val(sdev_blob, sdev); +} + /* * Input Output Remapping Table (IORT) * Conforms to "IO Remapping Table System Software on ARM Platforms", @@ -274,11 +296,12 @@ static int iort_idmap_compare(gconstpointer a, gconst= pointer b) static void build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) { - int i, nb_nodes, rc_mapping_count; - size_t node_size, smmu_offset =3D 0; - AcpiIortIdMapping *idmap; + int i, j, nb_nodes, rc_mapping_count; + AcpiIortSMMUv3Dev *sdev; + size_t node_size; + int num_smmus =3D 0; uint32_t id =3D 0; - GArray *smmu_idmaps =3D g_array_new(false, true, sizeof(AcpiIortIdMapp= ing)); + GArray *smmuv3_devs =3D g_array_new(false, true, sizeof(AcpiIortSMMUv3= Dev)); GArray *its_idmaps =3D g_array_new(false, true, sizeof(AcpiIortIdMappi= ng)); =20 AcpiTable table =3D { .sig =3D "IORT", .rev =3D 3, .oem_id =3D vms->oe= m_id, @@ -286,28 +309,41 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) /* Table 2 The IORT */ acpi_table_begin(&table, table_data); =20 - if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3) { - AcpiIortIdMapping next_range =3D {0}; - - object_child_foreach_recursive(object_get_root(), - iort_host_bridges, smmu_idmaps); - - /* Sort the smmu idmap by input_base */ - g_array_sort(smmu_idmaps, iort_idmap_compare); + nb_nodes =3D 2; /* RC, ITS */ + if (vms->legacy_smmuv3_present) { + get_smmuv3_legacy_dev(vms, smmuv3_devs); + /* + * There will be only one legacy SMMUv3 as it is a machine wide on= e. + * And since it covers all the PCIe RCs in the machine, may have + * multiple SMMUv3 idmaps. Sort it by input_base. + */ + sdev =3D &g_array_index(smmuv3_devs, AcpiIortSMMUv3Dev, 0); + g_array_sort(sdev->idmaps, iort_idmap_compare); + } =20 + num_smmus =3D smmuv3_devs->len; + if (num_smmus) { + AcpiIortIdMapping next_range =3D {0}; + int smmu_map_cnt =3D 0; /* * Split the whole RIDs by mapping from RC to SMMU, * build the ID mapping from RC to ITS directly. */ - for (i =3D 0; i < smmu_idmaps->len; i++) { - idmap =3D &g_array_index(smmu_idmaps, AcpiIortIdMapping, i); - - if (next_range.input_base < idmap->input_base) { - next_range.id_count =3D idmap->input_base - next_range.inp= ut_base; - g_array_append_val(its_idmaps, next_range); + for (i =3D 0; i < num_smmus; i++) { + AcpiIortIdMapping *idmap; + sdev =3D &g_array_index(smmuv3_devs, AcpiIortSMMUv3Dev, i); + + for (j =3D 0; j < sdev->idmaps->len; j++) { + idmap =3D &g_array_index(sdev->idmaps, AcpiIortIdMapping, = j); + + if (next_range.input_base < idmap->input_base) { + next_range.id_count =3D idmap->input_base - + next_range.input_base; + g_array_append_val(its_idmaps, next_range); + } + next_range.input_base =3D idmap->input_base + idmap->id_co= unt; + smmu_map_cnt++; } - - next_range.input_base =3D idmap->input_base + idmap->id_count; } =20 /* Append the last RC -> ITS ID mapping */ @@ -316,10 +352,9 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vir= tMachineState *vms) g_array_append_val(its_idmaps, next_range); } =20 - nb_nodes =3D 3; /* RC, ITS, SMMUv3 */ - rc_mapping_count =3D smmu_idmaps->len + its_idmaps->len; + nb_nodes +=3D num_smmus; + rc_mapping_count =3D smmu_map_cnt + its_idmaps->len; } else { - nb_nodes =3D 2; /* RC, ITS */ rc_mapping_count =3D 1; } /* Number of IORT Nodes */ @@ -341,10 +376,11 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) /* GIC ITS Identifier Array */ build_append_int_noprefix(table_data, 0 /* MADT translation_id */, 4); =20 - if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3) { - int irq =3D vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; + for (i =3D 0; i < num_smmus; i++) { + sdev =3D &g_array_index(smmuv3_devs, AcpiIortSMMUv3Dev, i); + int irq =3D sdev->irq; =20 - smmu_offset =3D table_data->len - table.table_offset; + sdev->offset =3D table_data->len - table.table_offset; /* Table 9 SMMUv3 Format */ build_append_int_noprefix(table_data, 4 /* SMMUv3 */, 1); /* Type = */ node_size =3D SMMU_V3_ENTRY_SIZE + ID_MAPPING_ENTRY_SIZE; @@ -355,7 +391,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) /* Reference to ID Array */ build_append_int_noprefix(table_data, SMMU_V3_ENTRY_SIZE, 4); /* Base address */ - build_append_int_noprefix(table_data, vms->memmap[VIRT_SMMU].base,= 8); + build_append_int_noprefix(table_data, sdev->base, 8); /* Flags */ build_append_int_noprefix(table_data, 1 /* COHACC Override */, 4); build_append_int_noprefix(table_data, 0, 4); /* Reserved */ @@ -404,15 +440,19 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) build_append_int_noprefix(table_data, 0, 3); /* Reserved */ =20 /* Output Reference */ - if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3) { + if (num_smmus) { AcpiIortIdMapping *range; =20 /* translated RIDs connect to SMMUv3 node: RC -> SMMUv3 -> ITS */ - for (i =3D 0; i < smmu_idmaps->len; i++) { - range =3D &g_array_index(smmu_idmaps, AcpiIortIdMapping, i); - /* output IORT node is the smmuv3 node */ - build_iort_id_mapping(table_data, range->input_base, - range->id_count, smmu_offset); + for (i =3D 0; i < num_smmus; i++) { + sdev =3D &g_array_index(smmuv3_devs, AcpiIortSMMUv3Dev, i); + + for (j =3D 0; j < sdev->idmaps->len; j++) { + range =3D &g_array_index(sdev->idmaps, AcpiIortIdMapping, = j); + /* output IORT node is the smmuv3 node */ + build_iort_id_mapping(table_data, range->input_base, + range->id_count, sdev->offset); + } } =20 /* bypassed RIDs connect to ITS group node directly: RC -> ITS */ @@ -428,8 +468,12 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vir= tMachineState *vms) } =20 acpi_table_end(linker, &table); - g_array_free(smmu_idmaps, true); g_array_free(its_idmaps, true); + for (i =3D 0; i < num_smmus; i++) { + sdev =3D &g_array_index(smmuv3_devs, AcpiIortSMMUv3Dev, i); + g_array_free(sdev->idmaps, true); + } + g_array_free(smmuv3_devs, true); } =20 /* diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 9a6cd085a3..73bd2bd5f2 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1614,6 +1614,7 @@ static void create_pcie(VirtMachineState *vms) create_smmu(vms, vms->bus); qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map", 0x0, vms->iommu_phandle, 0x0, 0x10000); + vms->legacy_smmuv3_present =3D true; break; default: g_assert_not_reached(); diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 9a1b0f53d2..8b1404b5f6 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -174,6 +174,7 @@ struct VirtMachineState { char *oem_id; char *oem_table_id; bool ns_el2_virt_timer_irq; + bool legacy_smmuv3_present; }; =20 #define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM) --=20 2.34.1