From nobody Sat Nov 15 17:21:16 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1748879040; cv=none; d=zohomail.com; s=zohoarc; b=IOH3UJ8GnsQakz8J59fZ7JttZwLENsr1pPxVdeLiCLTjqdNbhXvwJ6Ztd/rmRSA54PtOSnONSP++cLXC4k1GzMZ1RusaCpN1t2jvWHNBg/1x9oKG2cX5vczE61HbRHpaYvmUorQGuY0RCi7gxoQh+tcARf393MKnKNClpYVpqOs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1748879040; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=ckw8CXQULUSZ3qiI/INg/rbtUjwDTPrQ/I4GH6b6Fso=; b=ebXJcsrZCvVbM6xOF9uhdnmwL0+2oSS6L7hLTBe7+pOHc16NiEEkCGq6t328WCcJHviyZPQ6hc4U2Y6WEp0ClamP+ke4Gldcg9YFPoKbYshLDVztPwIAOMvKQT8XZTGEGXBWAi0Kn84L4KQT1tzt+Je3C092wBYis+kV6rQPGr8= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1748879040487326.18838317872246; Mon, 2 Jun 2025 08:44:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uM7Im-0002sy-IX; Mon, 02 Jun 2025 11:42:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uM7Id-0002sL-WC; Mon, 02 Jun 2025 11:42:08 -0400 Received: from [185.176.79.56] (helo=frasgout.his.huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uM7Ic-0003Gx-Hm; Mon, 02 Jun 2025 11:42:07 -0400 Received: from mail.maildlp.com (unknown [172.18.186.231]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4b9yj82G4yz6HJcD; Mon, 2 Jun 2025 23:40:28 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id E63341402CB; Mon, 2 Jun 2025 23:41:55 +0800 (CST) Received: from A2303104131.china.huawei.com (10.203.177.241) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Mon, 2 Jun 2025 17:41:48 +0200 To: , CC: , , , , , , , , , , , , , Subject: [PATCH v3 1/6] hw/arm/smmuv3: Check SMMUv3 has PCIe Root Complex association Date: Mon, 2 Jun 2025 16:41:05 +0100 Message-ID: <20250602154110.48392-2-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20250602154110.48392-1-shameerali.kolothum.thodi@huawei.com> References: <20250602154110.48392-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To frapeml500008.china.huawei.com (7.182.85.71) X-Host-Lookup-Failed: Reverse DNS lookup failed for 185.176.79.56 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1748879041677116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Although this change does not affect functionality at present, it is required when we add support for user-creatable SMMUv3 devices in future patches. Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index ab67972353..7e934336c2 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -24,6 +24,7 @@ #include "hw/qdev-properties.h" #include "hw/qdev-core.h" #include "hw/pci/pci.h" +#include "hw/pci/pci_bridge.h" #include "cpu.h" #include "exec/target_page.h" #include "trace.h" @@ -1881,6 +1882,13 @@ static void smmu_realize(DeviceState *d, Error **err= p) SMMUv3Class *c =3D ARM_SMMUV3_GET_CLASS(s); SysBusDevice *dev =3D SYS_BUS_DEVICE(d); Error *local_err =3D NULL; + Object *bus; + + bus =3D object_property_get_link(OBJECT(d), "primary-bus", &error_abor= t); + if (!bus || !object_dynamic_cast(bus->parent, TYPE_PCI_HOST_BRIDGE)) { + error_setg(errp, "SMMUv3 is not attached to any PCIe Root Complex!= "); + return; + } =20 c->parent_realize(d, &local_err); if (local_err) { --=20 2.34.1 From nobody Sat Nov 15 17:21:16 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1748879017910116600 Introduces=C2=A0a new struct AcpiIortSMMUv3Dev to hold all the information required for SMMUv3 IORT node and use that=C2=A0for populating the node. The current=C2=A0machine wide SMMUv3 is named as legacy SMMUv3 as we will soon add support for user-creatable SMMUv3 devices. These changes will be useful to have common code paths when we add that support. Signed-off-by: Shameer Kolothum --- hw/arm/virt-acpi-build.c | 112 +++++++++++++++++++++++++++------------ hw/arm/virt.c | 1 + include/hw/arm/virt.h | 1 + 3 files changed, 80 insertions(+), 34 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 7e8e0f0298..bd26853ef6 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -266,6 +266,28 @@ static int iort_idmap_compare(gconstpointer a, gconstp= ointer b) return idmap_a->input_base - idmap_b->input_base; } =20 +struct AcpiIortSMMUv3Dev { + int irq; + hwaddr base; + GArray *idmaps; + size_t offset; +}; +typedef struct AcpiIortSMMUv3Dev AcpiIortSMMUv3Dev; + +static void +get_smmuv3_legacy_dev(VirtMachineState *vms, void *opaque) +{ + GArray *sdev_blob =3D opaque; + AcpiIortSMMUv3Dev sdev; + + sdev.idmaps =3D g_array_new(false, true, sizeof(AcpiIortIdMapping)); + object_child_foreach_recursive(object_get_root(), + iort_host_bridges, sdev.idmaps); + sdev.base =3D vms->memmap[VIRT_SMMU].base; + sdev.irq =3D vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; + g_array_append_val(sdev_blob, sdev); +} + /* * Input Output Remapping Table (IORT) * Conforms to "IO Remapping Table System Software on ARM Platforms", @@ -274,11 +296,12 @@ static int iort_idmap_compare(gconstpointer a, gconst= pointer b) static void build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) { - int i, nb_nodes, rc_mapping_count; - size_t node_size, smmu_offset =3D 0; - AcpiIortIdMapping *idmap; + int i, j, nb_nodes, rc_mapping_count; + AcpiIortSMMUv3Dev *sdev; + size_t node_size; + int num_smmus =3D 0; uint32_t id =3D 0; - GArray *smmu_idmaps =3D g_array_new(false, true, sizeof(AcpiIortIdMapp= ing)); + GArray *smmuv3_devs =3D g_array_new(false, true, sizeof(AcpiIortSMMUv3= Dev)); GArray *its_idmaps =3D g_array_new(false, true, sizeof(AcpiIortIdMappi= ng)); =20 AcpiTable table =3D { .sig =3D "IORT", .rev =3D 3, .oem_id =3D vms->oe= m_id, @@ -286,28 +309,41 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) /* Table 2 The IORT */ acpi_table_begin(&table, table_data); =20 - if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3) { - AcpiIortIdMapping next_range =3D {0}; - - object_child_foreach_recursive(object_get_root(), - iort_host_bridges, smmu_idmaps); - - /* Sort the smmu idmap by input_base */ - g_array_sort(smmu_idmaps, iort_idmap_compare); + nb_nodes =3D 2; /* RC, ITS */ + if (vms->legacy_smmuv3_present) { + get_smmuv3_legacy_dev(vms, smmuv3_devs); + /* + * There will be only one legacy SMMUv3 as it is a machine wide on= e. + * And since it covers all the PCIe RCs in the machine, may have + * multiple SMMUv3 idmaps. Sort it by input_base. + */ + sdev =3D &g_array_index(smmuv3_devs, AcpiIortSMMUv3Dev, 0); + g_array_sort(sdev->idmaps, iort_idmap_compare); + } =20 + num_smmus =3D smmuv3_devs->len; + if (num_smmus) { + AcpiIortIdMapping next_range =3D {0}; + int smmu_map_cnt =3D 0; /* * Split the whole RIDs by mapping from RC to SMMU, * build the ID mapping from RC to ITS directly. */ - for (i =3D 0; i < smmu_idmaps->len; i++) { - idmap =3D &g_array_index(smmu_idmaps, AcpiIortIdMapping, i); - - if (next_range.input_base < idmap->input_base) { - next_range.id_count =3D idmap->input_base - next_range.inp= ut_base; - g_array_append_val(its_idmaps, next_range); + for (i =3D 0; i < num_smmus; i++) { + AcpiIortIdMapping *idmap; + sdev =3D &g_array_index(smmuv3_devs, AcpiIortSMMUv3Dev, i); + + for (j =3D 0; j < sdev->idmaps->len; j++) { + idmap =3D &g_array_index(sdev->idmaps, AcpiIortIdMapping, = j); + + if (next_range.input_base < idmap->input_base) { + next_range.id_count =3D idmap->input_base - + next_range.input_base; + g_array_append_val(its_idmaps, next_range); + } + next_range.input_base =3D idmap->input_base + idmap->id_co= unt; + smmu_map_cnt++; } - - next_range.input_base =3D idmap->input_base + idmap->id_count; } =20 /* Append the last RC -> ITS ID mapping */ @@ -316,10 +352,9 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vir= tMachineState *vms) g_array_append_val(its_idmaps, next_range); } =20 - nb_nodes =3D 3; /* RC, ITS, SMMUv3 */ - rc_mapping_count =3D smmu_idmaps->len + its_idmaps->len; + nb_nodes +=3D num_smmus; + rc_mapping_count =3D smmu_map_cnt + its_idmaps->len; } else { - nb_nodes =3D 2; /* RC, ITS */ rc_mapping_count =3D 1; } /* Number of IORT Nodes */ @@ -341,10 +376,11 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) /* GIC ITS Identifier Array */ build_append_int_noprefix(table_data, 0 /* MADT translation_id */, 4); =20 - if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3) { - int irq =3D vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; + for (i =3D 0; i < num_smmus; i++) { + sdev =3D &g_array_index(smmuv3_devs, AcpiIortSMMUv3Dev, i); + int irq =3D sdev->irq; =20 - smmu_offset =3D table_data->len - table.table_offset; + sdev->offset =3D table_data->len - table.table_offset; /* Table 9 SMMUv3 Format */ build_append_int_noprefix(table_data, 4 /* SMMUv3 */, 1); /* Type = */ node_size =3D SMMU_V3_ENTRY_SIZE + ID_MAPPING_ENTRY_SIZE; @@ -355,7 +391,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) /* Reference to ID Array */ build_append_int_noprefix(table_data, SMMU_V3_ENTRY_SIZE, 4); /* Base address */ - build_append_int_noprefix(table_data, vms->memmap[VIRT_SMMU].base,= 8); + build_append_int_noprefix(table_data, sdev->base, 8); /* Flags */ build_append_int_noprefix(table_data, 1 /* COHACC Override */, 4); build_append_int_noprefix(table_data, 0, 4); /* Reserved */ @@ -404,15 +440,19 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) build_append_int_noprefix(table_data, 0, 3); /* Reserved */ =20 /* Output Reference */ - if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3) { + if (num_smmus) { AcpiIortIdMapping *range; =20 /* translated RIDs connect to SMMUv3 node: RC -> SMMUv3 -> ITS */ - for (i =3D 0; i < smmu_idmaps->len; i++) { - range =3D &g_array_index(smmu_idmaps, AcpiIortIdMapping, i); - /* output IORT node is the smmuv3 node */ - build_iort_id_mapping(table_data, range->input_base, - range->id_count, smmu_offset); + for (i =3D 0; i < num_smmus; i++) { + sdev =3D &g_array_index(smmuv3_devs, AcpiIortSMMUv3Dev, i); + + for (j =3D 0; j < sdev->idmaps->len; j++) { + range =3D &g_array_index(sdev->idmaps, AcpiIortIdMapping, = j); + /* output IORT node is the smmuv3 node */ + build_iort_id_mapping(table_data, range->input_base, + range->id_count, sdev->offset); + } } =20 /* bypassed RIDs connect to ITS group node directly: RC -> ITS */ @@ -428,8 +468,12 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vir= tMachineState *vms) } =20 acpi_table_end(linker, &table); - g_array_free(smmu_idmaps, true); g_array_free(its_idmaps, true); + for (i =3D 0; i < num_smmus; i++) { + sdev =3D &g_array_index(smmuv3_devs, AcpiIortSMMUv3Dev, i); + g_array_free(sdev->idmaps, true); + } + g_array_free(smmuv3_devs, true); } =20 /* diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 9a6cd085a3..73bd2bd5f2 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1614,6 +1614,7 @@ static void create_pcie(VirtMachineState *vms) create_smmu(vms, vms->bus); qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map", 0x0, vms->iommu_phandle, 0x0, 0x10000); + vms->legacy_smmuv3_present =3D true; break; default: g_assert_not_reached(); diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 9a1b0f53d2..8b1404b5f6 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -174,6 +174,7 @@ struct VirtMachineState { char *oem_id; char *oem_table_id; bool ns_el2_virt_timer_irq; + bool legacy_smmuv3_present; }; =20 #define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM) --=20 2.34.1 From nobody Sat Nov 15 17:21:16 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1748879020; cv=none; d=zohomail.com; s=zohoarc; b=kN09EEsYv5smk646WjviTHyDlknzl3EpgXx1suq/1R641PFqlS5re5VRAlfR6DouRnPNtMYKIIVjYrTHmGaAMnaNX1FQeYZqI48uaDRwcwb+gJui2Q9UMyKtgwp6sc8XHCXZCvtuo4XnJIoU9C9/+ks2fjA1E21NnrNNRdzfKQs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1748879020; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=hb22Q56Rb3nhYwouoq9bmZ0y2AbXKSGVo9PS0aKf0Ho=; b=hzbkPmC6im0YMh8mIvRMUr30AN7nsPMEqdYzj1YsXU1gO24YWh7IVnACZ7Z5OMyiS1xW9GC8N1nlWHnXWYc2fqd1R85QQzeXhmUjziP8uf/cKccMPDHK6DLFxVRCz4sETA3mgV3GVbCXMMdL+rIvkYyZwqSCtw4p5jrjvkx6qcQ= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1748879020844615.4367645848771; Mon, 2 Jun 2025 08:43:40 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uM7J5-000331-2E; Mon, 02 Jun 2025 11:42:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uM7J0-00030z-4h; Mon, 02 Jun 2025 11:42:30 -0400 Received: from [185.176.79.56] (helo=frasgout.his.huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uM7Iy-0003IX-23; Mon, 02 Jun 2025 11:42:29 -0400 Received: from mail.maildlp.com (unknown [172.18.186.231]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4b9yfs4wPCz6DKxd; Mon, 2 Jun 2025 23:38:29 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id 4C76D14027A; Mon, 2 Jun 2025 23:42:19 +0800 (CST) Received: from A2303104131.china.huawei.com (10.203.177.241) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Mon, 2 Jun 2025 17:42:11 +0200 To: , CC: , , , , , , , , , , , , , Subject: [PATCH v3 3/6] hw/arm/virt-acpi-build: Update IORT for multiple smmuv3 devices Date: Mon, 2 Jun 2025 16:41:07 +0100 Message-ID: <20250602154110.48392-4-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20250602154110.48392-1-shameerali.kolothum.thodi@huawei.com> References: <20250602154110.48392-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To frapeml500008.china.huawei.com (7.182.85.71) X-Host-Lookup-Failed: Reverse DNS lookup failed for 185.176.79.56 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1748879021381116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" With the soon to be introduced user-creatable SMMUv3 devices for virt, it is possible to have multiple SMMUv3 devices associated with different PCIe root complexes. Update IORT nodes accordingly. Signed-off-by: Shameer Kolothum --- hw/arm/virt-acpi-build.c | 54 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index bd26853ef6..b4ff71b8b7 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -43,6 +43,7 @@ #include "hw/acpi/generic_event_device.h" #include "hw/acpi/tpm.h" #include "hw/acpi/hmat.h" +#include "hw/arm/smmuv3.h" #include "hw/pci/pcie_host.h" #include "hw/pci/pci.h" #include "hw/pci/pci_bus.h" @@ -288,6 +289,54 @@ get_smmuv3_legacy_dev(VirtMachineState *vms, void *opa= que) g_array_append_val(sdev_blob, sdev); } =20 +static int smmuv3_dev_idmap_compare(gconstpointer a, gconstpointer b) +{ + AcpiIortSMMUv3Dev *sdev_a =3D (AcpiIortSMMUv3Dev *)a; + AcpiIortSMMUv3Dev *sdev_b =3D (AcpiIortSMMUv3Dev *)b; + AcpiIortIdMapping *map_a =3D &g_array_index(sdev_a->idmaps, + AcpiIortIdMapping, 0); + AcpiIortIdMapping *map_b =3D &g_array_index(sdev_b->idmaps, + AcpiIortIdMapping, 0); + return map_a->input_base - map_b->input_base; +} + +static int get_smmuv3_devices(Object *obj, void *opaque) +{ + VirtMachineState *vms =3D VIRT_MACHINE(qdev_get_machine()); + GArray *sdev_blob =3D opaque; + AcpiIortIdMapping idmap; + PlatformBusDevice *pbus; + AcpiIortSMMUv3Dev sdev; + int min_bus, max_bus; + SysBusDevice *sbdev; + PCIBus *bus; + + if (!object_dynamic_cast(obj, TYPE_ARM_SMMUV3)) { + return 0; + } + + bus =3D PCI_BUS(object_property_get_link(obj, "primary-bus", &error_ab= ort)); + if (!bus) { + return 0; + } + + pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); + sbdev =3D SYS_BUS_DEVICE(obj); + sdev.base =3D platform_bus_get_mmio_addr(pbus, sbdev, 0); + sdev.base +=3D vms->memmap[VIRT_PLATFORM_BUS].base; + sdev.irq =3D platform_bus_get_irqn(pbus, sbdev, 0); + sdev.irq +=3D vms->irqmap[VIRT_PLATFORM_BUS]; + sdev.irq +=3D ARM_SPI_BASE; + + pci_bus_range(bus, &min_bus, &max_bus); + sdev.idmaps =3D g_array_new(false, true, sizeof(AcpiIortIdMapping)); + idmap.input_base =3D min_bus << 8, + idmap.id_count =3D (max_bus - min_bus + 1) << 8, + g_array_append_val(sdev.idmaps, idmap); + g_array_append_val(sdev_blob, sdev); + return 0; +} + /* * Input Output Remapping Table (IORT) * Conforms to "IO Remapping Table System Software on ARM Platforms", @@ -319,6 +368,11 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vir= tMachineState *vms) */ sdev =3D &g_array_index(smmuv3_devs, AcpiIortSMMUv3Dev, 0); g_array_sort(sdev->idmaps, iort_idmap_compare); + } else { + object_child_foreach_recursive(object_get_root(), + get_smmuv3_devices, smmuv3_devs); + /* Sort the smmuv3 devices(if any) by smmu idmap input_base */ + g_array_sort(smmuv3_devs, smmuv3_dev_idmap_compare); } =20 num_smmus =3D smmuv3_devs->len; --=20 2.34.1 From nobody Sat Nov 15 17:21:16 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1748879046; 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Mon, 2 Jun 2025 17:42:22 +0200 To: , CC: , , , , , , , , , , , , , Subject: [PATCH v3 4/6] hw/arm/virt: Factor out common SMMUV3 dt bindings code Date: Mon, 2 Jun 2025 16:41:08 +0100 Message-ID: <20250602154110.48392-5-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20250602154110.48392-1-shameerali.kolothum.thodi@huawei.com> References: <20250602154110.48392-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To frapeml500008.china.huawei.com (7.182.85.71) X-Host-Lookup-Failed: Reverse DNS lookup failed for 185.176.79.56 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1748879047623116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" No functional changes intended. This will be useful when we add support for user-creatable smmuv3 device. Reviewed-by: Nicolin Chen Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum --- hw/arm/virt.c | 54 +++++++++++++++++++++++++++------------------------ 1 file changed, 29 insertions(+), 25 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 73bd2bd5f2..71b923f786 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1412,19 +1412,43 @@ static void create_pcie_irq_map(const MachineState = *ms, 0x7 /* PCI irq */); } =20 +static void create_smmuv3_dt_bindings(const VirtMachineState *vms, hwaddr = base, + hwaddr size, int irq) +{ + char *node; + const char compat[] =3D "arm,smmu-v3"; + const char irq_names[] =3D "eventq\0priq\0cmdq-sync\0gerror"; + MachineState *ms =3D MACHINE(vms); + + node =3D g_strdup_printf("/smmuv3@%" PRIx64, base); + qemu_fdt_add_subnode(ms->fdt, node); + qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); + qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size); + + qemu_fdt_setprop_cells(ms->fdt, node, "interrupts", + GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, + GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, + GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, + GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); + + qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names, + sizeof(irq_names)); + + qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0); + qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); + qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); + g_free(node); +} + static void create_smmu(const VirtMachineState *vms, PCIBus *bus) { VirtMachineClass *vmc =3D VIRT_MACHINE_GET_CLASS(vms); - char *node; - const char compat[] =3D "arm,smmu-v3"; int irq =3D vms->irqmap[VIRT_SMMU]; int i; hwaddr base =3D vms->memmap[VIRT_SMMU].base; hwaddr size =3D vms->memmap[VIRT_SMMU].size; - const char irq_names[] =3D "eventq\0priq\0cmdq-sync\0gerror"; DeviceState *dev; - MachineState *ms =3D MACHINE(vms); =20 if (vms->iommu !=3D VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { return; @@ -1443,27 +1467,7 @@ static void create_smmu(const VirtMachineState *vms, sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, qdev_get_gpio_in(vms->gic, irq + i)); } - - node =3D g_strdup_printf("/smmuv3@%" PRIx64, base); - qemu_fdt_add_subnode(ms->fdt, node); - qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); - qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size); - - qemu_fdt_setprop_cells(ms->fdt, node, "interrupts", - GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, - GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, - GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, - GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); - - qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names, - sizeof(irq_names)); - - qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0); - - qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); - - qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); - g_free(node); + create_smmuv3_dt_bindings(vms, base, size, irq); } =20 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms) --=20 2.34.1 From nobody Sat Nov 15 17:21:16 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Nicolin Chen This is useful as the subsequent support for new SMMUv3 dev will also use the same. Signed-off-by: Nicolin Chen Reviewed-by: Donald Dutile Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum --- hw/arm/virt.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 71b923f786..eeace4754d 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -146,6 +146,9 @@ static void arm_virt_compat_set(MachineClass *mc) #define LEGACY_RAMLIMIT_GB 255 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB) =20 +/* MMIO region size for SMMUv3 */ +#define SMMU_IO_LEN 0x20000 + /* Addresses and sizes of our components. * 0..128MB is space for a flash device so we can run bootrom code such as= UEFI. * 128MB..256MB is used for miscellaneous device I/O. @@ -177,7 +180,7 @@ static const MemMapEntry base_memmap[] =3D { [VIRT_FW_CFG] =3D { 0x09020000, 0x00000018 }, [VIRT_GPIO] =3D { 0x09030000, 0x00001000 }, [VIRT_UART1] =3D { 0x09040000, 0x00001000 }, - [VIRT_SMMU] =3D { 0x09050000, 0x00020000 }, + [VIRT_SMMU] =3D { 0x09050000, SMMU_IO_LEN }, [VIRT_PCDIMM_ACPI] =3D { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, [VIRT_ACPI_GED] =3D { 0x09080000, ACPI_GED_EVT_SEL_LEN }, [VIRT_NVDIMM_ACPI] =3D { 0x09090000, NVDIMM_ACPI_IO_LEN}, @@ -1447,7 +1450,6 @@ static void create_smmu(const VirtMachineState *vms, int irq =3D vms->irqmap[VIRT_SMMU]; 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Mon, 2 Jun 2025 17:42:44 +0200 To: , CC: , , , , , , , , , , , , , Subject: [PATCH v3 6/6] hw/arm/virt: Allow user-creatable SMMUv3 dev instantiation Date: Mon, 2 Jun 2025 16:41:10 +0100 Message-ID: <20250602154110.48392-7-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20250602154110.48392-1-shameerali.kolothum.thodi@huawei.com> References: <20250602154110.48392-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To frapeml500008.china.huawei.com (7.182.85.71) X-Host-Lookup-Failed: Reverse DNS lookup failed for 185.176.79.56 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1748879033781116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Allow cold-plug of smmuv3 device to virt if there is no machine wide legacy smmuv3 or a virtio-iommu is specified. Device tree support for new smmuv3 dev is limited to the case where it is associated with the default pcie.0 RC. Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3.c | 2 ++ hw/arm/virt.c | 50 ++++++++++++++++++++++++++++++++++++++++++++ hw/core/sysbus-fdt.c | 3 +++ 3 files changed, 55 insertions(+) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 7e934336c2..d1f66dcd8f 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -2004,6 +2004,8 @@ static void smmuv3_class_init(ObjectClass *klass, con= st void *data) device_class_set_parent_realize(dc, smmu_realize, &c->parent_realize); device_class_set_props(dc, smmuv3_properties); + dc->hotpluggable =3D false; + dc->user_creatable =3D true; } =20 static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, diff --git a/hw/arm/virt.c b/hw/arm/virt.c index eeace4754d..04bc940fc3 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -56,6 +56,7 @@ #include "qemu/cutils.h" #include "qemu/error-report.h" #include "qemu/module.h" +#include "hw/pci/pci_bus.h" #include "hw/pci-host/gpex.h" #include "hw/virtio/virtio-pci.h" #include "hw/core/sysbus-fdt.h" @@ -1443,6 +1444,28 @@ static void create_smmuv3_dt_bindings(const VirtMach= ineState *vms, hwaddr base, g_free(node); } =20 +static void create_smmuv3_dev_dtb(VirtMachineState *vms, + DeviceState *dev, PCIBus *bus) +{ + PlatformBusDevice *pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); + SysBusDevice *sbdev =3D SYS_BUS_DEVICE(dev); + int irq =3D platform_bus_get_irqn(pbus, sbdev, 0); + hwaddr base =3D platform_bus_get_mmio_addr(pbus, sbdev, 0); + MachineState *ms =3D MACHINE(vms); + + if (strcmp("pcie.0", bus->qbus.name)) { + warn_report("SMMUv3 device only supported with pcie.0 for DT"); + return; + } + base +=3D vms->memmap[VIRT_PLATFORM_BUS].base; + irq +=3D vms->irqmap[VIRT_PLATFORM_BUS]; + + vms->iommu_phandle =3D qemu_fdt_alloc_phandle(ms->fdt); + create_smmuv3_dt_bindings(vms, base, SMMU_IO_LEN, irq); + qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map", + 0x0, vms->iommu_phandle, 0x0, 0x10000); +} + static void create_smmu(const VirtMachineState *vms, PCIBus *bus) { @@ -2931,6 +2954,13 @@ static void virt_machine_device_pre_plug_cb(HotplugH= andler *hotplug_dev, qlist_append_str(reserved_regions, resv_prop_str); qdev_prop_set_array(dev, "reserved-regions", reserved_regions); g_free(resv_prop_str); + } else if (object_dynamic_cast(OBJECT(dev), TYPE_ARM_SMMUV3)) { + if (vms->legacy_smmuv3_present || vms->iommu =3D=3D VIRT_IOMMU_VIR= TIO) { + error_setg(errp, "virt machine already has %s set. " + "Doesn't support incompatible iommus", + (vms->legacy_smmuv3_present) ? + "iommu=3Dsmmuv3" : "virtio-iommu"); + } } } =20 @@ -2954,6 +2984,25 @@ static void virt_machine_device_plug_cb(HotplugHandl= er *hotplug_dev, virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); } =20 + if (object_dynamic_cast(OBJECT(dev), TYPE_ARM_SMMUV3)) { + if (!vms->legacy_smmuv3_present && vms->platform_bus_dev) { + PCIBus *bus; + + bus =3D PCI_BUS(object_property_get_link(OBJECT(dev), "primary= -bus", + &error_abort)); + if (pci_bus_bypass_iommu(bus)) { + error_setg(errp, "Bypass option cannot be set for SMMUv3 " + "associated PCIe RC"); + return; + } + + create_smmuv3_dev_dtb(vms, dev, bus); + if (vms->iommu !=3D VIRT_IOMMU_SMMUV3) { + vms->iommu =3D VIRT_IOMMU_SMMUV3; + } + } + } + if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { PCIDevice *pdev =3D PCI_DEVICE(dev); =20 @@ -3156,6 +3205,7 @@ static void virt_machine_class_init(ObjectClass *oc, = const void *data) machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); machine_class_allow_dynamic_sysbus_dev(mc, TYPE_UEFI_VARS_SYSBUS); + machine_class_allow_dynamic_sysbus_dev(mc, TYPE_ARM_SMMUV3); #ifdef CONFIG_TPM machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); #endif diff --git a/hw/core/sysbus-fdt.c b/hw/core/sysbus-fdt.c index c339a27875..e80776080b 100644 --- a/hw/core/sysbus-fdt.c +++ b/hw/core/sysbus-fdt.c @@ -31,6 +31,7 @@ #include "qemu/error-report.h" #include "system/device_tree.h" #include "system/tpm.h" +#include "hw/arm/smmuv3.h" #include "hw/platform-bus.h" #include "hw/vfio/vfio-platform.h" #include "hw/vfio/vfio-calxeda-xgmac.h" @@ -518,6 +519,8 @@ static const BindingEntry bindings[] =3D { #ifdef CONFIG_TPM TYPE_BINDING(TYPE_TPM_TIS_SYSBUS, add_tpm_tis_fdt_node), #endif + /* No generic DT support for smmuv3 dev. Support added for arm virt on= ly */ + TYPE_BINDING(TYPE_ARM_SMMUV3, no_fdt_node), TYPE_BINDING(TYPE_RAMFB_DEVICE, no_fdt_node), TYPE_BINDING(TYPE_UEFI_VARS_SYSBUS, add_uefi_vars_node), TYPE_BINDING("", NULL), /* last element */ --=20 2.34.1