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Mon, 2 Jun 2025 14:00:43 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout4.samsung.com 20250602160249epoutp04df86d71da88b2c6af361422b5d246cd1~FRT_bk-n52225722257epoutp04r DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1748880169; bh=KrYuxyakbnI0aUfKV8KahEPEuvW90FgrJ3GbYGPxDR8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kUDtR3THaBC4NJE0/6pNiN/jRpdMQ/5TvZ7OCB8xtcJ43gKJuZQnYKLrgEDNoRrtB tOhlKlUTBVjJG6wYeQkXyBTUrAThBrRayx20RLI1sUSQZB4e8oL4T0A1J9FYaGGyvY IUjZNDsjTd7GUc1kFnFe0vQ4p/BTaiqs9DYHY2iM= From: Arpit Kumar To: qemu-devel@nongnu.org Cc: gost.dev@samsung.com, linux-cxl@vger.kernel.org, nifan.cxl@gmail.com, dave@stgolabs.net, vishak.g@samsung.com, krish.reddy@samsung.com, a.manzanares@samsung.com, alok.rathore@samsung.com, Arpit Kumar Subject: [PATCH 3/3] hw/cxl: Add Physical Port Control (Opcode 5102h) Date: Mon, 2 Jun 2025 19:29:42 +0530 Message-Id: <20250602135942.2773823-4-arpit1.kumar@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250602135942.2773823-1-arpit1.kumar@samsung.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250602140045epcas5p2445a99b249ba9588af027d59b0c8bd35 X-Msg-Generator: CA Content-Type: text/plain; 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Signed-off-by: Arpit Kumar --- hw/cxl/cxl-mailbox-utils.c | 128 ++++++++++++++++++++++++++++++++++++ include/hw/cxl/cxl_device.h | 8 +++ 2 files changed, 136 insertions(+) diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index b2fa79a721..4f09692713 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -118,12 +118,16 @@ enum { PHYSICAL_SWITCH =3D 0x51, #define IDENTIFY_SWITCH_DEVICE 0x0 #define GET_PHYSICAL_PORT_STATE 0x1 + #define PHYSICAL_PORT_CONTROL 0X2 TUNNEL =3D 0x53, #define MANAGEMENT_COMMAND 0x0 MHD =3D 0x55, #define GET_MHD_INFO 0x0 }; =20 +/* Assert - Deassert PERST */ +#define ASSERT_WAIT_TIME_MS 100 + /* link state flags */ #define LINK_STATE_FLAG_LANE_REVERSED (1 << 0) #define LINK_STATE_FLAG_PERST_ASSERTED (1 << 1) @@ -662,6 +666,114 @@ static CXLRetCode cmd_get_physical_port_state(const s= truct cxl_cmd *cmd, return CXL_MBOX_SUCCESS; } =20 +static struct PCIDevice *cxl_find_port_dev(uint8_t ppb_id, PCIBus *bus) +{ + PCIDevice *d; + int devfn; + + for (devfn =3D 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { + d =3D bus->devices[devfn]; + if (d) { + if (object_dynamic_cast(OBJECT(d), TYPE_CXL_DSP)) { + uint8_t port =3D PCIE_PORT(d)->port; + if (port =3D=3D ppb_id) { + return d; + } + } + } + } + return NULL; +} + +static CXLRetCode deassert_PERST(Object *obj, ResetType type, uint8_t pn, = CXLCCI *cci) +{ + ResettableClass *rc =3D RESETTABLE_GET_CLASS(obj); + ResettableState *s =3D rc->get_state(obj); + + if (cci->pports.perst[pn].issued_assert_PERST) { + if (cci->pports.perst[pn].asrt_time =3D=3D -1 && !s->hold_phase_pe= nding) { + qemu_mutex_lock(&cci->pports.perst[pn].lock); + resettable_release_reset(obj, type); + cci->pports.perst[pn].issued_assert_PERST =3D false; + cci->pports.pport_info[pn].link_state_flags &=3D + ~LINK_STATE_FLAG_PERST_ASSERTED; + cci->pports.perst[pn].asrt_time =3D ASSERT_WAIT_TIME_MS; + qemu_mutex_unlock(&cci->pports.perst[pn].lock); + } else { + return CXL_MBOX_INTERNAL_ERROR; + } + } else { + return CXL_MBOX_INTERNAL_ERROR; + } + return CXL_MBOX_SUCCESS; +} + +static CXLRetCode assert_PERST(Object *obj, ResetType type, uint8_t pn, CX= LCCI *cci) +{ + ResettableClass *rc =3D RESETTABLE_GET_CLASS(obj); + ResettableState *s =3D rc->get_state(obj); + + if (cci->pports.perst[pn].issued_assert_PERST || s->exit_phase_in_prog= ress) { + return CXL_MBOX_INTERNAL_ERROR; + } + + qemu_mutex_lock(&cci->pports.perst[pn].lock); + cci->pports.perst[pn].issued_assert_PERST =3D true; + cci->pports.pport_info[pn].link_state_flags |=3D + LINK_STATE_FLAG_PERST_ASSERTED; + resettable_assert_reset(obj, type); + qemu_mutex_unlock(&cci->pports.perst[pn].lock); + + /* holding reset phase for 100ms */ + while (cci->pports.perst[pn].asrt_time--) { + usleep(1000); + } + return CXL_MBOX_SUCCESS; +} + +/*CXL r3.2 Section 7.6.7.1.3: Get Physical Port Control (Opcode 5102h)*/ +static CXLRetCode cmd_physical_port_control(const struct cxl_cmd *cmd, + uint8_t *payload_in, + size_t len_in, + uint8_t *payload_out, + size_t *len_out, + CXLCCI *cci) +{ + PCIBus *bus =3D &PCI_BRIDGE(cci->d)->sec_bus; + PCIDevice *dev; + struct cxl_fmapi_get_physical_port_control_req_pl { + uint8_t PPB_ID; + uint8_t Ports_Op; + } QEMU_PACKED *in; + + in =3D (struct cxl_fmapi_get_physical_port_control_req_pl *)payload_in; + + if (len_in < sizeof(*in)) { + return CXL_MBOX_INVALID_PAYLOAD_LENGTH; + } + + uint8_t pn =3D in->PPB_ID; + dev =3D cxl_find_port_dev(pn, bus); + if (!dev) { + return CXL_MBOX_INTERNAL_ERROR; + } + + switch (in->Ports_Op) { + case 0: + assert_PERST(OBJECT(&dev->qdev), RESET_TYPE_COLD, pn, cci); + break; + case 1: + deassert_PERST(OBJECT(&dev->qdev), RESET_TYPE_COLD, pn, cci); + break; + case 2: + device_cold_reset(&dev->qdev); + break; + default: + return CXL_MBOX_INVALID_INPUT; + } + return CXL_MBOX_SUCCESS; +} + /* CXL r3.1 Section 8.2.9.1.2: Background Operation Status (Opcode 0002h) = */ static CXLRetCode cmd_infostat_bg_op_sts(const struct cxl_cmd *cmd, uint8_t *payload_in, @@ -3637,6 +3749,9 @@ void cxl_init_cci(CXLCCI *cci, size_t payload_max) void cxl_destroy_cci(CXLCCI *cci) { qemu_mutex_destroy(&cci->bg.lock); + for (int i =3D 0; i < PCI_DEVFN_MAX; i++) { + qemu_mutex_destroy(&cci->pports.perst[i].lock); + } cci->initialized =3D false; } =20 @@ -3866,6 +3981,8 @@ static const struct cxl_cmd cxl_cmd_set_usp_mctp[256]= [256] =3D { cmd_identify_switch_device, 0, 0 }, [PHYSICAL_SWITCH][GET_PHYSICAL_PORT_STATE] =3D { "SWITCH_PHYSICAL_PORT= _STATS", cmd_get_physical_port_state, ~0, 0 }, + [PHYSICAL_SWITCH][PHYSICAL_PORT_CONTROL] =3D { "SWITCH_PHYSICAL_PORT_C= ONTROL", + cmd_physical_port_control, 2, 0 }, [TUNNEL][MANAGEMENT_COMMAND] =3D { "TUNNEL_MANAGEMENT_COMMAND", cmd_tunnel_management_cmd, ~0, 0 }, }; @@ -3878,4 +3995,15 @@ void cxl_initialize_usp_mctpcci(CXLCCI *cci, DeviceS= tate *d, DeviceState *intf, cci->intf =3D intf; cxl_init_cci(cci, payload_max); cxl_set_phy_port_info(cci); /* store port info */ + /* physical port control */ + for (int i =3D 0; i < PCI_DEVFN_MAX; i++) { + qemu_mutex_init(&cci->pports.perst[i].lock); + cci->pports.perst[i].issued_assert_PERST =3D false; + /* Assert PERST involves physical port to be in + * hold reset phase for minimum 100ms. No other calls + * are entertained until Deassert PERST command. + * https://patchwork.ozlabs.org/project/linux-pci/patch/2019052319= 4409.17718-1-niklas.cassel@linaro.org/#2178369 + */ + cci->pports.perst[i].asrt_time =3D ASSERT_WAIT_TIME_MS; + } } diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index 9eb128a1e8..f877d60b39 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -146,10 +146,18 @@ struct cxl_phy_port_info { uint8_t supported_ld_count; } QEMU_PACKED; =20 +/* assert-deassert PERST */ +struct pperst { + bool issued_assert_PERST; + int asrt_time; + QemuMutex lock; +}; + struct phy_port { uint8_t num_ports; uint8_t active_port_bitmask[0x20]; struct cxl_phy_port_info pport_info[PCI_DEVFN_MAX]; + struct pperst perst[PCI_DEVFN_MAX]; }; =20 /* CXL r3.1 Table 8-34: Command Return Codes */ --=20 2.34.1