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Mon, 2 Jun 2025 14:00:17 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout3.samsung.com 20250602160233epoutp0337faecf7613a258d4f8d38b6f5d4d0b5~FRTu7zQrO2181921819epoutp03G DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1748880153; bh=gNt1A+G1hcdy1aQffIAfDZUX8n3iMKGTaux7QVLHRYE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VllU8F+OSZVA+ORS9YvDRLebNGKcWGU7wVT4RXchyDXRjf1Bg/g+wBW5cgqkieT1Y DnSGCoMI3tSy2K4M0aaTWaScJkIIEwmnQUpnkRweMK3PIaKqg3HMDL/2RQ2tVjzIum Hx3eWS3suxjVW8FIcTlLF979Yx+NNzM98cZ6aBw0= From: Arpit Kumar To: qemu-devel@nongnu.org Cc: gost.dev@samsung.com, linux-cxl@vger.kernel.org, nifan.cxl@gmail.com, dave@stgolabs.net, vishak.g@samsung.com, krish.reddy@samsung.com, a.manzanares@samsung.com, alok.rathore@samsung.com, Arpit Kumar Subject: [PATCH 1/3] hw/cxl: Storing physical ports info during enumeration Date: Mon, 2 Jun 2025 19:29:40 +0530 Message-Id: <20250602135942.2773823-2-arpit1.kumar@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250602135942.2773823-1-arpit1.kumar@samsung.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250602140018epcas5p2de38473dfcc0369193dd826c6e0e3fac X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250602140018epcas5p2de38473dfcc0369193dd826c6e0e3fac References: <20250602135942.2773823-1-arpit1.kumar@samsung.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=203.254.224.33; envelope-from=arpit1.kumar@samsung.com; helo=mailout3.samsung.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.015, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @samsung.com) X-ZM-MESSAGEID: 1748880214005116600 Physical ports info is stored for both mailbox cci & mctp based cci type as per spec CXL r3.2 Table 8-230: Physical Switch Signed-off-by: Arpit Kumar --- hw/cxl/cxl-mailbox-utils.c | 166 ++++++++++++++++++++++++++++++++++++ include/hw/cxl/cxl_device.h | 28 ++++++ 2 files changed, 194 insertions(+) diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index a02d130926..680055c6c0 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -124,6 +124,64 @@ enum { #define GET_MHD_INFO 0x0 }; =20 +/* link state flags */ +#define LINK_STATE_FLAG_LANE_REVERSED (1 << 0) +#define LINK_STATE_FLAG_PERST_ASSERTED (1 << 1) +#define LINK_STATE_FLAG_PRSNT (1 << 2) +#define LINK_STATE_FLAG_POWER_OFF (1 << 3) + +/* physical port control info - CXL r3.2 table 7-19 */ +typedef enum { + PORT_DISABLED =3D 0, + BIND_IN_PROGRESS =3D 1, + UNBIND_IN_PROGRESS =3D 2, + DSP =3D 3, + USP =3D 4, + FABRIC_PORT =3D 5, + INVALID_PORT_ID =3D 15 +} current_port_config_state; + +typedef enum { + NOT_CXL_OR_DISCONNECTED =3D 0x00, + RCD_MODE =3D 0x01, + CXL_68B_FLIT_AND_VH_MODE =3D 0x02, + STANDARD_256B_FLIT_MODE =3D 0x03, + CXL_LATENCY_OPTIMIZED_256B_FLIT_MODE =3D 0x04, + PBR_MODE =3D 0x05 +} connected_device_mode; + +typedef enum { + NO_DEVICE_DETECTED =3D 0, + PCIE_DEVICE =3D 1, + CXL_TYPE_1_DEVICE =3D 2, + CXL_TYPE_2_DEVICE_OR_HBR_SWITCH =3D 3, + CXL_TYPE_3_SLD =3D 4, + CXL_TYPE_3_MLD =3D 5, + PBR_COMPONENT =3D 6 +} connected_device_type; + +typedef enum { + CXL_RCD_MODE =3D 0x00, + CXL_68B_FLIT_AND_VH_CAPABLE =3D 0x01, + CXL_256B_FLIT_CAPABLE =3D 0x02, + CXL_LATENCY_OPTIMIZED_256B_FLIT =3D 0x03, + CXL_PBR_CAPABLE =3D 0x04 +} supported_cxl_modes; + +typedef enum { + LTSSM_DETECT =3D 0x00, + LTSSM_POLLING =3D 0x01, + LTSSM_CONFIGURATION =3D 0x02, + LTSSM_RECOVERY =3D 0x03, + LTSSM_L0 =3D 0x04, + LTSSM_L0S =3D 0x05, + LTSSM_L1 =3D 0x06, + LTSSM_L2 =3D 0x07, + LTSSM_DISABLED =3D 0x08, + LTSSM_LOOPBACK =3D 0x09, + LTSSM_HOT_RESET =3D 0x0A +} LTSSM_State; + /* CCI Message Format CXL r3.1 Figure 7-19 */ typedef struct CXLCCIMessage { uint8_t category; @@ -3686,6 +3744,112 @@ void cxl_add_cci_commands(CXLCCI *cci, const struct= cxl_cmd (*cxl_cmd_set)[256], cxl_rebuild_cel(cci); } =20 +static CXLRetCode cxl_set_port_type(struct phy_port *ports, int pnum, + CXLCCI *cci) +{ + PCIDevice *port_dev; + uint16_t lnkcap, lnkcap2, lnksta; + int i =3D pnum; + if (!cci) { + return CXL_MBOX_INTERNAL_ERROR; + } + + PCIBus *bus =3D &PCI_BRIDGE(cci->d)->sec_bus; + PCIEPort *usp =3D PCIE_PORT(cci->d); + port_dev =3D pcie_find_port_by_pn(bus, i); + + if (port_dev) { /* DSP */ + PCIDevice *ds_dev =3D pci_bridge_get_sec_bus(PCI_BRIDGE(port_dev)) + ->devices[0]; + ports->pport_info[i].port_id =3D i; + ports->pport_info[i].current_port_config_state =3D DSP; + ports->active_port_bitmask[i / 8] |=3D (1 << i % 8); + if (ds_dev) { + if (object_dynamic_cast(OBJECT(ds_dev), TYPE_CXL_TYPE3)) { + ports->pport_info[i].connected_device_type =3D CXL_TYPE_3_= MLD; + } else { + ports->pport_info[i].connected_device_type =3D PCIE_DEVICE; + } + } else { + ports->pport_info[i].connected_device_type =3D NO_DEVICE_DETEC= TED; + } + ports->pport_info[i].supported_ld_count =3D 3; + } else if (usp->port =3D=3D i) { /* USP */ + port_dev =3D PCI_DEVICE(usp); + ports->pport_info[i].port_id =3D i; + ports->pport_info[i].current_port_config_state =3D USP; + ports->pport_info[i].connected_device_type =3D NO_DEVICE_DETECTED; + ports->active_port_bitmask[i / 8] |=3D (1 << i % 8); + } else { + return CXL_MBOX_INVALID_INPUT; + } + + if (!port_dev->exp.exp_cap) { + return CXL_MBOX_INTERNAL_ERROR; + } + + lnksta =3D port_dev->config_read(port_dev, + port_dev->exp.exp_cap + PCI_EXP_LNKSTA, + sizeof(lnksta)); + lnkcap =3D port_dev->config_read(port_dev, + port_dev->exp.exp_cap + PCI_EXP_LNKCAP, + sizeof(lnkcap)); + lnkcap2 =3D port_dev->config_read(port_dev, + port_dev->exp.exp_cap + PCI_EXP_LNKCAP= 2, + sizeof(lnkcap2)); + + ports->pport_info[i].max_link_width =3D (lnkcap & PCI_EXP_LNKCAP_MLW) = >> 4; + ports->pport_info[i].negotiated_link_width =3D (lnksta & PCI_EXP_LNKST= A_NLW) >> 4; + ports->pport_info[i].supported_link_speeds_vector =3D (lnkcap2 & 0xFE)= >> 1; + ports->pport_info[i].max_link_speed =3D lnkcap & PCI_EXP_LNKCAP_SLS; + ports->pport_info[i].current_link_speed =3D lnksta & PCI_EXP_LNKSTA_CL= S; + + ports->pport_info[i].ltssm_state =3D LTSSM_L2; + ports->pport_info[i].first_negotiated_lane_num =3D 0; + ports->pport_info[i].link_state_flags =3D 0; + ports->pport_info[i].supported_cxl_modes =3D CXL_256B_FLIT_CAPABLE; + ports->pport_info[i].connected_device_mode =3D STANDARD_256B_FLIT_MODE; + + return CXL_MBOX_SUCCESS; +} + +static CXLRetCode cxl_set_phy_port_info(CXLCCI *cci) +{ + uint8_t phy_port_num; + if (!cci) { + return CXL_MBOX_INTERNAL_ERROR; + } + + PCIEPort *usp =3D PCIE_PORT(cci->d); + PCIBus *bus =3D &PCI_BRIDGE(cci->d)->sec_bus; + struct phy_port *ports =3D &cci->pports; + int num_phys_ports =3D pcie_count_ds_ports(bus) + 1; + if (num_phys_ports < 0) { + return CXL_MBOX_INTERNAL_ERROR; + } + + ports->num_ports =3D num_phys_ports; + phy_port_num =3D usp->port; + + cxl_set_port_type(ports, phy_port_num, cci); /* usp */ + + for (int devfn =3D 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { + PCIDevice *dev =3D bus->devices[devfn]; + + if (dev) { + phy_port_num =3D PCIE_PORT(dev)->port; + const char *typename =3D object_get_typename(OBJECT(dev)); + + if ((strcmp(typename, "cxl-downstream") =3D=3D 0)) { + cxl_set_port_type(ports, phy_port_num, cci); + } else { + return CXL_MBOX_INTERNAL_ERROR; + } + } + } + return CXL_MBOX_SUCCESS; +} + void cxl_initialize_mailbox_swcci(CXLCCI *cci, DeviceState *intf, DeviceState *d, size_t payload_max) { @@ -3693,6 +3857,7 @@ void cxl_initialize_mailbox_swcci(CXLCCI *cci, Device= State *intf, cci->d =3D d; cci->intf =3D intf; cxl_init_cci(cci, payload_max); + cxl_set_phy_port_info(cci); /* store port info */ } =20 void cxl_initialize_mailbox_t3(CXLCCI *cci, DeviceState *d, size_t payload= _max) @@ -3797,4 +3962,5 @@ void cxl_initialize_usp_mctpcci(CXLCCI *cci, DeviceSt= ate *d, DeviceState *intf, cci->d =3D d; cci->intf =3D intf; cxl_init_cci(cci, payload_max); + cxl_set_phy_port_info(cci); /* store port info */ } diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index ca515cab13..9eb128a1e8 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -127,6 +127,31 @@ CXL_NUM_CHMU_INSTANCES * (1 << 16), \ (1 << 16)) =20 +/* CXL r3.2 Table 7-19: Port Info */ +struct cxl_phy_port_info { + uint8_t port_id; + uint8_t current_port_config_state; + uint8_t connected_device_mode; + uint8_t rsv1; + uint8_t connected_device_type; + uint8_t supported_cxl_modes; + uint8_t max_link_width; + uint8_t negotiated_link_width; + uint8_t supported_link_speeds_vector; + uint8_t max_link_speed; + uint8_t current_link_speed; + uint8_t ltssm_state; + uint8_t first_negotiated_lane_num; + uint16_t link_state_flags; + uint8_t supported_ld_count; +} QEMU_PACKED; + +struct phy_port { + uint8_t num_ports; + uint8_t active_port_bitmask[0x20]; + struct cxl_phy_port_info pport_info[PCI_DEVFN_MAX]; +}; + /* CXL r3.1 Table 8-34: Command Return Codes */ typedef enum { CXL_MBOX_SUCCESS =3D 0x0, @@ -223,6 +248,9 @@ typedef struct CXLCCI { /* get log capabilities */ const CXLLogCapabilities *supported_log_cap; =20 + /*physical ports information */ + struct phy_port pports; + /* background command handling (times in ms) */ struct { uint16_t opcode; --=20 2.34.1 From nobody Wed Oct 15 19:09:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=samsung.com ARC-Seal: i=1; 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a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1748880161; bh=66WVFSP/xSbWixQ+H6vy956pgoDJ2ku2KIszXs8JQdo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WMBwEWyOEyhvifV3H0y73RBsNyAQ34YWagEnwj4qgDL372D0HAjwyx4fYays67wPG vcM9SP+GjtOYI/MV2rbJ+4CIbR4d/1gJGyMEbDMaeSUoJLfERO2J9ZMCi/lZ35TC5N VWs9sLxBG+QqLoMi+wjACdnrqLZQosdZM+iH9faE= From: Arpit Kumar To: qemu-devel@nongnu.org Cc: gost.dev@samsung.com, linux-cxl@vger.kernel.org, nifan.cxl@gmail.com, dave@stgolabs.net, vishak.g@samsung.com, krish.reddy@samsung.com, a.manzanares@samsung.com, alok.rathore@samsung.com, Arpit Kumar Subject: [PATCH 2/3] hw/cxl: Simplified Identify Switch Device & Get Physical Port State Date: Mon, 2 Jun 2025 19:29:41 +0530 Message-Id: <20250602135942.2773823-3-arpit1.kumar@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250602135942.2773823-1-arpit1.kumar@samsung.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250602140026epcas5p131c1af3cdd05056e7dccf0f91efe490b X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250602140026epcas5p131c1af3cdd05056e7dccf0f91efe490b References: <20250602135942.2773823-1-arpit1.kumar@samsung.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=203.254.224.25; envelope-from=arpit1.kumar@samsung.com; helo=mailout2.samsung.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.015, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @samsung.com) X-ZM-MESSAGEID: 1748880225741116600 Modified Identify Switch Device (Opcode 5100h) & Get Physical Port State(Opcode 5101h) using physical ports info stored during enumeration Signed-off-by: Arpit Kumar --- hw/cxl/cxl-mailbox-utils.c | 133 +++++++------------------------------ 1 file changed, 24 insertions(+), 109 deletions(-) diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index 680055c6c0..b2fa79a721 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -558,17 +558,7 @@ static CXLRetCode cmd_set_response_msg_limit(const str= uct cxl_cmd *cmd, return CXL_MBOX_SUCCESS; } =20 -static void cxl_set_dsp_active_bm(PCIBus *b, PCIDevice *d, - void *private) -{ - uint8_t *bm =3D private; - if (object_dynamic_cast(OBJECT(d), TYPE_CXL_DSP)) { - uint8_t port =3D PCIE_PORT(d)->port; - bm[port / 8] |=3D 1 << (port % 8); - } -} - -/* CXL r3.1 Section 7.6.7.1.1: Identify Switch Device (Opcode 5100h) */ +/* CXL r3.2 Section 7.6.7.1.1: Identify Switch Device (Opcode 5100h) */ static CXLRetCode cmd_identify_switch_device(const struct cxl_cmd *cmd, uint8_t *payload_in, size_t len_in, @@ -576,9 +566,7 @@ static CXLRetCode cmd_identify_switch_device(const stru= ct cxl_cmd *cmd, size_t *len_out, CXLCCI *cci) { - PCIEPort *usp =3D PCIE_PORT(cci->d); - PCIBus *bus =3D &PCI_BRIDGE(cci->d)->sec_bus; - int num_phys_ports =3D pcie_count_ds_ports(bus); + int num_phys_ports =3D cci->pports.num_ports; =20 struct cxl_fmapi_ident_switch_dev_resp_pl { uint8_t ingress_port_id; @@ -595,11 +583,11 @@ static CXLRetCode cmd_identify_switch_device(const st= ruct cxl_cmd *cmd, =20 out =3D (struct cxl_fmapi_ident_switch_dev_resp_pl *)payload_out; *out =3D (struct cxl_fmapi_ident_switch_dev_resp_pl) { - .num_physical_ports =3D num_phys_ports + 1, /* 1 USP */ + .num_physical_ports =3D num_phys_ports, .num_vcss =3D 1, /* Not yet support multiple VCS - potentially tri= cky */ .active_vcs_bitmask[0] =3D 0x1, - .total_vppbs =3D num_phys_ports + 1, - .bound_vppbs =3D num_phys_ports + 1, + .total_vppbs =3D num_phys_ports, + .bound_vppbs =3D num_phys_ports, .num_hdm_decoders_per_usp =3D 4, }; =20 @@ -611,16 +599,14 @@ static CXLRetCode cmd_identify_switch_device(const st= ruct cxl_cmd *cmd, out->ingress_port_id =3D 0; } =20 - pci_for_each_device_under_bus(bus, cxl_set_dsp_active_bm, - out->active_port_bitmask); - out->active_port_bitmask[usp->port / 8] |=3D (1 << usp->port % 8); - + memcpy(out->active_port_bitmask, cci->pports.active_port_bitmask, + sizeof(cci->pports.active_port_bitmask)); *len_out =3D sizeof(*out); =20 return CXL_MBOX_SUCCESS; } =20 -/* CXL r3.1 Section 7.6.7.1.2: Get Physical Port State (Opcode 5101h) */ +/* CXL r3.2 Section 7.6.7.1.2: Get Physical Port State (Opcode 5101h) */ static CXLRetCode cmd_get_physical_port_state(const struct cxl_cmd *cmd, uint8_t *payload_in, size_t len_in, @@ -628,44 +614,21 @@ static CXLRetCode cmd_get_physical_port_state(const s= truct cxl_cmd *cmd, size_t *len_out, CXLCCI *cci) { - /* CXL r3.1 Table 7-17: Get Physical Port State Request Payload */ + size_t pl_size; + int i; + + /* CXL r3.2 Table 7-17: Get Physical Port State Request Payload */ struct cxl_fmapi_get_phys_port_state_req_pl { uint8_t num_ports; uint8_t ports[]; } QEMU_PACKED *in; =20 - /* - * CXL r3.1 Table 7-19: Get Physical Port State Port Information Block - * Format - */ - struct cxl_fmapi_port_state_info_block { - uint8_t port_id; - uint8_t config_state; - uint8_t connected_device_cxl_version; - uint8_t rsv1; - uint8_t connected_device_type; - uint8_t port_cxl_version_bitmask; - uint8_t max_link_width; - uint8_t negotiated_link_width; - uint8_t supported_link_speeds_vector; - uint8_t max_link_speed; - uint8_t current_link_speed; - uint8_t ltssm_state; - uint8_t first_lane_num; - uint16_t link_state; - uint8_t supported_ld_count; - } QEMU_PACKED; - - /* CXL r3.1 Table 7-18: Get Physical Port State Response Payload */ + /* CXL r3.2 Table 7-18: Get Physical Port State Response Payload */ struct cxl_fmapi_get_phys_port_state_resp_pl { uint8_t num_ports; uint8_t rsv1[3]; - struct cxl_fmapi_port_state_info_block ports[]; + struct cxl_phy_port_info ports[]; } QEMU_PACKED *out; - PCIBus *bus =3D &PCI_BRIDGE(cci->d)->sec_bus; - PCIEPort *usp =3D PCIE_PORT(cci->d); - size_t pl_size; - int i; =20 in =3D (struct cxl_fmapi_get_phys_port_state_req_pl *)payload_in; out =3D (struct cxl_fmapi_get_phys_port_state_resp_pl *)payload_out; @@ -673,72 +636,24 @@ static CXLRetCode cmd_get_physical_port_state(const s= truct cxl_cmd *cmd, if (len_in < sizeof(*in)) { return CXL_MBOX_INVALID_PAYLOAD_LENGTH; } - /* Check if what was requested can fit */ + if (sizeof(*out) + sizeof(*out->ports) * in->num_ports > cci->payload_= max) { return CXL_MBOX_INVALID_INPUT; } =20 - /* For success there should be a match for each requested */ - out->num_ports =3D in->num_ports; + if (in->num_ports > cci->pports.num_ports) { + return CXL_MBOX_INVALID_INPUT; + } =20 + out->num_ports =3D in->num_ports; for (i =3D 0; i < in->num_ports; i++) { - struct cxl_fmapi_port_state_info_block *port; - /* First try to match on downstream port */ - PCIDevice *port_dev; - uint16_t lnkcap, lnkcap2, lnksta; - - port =3D &out->ports[i]; - - port_dev =3D pcie_find_port_by_pn(bus, in->ports[i]); - if (port_dev) { /* DSP */ - PCIDevice *ds_dev =3D pci_bridge_get_sec_bus(PCI_BRIDGE(port_d= ev)) - ->devices[0]; - port->config_state =3D 3; - if (ds_dev) { - if (object_dynamic_cast(OBJECT(ds_dev), TYPE_CXL_TYPE3)) { - port->connected_device_type =3D 5; /* Assume MLD for n= ow */ - } else { - port->connected_device_type =3D 1; - } - } else { - port->connected_device_type =3D 0; + int pn =3D in->ports[i]; + for (int j =3D 0; j < PCI_DEVFN_MAX; j++) { + if (pn =3D=3D cci->pports.pport_info[j].port_id) { + memcpy(&out->ports[i], &(cci->pports.pport_info[pn]), + sizeof(struct cxl_phy_port_info)); } - port->supported_ld_count =3D 3; - } else if (usp->port =3D=3D in->ports[i]) { /* USP */ - port_dev =3D PCI_DEVICE(usp); - port->config_state =3D 4; - port->connected_device_type =3D 0; - } else { - return CXL_MBOX_INVALID_INPUT; - } - - port->port_id =3D in->ports[i]; - /* Information on status of this port in lnksta, lnkcap */ - if (!port_dev->exp.exp_cap) { - return CXL_MBOX_INTERNAL_ERROR; } - lnksta =3D port_dev->config_read(port_dev, - port_dev->exp.exp_cap + PCI_EXP_LNK= STA, - sizeof(lnksta)); - lnkcap =3D port_dev->config_read(port_dev, - port_dev->exp.exp_cap + PCI_EXP_LNK= CAP, - sizeof(lnkcap)); - lnkcap2 =3D port_dev->config_read(port_dev, - port_dev->exp.exp_cap + PCI_EXP_LN= KCAP2, - sizeof(lnkcap2)); - - port->max_link_width =3D (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4; - port->negotiated_link_width =3D (lnksta & PCI_EXP_LNKSTA_NLW) >> 4; - /* No definition for SLS field in linux/pci_regs.h */ - port->supported_link_speeds_vector =3D (lnkcap2 & 0xFE) >> 1; - port->max_link_speed =3D lnkcap & PCI_EXP_LNKCAP_SLS; - port->current_link_speed =3D lnksta & PCI_EXP_LNKSTA_CLS; - /* TODO: Track down if we can get the rest of the info */ - port->ltssm_state =3D 0x7; - port->first_lane_num =3D 0; - port->link_state =3D 0; - port->port_cxl_version_bitmask =3D 0x2; - port->connected_device_cxl_version =3D 0x2; } =20 pl_size =3D sizeof(*out) + sizeof(*out->ports) * in->num_ports; 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Mon, 2 Jun 2025 14:00:43 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout4.samsung.com 20250602160249epoutp04df86d71da88b2c6af361422b5d246cd1~FRT_bk-n52225722257epoutp04r DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1748880169; bh=KrYuxyakbnI0aUfKV8KahEPEuvW90FgrJ3GbYGPxDR8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kUDtR3THaBC4NJE0/6pNiN/jRpdMQ/5TvZ7OCB8xtcJ43gKJuZQnYKLrgEDNoRrtB tOhlKlUTBVjJG6wYeQkXyBTUrAThBrRayx20RLI1sUSQZB4e8oL4T0A1J9FYaGGyvY IUjZNDsjTd7GUc1kFnFe0vQ4p/BTaiqs9DYHY2iM= From: Arpit Kumar To: qemu-devel@nongnu.org Cc: gost.dev@samsung.com, linux-cxl@vger.kernel.org, nifan.cxl@gmail.com, dave@stgolabs.net, vishak.g@samsung.com, krish.reddy@samsung.com, a.manzanares@samsung.com, alok.rathore@samsung.com, Arpit Kumar Subject: [PATCH 3/3] hw/cxl: Add Physical Port Control (Opcode 5102h) Date: Mon, 2 Jun 2025 19:29:42 +0530 Message-Id: <20250602135942.2773823-4-arpit1.kumar@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250602135942.2773823-1-arpit1.kumar@samsung.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250602140045epcas5p2445a99b249ba9588af027d59b0c8bd35 X-Msg-Generator: CA Content-Type: text/plain; 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Signed-off-by: Arpit Kumar --- hw/cxl/cxl-mailbox-utils.c | 128 ++++++++++++++++++++++++++++++++++++ include/hw/cxl/cxl_device.h | 8 +++ 2 files changed, 136 insertions(+) diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index b2fa79a721..4f09692713 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -118,12 +118,16 @@ enum { PHYSICAL_SWITCH =3D 0x51, #define IDENTIFY_SWITCH_DEVICE 0x0 #define GET_PHYSICAL_PORT_STATE 0x1 + #define PHYSICAL_PORT_CONTROL 0X2 TUNNEL =3D 0x53, #define MANAGEMENT_COMMAND 0x0 MHD =3D 0x55, #define GET_MHD_INFO 0x0 }; =20 +/* Assert - Deassert PERST */ +#define ASSERT_WAIT_TIME_MS 100 + /* link state flags */ #define LINK_STATE_FLAG_LANE_REVERSED (1 << 0) #define LINK_STATE_FLAG_PERST_ASSERTED (1 << 1) @@ -662,6 +666,114 @@ static CXLRetCode cmd_get_physical_port_state(const s= truct cxl_cmd *cmd, return CXL_MBOX_SUCCESS; } =20 +static struct PCIDevice *cxl_find_port_dev(uint8_t ppb_id, PCIBus *bus) +{ + PCIDevice *d; + int devfn; + + for (devfn =3D 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { + d =3D bus->devices[devfn]; + if (d) { + if (object_dynamic_cast(OBJECT(d), TYPE_CXL_DSP)) { + uint8_t port =3D PCIE_PORT(d)->port; + if (port =3D=3D ppb_id) { + return d; + } + } + } + } + return NULL; +} + +static CXLRetCode deassert_PERST(Object *obj, ResetType type, uint8_t pn, = CXLCCI *cci) +{ + ResettableClass *rc =3D RESETTABLE_GET_CLASS(obj); + ResettableState *s =3D rc->get_state(obj); + + if (cci->pports.perst[pn].issued_assert_PERST) { + if (cci->pports.perst[pn].asrt_time =3D=3D -1 && !s->hold_phase_pe= nding) { + qemu_mutex_lock(&cci->pports.perst[pn].lock); + resettable_release_reset(obj, type); + cci->pports.perst[pn].issued_assert_PERST =3D false; + cci->pports.pport_info[pn].link_state_flags &=3D + ~LINK_STATE_FLAG_PERST_ASSERTED; + cci->pports.perst[pn].asrt_time =3D ASSERT_WAIT_TIME_MS; + qemu_mutex_unlock(&cci->pports.perst[pn].lock); + } else { + return CXL_MBOX_INTERNAL_ERROR; + } + } else { + return CXL_MBOX_INTERNAL_ERROR; + } + return CXL_MBOX_SUCCESS; +} + +static CXLRetCode assert_PERST(Object *obj, ResetType type, uint8_t pn, CX= LCCI *cci) +{ + ResettableClass *rc =3D RESETTABLE_GET_CLASS(obj); + ResettableState *s =3D rc->get_state(obj); + + if (cci->pports.perst[pn].issued_assert_PERST || s->exit_phase_in_prog= ress) { + return CXL_MBOX_INTERNAL_ERROR; + } + + qemu_mutex_lock(&cci->pports.perst[pn].lock); + cci->pports.perst[pn].issued_assert_PERST =3D true; + cci->pports.pport_info[pn].link_state_flags |=3D + LINK_STATE_FLAG_PERST_ASSERTED; + resettable_assert_reset(obj, type); + qemu_mutex_unlock(&cci->pports.perst[pn].lock); + + /* holding reset phase for 100ms */ + while (cci->pports.perst[pn].asrt_time--) { + usleep(1000); + } + return CXL_MBOX_SUCCESS; +} + +/*CXL r3.2 Section 7.6.7.1.3: Get Physical Port Control (Opcode 5102h)*/ +static CXLRetCode cmd_physical_port_control(const struct cxl_cmd *cmd, + uint8_t *payload_in, + size_t len_in, + uint8_t *payload_out, + size_t *len_out, + CXLCCI *cci) +{ + PCIBus *bus =3D &PCI_BRIDGE(cci->d)->sec_bus; + PCIDevice *dev; + struct cxl_fmapi_get_physical_port_control_req_pl { + uint8_t PPB_ID; + uint8_t Ports_Op; + } QEMU_PACKED *in; + + in =3D (struct cxl_fmapi_get_physical_port_control_req_pl *)payload_in; + + if (len_in < sizeof(*in)) { + return CXL_MBOX_INVALID_PAYLOAD_LENGTH; + } + + uint8_t pn =3D in->PPB_ID; + dev =3D cxl_find_port_dev(pn, bus); + if (!dev) { + return CXL_MBOX_INTERNAL_ERROR; + } + + switch (in->Ports_Op) { + case 0: + assert_PERST(OBJECT(&dev->qdev), RESET_TYPE_COLD, pn, cci); + break; + case 1: + deassert_PERST(OBJECT(&dev->qdev), RESET_TYPE_COLD, pn, cci); + break; + case 2: + device_cold_reset(&dev->qdev); + break; + default: + return CXL_MBOX_INVALID_INPUT; + } + return CXL_MBOX_SUCCESS; +} + /* CXL r3.1 Section 8.2.9.1.2: Background Operation Status (Opcode 0002h) = */ static CXLRetCode cmd_infostat_bg_op_sts(const struct cxl_cmd *cmd, uint8_t *payload_in, @@ -3637,6 +3749,9 @@ void cxl_init_cci(CXLCCI *cci, size_t payload_max) void cxl_destroy_cci(CXLCCI *cci) { qemu_mutex_destroy(&cci->bg.lock); + for (int i =3D 0; i < PCI_DEVFN_MAX; i++) { + qemu_mutex_destroy(&cci->pports.perst[i].lock); + } cci->initialized =3D false; } =20 @@ -3866,6 +3981,8 @@ static const struct cxl_cmd cxl_cmd_set_usp_mctp[256]= [256] =3D { cmd_identify_switch_device, 0, 0 }, [PHYSICAL_SWITCH][GET_PHYSICAL_PORT_STATE] =3D { "SWITCH_PHYSICAL_PORT= _STATS", cmd_get_physical_port_state, ~0, 0 }, + [PHYSICAL_SWITCH][PHYSICAL_PORT_CONTROL] =3D { "SWITCH_PHYSICAL_PORT_C= ONTROL", + cmd_physical_port_control, 2, 0 }, [TUNNEL][MANAGEMENT_COMMAND] =3D { "TUNNEL_MANAGEMENT_COMMAND", cmd_tunnel_management_cmd, ~0, 0 }, }; @@ -3878,4 +3995,15 @@ void cxl_initialize_usp_mctpcci(CXLCCI *cci, DeviceS= tate *d, DeviceState *intf, cci->intf =3D intf; cxl_init_cci(cci, payload_max); cxl_set_phy_port_info(cci); /* store port info */ + /* physical port control */ + for (int i =3D 0; i < PCI_DEVFN_MAX; i++) { + qemu_mutex_init(&cci->pports.perst[i].lock); + cci->pports.perst[i].issued_assert_PERST =3D false; + /* Assert PERST involves physical port to be in + * hold reset phase for minimum 100ms. No other calls + * are entertained until Deassert PERST command. + * https://patchwork.ozlabs.org/project/linux-pci/patch/2019052319= 4409.17718-1-niklas.cassel@linaro.org/#2178369 + */ + cci->pports.perst[i].asrt_time =3D ASSERT_WAIT_TIME_MS; + } } diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index 9eb128a1e8..f877d60b39 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -146,10 +146,18 @@ struct cxl_phy_port_info { uint8_t supported_ld_count; } QEMU_PACKED; =20 +/* assert-deassert PERST */ +struct pperst { + bool issued_assert_PERST; + int asrt_time; + QemuMutex lock; +}; + struct phy_port { uint8_t num_ports; uint8_t active_port_bitmask[0x20]; struct cxl_phy_port_info pport_info[PCI_DEVFN_MAX]; + struct pperst perst[PCI_DEVFN_MAX]; }; =20 /* CXL r3.1 Table 8-34: Command Return Codes */ --=20 2.34.1