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b=IinxHF4YshLSHKGhGUNDWJ8ifXZXViI1AFmCt3h11iUQmlU4lN848ovTZ7tvaLcTG4xhGMk8h+Ig+mQkNdcCOO5IsHLEsIfo8D2Fd53HVWmmfcPx13gW4IRhwjDdJCxnJihIjITV9lTvWh3IbNAIW7IE7RUCPryNI2pPWcQuh6XZhiMcGvu9vdQc/BX8xXfxY6BMQsnDtyKo+hyys2l8PBCispiGz+iHDv/T5RU5w33xLQY+icV23dIRHwCPSxFmzd97z4SpLaBwKS7lomwu5iS38z/JXt2NRn/IJDH3ezF9nMsnP/AYZDUZjUcMLEB8wes8hGCoqQUkcm4+7ZgGCw== From: Djordje Todorovic To: "qemu-devel@nongnu.org" CC: "qemu-riscv@nongnu.org" , "cfu@mips.com" , Djordje Todorovic Subject: [PATCH v2 1/9] hw/intc: Allow gaps in hartids for aclint and aplic Thread-Topic: [PATCH v2 1/9] hw/intc: Allow gaps in hartids for aclint and aplic Thread-Index: AQHb08ABPHR9vHZGW0yKLO8lTfD9Ew== Date: Mon, 2 Jun 2025 13:12:34 +0000 Message-ID: <20250602131226.1137281-2-djordje.todorovic@htecgroup.com> References: <20250602131226.1137281-1-djordje.todorovic@htecgroup.com> In-Reply-To: <20250602131226.1137281-1-djordje.todorovic@htecgroup.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; 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Signed-off-by: Chao-ying Fu Signed-off-by: Djordje Todorovic --- hw/intc/riscv_aclint.c | 33 +++++++++++++++++++++++++++++++-- hw/intc/riscv_aplic.c | 10 +++++++--- 2 files changed, 38 insertions(+), 5 deletions(-) diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index b0139f03f5..5bda02a179 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -131,6 +131,9 @@ static uint64_t riscv_aclint_mtimer_read(void *opaque, = hwaddr addr, size_t hartid =3D mtimer->hartid_base + ((addr - mtimer->timecmp_base) >> 3); CPUState *cpu =3D cpu_by_arch_id(hartid); + if (cpu =3D=3D NULL) { + return 0; + } CPURISCVState *env =3D cpu ? cpu_env(cpu) : NULL; if (!env) { qemu_log_mask(LOG_GUEST_ERROR, @@ -174,6 +177,9 @@ static void riscv_aclint_mtimer_write(void *opaque, hwa= ddr addr, size_t hartid =3D mtimer->hartid_base + ((addr - mtimer->timecmp_base) >> 3); CPUState *cpu =3D cpu_by_arch_id(hartid); + if (cpu =3D=3D NULL) { + return; + } CPURISCVState *env =3D cpu ? cpu_env(cpu) : NULL; if (!env) { qemu_log_mask(LOG_GUEST_ERROR, @@ -233,6 +239,9 @@ static void riscv_aclint_mtimer_write(void *opaque, hwa= ddr addr, /* Check if timer interrupt is triggered for each hart. */ for (i =3D 0; i < mtimer->num_harts; i++) { CPUState *cpu =3D cpu_by_arch_id(mtimer->hartid_base + i); + if (cpu =3D=3D NULL) { + continue; + } CPURISCVState *env =3D cpu ? cpu_env(cpu) : NULL; if (!env) { continue; @@ -292,7 +301,11 @@ static void riscv_aclint_mtimer_realize(DeviceState *d= ev, Error **errp) s->timecmp =3D g_new0(uint64_t, s->num_harts); /* Claim timer interrupt bits */ for (i =3D 0; i < s->num_harts; i++) { - RISCVCPU *cpu =3D RISCV_CPU(cpu_by_arch_id(s->hartid_base + i)); + CPUState *temp =3D cpu_by_arch_id(s->hartid_base + i); + if (temp =3D=3D NULL) { + continue; + } + RISCVCPU *cpu =3D RISCV_CPU(temp); if (riscv_cpu_claim_interrupts(cpu, MIP_MTIP) < 0) { error_report("MTIP already claimed"); exit(1); @@ -373,6 +386,9 @@ DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hw= addr size, =20 for (i =3D 0; i < num_harts; i++) { CPUState *cpu =3D cpu_by_arch_id(hartid_base + i); + if (cpu =3D=3D NULL) { + continue; + } RISCVCPU *rvcpu =3D RISCV_CPU(cpu); CPURISCVState *env =3D cpu ? cpu_env(cpu) : NULL; riscv_aclint_mtimer_callback *cb =3D @@ -408,6 +424,9 @@ static uint64_t riscv_aclint_swi_read(void *opaque, hwa= ddr addr, if (addr < (swi->num_harts << 2)) { size_t hartid =3D swi->hartid_base + (addr >> 2); CPUState *cpu =3D cpu_by_arch_id(hartid); + if (cpu =3D=3D NULL) { + return 0; + } CPURISCVState *env =3D cpu ? cpu_env(cpu) : NULL; if (!env) { qemu_log_mask(LOG_GUEST_ERROR, @@ -431,6 +450,9 @@ static void riscv_aclint_swi_write(void *opaque, hwaddr= addr, uint64_t value, if (addr < (swi->num_harts << 2)) { size_t hartid =3D swi->hartid_base + (addr >> 2); CPUState *cpu =3D cpu_by_arch_id(hartid); + if (cpu =3D=3D NULL) { + return; + } CPURISCVState *env =3D cpu ? cpu_env(cpu) : NULL; if (!env) { qemu_log_mask(LOG_GUEST_ERROR, @@ -481,7 +503,11 @@ static void riscv_aclint_swi_realize(DeviceState *dev,= Error **errp) =20 /* Claim software interrupt bits */ for (i =3D 0; i < swi->num_harts; i++) { - RISCVCPU *cpu =3D RISCV_CPU(qemu_get_cpu(swi->hartid_base + i)); + CPUState *temp =3D cpu_by_arch_id(swi->hartid_base + i); + if (temp =3D=3D NULL) { + continue; + } + RISCVCPU *cpu =3D RISCV_CPU(temp); /* We don't claim mip.SSIP because it is writable by software */ if (riscv_cpu_claim_interrupts(cpu, swi->sswi ? 0 : MIP_MSIP) < 0)= { error_report("MSIP already claimed"); @@ -545,6 +571,9 @@ DeviceState *riscv_aclint_swi_create(hwaddr addr, uint3= 2_t hartid_base, =20 for (i =3D 0; i < num_harts; i++) { CPUState *cpu =3D cpu_by_arch_id(hartid_base + i); + if (cpu =3D=3D NULL) { + continue; + } RISCVCPU *rvcpu =3D RISCV_CPU(cpu); =20 qdev_connect_gpio_out(dev, i, diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index 8bcd9f4697..360a3dc117 100644 --- a/hw/intc/riscv_aplic.c +++ b/hw/intc/riscv_aplic.c @@ -899,9 +899,11 @@ static void riscv_aplic_realize(DeviceState *dev, Erro= r **errp) if (!aplic->msimode) { /* Claim the CPU interrupt to be triggered by this APLIC */ for (i =3D 0; i < aplic->num_harts; i++) { - RISCVCPU *cpu; - - cpu =3D RISCV_CPU(cpu_by_arch_id(aplic->hartid_base + i)); + CPUState *temp =3D cpu_by_arch_id(aplic->hartid_base + i); + if (temp =3D=3D NULL) { + continue; + } + RISCVCPU *cpu =3D RISCV_CPU(temp); if (riscv_cpu_claim_interrupts(cpu, (aplic->mmode) ? MIP_MEIP : MIP_SEIP) < 0) { error_report("%s already claimed", @@ -1076,6 +1078,8 @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr s= ize, if (!msimode) { for (i =3D 0; i < num_harts; i++) { CPUState *cpu =3D cpu_by_arch_id(hartid_base + i); + if (cpu =3D=3D NULL) + continue; =20 qdev_connect_gpio_out_named(dev, NULL, i, qdev_get_gpio_in(DEVICE(cpu), --=20 2.34.1