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Fri, 30 May 2025 00:15:19 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH09F5c5lNRGie69php26hZ5x/f9XdC27FLPy5m5ANRsKdBrNORJgzzqiiXDMApSwEHFdjOLw== X-Received: by 2002:a17:907:7ba7:b0:ad8:96d2:f3b with SMTP id a640c23a62f3a-adb322ab0f4mr205342166b.27.1748589319011; Fri, 30 May 2025 00:15:19 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Xiaoyao Li Subject: [PULL 58/77] i386/tdx: Add supported CPUID bits related to TD Attributes Date: Fri, 30 May 2025 09:12:28 +0200 Message-ID: <20250530071250.2050910-59-pbonzini@redhat.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250530071250.2050910-1-pbonzini@redhat.com> References: <20250530071250.2050910-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -49 X-Spam_score: -5.0 X-Spam_bar: ----- X-Spam_report: (-5.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.902, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1748589607930116600 Content-Type: text/plain; charset="utf-8" From: Xiaoyao Li For TDX, some CPUID feature bit is configured via TD attributes. They are not covered by tdx_caps.cpuid (which only contians the directly configurable CPUID bits), but they are actually supported when the related attributre bit is supported. Note, LASS and KeyLocker are not supported by KVM for TDX, nor does QEMU support it (see TDX_SUPPORTED_TD_ATTRS). They are defined in tdx_attrs_maps[] for the completeness of the existing TD Attribute bits that are related with CPUID features. Signed-off-by: Xiaoyao Li Link: https://lore.kernel.org/r/20250508150002.689633-47-xiaoyao.li@intel.c= om Signed-off-by: Paolo Bonzini --- target/i386/cpu.h | 4 +++ target/i386/kvm/tdx.c | 60 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 64 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 342e4f2a572..e50c57264dc 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -899,6 +899,8 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu= , FeatureWord w); #define CPUID_7_0_ECX_LA57 (1U << 16) /* Read Processor ID */ #define CPUID_7_0_ECX_RDPID (1U << 22) +/* KeyLocker */ +#define CPUID_7_0_ECX_KeyLocker (1U << 23) /* Bus Lock Debug Exception */ #define CPUID_7_0_ECX_BUS_LOCK_DETECT (1U << 24) /* Cache Line Demote Instruction */ @@ -959,6 +961,8 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu= , FeatureWord w); #define CPUID_7_1_EAX_AVX_VNNI (1U << 4) /* AVX512 BFloat16 Instruction */ #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) +/* Linear address space separation */ +#define CPUID_7_1_EAX_LASS (1U << 6) /* CMPCCXADD Instructions */ #define CPUID_7_1_EAX_CMPCCXADD (1U << 7) /* Fast Zero REP MOVS */ diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index 9d92ff1484b..fa161661fa8 100644 --- a/target/i386/kvm/tdx.c +++ b/target/i386/kvm/tdx.c @@ -458,6 +458,34 @@ KvmCpuidInfo tdx_fixed1_bits =3D { }, }; =20 +typedef struct TdxAttrsMap { + uint32_t attr_index; + uint32_t cpuid_leaf; + uint32_t cpuid_subleaf; + int cpuid_reg; + uint32_t feat_mask; +} TdxAttrsMap; + +static TdxAttrsMap tdx_attrs_maps[] =3D { + {.attr_index =3D 27, + .cpuid_leaf =3D 7, + .cpuid_subleaf =3D 1, + .cpuid_reg =3D R_EAX, + .feat_mask =3D CPUID_7_1_EAX_LASS,}, + + {.attr_index =3D 30, + .cpuid_leaf =3D 7, + .cpuid_subleaf =3D 0, + .cpuid_reg =3D R_ECX, + .feat_mask =3D CPUID_7_0_ECX_PKS,}, + + {.attr_index =3D 31, + .cpuid_leaf =3D 7, + .cpuid_subleaf =3D 0, + .cpuid_reg =3D R_ECX, + .feat_mask =3D CPUID_7_0_ECX_KeyLocker,}, +}; + static struct kvm_cpuid_entry2 *find_in_supported_entry(uint32_t function, uint32_t index) { @@ -494,6 +522,37 @@ static void tdx_add_supported_cpuid_by_fixed1_bits(voi= d) } } =20 +static void tdx_add_supported_cpuid_by_attrs(void) +{ + struct kvm_cpuid_entry2 *e; + TdxAttrsMap *map; + int i; + + for (i =3D 0; i < ARRAY_SIZE(tdx_attrs_maps); i++) { + map =3D &tdx_attrs_maps[i]; + if (!((1ULL << map->attr_index) & tdx_caps->supported_attrs)) { + continue; + } + + e =3D find_in_supported_entry(map->cpuid_leaf, map->cpuid_subleaf); + + switch(map->cpuid_reg) { + case R_EAX: + e->eax |=3D map->feat_mask; + break; + case R_EBX: + e->ebx |=3D map->feat_mask; + break; + case R_ECX: + e->ecx |=3D map->feat_mask; + break; + case R_EDX: + e->edx |=3D map->feat_mask; + break; + } + } +} + static void tdx_setup_supported_cpuid(void) { if (tdx_supported_cpuid) { @@ -508,6 +567,7 @@ static void tdx_setup_supported_cpuid(void) tdx_supported_cpuid->nent =3D tdx_caps->cpuid.nent; =20 tdx_add_supported_cpuid_by_fixed1_bits(); + tdx_add_supported_cpuid_by_attrs(); } =20 static int tdx_kvm_init(ConfidentialGuestSupport *cgs, Error **errp) --=20 2.49.0